All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
@ 2019-03-04 19:10 Christian König
       [not found] ` <20190304191027.1792-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Christian König @ 2019-03-04 19:10 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Disable overflow and enable full drain. This makes fault handling on ring 1
much more reliable since we don't generate back pressure any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 6d1f804277f8..d4a3cc413af8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
 
 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
 		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+					   WPTR_OVERFLOW_ENABLE, 0);
+		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+					   RB_FULL_DRAIN_ENABLE, 1);
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
 
 		/* set rptr, wptr to 0 */
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/3] drm/amdgpu: enable IH doorbell for ring 1&2 on Vega
       [not found] ` <20190304191027.1792-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2019-03-04 19:10   ` Christian König
  2019-03-04 19:10   ` [PATCH 3/3] drm/amdgpu: enable IH ring 1&2 for Vega20 as well Christian König
  2019-03-06  9:28   ` [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config Christian König
  2 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2019-03-04 19:10 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

The doorbells should already be reserved, just enable them.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c |  3 +-
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 66 +++++++++++++++++---------
 2 files changed, 45 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index cc967dbfd631..6590143c3f75 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -118,7 +118,8 @@ static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
 
 	if (use_doorbell) {
 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
-		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  BIF_IH_DOORBELL_RANGE, SIZE, 6);
 	} else
 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index d4a3cc413af8..fa45234f020f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -136,6 +136,25 @@ static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl
 	return ih_rb_cntl;
 }
 
+static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
+{
+	u32 ih_doorbell_rtpr = 0;
+
+	if (ih->use_doorbell) {
+		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+						 IH_DOORBELL_RPTR, OFFSET,
+						 ih->doorbell_index);
+		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+						 IH_DOORBELL_RPTR,
+						 ENABLE, 1);
+	} else {
+		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+						 IH_DOORBELL_RPTR,
+						 ENABLE, 0);
+	}
+	return ih_doorbell_rtpr;
+}
+
 /**
  * vega10_ih_irq_init - init and enable the interrupt ring
  *
@@ -150,8 +169,8 @@ static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl
 static int vega10_ih_irq_init(struct amdgpu_device *adev)
 {
 	struct amdgpu_ih_ring *ih;
+	u32 ih_rb_cntl;
 	int ret = 0;
-	u32 ih_rb_cntl, ih_doorbell_rtpr;
 	u32 tmp;
 
 	/* disable irqs */
@@ -177,23 +196,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
 		     upper_32_bits(ih->wptr_addr) & 0xFFFF);
 
 	/* set rptr, wptr to 0 */
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
 
-	ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
-	if (adev->irq.ih.use_doorbell) {
-		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
-						 IH_DOORBELL_RPTR, OFFSET,
-						 adev->irq.ih.doorbell_index);
-		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
-						 IH_DOORBELL_RPTR,
-						 ENABLE, 1);
-	} else {
-		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
-						 IH_DOORBELL_RPTR,
-						 ENABLE, 0);
-	}
-	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
+	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,
+		     vega10_ih_doorbell_rptr(ih));
 
 	ih = &adev->irq.ih1;
 	if (ih->ring_size) {
@@ -210,8 +217,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
 
 		/* set rptr, wptr to 0 */
-		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+
+		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,
+			     vega10_ih_doorbell_rptr(ih));
 	}
 
 	ih = &adev->irq.ih2;
@@ -220,13 +230,16 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
 			     (ih->gpu_addr >> 40) & 0xff);
 
-		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
 		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
 
 		/* set rptr, wptr to 0 */
-		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+
+		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2,
+			     vega10_ih_doorbell_rptr(ih));
 	}
 
 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
@@ -453,19 +466,26 @@ static int vega10_ih_sw_init(void *handle)
 	if (r)
 		return r;
 
+	adev->irq.ih.use_doorbell = true;
+	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
+
 	if (adev->asic_type == CHIP_VEGA10) {
 		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
 		if (r)
 			return r;
 
+		adev->irq.ih1.use_doorbell = true;
+		adev->irq.ih1.doorbell_index =
+			(adev->doorbell_index.ih + 1) << 1;
+
 		r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
 		if (r)
 			return r;
-	}
 
-	/* TODO add doorbell for IH1 & IH2 as well */
-	adev->irq.ih.use_doorbell = true;
-	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
+		adev->irq.ih2.use_doorbell = true;
+		adev->irq.ih2.doorbell_index =
+			(adev->doorbell_index.ih + 2) << 1;
+	}
 
 	r = amdgpu_irq_init(adev);
 
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 3/3] drm/amdgpu: enable IH ring 1&2 for Vega20 as well
       [not found] ` <20190304191027.1792-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
  2019-03-04 19:10   ` [PATCH 2/3] drm/amdgpu: enable IH doorbell for ring 1&2 on Vega Christian König
@ 2019-03-04 19:10   ` Christian König
  2019-03-06  9:28   ` [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config Christian König
  2 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2019-03-04 19:10 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

That doesn't seem to have any negative effects.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 30 +++++++++++---------------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index fa45234f020f..1b2f69a9a24e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -469,23 +469,19 @@ static int vega10_ih_sw_init(void *handle)
 	adev->irq.ih.use_doorbell = true;
 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-	if (adev->asic_type == CHIP_VEGA10) {
-		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
-		if (r)
-			return r;
-
-		adev->irq.ih1.use_doorbell = true;
-		adev->irq.ih1.doorbell_index =
-			(adev->doorbell_index.ih + 1) << 1;
-
-		r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
-		if (r)
-			return r;
-
-		adev->irq.ih2.use_doorbell = true;
-		adev->irq.ih2.doorbell_index =
-			(adev->doorbell_index.ih + 2) << 1;
-	}
+	r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
+	if (r)
+		return r;
+
+	adev->irq.ih1.use_doorbell = true;
+	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
+
+	r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
+	if (r)
+		return r;
+
+	adev->irq.ih2.use_doorbell = true;
+	adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
 
 	r = amdgpu_irq_init(adev);
 
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
       [not found] ` <20190304191027.1792-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
  2019-03-04 19:10   ` [PATCH 2/3] drm/amdgpu: enable IH doorbell for ring 1&2 on Vega Christian König
  2019-03-04 19:10   ` [PATCH 3/3] drm/amdgpu: enable IH ring 1&2 for Vega20 as well Christian König
@ 2019-03-06  9:28   ` Christian König
       [not found]     ` <d2e841e5-8c65-c46b-1346-d3cc96584f61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2 siblings, 1 reply; 6+ messages in thread
From: Christian König @ 2019-03-06  9:28 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Ping? Can anybody review this?

Thanks,
Christian.

Am 04.03.19 um 20:10 schrieb Christian König:
> Disable overflow and enable full drain. This makes fault handling on ring 1
> much more reliable since we don't generate back pressure any more.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 6d1f804277f8..d4a3cc413af8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
>   
>   		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
>   		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> +		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> +					   WPTR_OVERFLOW_ENABLE, 0);
> +		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> +					   RB_FULL_DRAIN_ENABLE, 1);
>   		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
>   
>   		/* set rptr, wptr to 0 */

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* RE: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
       [not found]     ` <d2e841e5-8c65-c46b-1346-d3cc96584f61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2019-03-06 11:54       ` Zhou, David(ChunMing)
  2019-03-06 16:10       ` Zeng, Oak
  1 sibling, 0 replies; 6+ messages in thread
From: Zhou, David(ChunMing) @ 2019-03-06 11:54 UTC (permalink / raw)
  To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Acked-by: Chunming Zhou <david1.zhou@amd.com>


> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Christian K?nig
> Sent: Wednesday, March 06, 2019 5:29 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
> 
> Ping? Can anybody review this?
> 
> Thanks,
> Christian.
> 
> Am 04.03.19 um 20:10 schrieb Christian König:
> > Disable overflow and enable full drain. This makes fault handling on
> > ring 1 much more reliable since we don't generate back pressure any more.
> >
> > Signed-off-by: Christian König <christian.koenig@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > index 6d1f804277f8..d4a3cc413af8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct
> > amdgpu_device *adev)
> >
> >   		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0,
> mmIH_RB_CNTL_RING1);
> >   		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> > +		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> > +					   WPTR_OVERFLOW_ENABLE, 0);
> > +		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> > +					   RB_FULL_DRAIN_ENABLE, 1);
> >   		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1,
> ih_rb_cntl);
> >
> >   		/* set rptr, wptr to 0 */
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* RE: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config
       [not found]     ` <d2e841e5-8c65-c46b-1346-d3cc96584f61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2019-03-06 11:54       ` Zhou, David(ChunMing)
@ 2019-03-06 16:10       ` Zeng, Oak
  1 sibling, 0 replies; 6+ messages in thread
From: Zeng, Oak @ 2019-03-06 16:10 UTC (permalink / raw)
  To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 2841 bytes --]

Copied register definitions below. I guess with this change, you changed how the IH block treat new interrupt when ring is full. Before this change, IH keep new interrupt in the ring and overwrite oldest interrupt. After your change, IH will simply drop new interrupt and keep old interrupt in the ring (keep wptr unchanged).



Is above understanding correct? If yes, can you explain why the new scheme is more reliable? If this is more reliable, should we use this scheme for all 3 interrupt ring?


RB_FULL_DRAIN_ENABLE

9

0x0

When Ring Buffer is full, this enables draining of interrupts to prevent back pressure to IH clients.
 POSSIBLE VALUES:
      00 - Disable

WPTR_OVERFLOW_ENABLE

16

0x1

Ring Buffer write pointer overflow.
 POSSIBLE VALUES:
      00 - Disable
      01 - Enable






Regards,

Oak



-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Christian König
Sent: Wednesday, March 6, 2019 4:29 AM
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config



Ping? Can anybody review this?



Thanks,

Christian.



Am 04.03.19 um 20:10 schrieb Christian König:

> Disable overflow and enable full drain. This makes fault handling on

> ring 1 much more reliable since we don't generate back pressure any more.

>

> Signed-off-by: Christian König <christian.koenig@amd.com<mailto:christian.koenig@amd.com>>

> ---

>   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++

>   1 file changed, 4 insertions(+)

>

> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> index 6d1f804277f8..d4a3cc413af8 100644

> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct

> amdgpu_device *adev)

>

>                            ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

>                            ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);

> +                         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

> +                                                                         WPTR_OVERFLOW_ENABLE, 0);

> +                         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

> +                                                                         RB_FULL_DRAIN_ENABLE, 1);

>                            WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

>

>                            /* set rptr, wptr to 0 */



_______________________________________________

amd-gfx mailing list

amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>

https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[-- Attachment #1.2: Type: text/html, Size: 11009 bytes --]

[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-03-06 16:10 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-04 19:10 [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config Christian König
     [not found] ` <20190304191027.1792-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2019-03-04 19:10   ` [PATCH 2/3] drm/amdgpu: enable IH doorbell for ring 1&2 on Vega Christian König
2019-03-04 19:10   ` [PATCH 3/3] drm/amdgpu: enable IH ring 1&2 for Vega20 as well Christian König
2019-03-06  9:28   ` [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config Christian König
     [not found]     ` <d2e841e5-8c65-c46b-1346-d3cc96584f61-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-03-06 11:54       ` Zhou, David(ChunMing)
2019-03-06 16:10       ` Zeng, Oak

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.