* [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
@ 2019-05-06 11:58 ` Sameer Pujar
0 siblings, 0 replies; 12+ messages in thread
From: Sameer Pujar @ 2019-05-06 11:58 UTC (permalink / raw)
To: thierry.reding, jonathanh, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel, Sameer Pujar
Add DT nodes for following devices on Tegra186 and Tegra194
* ACONNECT
* ADMA
* AGIC
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
2 files changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6e2b6ce..2c432c9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1153,4 +1153,71 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
+
+ aconnect@2a41000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA186_CLK_APE>,
+ <&bpmp TEGRA186_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ dma@2930000 {
+ compatible = "nvidia,tegra186-adma";
+ reg = <0x0 0x02930000 0x0 0x50000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA186_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: agic@2a41000 {
+ compatible = "nvidia,tegra210-agic";
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ reg = <0x0 0x02a41000 0x0 0x1000>,
+ <0x0 0x02a42000 0x0 0x1000>;
+ interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA186_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c77ca21..dcab504 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1054,4 +1054,71 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
+
+ aconnect@2a41000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA194_CLK_APE>,
+ <&bpmp TEGRA194_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ dma@2930000 {
+ compatible = "nvidia,tegra186-adma";
+ reg = <0x0 0x02930000 0x0 0x50000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA194_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: agic@2a41000 {
+ compatible = "nvidia,tegra210-agic";
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ reg = <0x0 0x02a41000 0x0 0x1000>,
+ <0x0 0x02a42000 0x0 0x1000>;
+ interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA194_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
@ 2019-05-06 11:58 ` Sameer Pujar
0 siblings, 0 replies; 12+ messages in thread
From: Sameer Pujar @ 2019-05-06 11:58 UTC (permalink / raw)
To: thierry.reding, jonathanh, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel, Sameer Pujar
Add DT nodes for following devices on Tegra186 and Tegra194
* ACONNECT
* ADMA
* AGIC
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
2 files changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6e2b6ce..2c432c9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1153,4 +1153,71 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
+
+ aconnect@2a41000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA186_CLK_APE>,
+ <&bpmp TEGRA186_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ dma@2930000 {
+ compatible = "nvidia,tegra186-adma";
+ reg = <0x0 0x02930000 0x0 0x50000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA186_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: agic@2a41000 {
+ compatible = "nvidia,tegra210-agic";
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ reg = <0x0 0x02a41000 0x0 0x1000>,
+ <0x0 0x02a42000 0x0 0x1000>;
+ interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA186_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c77ca21..dcab504 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1054,4 +1054,71 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
+
+ aconnect@2a41000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&bpmp TEGRA194_CLK_APE>,
+ <&bpmp TEGRA194_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ dma@2930000 {
+ compatible = "nvidia,tegra186-adma";
+ reg = <0x0 0x02930000 0x0 0x50000>;
+ interrupt-parent = <&agic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ clocks = <&bpmp TEGRA194_CLK_AHUB>;
+ clock-names = "d_audio";
+ status = "disabled";
+ };
+
+ agic: agic@2a41000 {
+ compatible = "nvidia,tegra210-agic";
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ reg = <0x0 0x02a41000 0x0 0x1000>,
+ <0x0 0x02a42000 0x0 0x1000>;
+ interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&bpmp TEGRA194_CLK_APE>;
+ clock-names = "clk";
+ status = "disabled";
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC
2019-05-06 11:58 ` Sameer Pujar
@ 2019-05-06 11:58 ` Sameer Pujar
-1 siblings, 0 replies; 12+ messages in thread
From: Sameer Pujar @ 2019-05-06 11:58 UTC (permalink / raw)
To: thierry.reding, jonathanh, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel, Sameer Pujar
Enable ACONNECT, ADMA and AGIC devices for following platforms
* Jetson TX2
* Jetson Xavier
Verified driver probe path and devices get registered fine.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 31457f3..21e73db 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -183,4 +183,16 @@
vin-supply = <&vdd_5v0_sys>;
};
};
+
+ aconnect@2a41000 {
+ status = "okay";
+
+ dma@2930000 {
+ status = "okay";
+ };
+
+ agic@2a41000 {
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index b62e969..bca28fc 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -169,4 +169,16 @@
};
};
};
+
+ aconnect@2a41000 {
+ status = "okay";
+
+ dma@2930000 {
+ status = "okay";
+ };
+
+ agic@2a41000 {
+ status = "okay";
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC
@ 2019-05-06 11:58 ` Sameer Pujar
0 siblings, 0 replies; 12+ messages in thread
From: Sameer Pujar @ 2019-05-06 11:58 UTC (permalink / raw)
To: thierry.reding, jonathanh, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel, Sameer Pujar
Enable ACONNECT, ADMA and AGIC devices for following platforms
* Jetson TX2
* Jetson Xavier
Verified driver probe path and devices get registered fine.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 12 ++++++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 31457f3..21e73db 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -183,4 +183,16 @@
vin-supply = <&vdd_5v0_sys>;
};
};
+
+ aconnect@2a41000 {
+ status = "okay";
+
+ dma@2930000 {
+ status = "okay";
+ };
+
+ agic@2a41000 {
+ status = "okay";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index b62e969..bca28fc 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -169,4 +169,16 @@
};
};
};
+
+ aconnect@2a41000 {
+ status = "okay";
+
+ dma@2930000 {
+ status = "okay";
+ };
+
+ agic@2a41000 {
+ status = "okay";
+ };
+ };
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
2019-05-06 11:58 ` Sameer Pujar
@ 2019-06-04 9:07 ` Jon Hunter
-1 siblings, 0 replies; 12+ messages in thread
From: Jon Hunter @ 2019-06-04 9:07 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 06/05/2019 12:58, Sameer Pujar wrote:
> Add DT nodes for following devices on Tegra186 and Tegra194
> * ACONNECT
> * ADMA
> * AGIC
>
> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
> 2 files changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 6e2b6ce..2c432c9 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -1153,4 +1153,71 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + aconnect@2a41000 {
> + compatible = "nvidia,tegra210-aconnect";
> + clocks = <&bpmp TEGRA186_CLK_APE>,
> + <&bpmp TEGRA186_CLK_APB2APE>;
> + clock-names = "ape", "apb2ape";
> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
My recollection is that non-empty range is preferred from what Rob told
me in the past. See the Tegra210 binding.
> + status = "disabled";
> +
> + dma@2930000 {
Although I did not do this for Tegra210, I think that the preferred
convention is 'dma-controller@xxxxxxxxx'.
> + compatible = "nvidia,tegra186-adma";
> + reg = <0x0 0x02930000 0x0 0x50000>;
> + interrupt-parent = <&agic>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> + #dma-cells = <1>;
> + clocks = <&bpmp TEGRA186_CLK_AHUB>;
> + clock-names = "d_audio";
> + status = "disabled";
> + };
> +
> + agic: agic@2a41000 {
> + compatible = "nvidia,tegra210-agic";
> + #interrupt-cells = <4>;
Why 4? This does not match the binding document for the arm-gic.
> + interrupt-controller;
> + reg = <0x0 0x02a41000 0x0 0x1000>,
> + <0x0 0x02a42000 0x0 0x1000>;
I believe that the 2nd address range should have size 0x2000 for the CPU
interfaces.
> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = <&bpmp TEGRA186_CLK_APE>;
> + clock-names = "clk";
> + status = "disabled";
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index c77ca21..dcab504 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1054,4 +1054,71 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + aconnect@2a41000 {
> + compatible = "nvidia,tegra210-aconnect";
> + clocks = <&bpmp TEGRA194_CLK_APE>,
> + <&bpmp TEGRA194_CLK_APB2APE>;
> + clock-names = "ape", "apb2ape";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Same as above.
> + status = "disabled";
> +
> + dma@2930000 {
Same as above.
> + compatible = "nvidia,tegra186-adma";
> + reg = <0x0 0x02930000 0x0 0x50000>;
> + interrupt-parent = <&agic>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> + #dma-cells = <1>;
> + clocks = <&bpmp TEGRA194_CLK_AHUB>;
> + clock-names = "d_audio";
> + status = "disabled";
> + };
> +
> + agic: agic@2a41000 {
> + compatible = "nvidia,tegra210-agic";
> + #interrupt-cells = <4>;
Same as above.
> + interrupt-controller;
> + reg = <0x0 0x02a41000 0x0 0x1000>,
> + <0x0 0x02a42000 0x0 0x1000>;
Same as above.
> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = <&bpmp TEGRA194_CLK_APE>;
> + clock-names = "clk";
> + status = "disabled";
> + };
> + };
> };
>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
@ 2019-06-04 9:07 ` Jon Hunter
0 siblings, 0 replies; 12+ messages in thread
From: Jon Hunter @ 2019-06-04 9:07 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 06/05/2019 12:58, Sameer Pujar wrote:
> Add DT nodes for following devices on Tegra186 and Tegra194
> * ACONNECT
> * ADMA
> * AGIC
>
> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
> 2 files changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 6e2b6ce..2c432c9 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -1153,4 +1153,71 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + aconnect@2a41000 {
> + compatible = "nvidia,tegra210-aconnect";
> + clocks = <&bpmp TEGRA186_CLK_APE>,
> + <&bpmp TEGRA186_CLK_APB2APE>;
> + clock-names = "ape", "apb2ape";
> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
My recollection is that non-empty range is preferred from what Rob told
me in the past. See the Tegra210 binding.
> + status = "disabled";
> +
> + dma@2930000 {
Although I did not do this for Tegra210, I think that the preferred
convention is 'dma-controller@xxxxxxxxx'.
> + compatible = "nvidia,tegra186-adma";
> + reg = <0x0 0x02930000 0x0 0x50000>;
> + interrupt-parent = <&agic>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> + #dma-cells = <1>;
> + clocks = <&bpmp TEGRA186_CLK_AHUB>;
> + clock-names = "d_audio";
> + status = "disabled";
> + };
> +
> + agic: agic@2a41000 {
> + compatible = "nvidia,tegra210-agic";
> + #interrupt-cells = <4>;
Why 4? This does not match the binding document for the arm-gic.
> + interrupt-controller;
> + reg = <0x0 0x02a41000 0x0 0x1000>,
> + <0x0 0x02a42000 0x0 0x1000>;
I believe that the 2nd address range should have size 0x2000 for the CPU
interfaces.
> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = <&bpmp TEGRA186_CLK_APE>;
> + clock-names = "clk";
> + status = "disabled";
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index c77ca21..dcab504 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1054,4 +1054,71 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> interrupt-parent = <&gic>;
> };
> +
> + aconnect@2a41000 {
> + compatible = "nvidia,tegra210-aconnect";
> + clocks = <&bpmp TEGRA194_CLK_APE>,
> + <&bpmp TEGRA194_CLK_APB2APE>;
> + clock-names = "ape", "apb2ape";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Same as above.
> + status = "disabled";
> +
> + dma@2930000 {
Same as above.
> + compatible = "nvidia,tegra186-adma";
> + reg = <0x0 0x02930000 0x0 0x50000>;
> + interrupt-parent = <&agic>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> + #dma-cells = <1>;
> + clocks = <&bpmp TEGRA194_CLK_AHUB>;
> + clock-names = "d_audio";
> + status = "disabled";
> + };
> +
> + agic: agic@2a41000 {
> + compatible = "nvidia,tegra210-agic";
> + #interrupt-cells = <4>;
Same as above.
> + interrupt-controller;
> + reg = <0x0 0x02a41000 0x0 0x1000>,
> + <0x0 0x02a42000 0x0 0x1000>;
Same as above.
> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = <&bpmp TEGRA194_CLK_APE>;
> + clock-names = "clk";
> + status = "disabled";
> + };
> + };
> };
>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC
2019-05-06 11:58 ` Sameer Pujar
@ 2019-06-04 9:08 ` Jon Hunter
-1 siblings, 0 replies; 12+ messages in thread
From: Jon Hunter @ 2019-06-04 9:08 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 06/05/2019 12:58, Sameer Pujar wrote:
> Enable ACONNECT, ADMA and AGIC devices for following platforms
> * Jetson TX2
> * Jetson Xavier
>
> Verified driver probe path and devices get registered fine.
>
> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 12 ++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> index 31457f3..21e73db 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> @@ -183,4 +183,16 @@
> vin-supply = <&vdd_5v0_sys>;
> };
> };
> +
> + aconnect@2a41000 {
> + status = "okay";
> +
> + dma@2930000 {
> + status = "okay";
> + };
> +
> + agic@2a41000 {
> + status = "okay";
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> index b62e969..bca28fc 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> @@ -169,4 +169,16 @@
> };
> };
> };
> +
> + aconnect@2a41000 {
> + status = "okay";
> +
> + dma@2930000 {
> + status = "okay";
> + };
> +
> + agic@2a41000 {
> + status = "okay";
> + };
> + };
> };
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC
@ 2019-06-04 9:08 ` Jon Hunter
0 siblings, 0 replies; 12+ messages in thread
From: Jon Hunter @ 2019-06-04 9:08 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 06/05/2019 12:58, Sameer Pujar wrote:
> Enable ACONNECT, ADMA and AGIC devices for following platforms
> * Jetson TX2
> * Jetson Xavier
>
> Verified driver probe path and devices get registered fine.
>
> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++
> arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 12 ++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> index 31457f3..21e73db 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
> @@ -183,4 +183,16 @@
> vin-supply = <&vdd_5v0_sys>;
> };
> };
> +
> + aconnect@2a41000 {
> + status = "okay";
> +
> + dma@2930000 {
> + status = "okay";
> + };
> +
> + agic@2a41000 {
> + status = "okay";
> + };
> + };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> index b62e969..bca28fc 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
> @@ -169,4 +169,16 @@
> };
> };
> };
> +
> + aconnect@2a41000 {
> + status = "okay";
> +
> + dma@2930000 {
> + status = "okay";
> + };
> +
> + agic@2a41000 {
> + status = "okay";
> + };
> + };
> };
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
2019-06-04 9:07 ` Jon Hunter
@ 2019-06-06 5:58 ` Sameer Pujar
-1 siblings, 0 replies; 12+ messages in thread
From: Sameer Pujar @ 2019-06-06 5:58 UTC (permalink / raw)
To: Jon Hunter, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 6/4/2019 2:37 PM, Jon Hunter wrote:
> On 06/05/2019 12:58, Sameer Pujar wrote:
>> Add DT nodes for following devices on Tegra186 and Tegra194
>> * ACONNECT
>> * ADMA
>> * AGIC
>>
>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>> ---
>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
>> 2 files changed, 134 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> index 6e2b6ce..2c432c9 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> @@ -1153,4 +1153,71 @@
>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> interrupt-parent = <&gic>;
>> };
>> +
>> + aconnect@2a41000 {
>> + compatible = "nvidia,tegra210-aconnect";
>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>> + <&bpmp TEGRA186_CLK_APB2APE>;
>> + clock-names = "ape", "apb2ape";
>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
> My recollection is that non-empty range is preferred from what Rob told
> me in the past. See the Tegra210 binding.
I see at various places empty ranges property is used. From DT spec, it
means
there is no translation in the address space between parent/child.
Also I looked at Tegra210 binding,
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
Should it be encoded as a triplet(child addr, parent addr, length)?
>
>> + status = "disabled";
>> +
>> + dma@2930000 {
> Although I did not do this for Tegra210, I think that the preferred
> convention is 'dma-controller@xxxxxxxxx'.
done.
>> + compatible = "nvidia,tegra186-adma";
>> + reg = <0x0 0x02930000 0x0 0x50000>;
>> + interrupt-parent = <&agic>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> + #dma-cells = <1>;
>> + clocks = <&bpmp TEGRA186_CLK_AHUB>;
>> + clock-names = "d_audio";
>> + status = "disabled";
>> + };
>> +
>> + agic: agic@2a41000 {
>> + compatible = "nvidia,tegra210-agic";
>> + #interrupt-cells = <4>;
> Why 4? This does not match the binding document for the arm-gic.
will fix.
>> + interrupt-controller;
>> + reg = <0x0 0x02a41000 0x0 0x1000>,
>> + <0x0 0x02a42000 0x0 0x1000>;
> I believe that the 2nd address range should have size 0x2000 for the CPU
> interfaces.
done
>> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_HIGH)>;
>> + clocks = <&bpmp TEGRA186_CLK_APE>;
>> + clock-names = "clk";
>> + status = "disabled";
>> + };
>> + };
>> };
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> index c77ca21..dcab504 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> @@ -1054,4 +1054,71 @@
>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> interrupt-parent = <&gic>;
>> };
>> +
>> + aconnect@2a41000 {
>> + compatible = "nvidia,tegra210-aconnect";
>> + clocks = <&bpmp TEGRA194_CLK_APE>,
>> + <&bpmp TEGRA194_CLK_APB2APE>;
>> + clock-names = "ape", "apb2ape";
>> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
> Same as above.
>
>> + status = "disabled";
>> +
>> + dma@2930000 {
> Same as above.
>
>> + compatible = "nvidia,tegra186-adma";
>> + reg = <0x0 0x02930000 0x0 0x50000>;
>> + interrupt-parent = <&agic>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> + #dma-cells = <1>;
>> + clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> + clock-names = "d_audio";
>> + status = "disabled";
>> + };
>> +
>> + agic: agic@2a41000 {
>> + compatible = "nvidia,tegra210-agic";
>> + #interrupt-cells = <4>;
> Same as above.
>
>> + interrupt-controller;
>> + reg = <0x0 0x02a41000 0x0 0x1000>,
>> + <0x0 0x02a42000 0x0 0x1000>;
> Same as above.
>
>> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_HIGH)>;
>> + clocks = <&bpmp TEGRA194_CLK_APE>;
>> + clock-names = "clk";
>> + status = "disabled";
>> + };
>> + };
>> };
>>
> Cheers
> Jon
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
@ 2019-06-06 5:58 ` Sameer Pujar
0 siblings, 0 replies; 12+ messages in thread
From: Sameer Pujar @ 2019-06-06 5:58 UTC (permalink / raw)
To: Jon Hunter, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 6/4/2019 2:37 PM, Jon Hunter wrote:
> On 06/05/2019 12:58, Sameer Pujar wrote:
>> Add DT nodes for following devices on Tegra186 and Tegra194
>> * ACONNECT
>> * ADMA
>> * AGIC
>>
>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>> ---
>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67 ++++++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67 ++++++++++++++++++++++++++++++++
>> 2 files changed, 134 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> index 6e2b6ce..2c432c9 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>> @@ -1153,4 +1153,71 @@
>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> interrupt-parent = <&gic>;
>> };
>> +
>> + aconnect@2a41000 {
>> + compatible = "nvidia,tegra210-aconnect";
>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>> + <&bpmp TEGRA186_CLK_APB2APE>;
>> + clock-names = "ape", "apb2ape";
>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
> My recollection is that non-empty range is preferred from what Rob told
> me in the past. See the Tegra210 binding.
I see at various places empty ranges property is used. From DT spec, it
means
there is no translation in the address space between parent/child.
Also I looked at Tegra210 binding,
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
Should it be encoded as a triplet(child addr, parent addr, length)?
>
>> + status = "disabled";
>> +
>> + dma@2930000 {
> Although I did not do this for Tegra210, I think that the preferred
> convention is 'dma-controller@xxxxxxxxx'.
done.
>> + compatible = "nvidia,tegra186-adma";
>> + reg = <0x0 0x02930000 0x0 0x50000>;
>> + interrupt-parent = <&agic>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> + #dma-cells = <1>;
>> + clocks = <&bpmp TEGRA186_CLK_AHUB>;
>> + clock-names = "d_audio";
>> + status = "disabled";
>> + };
>> +
>> + agic: agic@2a41000 {
>> + compatible = "nvidia,tegra210-agic";
>> + #interrupt-cells = <4>;
> Why 4? This does not match the binding document for the arm-gic.
will fix.
>> + interrupt-controller;
>> + reg = <0x0 0x02a41000 0x0 0x1000>,
>> + <0x0 0x02a42000 0x0 0x1000>;
> I believe that the 2nd address range should have size 0x2000 for the CPU
> interfaces.
done
>> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_HIGH)>;
>> + clocks = <&bpmp TEGRA186_CLK_APE>;
>> + clock-names = "clk";
>> + status = "disabled";
>> + };
>> + };
>> };
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> index c77ca21..dcab504 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> @@ -1054,4 +1054,71 @@
>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> interrupt-parent = <&gic>;
>> };
>> +
>> + aconnect@2a41000 {
>> + compatible = "nvidia,tegra210-aconnect";
>> + clocks = <&bpmp TEGRA194_CLK_APE>,
>> + <&bpmp TEGRA194_CLK_APB2APE>;
>> + clock-names = "ape", "apb2ape";
>> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
> Same as above.
>
>> + status = "disabled";
>> +
>> + dma@2930000 {
> Same as above.
>
>> + compatible = "nvidia,tegra186-adma";
>> + reg = <0x0 0x02930000 0x0 0x50000>;
>> + interrupt-parent = <&agic>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
>> + #dma-cells = <1>;
>> + clocks = <&bpmp TEGRA194_CLK_AHUB>;
>> + clock-names = "d_audio";
>> + status = "disabled";
>> + };
>> +
>> + agic: agic@2a41000 {
>> + compatible = "nvidia,tegra210-agic";
>> + #interrupt-cells = <4>;
> Same as above.
>
>> + interrupt-controller;
>> + reg = <0x0 0x02a41000 0x0 0x1000>,
>> + <0x0 0x02a42000 0x0 0x1000>;
> Same as above.
>
>> + interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) |
>> + IRQ_TYPE_LEVEL_HIGH)>;
>> + clocks = <&bpmp TEGRA194_CLK_APE>;
>> + clock-names = "clk";
>> + status = "disabled";
>> + };
>> + };
>> };
>>
> Cheers
> Jon
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
2019-06-06 5:58 ` Sameer Pujar
@ 2019-06-06 7:06 ` Jon Hunter
-1 siblings, 0 replies; 12+ messages in thread
From: Jon Hunter @ 2019-06-06 7:06 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 06/06/2019 06:58, Sameer Pujar wrote:
>
> On 6/4/2019 2:37 PM, Jon Hunter wrote:
>> On 06/05/2019 12:58, Sameer Pujar wrote:
>>> Add DT nodes for following devices on Tegra186 and Tegra194
>>> * ACONNECT
>>> * ADMA
>>> * AGIC
>>>
>>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>>> ---
>>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> 2 files changed, 134 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> index 6e2b6ce..2c432c9 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> @@ -1153,4 +1153,71 @@
>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>> interrupt-parent = <&gic>;
>>> };
>>> +
>>> + aconnect@2a41000 {
>>> + compatible = "nvidia,tegra210-aconnect";
>>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>>> + <&bpmp TEGRA186_CLK_APB2APE>;
>>> + clock-names = "ape", "apb2ape";
>>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>> My recollection is that non-empty range is preferred from what Rob told
>> me in the past. See the Tegra210 binding.
> I see at various places empty ranges property is used. From DT spec, it
> means
> there is no translation in the address space between parent/child.
Yes that is correct, but this is what Rob told me in the past ...
"Use of non-empty ranges is preferred though there is not much benefit
if the parent and child sizes are the same. However, it does also
limit what is a valid address for those child nodes."
So I think it is best to be consistent.
> Also I looked at Tegra210 binding,
> ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
> Should it be encoded as a triplet(child addr, parent addr, length)?
Right but remember the parent address is 2 cells, hence the 4 values.
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes
@ 2019-06-06 7:06 ` Jon Hunter
0 siblings, 0 replies; 12+ messages in thread
From: Jon Hunter @ 2019-06-06 7:06 UTC (permalink / raw)
To: Sameer Pujar, thierry.reding, robh+dt, mark.rutland
Cc: devicetree, linux-tegra, linux-kernel
On 06/06/2019 06:58, Sameer Pujar wrote:
>
> On 6/4/2019 2:37 PM, Jon Hunter wrote:
>> On 06/05/2019 12:58, Sameer Pujar wrote:
>>> Add DT nodes for following devices on Tegra186 and Tegra194
>>> * ACONNECT
>>> * ADMA
>>> * AGIC
>>>
>>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>>> ---
>>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>> 2 files changed, 134 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> index 6e2b6ce..2c432c9 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> @@ -1153,4 +1153,71 @@
>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>> interrupt-parent = <&gic>;
>>> };
>>> +
>>> + aconnect@2a41000 {
>>> + compatible = "nvidia,tegra210-aconnect";
>>> + clocks = <&bpmp TEGRA186_CLK_APE>,
>>> + <&bpmp TEGRA186_CLK_APB2APE>;
>>> + clock-names = "ape", "apb2ape";
>>> + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>> My recollection is that non-empty range is preferred from what Rob told
>> me in the past. See the Tegra210 binding.
> I see at various places empty ranges property is used. From DT spec, it
> means
> there is no translation in the address space between parent/child.
Yes that is correct, but this is what Rob told me in the past ...
"Use of non-empty ranges is preferred though there is not much benefit
if the parent and child sizes are the same. However, it does also
limit what is a valid address for those child nodes."
So I think it is best to be consistent.
> Also I looked at Tegra210 binding,
> ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
> Should it be encoded as a triplet(child addr, parent addr, length)?
Right but remember the parent address is 2 cells, hence the 4 values.
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-06-06 7:07 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-06 11:58 [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Sameer Pujar
2019-05-06 11:58 ` Sameer Pujar
2019-05-06 11:58 ` [PATCH 2/2] arm64: tegra: enable ACONNECT, ADMA and AGIC Sameer Pujar
2019-05-06 11:58 ` Sameer Pujar
2019-06-04 9:08 ` Jon Hunter
2019-06-04 9:08 ` Jon Hunter
2019-06-04 9:07 ` [PATCH 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes Jon Hunter
2019-06-04 9:07 ` Jon Hunter
2019-06-06 5:58 ` Sameer Pujar
2019-06-06 5:58 ` Sameer Pujar
2019-06-06 7:06 ` Jon Hunter
2019-06-06 7:06 ` Jon Hunter
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