[Intel-gfx] [PATCH 0/3] drm/i915/dg2: 5th Display output

All of lore.kernel.org
 help / color / mirror / Atom feed

* [Intel-gfx] [PATCH 0/3] drm/i915/dg2: 5th Display output
@ 2022-02-15  5:51 ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel

Fixing the 5th Display output for DG2.

Jouni Högander (1):
  drm/i915: Fix for PHY_MISC_TC1 offset

Matt Roper (2):
  drm/i915/dg2: Enable 5th display
  drm/i915/dg2: Drop 38.4 MHz MPLLB tables

 drivers/gpu/drm/i915/display/intel_gmbus.c    |  16 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 210 +-----------------
 drivers/gpu/drm/i915/i915_irq.c               |   5 +-
 drivers/gpu/drm/i915/i915_reg.h               |   7 +-
 4 files changed, 25 insertions(+), 213 deletions(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH 0/3] drm/i915/dg2: 5th Display output
@ 2022-02-15  5:51 ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Shankar Uma

Fixing the 5th Display output for DG2.

Jouni Högander (1):
  drm/i915: Fix for PHY_MISC_TC1 offset

Matt Roper (2):
  drm/i915/dg2: Enable 5th display
  drm/i915/dg2: Drop 38.4 MHz MPLLB tables

 drivers/gpu/drm/i915/display/intel_gmbus.c    |  16 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 210 +-----------------
 drivers/gpu/drm/i915/i915_irq.c               |   5 +-
 drivers/gpu/drm/i915/i915_reg.h               |   7 +-
 4 files changed, 25 insertions(+), 213 deletions(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] [PATCH 1/3] drm/i915/dg2: Enable 5th display
  2022-02-15  5:51 ` Ramalingam C
@ 2022-02-15  5:51   ` Ramalingam C
  -1 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Lucas De Marchi

From: Matt Roper <matthew.d.roper@intel.com>

DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output.  This behaves similarly to the TC1
on past platforms with just a couple minor differences:

 * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
   ICP/TGP/ADP.
 * DG2 doesn't need the hpd inversion setting that we had to use on DG1

Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
 drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
 drivers/gpu/drm/i915/i915_reg.h            |  1 +
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975..2fad03250661 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 };
 
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		return &gmbus_pins_dg2[pin];
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		return &gmbus_pins_dg1[pin];
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		return &gmbus_pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		size = ARRAY_SIZE(gmbus_pins_dg2);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		size = ARRAY_SIZE(gmbus_pins_dg1);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a16..4d81063b128c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->hotplug_funcs = &i915_hpd_funcs;
 	} else {
-		if (HAS_PCH_DG1(dev_priv))
+		if (HAS_PCH_DG2(dev_priv))
+			dev_priv->hotplug_funcs = &icp_hpd_funcs;
+		else if (HAS_PCH_DG1(dev_priv))
 			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
 		else if (DISPLAY_VER(dev_priv) >= 11)
 			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ea1713e6b60..4d12abb2d7ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6182,6 +6182,7 @@
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 1/3] drm/i915/dg2: Enable 5th display
@ 2022-02-15  5:51   ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: Swathi Dhanavanthri, Lucas De Marchi, José Roberto de Souza,
	Shankar Uma

From: Matt Roper <matthew.d.roper@intel.com>

DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output.  This behaves similarly to the TC1
on past platforms with just a couple minor differences:

 * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
   ICP/TGP/ADP.
 * DG2 doesn't need the hpd inversion setting that we had to use on DG1

Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
 drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
 drivers/gpu/drm/i915/i915_reg.h            |  1 +
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975..2fad03250661 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 };
 
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		return &gmbus_pins_dg2[pin];
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		return &gmbus_pins_dg1[pin];
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		return &gmbus_pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		size = ARRAY_SIZE(gmbus_pins_dg2);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		size = ARRAY_SIZE(gmbus_pins_dg1);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a16..4d81063b128c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->hotplug_funcs = &i915_hpd_funcs;
 	} else {
-		if (HAS_PCH_DG1(dev_priv))
+		if (HAS_PCH_DG2(dev_priv))
+			dev_priv->hotplug_funcs = &icp_hpd_funcs;
+		else if (HAS_PCH_DG1(dev_priv))
 			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
 		else if (DISPLAY_VER(dev_priv) >= 11)
 			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ea1713e6b60..4d12abb2d7ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6182,6 +6182,7 @@
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
  2022-02-15  5:51 ` Ramalingam C
@ 2022-02-15  5:51   ` Ramalingam C
  -1 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: Anusha Srivatsa, José Roberto de Souza, Shankar Uma

From: Matt Roper <matthew.d.roper@intel.com>

Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-----------------
 1 file changed, 1 insertion(+), 207 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 8573a458811a..c60575cb5368 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
 	NULL,
 };
 
-/*
- * Basic DP link rates with 38.4 MHz reference clock.
- */
-
-static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
-	.clock = 162000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
-	.clock = 270000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
-	.clock = 540000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
-	.clock = 810000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
-};
-
-static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
-	.clock = 1000000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
-
-	/*
-	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
-	 */
-	.mpllb_sscen =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
-	.mpllb_sscstep =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
-};
-
-static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
-	.clock = 1350000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
-
-	/*
-	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
-	 */
-	.mpllb_sscen =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
-	.mpllb_sscstep =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
-};
-
-static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
-	&dg2_dp_rbr_38_4,
-	&dg2_dp_hbr1_38_4,
-	&dg2_dp_hbr2_38_4,
-	&dg2_dp_hbr3_38_4,
-	&dg2_dp_uhbr10_38_4,
-	&dg2_dp_uhbr13_38_4,
-	NULL,
-};
-
 /*
  * eDP link rates with 100 MHz reference clock.
  */
@@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		return dg2_edp_tables;
 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
-		/*
-		 * FIXME: Initially we're just enabling the "combo" outputs on
-		 * port A-D.  The MPLLB for those ports takes an input from the
-		 * "Display Filter PLL" which always has an output frequency
-		 * of 100 MHz, hence the use of the _100 tables below.
-		 *
-		 * Once we enable port TC1 it will either use the same 100 MHz
-		 * "Display Filter PLL" (when strapped to support a native
-		 * display connection) or different 38.4 MHz "Filter PLL" when
-		 * strapped to support a USB connection, so we'll need to check
-		 * that to determine which table to use.
-		 */
-		if (0)
-			return dg2_dp_38_4_tables;
-		else
-			return dg2_dp_100_tables;
+		return dg2_dp_100_tables;
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 		return dg2_hdmi_tables;
 	}
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
@ 2022-02-15  5:51   ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel

From: Matt Roper <matthew.d.roper@intel.com>

Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-----------------
 1 file changed, 1 insertion(+), 207 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 8573a458811a..c60575cb5368 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
 	NULL,
 };
 
-/*
- * Basic DP link rates with 38.4 MHz reference clock.
- */
-
-static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
-	.clock = 162000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
-	.clock = 270000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
-	.clock = 540000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
-	.clock = 810000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
-};
-
-static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
-	.clock = 1000000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
-
-	/*
-	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
-	 */
-	.mpllb_sscen =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
-	.mpllb_sscstep =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
-};
-
-static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
-	.clock = 1350000,
-	.ref_control =
-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
-	.mpllb_cp =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
-	.mpllb_div =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
-	.mpllb_div2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
-	.mpllb_fracn1 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
-	.mpllb_fracn2 =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
-
-	/*
-	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
-	 */
-	.mpllb_sscen =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
-	.mpllb_sscstep =
-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
-};
-
-static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
-	&dg2_dp_rbr_38_4,
-	&dg2_dp_hbr1_38_4,
-	&dg2_dp_hbr2_38_4,
-	&dg2_dp_hbr3_38_4,
-	&dg2_dp_uhbr10_38_4,
-	&dg2_dp_uhbr13_38_4,
-	NULL,
-};
-
 /*
  * eDP link rates with 100 MHz reference clock.
  */
@@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		return dg2_edp_tables;
 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
-		/*
-		 * FIXME: Initially we're just enabling the "combo" outputs on
-		 * port A-D.  The MPLLB for those ports takes an input from the
-		 * "Display Filter PLL" which always has an output frequency
-		 * of 100 MHz, hence the use of the _100 tables below.
-		 *
-		 * Once we enable port TC1 it will either use the same 100 MHz
-		 * "Display Filter PLL" (when strapped to support a native
-		 * display connection) or different 38.4 MHz "Filter PLL" when
-		 * strapped to support a USB connection, so we'll need to check
-		 * that to determine which table to use.
-		 */
-		if (0)
-			return dg2_dp_38_4_tables;
-		else
-			return dg2_dp_100_tables;
+		return dg2_dp_100_tables;
 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 		return dg2_hdmi_tables;
 	}
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-15  5:51 ` Ramalingam C
@ 2022-02-15  5:51   ` Ramalingam C
  -1 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Jouni Högander, Shankar Uma

From: Jouni Högander <jouni.hogander@intel.com>

Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
port. Correct offset is 0x64C14.

Fix this by handling PHY_E port seprately.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index c60575cb5368..f08061c748b3 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
 		if (!intel_phy_is_snps(i915, phy))
 			continue;
 
-		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
+		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
 					    DG2_PHY_DP_TX_ACK_MASK, 25))
 			drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
 				phy);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d12abb2d7ff..354c25f483cb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9559,8 +9559,10 @@ enum skl_power_gate {
 
 #define _ICL_PHY_MISC_A		0x64C00
 #define _ICL_PHY_MISC_B		0x64C04
-#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
-						 _ICL_PHY_MISC_B)
+#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+				 ICL_PHY_MISC(port))
 #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
 #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-15  5:51   ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-15  5:51 UTC (permalink / raw)
  To: intel-gfx, dri-devel

From: Jouni Högander <jouni.hogander@intel.com>

Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
port. Correct offset is 0x64C14.

Fix this by handling PHY_E port seprately.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index c60575cb5368..f08061c748b3 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
 		if (!intel_phy_is_snps(i915, phy))
 			continue;
 
-		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
+		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
 					    DG2_PHY_DP_TX_ACK_MASK, 25))
 			drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
 				phy);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d12abb2d7ff..354c25f483cb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9559,8 +9559,10 @@ enum skl_power_gate {
 
 #define _ICL_PHY_MISC_A		0x64C00
 #define _ICL_PHY_MISC_B		0x64C04
-#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
-						 _ICL_PHY_MISC_B)
+#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+				 ICL_PHY_MISC(port))
 #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
 #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: 5th Display output
  2022-02-15  5:51 ` Ramalingam C
                   ` (3 preceding siblings ...)
  (?)
@ 2022-02-16  5:01 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-16  5:01 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/dg2: 5th Display output
URL   : https://patchwork.freedesktop.org/series/100151/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
29a23013314f drm/i915/dg2: Enable 5th display
f7ec8750ea22 drm/i915/dg2: Drop 38.4 MHz MPLLB tables
6ec3dcb34d04 drm/i915: Fix for PHY_MISC_TC1 offset
-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:9564:
+#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+				 ICL_PHY_MISC(port))

total: 0 errors, 0 warnings, 1 checks, 20 lines checked



^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: 5th Display output
  2022-02-15  5:51 ` Ramalingam C
                   ` (4 preceding siblings ...)
  (?)
@ 2022-02-16  5:02 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-16  5:02 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/dg2: 5th Display output
URL   : https://patchwork.freedesktop.org/series/100151/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: 5th Display output
  2022-02-15  5:51 ` Ramalingam C
                   ` (5 preceding siblings ...)
  (?)
@ 2022-02-16  5:36 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-16  5:36 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 5690 bytes --]

== Series Details ==

Series: drm/i915/dg2: 5th Display output
URL   : https://patchwork.freedesktop.org/series/100151/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11230 -> Patchwork_22277
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22277 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22277, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/index.html

Participating hosts (50 -> 45)
------------------------------

  Missing    (5): shard-tglu fi-bsw-cyan fi-pnv-d510 shard-rkl shard-dg1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22277:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@hangcheck:
    - fi-rkl-guc:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11230/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html

  
Known issues
------------

  Here are the changes found in Patchwork_22277 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-skl-6600u:       NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [PASS][5] -> [DMESG-FAIL][6] ([i915#4528] / [i915#5026])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11230/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-blb-e6850/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@vga-edid-read:
    - fi-skl-6600u:       NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][8] ([fdo#109271]) +21 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6600u:       NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-blb-e6850:       NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-blb-e6850/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-skl-6600u:       [INCOMPLETE][11] ([i915#4547]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11230/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html

  
#### Warnings ####

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [DMESG-FAIL][13] ([i915#4957]) -> [DMESG-FAIL][14] ([i915#4494] / [i915#4957])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11230/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/bat-dg1-6/igt@i915_selftest@live@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11230 -> Patchwork_22277

  CI-20190529: 20190529
  CI_DRM_11230: e3741d576f60e3d0df5b385ba96a08ada3c760af @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6345: ee18c0497ec2c74007e299c3fdd26f1613b9f514 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22277: 6ec3dcb34d04a41a4ccb3d80ef3cbe90927eb429 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6ec3dcb34d04 drm/i915: Fix for PHY_MISC_TC1 offset
f7ec8750ea22 drm/i915/dg2: Drop 38.4 MHz MPLLB tables
29a23013314f drm/i915/dg2: Enable 5th display

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22277/index.html

[-- Attachment #2: Type: text/html, Size: 6928 bytes --]

^ permalink raw reply	[flat|nested] 45+ messages in thread

* RE: [PATCH 1/3] drm/i915/dg2: Enable 5th display
  2022-02-15  5:51   ` Ramalingam C
@ 2022-02-16  8:02     ` Shankar, Uma
  -1 siblings, 0 replies; 45+ messages in thread
From: Shankar, Uma @ 2022-02-16  8:02 UTC (permalink / raw)
  To: C, Ramalingam, intel-gfx, dri-devel
  Cc: Dhanavanthri, Swathi, De Marchi, Lucas, Souza, Jose



> -----Original Message-----
> From: C, Ramalingam <ramalingam.c@intel.com>
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> devel@lists.freedesktop.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>;
> Dhanavanthri, Swathi <swathi.dhanavanthri@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Souza, Jose <jose.souza@intel.com>; C, Ramalingam
> <ramalingam.c@intel.com>
> Subject: [PATCH 1/3] drm/i915/dg2: Enable 5th display
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> DG2 supports a 5th display output which the hardware refers to as "TC1,"
> even though it isn't a Type-C output.  This behaves similarly to the TC1 on past
> platforms with just a couple minor differences:
> 
>  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
>    ICP/TGP/ADP.
>  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> 
> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
>  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
>  drivers/gpu/drm/i915/i915_reg.h            |  1 +
>  3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6ce8c10fe975..2fad03250661 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
>  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
>  };
> 
> +static const struct gmbus_pin gmbus_pins_dg2[] = {
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, };
> +
>  /* pin is expected to be valid */
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
>  					     unsigned int pin)
>  {
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		return &gmbus_pins_dg2[pin];
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		return &gmbus_pins_dg1[pin];
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		return &gmbus_pins_icp[pin];
> @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> *dev_priv,  {
>  	unsigned int size;
> 
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		size = ARRAY_SIZE(gmbus_pins_dg2);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		size = ARRAY_SIZE(gmbus_pins_dg1);
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index
> fdd568ba4a16..4d81063b128c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
>  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
>  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
>  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),

Not sure if this applies to DG1, the 5th TC1 port is only for DG2.  Should we not have a separate
DG2 struct. Can you please clarify to help understand.

Regards,
Uma Shankar

>  };
> 
>  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -4424,7
> +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		if (I915_HAS_HOTPLUG(dev_priv))
>  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
>  	} else {
> -		if (HAS_PCH_DG1(dev_priv))
> +		if (HAS_PCH_DG2(dev_priv))
> +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> +		else if (HAS_PCH_DG1(dev_priv))
>  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
>  		else if (DISPLAY_VER(dev_priv) >= 11)
>  			dev_priv->hotplug_funcs = &gen11_hpd_funcs; diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 4ea1713e6b60..4d12abb2d7ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6182,6 +6182,7 @@
>  /* south display engine interrupt: ICP/TGP */
>  #define SDE_GMBUS_ICP			(1 << 23)
>  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 +
> _HPD_PIN_TC(hpd_pin))
> +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 +
> _HPD_PIN_TC(hpd_pin)) /* sigh */
>  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 +
> _HPD_PIN_DDI(hpd_pin))
>  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
>  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> --
> 2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg2: Enable 5th display
@ 2022-02-16  8:02     ` Shankar, Uma
  0 siblings, 0 replies; 45+ messages in thread
From: Shankar, Uma @ 2022-02-16  8:02 UTC (permalink / raw)
  To: C, Ramalingam, intel-gfx, dri-devel; +Cc: De Marchi, Lucas



> -----Original Message-----
> From: C, Ramalingam <ramalingam.c@intel.com>
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> devel@lists.freedesktop.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>;
> Dhanavanthri, Swathi <swathi.dhanavanthri@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Souza, Jose <jose.souza@intel.com>; C, Ramalingam
> <ramalingam.c@intel.com>
> Subject: [PATCH 1/3] drm/i915/dg2: Enable 5th display
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> DG2 supports a 5th display output which the hardware refers to as "TC1,"
> even though it isn't a Type-C output.  This behaves similarly to the TC1 on past
> platforms with just a couple minor differences:
> 
>  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
>    ICP/TGP/ADP.
>  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> 
> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
>  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
>  drivers/gpu/drm/i915/i915_reg.h            |  1 +
>  3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6ce8c10fe975..2fad03250661 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
>  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
>  };
> 
> +static const struct gmbus_pin gmbus_pins_dg2[] = {
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, };
> +
>  /* pin is expected to be valid */
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
>  					     unsigned int pin)
>  {
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		return &gmbus_pins_dg2[pin];
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		return &gmbus_pins_dg1[pin];
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		return &gmbus_pins_icp[pin];
> @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> *dev_priv,  {
>  	unsigned int size;
> 
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		size = ARRAY_SIZE(gmbus_pins_dg2);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		size = ARRAY_SIZE(gmbus_pins_dg1);
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index
> fdd568ba4a16..4d81063b128c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
>  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
>  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
>  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),

Not sure if this applies to DG1, the 5th TC1 port is only for DG2.  Should we not have a separate
DG2 struct. Can you please clarify to help understand.

Regards,
Uma Shankar

>  };
> 
>  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -4424,7
> +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		if (I915_HAS_HOTPLUG(dev_priv))
>  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
>  	} else {
> -		if (HAS_PCH_DG1(dev_priv))
> +		if (HAS_PCH_DG2(dev_priv))
> +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> +		else if (HAS_PCH_DG1(dev_priv))
>  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
>  		else if (DISPLAY_VER(dev_priv) >= 11)
>  			dev_priv->hotplug_funcs = &gen11_hpd_funcs; diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> 4ea1713e6b60..4d12abb2d7ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6182,6 +6182,7 @@
>  /* south display engine interrupt: ICP/TGP */
>  #define SDE_GMBUS_ICP			(1 << 23)
>  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 +
> _HPD_PIN_TC(hpd_pin))
> +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 +
> _HPD_PIN_TC(hpd_pin)) /* sigh */
>  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 +
> _HPD_PIN_DDI(hpd_pin))
>  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
>  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> --
> 2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* RE: [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
  2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
@ 2022-02-16  8:06     ` Shankar, Uma
  -1 siblings, 0 replies; 45+ messages in thread
From: Shankar, Uma @ 2022-02-16  8:06 UTC (permalink / raw)
  To: C, Ramalingam, intel-gfx, dri-devel; +Cc: Srivatsa, Anusha, Souza, Jose



> -----Original Message-----
> From: C, Ramalingam <ramalingam.c@intel.com>
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> devel@lists.freedesktop.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Souza, Jose
> <jose.souza@intel.com>; C, Ramalingam <ramalingam.c@intel.com>
> Subject: [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Our early understanding of DG2 was incorrect; since the 5th display isn't actually a
> Type-C output, 38.4 MHz input clocks are never used on this platform and we can
> drop the corresponding MPLLB tables.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-----------------
>  1 file changed, 1 insertion(+), 207 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 8573a458811a..c60575cb5368 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const
> dg2_dp_100_tables[] = {
>  	NULL,
>  };
> 
> -/*
> - * Basic DP link rates with 38.4 MHz reference clock.
> - */
> -
> -static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
> -	.clock = 162000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
> -	.clock = 270000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
> -	.clock = 540000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
> -	.clock = 810000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
> -	.clock = 1000000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
> -
> -	/*
> -	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> -	 */
> -	.mpllb_sscen =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
> -	.mpllb_sscstep =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
> -	.clock = 1350000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
> -
> -	/*
> -	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> -	 */
> -	.mpllb_sscen =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
> -	.mpllb_sscstep =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
> -};
> -
> -static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
> -	&dg2_dp_rbr_38_4,
> -	&dg2_dp_hbr1_38_4,
> -	&dg2_dp_hbr2_38_4,
> -	&dg2_dp_hbr3_38_4,
> -	&dg2_dp_uhbr10_38_4,
> -	&dg2_dp_uhbr13_38_4,
> -	NULL,
> -};
> -
>  /*
>   * eDP link rates with 100 MHz reference clock.
>   */
> @@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		return dg2_edp_tables;
>  	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		/*
> -		 * FIXME: Initially we're just enabling the "combo" outputs on
> -		 * port A-D.  The MPLLB for those ports takes an input from the
> -		 * "Display Filter PLL" which always has an output frequency
> -		 * of 100 MHz, hence the use of the _100 tables below.
> -		 *
> -		 * Once we enable port TC1 it will either use the same 100 MHz
> -		 * "Display Filter PLL" (when strapped to support a native
> -		 * display connection) or different 38.4 MHz "Filter PLL" when
> -		 * strapped to support a USB connection, so we'll need to check
> -		 * that to determine which table to use.
> -		 */
> -		if (0)
> -			return dg2_dp_38_4_tables;
> -		else
> -			return dg2_dp_100_tables;
> +		return dg2_dp_100_tables;
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>  		return dg2_hdmi_tables;
>  	}
> --
> 2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
@ 2022-02-16  8:06     ` Shankar, Uma
  0 siblings, 0 replies; 45+ messages in thread
From: Shankar, Uma @ 2022-02-16  8:06 UTC (permalink / raw)
  To: C, Ramalingam, intel-gfx, dri-devel



> -----Original Message-----
> From: C, Ramalingam <ramalingam.c@intel.com>
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> devel@lists.freedesktop.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Souza, Jose
> <jose.souza@intel.com>; C, Ramalingam <ramalingam.c@intel.com>
> Subject: [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
> 
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Our early understanding of DG2 was incorrect; since the 5th display isn't actually a
> Type-C output, 38.4 MHz input clocks are never used on this platform and we can
> drop the corresponding MPLLB tables.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-----------------
>  1 file changed, 1 insertion(+), 207 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 8573a458811a..c60575cb5368 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const
> dg2_dp_100_tables[] = {
>  	NULL,
>  };
> 
> -/*
> - * Basic DP link rates with 38.4 MHz reference clock.
> - */
> -
> -static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
> -	.clock = 162000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
> -	.clock = 270000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
> -	.clock = 540000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
> -	.clock = 810000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
> -	.clock = 1000000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
> -
> -	/*
> -	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> -	 */
> -	.mpllb_sscen =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
> -	.mpllb_sscstep =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
> -};
> -
> -static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
> -	.clock = 1350000,
> -	.ref_control =
> -		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> -	.mpllb_cp =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> -	.mpllb_div =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
> -	.mpllb_div2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
> -	.mpllb_fracn1 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -	.mpllb_fracn2 =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
> -
> -	/*
> -	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> -	 */
> -	.mpllb_sscen =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
> -	.mpllb_sscstep =
> -		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
> -};
> -
> -static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
> -	&dg2_dp_rbr_38_4,
> -	&dg2_dp_hbr1_38_4,
> -	&dg2_dp_hbr2_38_4,
> -	&dg2_dp_hbr3_38_4,
> -	&dg2_dp_uhbr10_38_4,
> -	&dg2_dp_uhbr13_38_4,
> -	NULL,
> -};
> -
>  /*
>   * eDP link rates with 100 MHz reference clock.
>   */
> @@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		return dg2_edp_tables;
>  	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		/*
> -		 * FIXME: Initially we're just enabling the "combo" outputs on
> -		 * port A-D.  The MPLLB for those ports takes an input from the
> -		 * "Display Filter PLL" which always has an output frequency
> -		 * of 100 MHz, hence the use of the _100 tables below.
> -		 *
> -		 * Once we enable port TC1 it will either use the same 100 MHz
> -		 * "Display Filter PLL" (when strapped to support a native
> -		 * display connection) or different 38.4 MHz "Filter PLL" when
> -		 * strapped to support a USB connection, so we'll need to check
> -		 * that to determine which table to use.
> -		 */
> -		if (0)
> -			return dg2_dp_38_4_tables;
> -		else
> -			return dg2_dp_100_tables;
> +		return dg2_dp_100_tables;
>  	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>  		return dg2_hdmi_tables;
>  	}
> --
> 2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* RE: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
@ 2022-02-16  8:16     ` Shankar, Uma
  -1 siblings, 0 replies; 45+ messages in thread
From: Shankar, Uma @ 2022-02-16  8:16 UTC (permalink / raw)
  To: C, Ramalingam, intel-gfx, dri-devel; +Cc: Hogander, Jouni



> -----Original Message-----
> From: C, Ramalingam <ramalingam.c@intel.com>
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> devel@lists.freedesktop.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Hogander, Jouni <jouni.hogander@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>
> Subject: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
> 
> From: Jouni Högander <jouni.hogander@intel.com>
> 
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E port. Correct
> offset is 0x64C14.
> 
> Fix this by handling PHY_E port seprately.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index c60575cb5368..f08061c748b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
> drm_i915_private *i915)
>  		if (!intel_phy_is_snps(i915, phy))
>  			continue;
> 
> -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>  					    DG2_PHY_DP_TX_ACK_MASK, 25))
>  			drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after
> 25ms.\n",
>  				phy);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d12abb2d7ff..354c25f483cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9559,8 +9559,10 @@ enum skl_power_gate {
> 
>  #define _ICL_PHY_MISC_A		0x64C00
>  #define _ICL_PHY_MISC_B		0x64C04
> -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> -						 _ICL_PHY_MISC_B)
> +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
> +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A,
> _ICL_PHY_MISC_B)

Nit: Align it as was defined earlier to honor line limit.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> +#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) :
> \
> +				 ICL_PHY_MISC(port))
>  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
>  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
>  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
> --
> 2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-16  8:16     ` Shankar, Uma
  0 siblings, 0 replies; 45+ messages in thread
From: Shankar, Uma @ 2022-02-16  8:16 UTC (permalink / raw)
  To: C, Ramalingam, intel-gfx, dri-devel



> -----Original Message-----
> From: C, Ramalingam <ramalingam.c@intel.com>
> Sent: Tuesday, February 15, 2022 11:22 AM
> To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> devel@lists.freedesktop.org>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Hogander, Jouni <jouni.hogander@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>
> Subject: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
> 
> From: Jouni Högander <jouni.hogander@intel.com>
> 
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E port. Correct
> offset is 0x64C14.
> 
> Fix this by handling PHY_E port seprately.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index c60575cb5368..f08061c748b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
> drm_i915_private *i915)
>  		if (!intel_phy_is_snps(i915, phy))
>  			continue;
> 
> -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>  					    DG2_PHY_DP_TX_ACK_MASK, 25))
>  			drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after
> 25ms.\n",
>  				phy);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d12abb2d7ff..354c25f483cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9559,8 +9559,10 @@ enum skl_power_gate {
> 
>  #define _ICL_PHY_MISC_A		0x64C00
>  #define _ICL_PHY_MISC_B		0x64C04
> -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> -						 _ICL_PHY_MISC_B)
> +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
> +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A,
> _ICL_PHY_MISC_B)

Nit: Align it as was defined earlier to honor line limit.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> +#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) :
> \
> +				 ICL_PHY_MISC(port))
>  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
>  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
>  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
> --
> 2.20.1


^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
@ 2022-02-16  8:50     ` Ville Syrjälä
  -1 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-16  8:50 UTC (permalink / raw)
  To: Ramalingam C; +Cc: Jouni Högander, intel-gfx, Shankar Uma, dri-devel

On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> From: Jouni Högander <jouni.hogander@intel.com>
> 
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> port. Correct offset is 0x64C14.

Why is it PHY_E and not PHY_F?

> 
> Fix this by handling PHY_E port seprately.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index c60575cb5368..f08061c748b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
>  		if (!intel_phy_is_snps(i915, phy))
>  			continue;
>  
> -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>  					    DG2_PHY_DP_TX_ACK_MASK, 25))
>  			drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
>  				phy);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d12abb2d7ff..354c25f483cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9559,8 +9559,10 @@ enum skl_power_gate {
>  
>  #define _ICL_PHY_MISC_A		0x64C00
>  #define _ICL_PHY_MISC_B		0x64C04
> -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> -						 _ICL_PHY_MISC_B)
> +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
> +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
> +#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
> +				 ICL_PHY_MISC(port))
>  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
>  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
>  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-16  8:50     ` Ville Syrjälä
  0 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-16  8:50 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx, dri-devel

On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> From: Jouni Högander <jouni.hogander@intel.com>
> 
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> port. Correct offset is 0x64C14.

Why is it PHY_E and not PHY_F?

> 
> Fix this by handling PHY_E port seprately.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index c60575cb5368..f08061c748b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
>  		if (!intel_phy_is_snps(i915, phy))
>  			continue;
>  
> -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>  					    DG2_PHY_DP_TX_ACK_MASK, 25))
>  			drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
>  				phy);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d12abb2d7ff..354c25f483cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9559,8 +9559,10 @@ enum skl_power_gate {
>  
>  #define _ICL_PHY_MISC_A		0x64C00
>  #define _ICL_PHY_MISC_B		0x64C04
> -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> -						 _ICL_PHY_MISC_B)
> +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
> +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
> +#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
> +				 ICL_PHY_MISC(port))
>  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
>  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
>  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23, 20)
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-16  8:50     ` [Intel-gfx] " Ville Syrjälä
@ 2022-02-16  9:36       ` Hogander, Jouni
  -1 siblings, 0 replies; 45+ messages in thread
From: Hogander, Jouni @ 2022-02-16  9:36 UTC (permalink / raw)
  To: ville.syrjala, C, Ramalingam; +Cc: intel-gfx, Shankar, Uma, dri-devel

On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > From: Jouni Högander <jouni.hogander@intel.com>
> > 
> > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> > port. Correct offset is 0x64C14.
> 
> Why is it PHY_E and not PHY_F?

This is a valid question. It seems we have followed intel_phy_is_snps()
here:

// snip
else if (IS_DG2(dev_priv))
		/*
		 * All four "combo" ports and the TC1 port (PHY E) use
		 * Synopsis PHYs.
		 */
		return phy <= PHY_E;
// snip

According to spec port E is "No connection". Better place to fix this
could be intel_phy_is_snps() itself?

> 
> > Fix this by handling PHY_E port seprately.
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
> >  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
> >  2 files changed, 5 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > index c60575cb5368..f08061c748b3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
> > drm_i915_private *i915)
> >  		if (!intel_phy_is_snps(i915, phy))
> >  			continue;
> >  
> > -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> > +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
> >  					    DG2_PHY_DP_TX_ACK_MASK,
> > 25))
> >  			drm_err(&i915->drm, "SNPS PHY %c failed to
> > calibrate after 25ms.\n",
> >  				phy);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4d12abb2d7ff..354c25f483cb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9559,8 +9559,10 @@ enum skl_power_gate {
> >  
> >  #define _ICL_PHY_MISC_A		0x64C00
> >  #define _ICL_PHY_MISC_B		0x64C04
> > -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> > -						 _ICL_PHY_MISC_B)
> > +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if
> > "PHY F" */
> > +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A,
> > _ICL_PHY_MISC_B)
> > +#define DG2_PHY_MISC(port)	((port) == PHY_E ?
> > _MMIO(_DG2_PHY_MISC_TC1) : \
> > +				 ICL_PHY_MISC(port))
> >  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
> >  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
> >  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23,
> > 20)
> > -- 
> > 2.20.1

BR,

Jouni Högander

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-16  9:36       ` Hogander, Jouni
  0 siblings, 0 replies; 45+ messages in thread
From: Hogander, Jouni @ 2022-02-16  9:36 UTC (permalink / raw)
  To: ville.syrjala, C, Ramalingam; +Cc: intel-gfx, dri-devel

On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > From: Jouni Högander <jouni.hogander@intel.com>
> > 
> > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> > port. Correct offset is 0x64C14.
> 
> Why is it PHY_E and not PHY_F?

This is a valid question. It seems we have followed intel_phy_is_snps()
here:

// snip
else if (IS_DG2(dev_priv))
		/*
		 * All four "combo" ports and the TC1 port (PHY E) use
		 * Synopsis PHYs.
		 */
		return phy <= PHY_E;
// snip

According to spec port E is "No connection". Better place to fix this
could be intel_phy_is_snps() itself?

> 
> > Fix this by handling PHY_E port seprately.
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
> >  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
> >  2 files changed, 5 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > index c60575cb5368..f08061c748b3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
> > drm_i915_private *i915)
> >  		if (!intel_phy_is_snps(i915, phy))
> >  			continue;
> >  
> > -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> > +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
> >  					    DG2_PHY_DP_TX_ACK_MASK,
> > 25))
> >  			drm_err(&i915->drm, "SNPS PHY %c failed to
> > calibrate after 25ms.\n",
> >  				phy);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4d12abb2d7ff..354c25f483cb 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9559,8 +9559,10 @@ enum skl_power_gate {
> >  
> >  #define _ICL_PHY_MISC_A		0x64C00
> >  #define _ICL_PHY_MISC_B		0x64C04
> > -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> > -						 _ICL_PHY_MISC_B)
> > +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if
> > "PHY F" */
> > +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A,
> > _ICL_PHY_MISC_B)
> > +#define DG2_PHY_MISC(port)	((port) == PHY_E ?
> > _MMIO(_DG2_PHY_MISC_TC1) : \
> > +				 ICL_PHY_MISC(port))
> >  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
> >  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
> >  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23,
> > 20)
> > -- 
> > 2.20.1

BR,

Jouni Högander

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-16  9:36       ` [Intel-gfx] " Hogander, Jouni
@ 2022-02-16 10:07         ` Ville Syrjälä
  -1 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-16 10:07 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, Shankar, Uma, dri-devel

On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > From: Jouni Högander <jouni.hogander@intel.com>
> > > 
> > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> > > port. Correct offset is 0x64C14.
> > 
> > Why is it PHY_E and not PHY_F?
> 
> This is a valid question. It seems we have followed intel_phy_is_snps()
> here:
> 
> // snip
> else if (IS_DG2(dev_priv))
> 		/*
> 		 * All four "combo" ports and the TC1 port (PHY E) use
> 		 * Synopsis PHYs.
> 		 */
> 		return phy <= PHY_E;
> // snip
> 
> According to spec port E is "No connection". Better place to fix this
> could be intel_phy_is_snps() itself?

I think the crucial question is where are all the places that
the results of intel_port_to_phy() get used.

I do see that for all the actual snps phy registers we
do want PHY_E, but maybe it would be better to have a local
SNPS_PHY enum just for intel_snps_phy.c, and leave the other
phy thing for everything else?

Not sure if there is some other register we index with the
phy that specifically wants PHY_E?

Also it kinda looks to me like for VBT port mapping we also
want PHY_F essentially since the modern platforms make the
VBT port mapping PHY based and xelpd_port_mapping() uses
PORT_TC1<->DVO_PORT_*F. Not that we actually use enum phy
in the VBT code atm, but I'm thinking we probably should
since it might allow us to get rid of all those different
mapping tables. Though the whole intel_port_to_phy()
disaster needs to get cleaned up first IMO.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-16 10:07         ` Ville Syrjälä
  0 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-16 10:07 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, dri-devel

On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > From: Jouni Högander <jouni.hogander@intel.com>
> > > 
> > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> > > port. Correct offset is 0x64C14.
> > 
> > Why is it PHY_E and not PHY_F?
> 
> This is a valid question. It seems we have followed intel_phy_is_snps()
> here:
> 
> // snip
> else if (IS_DG2(dev_priv))
> 		/*
> 		 * All four "combo" ports and the TC1 port (PHY E) use
> 		 * Synopsis PHYs.
> 		 */
> 		return phy <= PHY_E;
> // snip
> 
> According to spec port E is "No connection". Better place to fix this
> could be intel_phy_is_snps() itself?

I think the crucial question is where are all the places that
the results of intel_port_to_phy() get used.

I do see that for all the actual snps phy registers we
do want PHY_E, but maybe it would be better to have a local
SNPS_PHY enum just for intel_snps_phy.c, and leave the other
phy thing for everything else?

Not sure if there is some other register we index with the
phy that specifically wants PHY_E?

Also it kinda looks to me like for VBT port mapping we also
want PHY_F essentially since the modern platforms make the
VBT port mapping PHY based and xelpd_port_mapping() uses
PORT_TC1<->DVO_PORT_*F. Not that we actually use enum phy
in the VBT code atm, but I'm thinking we probably should
since it might allow us to get rid of all those different
mapping tables. Though the whole intel_port_to_phy()
disaster needs to get cleaned up first IMO.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-16 10:07         ` [Intel-gfx] " Ville Syrjälä
@ 2022-02-16 14:11           ` Hogander, Jouni
  -1 siblings, 0 replies; 45+ messages in thread
From: Hogander, Jouni @ 2022-02-16 14:11 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx, Shankar, Uma, dri-devel

On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > From: Jouni Högander <jouni.hogander@intel.com>
> > > > 
> > > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for
> > > > PHY_E
> > > > port. Correct offset is 0x64C14.
> > > 
> > > Why is it PHY_E and not PHY_F?
> > 
> > This is a valid question. It seems we have followed
> > intel_phy_is_snps()
> > here:
> > 
> > // snip
> > else if (IS_DG2(dev_priv))
> > 		/*
> > 		 * All four "combo" ports and the TC1 port (PHY E) use
> > 		 * Synopsis PHYs.
> > 		 */
> > 		return phy <= PHY_E;
> > // snip
> > 
> > According to spec port E is "No connection". Better place to fix
> > this
> > could be intel_phy_is_snps() itself?
> 
> I think the crucial question is where are all the places that
> the results of intel_port_to_phy() get used.
> 
> I do see that for all the actual snps phy registers we
> do want PHY_E, but maybe it would be better to have a local
> SNPS_PHY enum just for intel_snps_phy.c, and leave the other
> phy thing for everything else?
> 
> Not sure if there is some other register we index with the
> phy that specifically wants PHY_E?

I went through registers accesses in intel_snps_phy.c. It is actually
only this one register which offset is wrong with PHY_E. Everything
else seems to be assuming PHY_E including those SNPS_* registers (as
you mentioned). I'm starting to think it would be overkill to open up
this phy enum for this purpose. I would propose to stick with current
patch. Maybe just update commit message. What do you think?

> 
> Also it kinda looks to me like for VBT port mapping we also
> want PHY_F essentially since the modern platforms make the
> VBT port mapping PHY based and xelpd_port_mapping() uses
> PORT_TC1<->DVO_PORT_*F. Not that we actually use enum phy
> in the VBT code atm, but I'm thinking we probably should
> since it might allow us to get rid of all those different
> mapping tables. Though the whole intel_port_to_phy()
> disaster needs to get cleaned up first IMO.
> 

BR,

Jouni Högander

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-16 14:11           ` Hogander, Jouni
  0 siblings, 0 replies; 45+ messages in thread
From: Hogander, Jouni @ 2022-02-16 14:11 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx, dri-devel

On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > From: Jouni Högander <jouni.hogander@intel.com>
> > > > 
> > > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for
> > > > PHY_E
> > > > port. Correct offset is 0x64C14.
> > > 
> > > Why is it PHY_E and not PHY_F?
> > 
> > This is a valid question. It seems we have followed
> > intel_phy_is_snps()
> > here:
> > 
> > // snip
> > else if (IS_DG2(dev_priv))
> > 		/*
> > 		 * All four "combo" ports and the TC1 port (PHY E) use
> > 		 * Synopsis PHYs.
> > 		 */
> > 		return phy <= PHY_E;
> > // snip
> > 
> > According to spec port E is "No connection". Better place to fix
> > this
> > could be intel_phy_is_snps() itself?
> 
> I think the crucial question is where are all the places that
> the results of intel_port_to_phy() get used.
> 
> I do see that for all the actual snps phy registers we
> do want PHY_E, but maybe it would be better to have a local
> SNPS_PHY enum just for intel_snps_phy.c, and leave the other
> phy thing for everything else?
> 
> Not sure if there is some other register we index with the
> phy that specifically wants PHY_E?

I went through registers accesses in intel_snps_phy.c. It is actually
only this one register which offset is wrong with PHY_E. Everything
else seems to be assuming PHY_E including those SNPS_* registers (as
you mentioned). I'm starting to think it would be overkill to open up
this phy enum for this purpose. I would propose to stick with current
patch. Maybe just update commit message. What do you think?

> 
> Also it kinda looks to me like for VBT port mapping we also
> want PHY_F essentially since the modern platforms make the
> VBT port mapping PHY based and xelpd_port_mapping() uses
> PORT_TC1<->DVO_PORT_*F. Not that we actually use enum phy
> in the VBT code atm, but I'm thinking we probably should
> since it might allow us to get rid of all those different
> mapping tables. Though the whole intel_port_to_phy()
> disaster needs to get cleaned up first IMO.
> 

BR,

Jouni Högander

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-16 14:11           ` [Intel-gfx] " Hogander, Jouni
@ 2022-02-16 15:01             ` Ville Syrjälä
  -1 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-16 15:01 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, Shankar, Uma, dri-devel

On Wed, Feb 16, 2022 at 02:11:54PM +0000, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> > > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > > From: Jouni Högander <jouni.hogander@intel.com>
> > > > > 
> > > > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for
> > > > > PHY_E
> > > > > port. Correct offset is 0x64C14.
> > > > 
> > > > Why is it PHY_E and not PHY_F?
> > > 
> > > This is a valid question. It seems we have followed
> > > intel_phy_is_snps()
> > > here:
> > > 
> > > // snip
> > > else if (IS_DG2(dev_priv))
> > > 		/*
> > > 		 * All four "combo" ports and the TC1 port (PHY E) use
> > > 		 * Synopsis PHYs.
> > > 		 */
> > > 		return phy <= PHY_E;
> > > // snip
> > > 
> > > According to spec port E is "No connection". Better place to fix
> > > this
> > > could be intel_phy_is_snps() itself?
> > 
> > I think the crucial question is where are all the places that
> > the results of intel_port_to_phy() get used.
> > 
> > I do see that for all the actual snps phy registers we
> > do want PHY_E, but maybe it would be better to have a local
> > SNPS_PHY enum just for intel_snps_phy.c, and leave the other
> > phy thing for everything else?
> > 
> > Not sure if there is some other register we index with the
> > phy that specifically wants PHY_E?
> 
> I went through registers accesses in intel_snps_phy.c. It is actually
> only this one register which offset is wrong with PHY_E. Everything
> else seems to be assuming PHY_E including those SNPS_* registers (as
> you mentioned). I'm starting to think it would be overkill to open up
> this phy enum for this purpose. I would propose to stick with current
> patch. Maybe just update commit message. What do you think?

I would put it the other way. It is *only* the SNPS PHY IP registers
that use the wonky offsets (unless you found some others?). Everythting
on the Intel IP side wants it to be PHY_F.

So still would make more sense to me to add a new enum for the
SNPS PHY instance and remap across the boundary. Otherwise we're
just propagating this madness everwhere rather than containing in
the SNPS PHY implementation.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-16 15:01             ` Ville Syrjälä
  0 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-16 15:01 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, dri-devel

On Wed, Feb 16, 2022 at 02:11:54PM +0000, Hogander, Jouni wrote:
> On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> > > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > > From: Jouni Högander <jouni.hogander@intel.com>
> > > > > 
> > > > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for
> > > > > PHY_E
> > > > > port. Correct offset is 0x64C14.
> > > > 
> > > > Why is it PHY_E and not PHY_F?
> > > 
> > > This is a valid question. It seems we have followed
> > > intel_phy_is_snps()
> > > here:
> > > 
> > > // snip
> > > else if (IS_DG2(dev_priv))
> > > 		/*
> > > 		 * All four "combo" ports and the TC1 port (PHY E) use
> > > 		 * Synopsis PHYs.
> > > 		 */
> > > 		return phy <= PHY_E;
> > > // snip
> > > 
> > > According to spec port E is "No connection". Better place to fix
> > > this
> > > could be intel_phy_is_snps() itself?
> > 
> > I think the crucial question is where are all the places that
> > the results of intel_port_to_phy() get used.
> > 
> > I do see that for all the actual snps phy registers we
> > do want PHY_E, but maybe it would be better to have a local
> > SNPS_PHY enum just for intel_snps_phy.c, and leave the other
> > phy thing for everything else?
> > 
> > Not sure if there is some other register we index with the
> > phy that specifically wants PHY_E?
> 
> I went through registers accesses in intel_snps_phy.c. It is actually
> only this one register which offset is wrong with PHY_E. Everything
> else seems to be assuming PHY_E including those SNPS_* registers (as
> you mentioned). I'm starting to think it would be overkill to open up
> this phy enum for this purpose. I would propose to stick with current
> patch. Maybe just update commit message. What do you think?

I would put it the other way. It is *only* the SNPS PHY IP registers
that use the wonky offsets (unless you found some others?). Everythting
on the Intel IP side wants it to be PHY_F.

So still would make more sense to me to add a new enum for the
SNPS PHY instance and remap across the boundary. Otherwise we're
just propagating this madness everwhere rather than containing in
the SNPS PHY implementation.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-16 15:01             ` [Intel-gfx] " Ville Syrjälä
  (?)
@ 2022-02-17 12:56             ` Ville Syrjälä
  -1 siblings, 0 replies; 45+ messages in thread
From: Ville Syrjälä @ 2022-02-17 12:56 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, dri-devel

On Wed, Feb 16, 2022 at 05:01:35PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 16, 2022 at 02:11:54PM +0000, Hogander, Jouni wrote:
> > On Wed, 2022-02-16 at 12:07 +0200, Ville Syrjälä wrote:
> > > On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
> > > > On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
> > > > > On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> > > > > > From: Jouni Högander <jouni.hogander@intel.com>
> > > > > > 
> > > > > > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for
> > > > > > PHY_E
> > > > > > port. Correct offset is 0x64C14.
> > > > > 
> > > > > Why is it PHY_E and not PHY_F?
> > > > 
> > > > This is a valid question. It seems we have followed
> > > > intel_phy_is_snps()
> > > > here:
> > > > 
> > > > // snip
> > > > else if (IS_DG2(dev_priv))
> > > > 		/*
> > > > 		 * All four "combo" ports and the TC1 port (PHY E) use
> > > > 		 * Synopsis PHYs.
> > > > 		 */
> > > > 		return phy <= PHY_E;
> > > > // snip
> > > > 
> > > > According to spec port E is "No connection". Better place to fix
> > > > this
> > > > could be intel_phy_is_snps() itself?
> > > 
> > > I think the crucial question is where are all the places that
> > > the results of intel_port_to_phy() get used.
> > > 
> > > I do see that for all the actual snps phy registers we
> > > do want PHY_E, but maybe it would be better to have a local
> > > SNPS_PHY enum just for intel_snps_phy.c, and leave the other
> > > phy thing for everything else?
> > > 
> > > Not sure if there is some other register we index with the
> > > phy that specifically wants PHY_E?
> > 
> > I went through registers accesses in intel_snps_phy.c. It is actually
> > only this one register which offset is wrong with PHY_E. Everything
> > else seems to be assuming PHY_E including those SNPS_* registers (as
> > you mentioned). I'm starting to think it would be overkill to open up
> > this phy enum for this purpose. I would propose to stick with current
> > patch. Maybe just update commit message. What do you think?
> 
> I would put it the other way. It is *only* the SNPS PHY IP registers
> that use the wonky offsets (unless you found some others?). Everythting
> on the Intel IP side wants it to be PHY_F.
> 
> So still would make more sense to me to add a new enum for the
> SNPS PHY instance and remap across the boundary. Otherwise we're
> just propagating this madness everwhere rather than containing in
> the SNPS PHY implementation.

Seems people want this is asap. I suppose it'll do as a temporary
measure given the phy stuff is already such mess.
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

As for the proper way to do stuff, I'm thinking roughly:
enum intel_spns_phy {
	SNPS_PHY_A,
	...
	SNPS_PHY_TC1, // == current PHY_E in value
};
and I think that can stay entirely inside intel_snps_phy.c.

As for our currnet enum phy I think we could start with something like
this:
enum phy {
	PHY_A,
	...
	PHY_F,

	PHY_TC1 = PHY_F,
	...
};

I think that should make it line up with PHY_MISC stuff and the 
VBT as well. So in the VBT code we could nuke all those crazy mapping
tables and just do:
 old platform: port -> VBT port
 new platform: phy -> VBT port

And we could probably have encoder->phy which gets populated
in the encoder init per-platform, similar to hpd_pin. That
would get rid of the intel_port_to_phy() disaster.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 1/3] drm/i915/dg2: Enable 5th display
  2022-02-16  8:02     ` [Intel-gfx] " Shankar, Uma
@ 2022-02-17 16:33       ` Matt Roper
  -1 siblings, 0 replies; 45+ messages in thread
From: Matt Roper @ 2022-02-17 16:33 UTC (permalink / raw)
  To: Shankar, Uma
  Cc: Dhanavanthri, Swathi, intel-gfx, De Marchi, Lucas, dri-devel,
	Souza, Jose

On Wed, Feb 16, 2022 at 12:02:31AM -0800, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: C, Ramalingam <ramalingam.c@intel.com>
> > Sent: Tuesday, February 15, 2022 11:22 AM
> > To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> > devel@lists.freedesktop.org>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>;
> > Dhanavanthri, Swathi <swathi.dhanavanthri@intel.com>; De Marchi, Lucas
> > <lucas.demarchi@intel.com>; Souza, Jose <jose.souza@intel.com>; C, Ramalingam
> > <ramalingam.c@intel.com>
> > Subject: [PATCH 1/3] drm/i915/dg2: Enable 5th display
> > 
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > DG2 supports a 5th display output which the hardware refers to as "TC1,"
> > even though it isn't a Type-C output.  This behaves similarly to the TC1 on past
> > platforms with just a couple minor differences:
> > 
> >  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
> >    ICP/TGP/ADP.
> >  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> > 
> > Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
> >  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
> >  drivers/gpu/drm/i915/i915_reg.h            |  1 +
> >  3 files changed, 19 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > index 6ce8c10fe975..2fad03250661 100644
> > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
> >  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> >  };
> > 
> > +static const struct gmbus_pin gmbus_pins_dg2[] = {
> > +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> > +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> > +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, };
> > +
> >  /* pin is expected to be valid */
> >  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> >  					     unsigned int pin)
> >  {
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		return &gmbus_pins_dg2[pin];
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		return &gmbus_pins_dg1[pin];
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		return &gmbus_pins_icp[pin];
> > @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> > *dev_priv,  {
> >  	unsigned int size;
> > 
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		size = ARRAY_SIZE(gmbus_pins_dg2);
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		size = ARRAY_SIZE(gmbus_pins_dg1);
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		size = ARRAY_SIZE(gmbus_pins_icp);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index
> > fdd568ba4a16..4d81063b128c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
> >  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
> >  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
> >  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> > +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
> 
> Not sure if this applies to DG1, the 5th TC1 port is only for DG2.  Should we not have a separate
> DG2 struct. Can you please clarify to help understand.

It's fine to add this to the DG1 structure since it's just a mapping
table.  DG1 will never use TC1 as an input into the table, but there
aren't any conflicting mappings between DG1/DG2 so we can use the same
table for both.


Matt

> 
> Regards,
> Uma Shankar
> 
> >  };
> > 
> >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -4424,7
> > +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> >  		if (I915_HAS_HOTPLUG(dev_priv))
> >  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
> >  	} else {
> > -		if (HAS_PCH_DG1(dev_priv))
> > +		if (HAS_PCH_DG2(dev_priv))
> > +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> > +		else if (HAS_PCH_DG1(dev_priv))
> >  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
> >  		else if (DISPLAY_VER(dev_priv) >= 11)
> >  			dev_priv->hotplug_funcs = &gen11_hpd_funcs; diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> > 4ea1713e6b60..4d12abb2d7ff 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6182,6 +6182,7 @@
> >  /* south display engine interrupt: ICP/TGP */
> >  #define SDE_GMBUS_ICP			(1 << 23)
> >  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 +
> > _HPD_PIN_TC(hpd_pin))
> > +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 +
> > _HPD_PIN_TC(hpd_pin)) /* sigh */
> >  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 +
> > _HPD_PIN_DDI(hpd_pin))
> >  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
> >  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> > --
> > 2.20.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg2: Enable 5th display
@ 2022-02-17 16:33       ` Matt Roper
  0 siblings, 0 replies; 45+ messages in thread
From: Matt Roper @ 2022-02-17 16:33 UTC (permalink / raw)
  To: Shankar, Uma; +Cc: intel-gfx, De Marchi, Lucas, dri-devel

On Wed, Feb 16, 2022 at 12:02:31AM -0800, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: C, Ramalingam <ramalingam.c@intel.com>
> > Sent: Tuesday, February 15, 2022 11:22 AM
> > To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-
> > devel@lists.freedesktop.org>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>;
> > Dhanavanthri, Swathi <swathi.dhanavanthri@intel.com>; De Marchi, Lucas
> > <lucas.demarchi@intel.com>; Souza, Jose <jose.souza@intel.com>; C, Ramalingam
> > <ramalingam.c@intel.com>
> > Subject: [PATCH 1/3] drm/i915/dg2: Enable 5th display
> > 
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > DG2 supports a 5th display output which the hardware refers to as "TC1,"
> > even though it isn't a Type-C output.  This behaves similarly to the TC1 on past
> > platforms with just a couple minor differences:
> > 
> >  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
> >    ICP/TGP/ADP.
> >  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> > 
> > Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
> >  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
> >  drivers/gpu/drm/i915/i915_reg.h            |  1 +
> >  3 files changed, 19 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > index 6ce8c10fe975..2fad03250661 100644
> > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
> >  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> >  };
> > 
> > +static const struct gmbus_pin gmbus_pins_dg2[] = {
> > +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> > +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> > +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, };
> > +
> >  /* pin is expected to be valid */
> >  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> >  					     unsigned int pin)
> >  {
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		return &gmbus_pins_dg2[pin];
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		return &gmbus_pins_dg1[pin];
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		return &gmbus_pins_icp[pin];
> > @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> > *dev_priv,  {
> >  	unsigned int size;
> > 
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		size = ARRAY_SIZE(gmbus_pins_dg2);
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		size = ARRAY_SIZE(gmbus_pins_dg1);
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		size = ARRAY_SIZE(gmbus_pins_icp);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index
> > fdd568ba4a16..4d81063b128c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
> >  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
> >  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
> >  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> > +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
> 
> Not sure if this applies to DG1, the 5th TC1 port is only for DG2.  Should we not have a separate
> DG2 struct. Can you please clarify to help understand.

It's fine to add this to the DG1 structure since it's just a mapping
table.  DG1 will never use TC1 as an input into the table, but there
aren't any conflicting mappings between DG1/DG2 so we can use the same
table for both.


Matt

> 
> Regards,
> Uma Shankar
> 
> >  };
> > 
> >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -4424,7
> > +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> >  		if (I915_HAS_HOTPLUG(dev_priv))
> >  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
> >  	} else {
> > -		if (HAS_PCH_DG1(dev_priv))
> > +		if (HAS_PCH_DG2(dev_priv))
> > +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> > +		else if (HAS_PCH_DG1(dev_priv))
> >  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
> >  		else if (DISPLAY_VER(dev_priv) >= 11)
> >  			dev_priv->hotplug_funcs = &gen11_hpd_funcs; diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> > 4ea1713e6b60..4d12abb2d7ff 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6182,6 +6182,7 @@
> >  /* south display engine interrupt: ICP/TGP */
> >  #define SDE_GMBUS_ICP			(1 << 23)
> >  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 +
> > _HPD_PIN_TC(hpd_pin))
> > +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 +
> > _HPD_PIN_TC(hpd_pin)) /* sigh */
> >  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 +
> > _HPD_PIN_DDI(hpd_pin))
> >  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
> >  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> > --
> > 2.20.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 1/3] drm/i915/dg2: Enable 5th display
  2022-02-15  5:51   ` Ramalingam C
@ 2022-02-17 16:37     ` Matt Roper
  -1 siblings, 0 replies; 45+ messages in thread
From: Matt Roper @ 2022-02-17 16:37 UTC (permalink / raw)
  To: Ramalingam C
  Cc: Swathi Dhanavanthri, intel-gfx, Lucas De Marchi, dri-devel,
	Shankar Uma, José Roberto de Souza

Since it apparently caused some confusion on various websites, maybe we
should change the title of the patch to "Enable 5th port" to make it
more clear that this is only a port, not a pipe.

Also, I believe one last line that we need to add to this patch is an
intel_ddi_init() call for TC1 in the intel_setup_outputs() function.  I
think I previously had that in a separate patch, but it went missing
when we reorganized and refactored some of these patches


Matt

On Tue, Feb 15, 2022 at 11:21:52AM +0530, Ramalingam C wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> DG2 supports a 5th display output which the hardware refers to as "TC1,"
> even though it isn't a Type-C output.  This behaves similarly to the TC1
> on past platforms with just a couple minor differences:
> 
>  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
>    ICP/TGP/ADP.
>  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> 
> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
>  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
>  drivers/gpu/drm/i915/i915_reg.h            |  1 +
>  3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6ce8c10fe975..2fad03250661 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
>  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
>  };
>  
> +static const struct gmbus_pin gmbus_pins_dg2[] = {
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> +};
> +
>  /* pin is expected to be valid */
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
>  					     unsigned int pin)
>  {
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		return &gmbus_pins_dg2[pin];
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		return &gmbus_pins_dg1[pin];
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		return &gmbus_pins_icp[pin];
> @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  {
>  	unsigned int size;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		size = ARRAY_SIZE(gmbus_pins_dg2);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		size = ARRAY_SIZE(gmbus_pins_dg1);
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index fdd568ba4a16..4d81063b128c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
>  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
>  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
>  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
>  };
>  
>  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> @@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		if (I915_HAS_HOTPLUG(dev_priv))
>  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
>  	} else {
> -		if (HAS_PCH_DG1(dev_priv))
> +		if (HAS_PCH_DG2(dev_priv))
> +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> +		else if (HAS_PCH_DG1(dev_priv))
>  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
>  		else if (DISPLAY_VER(dev_priv) >= 11)
>  			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4ea1713e6b60..4d12abb2d7ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6182,6 +6182,7 @@
>  /* south display engine interrupt: ICP/TGP */
>  #define SDE_GMBUS_ICP			(1 << 23)
>  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
>  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
>  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
>  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> -- 
> 2.20.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg2: Enable 5th display
@ 2022-02-17 16:37     ` Matt Roper
  0 siblings, 0 replies; 45+ messages in thread
From: Matt Roper @ 2022-02-17 16:37 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx, Lucas De Marchi, dri-devel

Since it apparently caused some confusion on various websites, maybe we
should change the title of the patch to "Enable 5th port" to make it
more clear that this is only a port, not a pipe.

Also, I believe one last line that we need to add to this patch is an
intel_ddi_init() call for TC1 in the intel_setup_outputs() function.  I
think I previously had that in a separate patch, but it went missing
when we reorganized and refactored some of these patches


Matt

On Tue, Feb 15, 2022 at 11:21:52AM +0530, Ramalingam C wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> DG2 supports a 5th display output which the hardware refers to as "TC1,"
> even though it isn't a Type-C output.  This behaves similarly to the TC1
> on past platforms with just a couple minor differences:
> 
>  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
>    ICP/TGP/ADP.
>  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> 
> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
>  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
>  drivers/gpu/drm/i915/i915_reg.h            |  1 +
>  3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6ce8c10fe975..2fad03250661 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
>  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
>  };
>  
> +static const struct gmbus_pin gmbus_pins_dg2[] = {
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> +};
> +
>  /* pin is expected to be valid */
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
>  					     unsigned int pin)
>  {
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		return &gmbus_pins_dg2[pin];
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		return &gmbus_pins_dg1[pin];
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		return &gmbus_pins_icp[pin];
> @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  {
>  	unsigned int size;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> +		size = ARRAY_SIZE(gmbus_pins_dg2);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>  		size = ARRAY_SIZE(gmbus_pins_dg1);
>  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>  		size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index fdd568ba4a16..4d81063b128c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
>  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
>  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
>  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
>  };
>  
>  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> @@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		if (I915_HAS_HOTPLUG(dev_priv))
>  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
>  	} else {
> -		if (HAS_PCH_DG1(dev_priv))
> +		if (HAS_PCH_DG2(dev_priv))
> +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> +		else if (HAS_PCH_DG1(dev_priv))
>  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
>  		else if (DISPLAY_VER(dev_priv) >= 11)
>  			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4ea1713e6b60..4d12abb2d7ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6182,6 +6182,7 @@
>  /* south display engine interrupt: ICP/TGP */
>  #define SDE_GMBUS_ICP			(1 << 23)
>  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
>  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
>  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
>  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> -- 
> 2.20.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 1/3] drm/i915/dg2: Enable 5th display
  2022-02-17 16:37     ` [Intel-gfx] " Matt Roper
@ 2022-02-17 17:46       ` Ramalingam C
  -1 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-17 17:46 UTC (permalink / raw)
  To: Matt Roper
  Cc: Swathi Dhanavanthri, intel-gfx, Lucas De Marchi, dri-devel,
	Shankar Uma, José Roberto de Souza

On 2022-02-17 at 08:37:47 -0800, Matt Roper wrote:
> Since it apparently caused some confusion on various websites, maybe we
> should change the title of the patch to "Enable 5th port" to make it
> more clear that this is only a port, not a pipe.
Ok sure.

> 
> Also, I believe one last line that we need to add to this patch is an
> intel_ddi_init() call for TC1 in the intel_setup_outputs() function.  I
> think I previously had that in a separate patch, but it went missing
> when we reorganized and refactored some of these patches

like 

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 59961621fe4a..18531ffd4789 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8760,6 +8760,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
                intel_ddi_init(dev_priv, PORT_B);
                intel_ddi_init(dev_priv, PORT_C);
                intel_ddi_init(dev_priv, PORT_D_XELPD);
+               intel_ddi_init(dev_priv, PORT_TC1);
        } else if (IS_ALDERLAKE_P(dev_priv)) {
                intel_ddi_init(dev_priv, PORT_A);
                intel_ddi_init(dev_priv, PORT_B);

Ram
> 
> 
> Matt
> 
> On Tue, Feb 15, 2022 at 11:21:52AM +0530, Ramalingam C wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > DG2 supports a 5th display output which the hardware refers to as "TC1,"
> > even though it isn't a Type-C output.  This behaves similarly to the TC1
> > on past platforms with just a couple minor differences:
> > 
> >  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
> >    ICP/TGP/ADP.
> >  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> > 
> > Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
> >  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
> >  drivers/gpu/drm/i915/i915_reg.h            |  1 +
> >  3 files changed, 19 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > index 6ce8c10fe975..2fad03250661 100644
> > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
> >  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> >  };
> >  
> > +static const struct gmbus_pin gmbus_pins_dg2[] = {
> > +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> > +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> > +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> > +};
> > +
> >  /* pin is expected to be valid */
> >  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> >  					     unsigned int pin)
> >  {
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		return &gmbus_pins_dg2[pin];
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		return &gmbus_pins_dg1[pin];
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		return &gmbus_pins_icp[pin];
> > @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> >  {
> >  	unsigned int size;
> >  
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		size = ARRAY_SIZE(gmbus_pins_dg2);
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		size = ARRAY_SIZE(gmbus_pins_dg1);
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		size = ARRAY_SIZE(gmbus_pins_icp);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index fdd568ba4a16..4d81063b128c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
> >  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
> >  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
> >  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> > +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
> >  };
> >  
> >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> > @@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> >  		if (I915_HAS_HOTPLUG(dev_priv))
> >  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
> >  	} else {
> > -		if (HAS_PCH_DG1(dev_priv))
> > +		if (HAS_PCH_DG2(dev_priv))
> > +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> > +		else if (HAS_PCH_DG1(dev_priv))
> >  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
> >  		else if (DISPLAY_VER(dev_priv) >= 11)
> >  			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4ea1713e6b60..4d12abb2d7ff 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6182,6 +6182,7 @@
> >  /* south display engine interrupt: ICP/TGP */
> >  #define SDE_GMBUS_ICP			(1 << 23)
> >  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> > +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
> >  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
> >  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
> >  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> > -- 
> > 2.20.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg2: Enable 5th display
@ 2022-02-17 17:46       ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-17 17:46 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi, dri-devel

On 2022-02-17 at 08:37:47 -0800, Matt Roper wrote:
> Since it apparently caused some confusion on various websites, maybe we
> should change the title of the patch to "Enable 5th port" to make it
> more clear that this is only a port, not a pipe.
Ok sure.

> 
> Also, I believe one last line that we need to add to this patch is an
> intel_ddi_init() call for TC1 in the intel_setup_outputs() function.  I
> think I previously had that in a separate patch, but it went missing
> when we reorganized and refactored some of these patches

like 

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 59961621fe4a..18531ffd4789 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8760,6 +8760,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
                intel_ddi_init(dev_priv, PORT_B);
                intel_ddi_init(dev_priv, PORT_C);
                intel_ddi_init(dev_priv, PORT_D_XELPD);
+               intel_ddi_init(dev_priv, PORT_TC1);
        } else if (IS_ALDERLAKE_P(dev_priv)) {
                intel_ddi_init(dev_priv, PORT_A);
                intel_ddi_init(dev_priv, PORT_B);

Ram
> 
> 
> Matt
> 
> On Tue, Feb 15, 2022 at 11:21:52AM +0530, Ramalingam C wrote:
> > From: Matt Roper <matthew.d.roper@intel.com>
> > 
> > DG2 supports a 5th display output which the hardware refers to as "TC1,"
> > even though it isn't a Type-C output.  This behaves similarly to the TC1
> > on past platforms with just a couple minor differences:
> > 
> >  * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
> >    ICP/TGP/ADP.
> >  * DG2 doesn't need the hpd inversion setting that we had to use on DG1
> > 
> > Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++--
> >  drivers/gpu/drm/i915/i915_irq.c            |  5 ++++-
> >  drivers/gpu/drm/i915/i915_reg.h            |  1 +
> >  3 files changed, 19 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > index 6ce8c10fe975..2fad03250661 100644
> > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> > @@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
> >  	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> >  };
> >  
> > +static const struct gmbus_pin gmbus_pins_dg2[] = {
> > +	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> > +	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> > +	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> > +	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> > +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> > +};
> > +
> >  /* pin is expected to be valid */
> >  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> >  					     unsigned int pin)
> >  {
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		return &gmbus_pins_dg2[pin];
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		return &gmbus_pins_dg1[pin];
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		return &gmbus_pins_icp[pin];
> > @@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> >  {
> >  	unsigned int size;
> >  
> > -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> > +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
> > +		size = ARRAY_SIZE(gmbus_pins_dg2);
> > +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >  		size = ARRAY_SIZE(gmbus_pins_dg1);
> >  	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> >  		size = ARRAY_SIZE(gmbus_pins_icp);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index fdd568ba4a16..4d81063b128c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
> >  	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
> >  	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
> >  	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
> > +	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
> >  };
> >  
> >  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> > @@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> >  		if (I915_HAS_HOTPLUG(dev_priv))
> >  			dev_priv->hotplug_funcs = &i915_hpd_funcs;
> >  	} else {
> > -		if (HAS_PCH_DG1(dev_priv))
> > +		if (HAS_PCH_DG2(dev_priv))
> > +			dev_priv->hotplug_funcs = &icp_hpd_funcs;
> > +		else if (HAS_PCH_DG1(dev_priv))
> >  			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
> >  		else if (DISPLAY_VER(dev_priv) >= 11)
> >  			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4ea1713e6b60..4d12abb2d7ff 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6182,6 +6182,7 @@
> >  /* south display engine interrupt: ICP/TGP */
> >  #define SDE_GMBUS_ICP			(1 << 23)
> >  #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> > +#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
> >  #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
> >  #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
> >  					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> > -- 
> > 2.20.1
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [Intel-gfx] [PATCH v2 1/3] drm/i915/dg2: Enable 5th port
  2022-02-15  5:51   ` Ramalingam C
@ 2022-02-17 18:42     ` Ramalingam C
  -1 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-17 18:42 UTC (permalink / raw)
  To: intel-gfx, dri-devel; +Cc: Lucas De Marchi

From: Matt Roper <matthew.d.roper@intel.com>

DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output.  This behaves similarly to the TC1
on past platforms with just a couple minor differences:

 * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
   ICP/TGP/ADP.
 * DG2 doesn't need the hpd inversion setting that we had to use on DG1

v2:
  intel_ddi_init(dev_priv, PORT_TC1); [Matt]

Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/display/intel_gmbus.c   | 16 ++++++++++++++--
 drivers/gpu/drm/i915/i915_irq.c              |  5 ++++-
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 4 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 59961621fe4a..18531ffd4789 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8760,6 +8760,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		intel_ddi_init(dev_priv, PORT_D_XELPD);
+		intel_ddi_init(dev_priv, PORT_TC1);
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975..2fad03250661 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 };
 
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		return &gmbus_pins_dg2[pin];
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		return &gmbus_pins_dg1[pin];
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		return &gmbus_pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		size = ARRAY_SIZE(gmbus_pins_dg2);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		size = ARRAY_SIZE(gmbus_pins_dg1);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a16..4d81063b128c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->hotplug_funcs = &i915_hpd_funcs;
 	} else {
-		if (HAS_PCH_DG1(dev_priv))
+		if (HAS_PCH_DG2(dev_priv))
+			dev_priv->hotplug_funcs = &icp_hpd_funcs;
+		else if (HAS_PCH_DG1(dev_priv))
 			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
 		else if (DISPLAY_VER(dev_priv) >= 11)
 			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2243d9d1d941..b5acbbcc8574 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6065,6 +6065,7 @@
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH v2 1/3] drm/i915/dg2: Enable 5th port
@ 2022-02-17 18:42     ` Ramalingam C
  0 siblings, 0 replies; 45+ messages in thread
From: Ramalingam C @ 2022-02-17 18:42 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: Swathi Dhanavanthri, Lucas De Marchi, José Roberto de Souza,
	Shankar Uma

From: Matt Roper <matthew.d.roper@intel.com>

DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output.  This behaves similarly to the TC1
on past platforms with just a couple minor differences:

 * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
   ICP/TGP/ADP.
 * DG2 doesn't need the hpd inversion setting that we had to use on DG1

v2:
  intel_ddi_init(dev_priv, PORT_TC1); [Matt]

Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/display/intel_gmbus.c   | 16 ++++++++++++++--
 drivers/gpu/drm/i915/i915_irq.c              |  5 ++++-
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 4 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 59961621fe4a..18531ffd4789 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8760,6 +8760,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		intel_ddi_init(dev_priv, PORT_D_XELPD);
+		intel_ddi_init(dev_priv, PORT_TC1);
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975..2fad03250661 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
 	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 };
 
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		return &gmbus_pins_dg2[pin];
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		return &gmbus_pins_dg1[pin];
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		return &gmbus_pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+		size = ARRAY_SIZE(gmbus_pins_dg2);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 		size = ARRAY_SIZE(gmbus_pins_dg1);
 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a16..4d81063b128c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->hotplug_funcs = &i915_hpd_funcs;
 	} else {
-		if (HAS_PCH_DG1(dev_priv))
+		if (HAS_PCH_DG2(dev_priv))
+			dev_priv->hotplug_funcs = &icp_hpd_funcs;
+		else if (HAS_PCH_DG1(dev_priv))
 			dev_priv->hotplug_funcs = &dg1_hpd_funcs;
 		else if (DISPLAY_VER(dev_priv) >= 11)
 			dev_priv->hotplug_funcs = &gen11_hpd_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2243d9d1d941..b5acbbcc8574 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6065,6 +6065,7 @@
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)	REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
  2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
  (?)
  (?)
@ 2022-02-17 19:35   ` Lucas De Marchi
  -1 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2022-02-17 19:35 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx, dri-devel

On Tue, Feb 15, 2022 at 11:21:53AM +0530, Ramalingam C wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>Our early understanding of DG2 was incorrect; since the 5th display
>isn't actually a Type-C output, 38.4 MHz input clocks are never used on
>this platform and we can drop the corresponding MPLLB tables.
>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Ramalingam C <ramalingam.c@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi


>---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-----------------
> 1 file changed, 1 insertion(+), 207 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>index 8573a458811a..c60575cb5368 100644
>--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>@@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
> 	NULL,
> };
>
>-/*
>- * Basic DP link rates with 38.4 MHz reference clock.
>- */
>-
>-static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
>-	.clock = 162000,
>-	.ref_control =
>-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
>-	.mpllb_cp =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
>-	.mpllb_div =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
>-	.mpllb_div2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
>-	.mpllb_fracn1 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
>-	.mpllb_fracn2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
>-};
>-
>-static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
>-	.clock = 270000,
>-	.ref_control =
>-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
>-	.mpllb_cp =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
>-	.mpllb_div =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
>-	.mpllb_div2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
>-	.mpllb_fracn1 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
>-	.mpllb_fracn2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
>-};
>-
>-static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
>-	.clock = 540000,
>-	.ref_control =
>-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
>-	.mpllb_cp =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
>-	.mpllb_div =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
>-	.mpllb_div2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
>-	.mpllb_fracn1 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
>-	.mpllb_fracn2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
>-};
>-
>-static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
>-	.clock = 810000,
>-	.ref_control =
>-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
>-	.mpllb_cp =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
>-	.mpllb_div =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
>-	.mpllb_div2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
>-	.mpllb_fracn1 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
>-	.mpllb_fracn2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
>-};
>-
>-static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
>-	.clock = 1000000,
>-	.ref_control =
>-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
>-	.mpllb_cp =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
>-	.mpllb_div =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
>-	.mpllb_div2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
>-	.mpllb_fracn1 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
>-	.mpllb_fracn2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
>-
>-	/*
>-	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
>-	 */
>-	.mpllb_sscen =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
>-	.mpllb_sscstep =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
>-};
>-
>-static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
>-	.clock = 1350000,
>-	.ref_control =
>-		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
>-	.mpllb_cp =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
>-	.mpllb_div =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
>-	.mpllb_div2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
>-	.mpllb_fracn1 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
>-	.mpllb_fracn2 =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
>-
>-	/*
>-	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
>-	 */
>-	.mpllb_sscen =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
>-	.mpllb_sscstep =
>-		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
>-};
>-
>-static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
>-	&dg2_dp_rbr_38_4,
>-	&dg2_dp_hbr1_38_4,
>-	&dg2_dp_hbr2_38_4,
>-	&dg2_dp_hbr3_38_4,
>-	&dg2_dp_uhbr10_38_4,
>-	&dg2_dp_uhbr13_38_4,
>-	NULL,
>-};
>-
> /*
>  * eDP link rates with 100 MHz reference clock.
>  */
>@@ -749,22 +558,7 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> 		return dg2_edp_tables;
> 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
>-		/*
>-		 * FIXME: Initially we're just enabling the "combo" outputs on
>-		 * port A-D.  The MPLLB for those ports takes an input from the
>-		 * "Display Filter PLL" which always has an output frequency
>-		 * of 100 MHz, hence the use of the _100 tables below.
>-		 *
>-		 * Once we enable port TC1 it will either use the same 100 MHz
>-		 * "Display Filter PLL" (when strapped to support a native
>-		 * display connection) or different 38.4 MHz "Filter PLL" when
>-		 * strapped to support a USB connection, so we'll need to check
>-		 * that to determine which table to use.
>-		 */
>-		if (0)
>-			return dg2_dp_38_4_tables;
>-		else
>-			return dg2_dp_100_tables;
>+		return dg2_dp_100_tables;
> 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> 		return dg2_hdmi_tables;
> 	}
>-- 
>2.20.1
>

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
                     ` (2 preceding siblings ...)
  (?)
@ 2022-02-17 19:38   ` Lucas De Marchi
  -1 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2022-02-17 19:38 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx, dri-devel

On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
>From: Jouni Högander <jouni.hogander@intel.com>
>
>Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
>port. Correct offset is 0x64C14.
>
>Fix this by handling PHY_E port seprately.

order of the patch here is wrong. This patch should come before
the patch initializing the 5th port. Then the commit message is not
a fix.

This can be done while applying since it's more an order to avoid
breaking the tree.

Lucas De Marchi

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
  2022-02-16  9:36       ` [Intel-gfx] " Hogander, Jouni
@ 2022-02-17 20:46         ` Lucas De Marchi
  -1 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2022-02-17 20:46 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, Shankar, Uma, dri-devel

On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
>On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
>> On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
>> > From: Jouni Högander <jouni.hogander@intel.com>
>> >
>> > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
>> > port. Correct offset is 0x64C14.
>>
>> Why is it PHY_E and not PHY_F?
>
>This is a valid question. It seems we have followed intel_phy_is_snps()
>here:
>
>// snip
>else if (IS_DG2(dev_priv))
>		/*
>		 * All four "combo" ports and the TC1 port (PHY E) use
>		 * Synopsis PHYs.
>		 */
>		return phy <= PHY_E;
>// snip

And this is actually the bug that we had. We wouldn't need to bring the
incomplete support for the 5th port if this single had changed:  it's
often preferred to prepare the driver first and enable the port/phy as
the last step:

-		return phy <= PHY_E;
+		return phy <= PHY_D;

With possibly a change in the commit above. Because in
drivers/gpu/drm/i915/display/intel_snps_phy.c we do:

intel_snps_phy_wait_for_calibration()
{
...
         for_each_phy_masked(phy, ~0) {
                 if (!intel_phy_is_snps(i915, phy))
                         continue;
...
}

Relying on intel_phy_is_snps() to mask out the unavailable phys.

However, since now we almost have the extra port wired up, I'm not going
to push back on it. Let's just add a comment on the commit message.
And since going with this approach is also acked by Ville who preferred
to contain the additional mapping inside intel_phy_snps.c:

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi


>
>According to spec port E is "No connection". Better place to fix this
>could be intel_phy_is_snps() itself?
>
>>
>> > Fix this by handling PHY_E port seprately.
>> >
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>> >  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
>> >  2 files changed, 5 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > index c60575cb5368..f08061c748b3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
>> > drm_i915_private *i915)
>> >  		if (!intel_phy_is_snps(i915, phy))
>> >  			continue;
>> >
>> > -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
>> > +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>> >  					    DG2_PHY_DP_TX_ACK_MASK,
>> > 25))
>> >  			drm_err(&i915->drm, "SNPS PHY %c failed to
>> > calibrate after 25ms.\n",
>> >  				phy);
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index 4d12abb2d7ff..354c25f483cb 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -9559,8 +9559,10 @@ enum skl_power_gate {
>> >
>> >  #define _ICL_PHY_MISC_A		0x64C00
>> >  #define _ICL_PHY_MISC_B		0x64C04
>> > -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
>> > -						 _ICL_PHY_MISC_B)
>> > +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if
>> > "PHY F" */
>> > +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A,
>> > _ICL_PHY_MISC_B)
>> > +#define DG2_PHY_MISC(port)	((port) == PHY_E ?
>> > _MMIO(_DG2_PHY_MISC_TC1) : \
>> > +				 ICL_PHY_MISC(port))
>> >  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
>> >  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
>> >  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23,
>> > 20)
>> > --
>> > 2.20.1
>
>BR,
>
>Jouni Högander

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
@ 2022-02-17 20:46         ` Lucas De Marchi
  0 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2022-02-17 20:46 UTC (permalink / raw)
  To: Hogander, Jouni; +Cc: intel-gfx, dri-devel

On Wed, Feb 16, 2022 at 09:36:02AM +0000, Hogander, Jouni wrote:
>On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
>> On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
>> > From: Jouni Högander <jouni.hogander@intel.com>
>> >
>> > Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
>> > port. Correct offset is 0x64C14.
>>
>> Why is it PHY_E and not PHY_F?
>
>This is a valid question. It seems we have followed intel_phy_is_snps()
>here:
>
>// snip
>else if (IS_DG2(dev_priv))
>		/*
>		 * All four "combo" ports and the TC1 port (PHY E) use
>		 * Synopsis PHYs.
>		 */
>		return phy <= PHY_E;
>// snip

And this is actually the bug that we had. We wouldn't need to bring the
incomplete support for the 5th port if this single had changed:  it's
often preferred to prepare the driver first and enable the port/phy as
the last step:

-		return phy <= PHY_E;
+		return phy <= PHY_D;

With possibly a change in the commit above. Because in
drivers/gpu/drm/i915/display/intel_snps_phy.c we do:

intel_snps_phy_wait_for_calibration()
{
...
         for_each_phy_masked(phy, ~0) {
                 if (!intel_phy_is_snps(i915, phy))
                         continue;
...
}

Relying on intel_phy_is_snps() to mask out the unavailable phys.

However, since now we almost have the extra port wired up, I'm not going
to push back on it. Let's just add a comment on the commit message.
And since going with this approach is also acked by Ville who preferred
to contain the additional mapping inside intel_phy_snps.c:

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi


>
>According to spec port E is "No connection". Better place to fix this
>could be intel_phy_is_snps() itself?
>
>>
>> > Fix this by handling PHY_E port seprately.
>> >
>> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>> >  drivers/gpu/drm/i915/i915_reg.h               | 6 ++++--
>> >  2 files changed, 5 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > index c60575cb5368..f08061c748b3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
>> > @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
>> > drm_i915_private *i915)
>> >  		if (!intel_phy_is_snps(i915, phy))
>> >  			continue;
>> >
>> > -		if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
>> > +		if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>> >  					    DG2_PHY_DP_TX_ACK_MASK,
>> > 25))
>> >  			drm_err(&i915->drm, "SNPS PHY %c failed to
>> > calibrate after 25ms.\n",
>> >  				phy);
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index 4d12abb2d7ff..354c25f483cb 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -9559,8 +9559,10 @@ enum skl_power_gate {
>> >
>> >  #define _ICL_PHY_MISC_A		0x64C00
>> >  #define _ICL_PHY_MISC_B		0x64C04
>> > -#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
>> > -						 _ICL_PHY_MISC_B)
>> > +#define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if
>> > "PHY F" */
>> > +#define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A,
>> > _ICL_PHY_MISC_B)
>> > +#define DG2_PHY_MISC(port)	((port) == PHY_E ?
>> > _MMIO(_DG2_PHY_MISC_TC1) : \
>> > +				 ICL_PHY_MISC(port))
>> >  #define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
>> >  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
>> >  #define  DG2_PHY_DP_TX_ACK_MASK			REG_GENMASK(23,
>> > 20)
>> > --
>> > 2.20.1
>
>BR,
>
>Jouni Högander

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/dg2: Enable 5th port
  2022-02-17 18:42     ` Ramalingam C
  (?)
@ 2022-02-17 21:15     ` Lucas De Marchi
  -1 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2022-02-17 21:15 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx, dri-devel

On Fri, Feb 18, 2022 at 12:12:21AM +0530, Ramalingam C wrote:
>From: Matt Roper <matthew.d.roper@intel.com>
>
>DG2 supports a 5th display output which the hardware refers to as "TC1,"
>even though it isn't a Type-C output.  This behaves similarly to the TC1
>on past platforms with just a couple minor differences:
>
> * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
>   ICP/TGP/ADP.
> * DG2 doesn't need the hpd inversion setting that we had to use on DG1
>
>v2:
>  intel_ddi_init(dev_priv, PORT_TC1); [Matt]
>
>Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Ramalingam C <ramalingam.c@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: 5th Display output (rev3)
  2022-02-15  5:51 ` Ramalingam C
                   ` (6 preceding siblings ...)
  (?)
@ 2022-02-18  2:33 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-18  2:33 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/dg2: 5th Display output (rev3)
URL   : https://patchwork.freedesktop.org/series/100151/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8c0d7cd7a8d7 drm/i915/dg2: Enable 5th port
25ac2dc4165f drm/i915/dg2: Drop 38.4 MHz MPLLB tables
34df0ad1a986 drm/i915: Fix for PHY_MISC_TC1 offset
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_reg.h:9361:
+#define DG2_PHY_MISC(port)	((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+				 ICL_PHY_MISC(port))

total: 0 errors, 0 warnings, 1 checks, 20 lines checked



^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: 5th Display output (rev3)
  2022-02-15  5:51 ` Ramalingam C
                   ` (7 preceding siblings ...)
  (?)
@ 2022-02-18  2:34 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-18  2:34 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/dg2: 5th Display output (rev3)
URL   : https://patchwork.freedesktop.org/series/100151/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: 5th Display output (rev3)
  2022-02-15  5:51 ` Ramalingam C
                   ` (8 preceding siblings ...)
  (?)
@ 2022-02-18  3:02 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-18  3:02 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 8749 bytes --]

== Series Details ==

Series: drm/i915/dg2: 5th Display output (rev3)
URL   : https://patchwork.freedesktop.org/series/100151/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22320
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/index.html

Participating hosts (44 -> 42)
------------------------------

  Additional (1): fi-kbl-8809g 
  Missing    (3): fi-bsw-cyan bat-jsl-2 shard-tglu 

Known issues
------------

  Here are the changes found in Patchwork_22320 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][1] ([i915#4962]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-bdw-5557u:       [PASS][2] -> [INCOMPLETE][3] ([i915#146])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-skl-6600u:       NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][8] ([fdo#109271]) +54 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        [PASS][9] -> [DMESG-FAIL][10] ([i915#2927] / [i915#3428])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@vga-edid-read:
    - fi-skl-6600u:       NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-skl-6600u:       NOTRUN -> [SKIP][13] ([fdo#109271]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [PASS][14] -> [DMESG-WARN][15] ([i915#4269])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6600u:       NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
    - fi-kbl-8809g:       NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-skl-6600u:       NOTRUN -> [INCOMPLETE][18] ([i915#5128])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][19] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-bsw-nick/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-skl-6600u:       [INCOMPLETE][20] ([i915#4547]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
    - {bat-rpls-2}:       [INCOMPLETE][22] ([i915#4898]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@hangcheck:
    - {fi-jsl-1}:         [INCOMPLETE][24] -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-jsl-1/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#4962]: https://gitlab.freedesktop.org/drm/intel/issues/4962
  [i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
  [i915#5128]: https://gitlab.freedesktop.org/drm/intel/issues/5128
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11244 -> Patchwork_22320

  CI-20190529: 20190529
  CI_DRM_11244: 6bde77454434bcd6c80f64fc638ffd0c8e1d5b07 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6347: 37ea4c86f97c0e05fcb6b04cff72ec927930536e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22320: 34df0ad1a986658ca5cb49a4211648034655971e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

34df0ad1a986 drm/i915: Fix for PHY_MISC_TC1 offset
25ac2dc4165f drm/i915/dg2: Drop 38.4 MHz MPLLB tables
8c0d7cd7a8d7 drm/i915/dg2: Enable 5th port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/index.html

[-- Attachment #2: Type: text/html, Size: 9800 bytes --]

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: 5th Display output (rev3)
  2022-02-15  5:51 ` Ramalingam C
                   ` (9 preceding siblings ...)
  (?)
@ 2022-02-18 13:49 ` Patchwork
  -1 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2022-02-18 13:49 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30263 bytes --]

== Series Details ==

Series: drm/i915/dg2: 5th Display output (rev3)
URL   : https://patchwork.freedesktop.org/series/100151/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11244_full -> Patchwork_22320_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_22320_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][1] ([i915#4991])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl3/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][2] -> [FAIL][3] ([i915#2410])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-iclb:         [PASS][4] -> [SKIP][5] ([i915#4525])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb2/igt@gem_exec_balancer@parallel-balancer.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-kbl:          [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl3/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][9] -> [FAIL][10] ([i915#2849])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_parallel@engines@basic:
    - shard-glk:          [PASS][11] -> [DMESG-WARN][12] ([i915#118]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk3/igt@gem_exec_parallel@engines@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk8/igt@gem_exec_parallel@engines@basic.html

  * igt@gem_exec_params@secure-non-root:
    - shard-iclb:         NOTRUN -> [SKIP][13] ([fdo#112283])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@gem_exec_params@secure-non-root.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-kbl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-skl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl7/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-skl:          NOTRUN -> [WARN][16] ([i915#2658])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl8/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-skl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl9/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-iclb:         NOTRUN -> [SKIP][18] ([i915#2856])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][19] ([fdo#110725] / [fdo#111614])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][20] ([i915#3743]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][21] ([fdo#111615])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-tglb5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][22] ([fdo#110723])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3777])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-skl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3777]) +2 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([fdo#109278] / [i915#3886]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +9 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl9/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl1/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@dp-frame-dump:
    - shard-skl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl8/igt@kms_chamelium@dp-frame-dump.html

  * igt@kms_chamelium@hdmi-cmp-planar-formats:
    - shard-kbl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@kms_chamelium@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium@vga-edid-read:
    - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_color@pipe-d-ctm-0-5:
    - shard-skl:          NOTRUN -> [SKIP][32] ([fdo#109271]) +161 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl9/igt@kms_color@pipe-d-ctm-0-5.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
    - shard-apl:          [PASS][35] -> [DMESG-WARN][36] ([i915#180])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-skl:          [PASS][37] -> [INCOMPLETE][38] ([i915#300])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][39] ([fdo#109278]) +6 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#3359])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#109278] / [fdo#109279])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([fdo#109274] / [fdo#109278])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][43] -> [FAIL][44] ([i915#2346])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109274])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-glk:          [PASS][46] -> [FAIL][47] ([i915#4911])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#109280]) +5 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-modesetfrombusy:
    - shard-glk:          [PASS][49] -> [FAIL][50] ([i915#2546])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk3/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk8/igt@kms_frontbuffer_tracking@fbc-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-kbl:          NOTRUN -> [SKIP][51] ([fdo#109271]) +21 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([fdo#109280] / [fdo#111825])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-apl:          NOTRUN -> [SKIP][53] ([fdo#109271]) +40 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#1839])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-skl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl8/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][57] -> [FAIL][58] ([fdo#108145] / [i915#265]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-skl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl7/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-kbl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][63] -> [SKIP][64] ([fdo#109441]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         NOTRUN -> [SKIP][65] ([fdo#109441])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_setmode@basic:
    - shard-glk:          [PASS][66] -> [FAIL][67] ([i915#31])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk3/igt@kms_setmode@basic.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk8/igt@kms_setmode@basic.html

  * igt@kms_vrr@flip-dpms:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([fdo#109502])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2437])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl3/igt@kms_writeback@writeback-fb-id.html

  * igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
    - shard-iclb:         NOTRUN -> [SKIP][70] ([fdo#109278] / [i915#2530])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html

  * igt@perf_pmu@module-unload:
    - shard-skl:          NOTRUN -> [FAIL][71] ([i915#5136])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl9/igt@perf_pmu@module-unload.html

  * igt@syncobj_timeline@invalid-transfer-non-existent-point:
    - shard-skl:          NOTRUN -> [DMESG-WARN][72] ([i915#5098])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl1/igt@syncobj_timeline@invalid-transfer-non-existent-point.html

  * igt@sysfs_clients@create:
    - shard-skl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2994]) +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl9/igt@sysfs_clients@create.html

  * igt@sysfs_clients@split-10:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([i915#2994])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][75] ([i915#658]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb8/igt@feature_discovery@psr2.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_exec_capture@pi@bcs0:
    - shard-iclb:         [INCOMPLETE][77] ([i915#3371]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb6/igt@gem_exec_capture@pi@bcs0.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb6/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-skl:          [INCOMPLETE][79] ([i915#4547]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-skl1/igt@gem_exec_capture@pi@rcs0.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl4/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][81] ([i915#2846]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk4/igt@gem_exec_fair@basic-deadline.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][83] ([i915#2842]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_whisper@basic-normal-all:
    - shard-glk:          [DMESG-WARN][85] ([i915#118]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk3/igt@gem_exec_whisper@basic-normal-all.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk8/igt@gem_exec_whisper@basic-normal-all.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][87] ([i915#454]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-180:
    - shard-glk:          [FAIL][89] ([i915#5138]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk5/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk8/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen:
    - shard-glk:          [DMESG-FAIL][91] ([i915#118] / [i915#1888]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - shard-iclb:         [FAIL][93] -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb5/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][95] ([i915#79]) -> [PASS][96] +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [DMESG-WARN][97] ([i915#180]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-kbl:          [DMESG-WARN][99] ([i915#180]) -> [PASS][100] +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl6/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-glk:          [FAIL][101] ([i915#4911]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][103] ([i915#1188]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-skl7/igt@kms_hdr@bpc-switch.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-skl4/igt@kms_hdr@bpc-switch.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][105] ([fdo#109441]) -> [PASS][106] +2 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-a-ts-continuation-modeset-hang:
    - shard-glk:          [TIMEOUT][107] ([i915#5140]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-glk1/igt@kms_vblank@pipe-a-ts-continuation-modeset-hang.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-glk3/igt@kms_vblank@pipe-a-ts-continuation-modeset-hang.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-iclb:         [DMESG-WARN][109] ([i915#5076]) -> [SKIP][110] ([i915#4525])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-iclb:         [SKIP][111] ([i915#4525]) -> [DMESG-WARN][112] ([i915#5076])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb7/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb4/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [SKIP][113] ([i915#4525]) -> [DMESG-FAIL][114] ([i915#5076])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][115] ([i915#2852]) -> [FAIL][116] ([i915#2842])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#4312]) -> ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#4312] / [i915#602])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl1/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl1/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl4/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl3/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl1/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl1/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl3/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl4/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-kbl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl7/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl6/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl7/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl7/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl3/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl6/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl4/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl7/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl6/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl6/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl6/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl7/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@runner@aborted.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@runner@aborted.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-kbl1/igt@runner@aborted.html
    - shard-apl:          ([FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155]) ([i915#180] / [i915#2426] / [i915#3002] / [i915#4312]) -> ([FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161]) ([i915#1814] / [i915#2426] / [i915#3002] / [i915#4312])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl8/igt@runner@aborted.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl1/igt@runner@aborted.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl4/igt@runner@aborted.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl8/igt@runner@aborted.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl2/igt@runner@aborted.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/shard-apl2/igt@runner@aborted.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl4/igt@runner@aborted.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/shard-apl8/igt@ru

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/index.html

[-- Attachment #2: Type: text/html, Size: 33565 bytes --]

^ permalink raw reply	[flat|nested] 45+ messages in thread

end of thread, other threads:[~2022-02-18 13:49 UTC | newest]

Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-15  5:51 [Intel-gfx] [PATCH 0/3] drm/i915/dg2: 5th Display output Ramalingam C
2022-02-15  5:51 ` Ramalingam C
2022-02-15  5:51 ` [Intel-gfx] [PATCH 1/3] drm/i915/dg2: Enable 5th display Ramalingam C
2022-02-15  5:51   ` Ramalingam C
2022-02-16  8:02   ` Shankar, Uma
2022-02-16  8:02     ` [Intel-gfx] " Shankar, Uma
2022-02-17 16:33     ` Matt Roper
2022-02-17 16:33       ` [Intel-gfx] " Matt Roper
2022-02-17 16:37   ` Matt Roper
2022-02-17 16:37     ` [Intel-gfx] " Matt Roper
2022-02-17 17:46     ` Ramalingam C
2022-02-17 17:46       ` [Intel-gfx] " Ramalingam C
2022-02-17 18:42   ` [Intel-gfx] [PATCH v2 1/3] drm/i915/dg2: Enable 5th port Ramalingam C
2022-02-17 18:42     ` Ramalingam C
2022-02-17 21:15     ` [Intel-gfx] " Lucas De Marchi
2022-02-15  5:51 ` [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables Ramalingam C
2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
2022-02-16  8:06   ` Shankar, Uma
2022-02-16  8:06     ` [Intel-gfx] " Shankar, Uma
2022-02-17 19:35   ` Lucas De Marchi
2022-02-15  5:51 ` [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset Ramalingam C
2022-02-15  5:51   ` [Intel-gfx] " Ramalingam C
2022-02-16  8:16   ` Shankar, Uma
2022-02-16  8:16     ` [Intel-gfx] " Shankar, Uma
2022-02-16  8:50   ` Ville Syrjälä
2022-02-16  8:50     ` [Intel-gfx] " Ville Syrjälä
2022-02-16  9:36     ` Hogander, Jouni
2022-02-16  9:36       ` [Intel-gfx] " Hogander, Jouni
2022-02-16 10:07       ` Ville Syrjälä
2022-02-16 10:07         ` [Intel-gfx] " Ville Syrjälä
2022-02-16 14:11         ` Hogander, Jouni
2022-02-16 14:11           ` [Intel-gfx] " Hogander, Jouni
2022-02-16 15:01           ` Ville Syrjälä
2022-02-16 15:01             ` [Intel-gfx] " Ville Syrjälä
2022-02-17 12:56             ` Ville Syrjälä
2022-02-17 20:46       ` Lucas De Marchi
2022-02-17 20:46         ` [Intel-gfx] " Lucas De Marchi
2022-02-17 19:38   ` Lucas De Marchi
2022-02-16  5:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: 5th Display output Patchwork
2022-02-16  5:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-16  5:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-02-18  2:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: 5th Display output (rev3) Patchwork
2022-02-18  2:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-18  3:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-18 13:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.