* [PATCH for-9.0 v2 0/3] target/hppa: Fix some wide mode displacements
@ 2024-03-13 22:51 Richard Henderson
2024-03-13 22:51 ` [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Richard Henderson @ 2024-03-13 22:51 UTC (permalink / raw)
To: qemu-devel
As reported by Sven Schnelle, fixed via decodetree functions.
Changes for v2:
- Fix extract_16 implementation (deller)
- Adjust some local variables to match arch doc field names.
r~
Richard Henderson (3):
target/hppa: Fix assemble_16 insns for wide mode
target/hppa: Fix assemble_11a insns for wide mode
target/hppa: Fix assemble_12a insns for wide mode
target/hppa/insns.decode | 49 ++++++++++++++++++-------------
target/hppa/translate.c | 62 ++++++++++++++++++++++++++++++++++++----
2 files changed, 85 insertions(+), 26 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode
2024-03-13 22:51 [PATCH for-9.0 v2 0/3] target/hppa: Fix some wide mode displacements Richard Henderson
@ 2024-03-13 22:51 ` Richard Henderson
2024-03-18 13:58 ` Helge Deller
2024-03-13 22:51 ` [PATCH v2 2/3] target/hppa: Fix assemble_11a " Richard Henderson
2024-03-13 22:51 ` [PATCH v2 3/3] target/hppa: Fix assemble_12a " Richard Henderson
2 siblings, 1 reply; 5+ messages in thread
From: Richard Henderson @ 2024-03-13 22:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Sven Schnelle
Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 15 +++++++++------
target/hppa/translate.c | 22 ++++++++++++++++++++++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index f5a3f02fd1..0d9f8159ec 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -27,13 +27,14 @@
%assemble_11a 0:s1 4:10 !function=expand_shl3
%assemble_12 0:s1 2:1 3:10 !function=expand_shl2
%assemble_12a 0:s1 3:11 !function=expand_shl2
+%assemble_16 0:16 !function=expand_16
%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
+%assemble_sp 14:2 !function=sp0_if_wide
%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
%lowsign_11 0:s1 1:10
-%lowsign_14 0:s1 1:13
%sm_imm 16:10 !function=expand_sm_imm
@@ -221,7 +222,7 @@ sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
ldil 001000 t:5 ..................... i=%assemble_21
addil 001010 r:5 ..................... i=%assemble_21
-ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
+ldo 001101 b:5 t:5 ................ i=%assemble_16
addi 101101 ..... ..... .... 0 ........... @rri_cf
addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
@@ -306,10 +307,12 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
@ldstim11 ...... b:5 t:5 sp:2 .............. \
&ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
-@ldstim14 ...... b:5 t:5 sp:2 .............. \
- &ldst disp=%lowsign_14 x=0 scale=0 m=0
-@ldstim14m ...... b:5 t:5 sp:2 .............. \
- &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
+@ldstim14 ...... b:5 t:5 ................ \
+ &ldst sp=%assemble_sp disp=%assemble_16 \
+ x=0 scale=0 m=0
+@ldstim14m ...... b:5 t:5 ................ \
+ &ldst sp=%assemble_sp disp=%assemble_16 \
+ x=0 scale=0 m=%neg_to_m
@ldstim12m ...... b:5 t:5 sp:2 .............. \
&ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index eb2046c5ad..cbe44ef75a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -144,6 +144,28 @@ static int assemble_6(DisasContext *ctx, int val)
return (val ^ 31) + 1;
}
+/* Expander for assemble_16(s,im14). */
+static int expand_16(DisasContext *ctx, int val)
+{
+ /*
+ * @val is bits [0:15], containing both im14 and s.
+ * Swizzle thing around depending on PSW.W.
+ */
+ int s = extract32(val, 14, 2);
+ int i = (-(val & 1) << 13) | extract32(val, 1, 13);
+
+ if (ctx->tb_flags & PSW_W) {
+ i ^= s << 13;
+ }
+ return i;
+}
+
+/* The sp field is only present with !PSW_W. */
+static int sp0_if_wide(DisasContext *ctx, int sp)
+{
+ return ctx->tb_flags & PSW_W ? 0 : sp;
+}
+
/* Translate CMPI doubleword conditions to standard. */
static int cmpbid_c(DisasContext *ctx, int val)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/3] target/hppa: Fix assemble_11a insns for wide mode
2024-03-13 22:51 [PATCH for-9.0 v2 0/3] target/hppa: Fix some wide mode displacements Richard Henderson
2024-03-13 22:51 ` [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode Richard Henderson
@ 2024-03-13 22:51 ` Richard Henderson
2024-03-13 22:51 ` [PATCH v2 3/3] target/hppa: Fix assemble_12a " Richard Henderson
2 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2024-03-13 22:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Helge Deller, Sven Schnelle
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 7 ++++---
target/hppa/translate.c | 23 +++++++++++++++++------
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 0d9f8159ec..9c6f92444c 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -24,7 +24,7 @@
%assemble_sr3 13:1 14:2
%assemble_sr3x 13:1 14:2 !function=expand_sr3x
-%assemble_11a 0:s1 4:10 !function=expand_shl3
+%assemble_11a 4:12 0:1 !function=expand_11a
%assemble_12 0:s1 2:1 3:10 !function=expand_shl2
%assemble_12a 0:s1 3:11 !function=expand_shl2
%assemble_16 0:16 !function=expand_16
@@ -305,8 +305,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
# Offset Mem
####
-@ldstim11 ...... b:5 t:5 sp:2 .............. \
- &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
+@ldstim11 ...... b:5 t:5 ................ \
+ &ldst sp=%assemble_sp disp=%assemble_11a \
+ m=%ma2_to_m x=0 scale=0 size=3
@ldstim14 ...... b:5 t:5 ................ \
&ldst sp=%assemble_sp disp=%assemble_16 \
x=0 scale=0 m=0
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index cbe44ef75a..40b9ff6d59 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -121,12 +121,6 @@ static int expand_shl2(DisasContext *ctx, int val)
return val << 2;
}
-/* Used for fp memory ops. */
-static int expand_shl3(DisasContext *ctx, int val)
-{
- return val << 3;
-}
-
/* Used for assemble_21. */
static int expand_shl11(DisasContext *ctx, int val)
{
@@ -144,6 +138,23 @@ static int assemble_6(DisasContext *ctx, int val)
return (val ^ 31) + 1;
}
+/* Expander for assemble_16a(s,cat(im10a,0),i). */
+static int expand_11a(DisasContext *ctx, int val)
+{
+ /*
+ * @val is bit 0 and bits [4:15].
+ * Swizzle thing around depending on PSW.W.
+ */
+ int im10a = extract32(val, 1, 10);
+ int s = extract32(val, 11, 2);
+ int i = (-(val & 1) << 13) | (im10a << 3);
+
+ if (ctx->tb_flags & PSW_W) {
+ i ^= s << 13;
+ }
+ return i;
+}
+
/* Expander for assemble_16(s,im14). */
static int expand_16(DisasContext *ctx, int val)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] target/hppa: Fix assemble_12a insns for wide mode
2024-03-13 22:51 [PATCH for-9.0 v2 0/3] target/hppa: Fix some wide mode displacements Richard Henderson
2024-03-13 22:51 ` [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode Richard Henderson
2024-03-13 22:51 ` [PATCH v2 2/3] target/hppa: Fix assemble_11a " Richard Henderson
@ 2024-03-13 22:51 ` Richard Henderson
2 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2024-03-13 22:51 UTC (permalink / raw)
To: qemu-devel; +Cc: Helge Deller, Sven Schnelle
Tested-by: Helge Deller <deller@gmx.de>
Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 27 ++++++++++++++++-----------
target/hppa/translate.c | 17 +++++++++++++++++
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 9c6f92444c..5412ff9836 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -26,7 +26,7 @@
%assemble_11a 4:12 0:1 !function=expand_11a
%assemble_12 0:s1 2:1 3:10 !function=expand_shl2
-%assemble_12a 0:s1 3:11 !function=expand_shl2
+%assemble_12a 3:13 0:1 !function=expand_12a
%assemble_16 0:16 !function=expand_16
%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
@@ -314,8 +314,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
@ldstim14m ...... b:5 t:5 ................ \
&ldst sp=%assemble_sp disp=%assemble_16 \
x=0 scale=0 m=%neg_to_m
-@ldstim12m ...... b:5 t:5 sp:2 .............. \
- &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
+@ldstim12m ...... b:5 t:5 ................ \
+ &ldst sp=%assemble_sp disp=%assemble_12a \
+ x=0 scale=0 m=%pos_to_m
# LDB, LDH, LDW, LDWM
ld 010000 ..... ..... .. .............. @ldstim14 size=0
@@ -331,15 +332,19 @@ st 011010 ..... ..... .. .............. @ldstim14 size=2
st 011011 ..... ..... .. .............. @ldstim14m size=2
st 011111 ..... ..... .. ...........10. @ldstim12m size=2
-fldw 010110 b:5 ..... sp:2 .............. \
- &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
-fldw 010111 b:5 ..... sp:2 ...........0.. \
- &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
+fldw 010110 b:5 ..... ................ \
+ &ldst disp=%assemble_12a sp=%assemble_sp \
+ t=%rm64 m=%a_to_m x=0 scale=0 size=2
+fldw 010111 b:5 ..... .............0.. \
+ &ldst disp=%assemble_12a sp=%assemble_sp \
+ t=%rm64 m=0 x=0 scale=0 size=2
-fstw 011110 b:5 ..... sp:2 .............. \
- &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
-fstw 011111 b:5 ..... sp:2 ...........0.. \
- &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
+fstw 011110 b:5 ..... ................ \
+ &ldst disp=%assemble_12a sp=%assemble_sp \
+ t=%rm64 m=%a_to_m x=0 scale=0 size=2
+fstw 011111 b:5 ..... .............0.. \
+ &ldst disp=%assemble_12a sp=%assemble_sp \
+ t=%rm64 m=0 x=0 scale=0 size=2
ld 010100 ..... ..... .. ............0. @ldstim11
fldd 010100 ..... ..... .. ............1. @ldstim11
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 40b9ff6d59..be0b0494d0 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -155,6 +155,23 @@ static int expand_11a(DisasContext *ctx, int val)
return i;
}
+/* Expander for assemble_16a(s,im11a,i). */
+static int expand_12a(DisasContext *ctx, int val)
+{
+ /*
+ * @val is bit 0 and bits [3:15].
+ * Swizzle thing around depending on PSW.W.
+ */
+ int im11a = extract32(val, 1, 11);
+ int s = extract32(val, 12, 2);
+ int i = (-(val & 1) << 13) | (im11a << 2);
+
+ if (ctx->tb_flags & PSW_W) {
+ i ^= s << 13;
+ }
+ return i;
+}
+
/* Expander for assemble_16(s,im14). */
static int expand_16(DisasContext *ctx, int val)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode
2024-03-13 22:51 ` [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode Richard Henderson
@ 2024-03-18 13:58 ` Helge Deller
0 siblings, 0 replies; 5+ messages in thread
From: Helge Deller @ 2024-03-18 13:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Sven Schnelle
On 3/13/24 23:51, Richard Henderson wrote:
> Reported-by: Sven Schnelle <svens@stackframe.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
> ---
> target/hppa/insns.decode | 15 +++++++++------
> target/hppa/translate.c | 22 ++++++++++++++++++++++
> 2 files changed, 31 insertions(+), 6 deletions(-)
>
> diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
> index f5a3f02fd1..0d9f8159ec 100644
> --- a/target/hppa/insns.decode
> +++ b/target/hppa/insns.decode
> @@ -27,13 +27,14 @@
> %assemble_11a 0:s1 4:10 !function=expand_shl3
> %assemble_12 0:s1 2:1 3:10 !function=expand_shl2
> %assemble_12a 0:s1 3:11 !function=expand_shl2
> +%assemble_16 0:16 !function=expand_16
> %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
> %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
> +%assemble_sp 14:2 !function=sp0_if_wide
>
> %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
>
> %lowsign_11 0:s1 1:10
> -%lowsign_14 0:s1 1:13
>
> %sm_imm 16:10 !function=expand_sm_imm
>
> @@ -221,7 +222,7 @@ sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
>
> ldil 001000 t:5 ..................... i=%assemble_21
> addil 001010 r:5 ..................... i=%assemble_21
> -ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
> +ldo 001101 b:5 t:5 ................ i=%assemble_16
>
> addi 101101 ..... ..... .... 0 ........... @rri_cf
> addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
> @@ -306,10 +307,12 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
>
> @ldstim11 ...... b:5 t:5 sp:2 .............. \
> &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
> -@ldstim14 ...... b:5 t:5 sp:2 .............. \
> - &ldst disp=%lowsign_14 x=0 scale=0 m=0
> -@ldstim14m ...... b:5 t:5 sp:2 .............. \
> - &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
> +@ldstim14 ...... b:5 t:5 ................ \
> + &ldst sp=%assemble_sp disp=%assemble_16 \
> + x=0 scale=0 m=0
> +@ldstim14m ...... b:5 t:5 ................ \
> + &ldst sp=%assemble_sp disp=%assemble_16 \
> + x=0 scale=0 m=%neg_to_m
> @ldstim12m ...... b:5 t:5 sp:2 .............. \
> &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
>
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index eb2046c5ad..cbe44ef75a 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -144,6 +144,28 @@ static int assemble_6(DisasContext *ctx, int val)
> return (val ^ 31) + 1;
> }
>
> +/* Expander for assemble_16(s,im14). */
> +static int expand_16(DisasContext *ctx, int val)
> +{
> + /*
> + * @val is bits [0:15], containing both im14 and s.
> + * Swizzle thing around depending on PSW.W.
> + */
> + int s = extract32(val, 14, 2);
> + int i = (-(val & 1) << 13) | extract32(val, 1, 13);
> +
> + if (ctx->tb_flags & PSW_W) {
> + i ^= s << 13;
> + }
> + return i;
> +}
> +
> +/* The sp field is only present with !PSW_W. */
> +static int sp0_if_wide(DisasContext *ctx, int sp)
> +{
> + return ctx->tb_flags & PSW_W ? 0 : sp;
> +}
> +
> /* Translate CMPI doubleword conditions to standard. */
> static int cmpbid_c(DisasContext *ctx, int val)
> {
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-03-18 14:00 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-13 22:51 [PATCH for-9.0 v2 0/3] target/hppa: Fix some wide mode displacements Richard Henderson
2024-03-13 22:51 ` [PATCH v2 1/3] target/hppa: Fix assemble_16 insns for wide mode Richard Henderson
2024-03-18 13:58 ` Helge Deller
2024-03-13 22:51 ` [PATCH v2 2/3] target/hppa: Fix assemble_11a " Richard Henderson
2024-03-13 22:51 ` [PATCH v2 3/3] target/hppa: Fix assemble_12a " Richard Henderson
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