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* [PATCH v5 0/2] Renesas R8A7743 CPG/MSSR clock support
@ 2016-11-02 21:53 ` Sergei Shtylyov
  0 siblings, 0 replies; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-02 21:53 UTC (permalink / raw)
  To: mturquette-rdvid1DuHRBWk0Htik3J/w,
	linux-clk-u79uwXL29TY76Z2rM5mHXA, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	devicetree-u79uwXL29TY76Z2rM5mHXA
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
	horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ

Hello.

   Here's the set of 2 patches against the 'clk-next' branch of CLK group's
'linux.git' repo. I've split them from the R-Car gen2 common support patch.
As the DT patches in the R8A7743/SK-RZG1M board support series depend on the
patch #1 of this series, it might make sense to merge this patch to the
'renesas.git' repo as well...

[1/2] ARM: shmobile: r8a7743: add CPG clock index macros
[2/2] clk: renesas: cpg-mssr: add R8A7743 support

MBR, Sergei

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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v5 0/2] Renesas R8A7743 CPG/MSSR clock support
@ 2016-11-02 21:53 ` Sergei Shtylyov
  0 siblings, 0 replies; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-02 21:53 UTC (permalink / raw)
  To: mturquette, linux-clk, sboyd, robh+dt, mark.rutland, devicetree
  Cc: linux-renesas-soc, horms+renesas

Hello.

   Here's the set of 2 patches against the 'clk-next' branch of CLK group's
'linux.git' repo. I've split them from the R-Car gen2 common support patch.
As the DT patches in the R8A7743/SK-RZG1M board support series depend on the
patch #1 of this series, it might make sense to merge this patch to the
'renesas.git' repo as well...

[1/2] ARM: shmobile: r8a7743: add CPG clock index macros
[2/2] clk: renesas: cpg-mssr: add R8A7743 support

MBR, Sergei

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v5 1/2] ARM: shmobile: r8a7743: add CPG clock index macros
  2016-11-02 21:53 ` Sergei Shtylyov
  (?)
@ 2016-11-02 21:57 ` Sergei Shtylyov
  2016-11-07 18:40   ` Geert Uytterhoeven
  -1 siblings, 1 reply; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-02 21:57 UTC (permalink / raw)
  To: robh+dt, mark.rutland, devicetree
  Cc: mturquette, linux-clk, sboyd, linux-renesas-soc, horms+renesas

Add macros usable by  the device tree sources to reference the R8A7743 CPG
clocks  by index. The data comes from the  table 7.2b in the revision 0.50
of the RZ/G Series User's Manual.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changes in version 4:
- added Geert's tag.

Changes in version 3:
- renumbered the #define's in order to match the R8A7791 CPG clocks;
- added the reference to the manual in the patch description.

Changes in version 2:
- reduced the macro value indentation.

 include/dt-bindings/clock/r8a7743-cpg-mssr.h |   43 +++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

Index: linux/include/dt-bindings/clock/r8a7743-cpg-mssr.h
===================================================================
--- /dev/null
+++ linux/include/dt-bindings/clock/r8a7743-cpg-mssr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7743 CPG Core Clocks */
+#define R8A7743_CLK_Z		0
+#define R8A7743_CLK_ZG		1
+#define R8A7743_CLK_ZTR		2
+#define R8A7743_CLK_ZTRD2	3
+#define R8A7743_CLK_ZT		4
+#define R8A7743_CLK_ZX		5
+#define R8A7743_CLK_ZS		6
+#define R8A7743_CLK_HP		7
+#define R8A7743_CLK_B		9
+#define R8A7743_CLK_LB		10
+#define R8A7743_CLK_P		11
+#define R8A7743_CLK_CL		12
+#define R8A7743_CLK_M2		13
+#define R8A7743_CLK_ZB3		15
+#define R8A7743_CLK_ZB3D2	16
+#define R8A7743_CLK_DDR		17
+#define R8A7743_CLK_SDH		18
+#define R8A7743_CLK_SD0		19
+#define R8A7743_CLK_SD2		20
+#define R8A7743_CLK_SD3		21
+#define R8A7743_CLK_MMC0	22
+#define R8A7743_CLK_MP		23
+#define R8A7743_CLK_QSPI	26
+#define R8A7743_CLK_CP		27
+#define R8A7743_CLK_RCAN	28
+#define R8A7743_CLK_R		29
+#define R8A7743_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v5 2/2] clk: renesas: cpg-mssr: add R8A7743 support
  2016-11-02 21:53 ` Sergei Shtylyov
@ 2016-11-02 21:59     ` Sergei Shtylyov
  -1 siblings, 0 replies; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-02 21:59 UTC (permalink / raw)
  To: mturquette-rdvid1DuHRBWk0Htik3J/w,
	linux-clk-u79uwXL29TY76Z2rM5mHXA, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	devicetree-u79uwXL29TY76Z2rM5mHXA
  Cc: linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
	horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ

Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
<geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

---
Changes in version 5:
- describe the Z clock as PLL0/VCO divided by 2.

Changes in version 4:
- made use of the new RST  driver's API to read the mode pins;
- cleaned  up the table copied from the manual, fixed the manual reference.

Changes in version 3:
- exchanged  Audio-DMAC0/1  entries in r8a7743_mod_clks[];
- renamed the I2C6 entry to IICDVFS;
- fixed the comment to the INTC-SYS entry in r8a7743_crit_mod_clks[];
- removed the useless EXTAL divisor check from r8a7743_cpg_mssr_init();
- added Rob's ACK and Geert's tag.

Changes in version 2:
- documented the R8A7743 device tree binding;
- fixed whitespace errors/warnings reported by checkpatch.pl;
- used  tabs instead of spaces for indentation;
- fixed the PLL3 column name in the PLL table.

 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt |    4 
 drivers/clk/renesas/Kconfig                                  |    1 
 drivers/clk/renesas/Makefile                                 |    1 
 drivers/clk/renesas/r8a7743-cpg-mssr.c                       |  270 +++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c                       |    6 
 drivers/clk/renesas/renesas-cpg-mssr.h                       |    1 
 6 files changed, 282 insertions(+), 1 deletion(-)

Index: renesas/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ renesas/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,6 +13,7 @@ They provide the following functionaliti
 
 Required Properties:
   - compatible: Must be one of:
+      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
 
@@ -22,7 +23,8 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
-      - "extal" (r8a7795, r8a7796)
+      - "extal" (r8a7743, r8a7795, r8a7796)
+      - "usb_extal" (r8a7743)
       - "extalr" (r8a7795, r8a7796)
 
   - #clock-cells: Must be 2
Index: renesas/drivers/clk/renesas/Kconfig
===================================================================
--- renesas.orig/drivers/clk/renesas/Kconfig
+++ renesas/drivers/clk/renesas/Kconfig
@@ -1,5 +1,6 @@
 config CLK_RENESAS_CPG_MSSR
 	bool
+	default y if ARCH_R8A7743
 	default y if ARCH_R8A7795
 	default y if ARCH_R8A7796
 
Index: renesas/drivers/clk/renesas/Makefile
===================================================================
--- renesas.orig/drivers/clk/renesas/Makefile
+++ renesas/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o
 obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7743)		+= r8a7743-cpg-mssr.o rcar-gen2-cpg.o
 obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-div6.o
Index: renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
===================================================================
--- /dev/null
+++ renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -0,0 +1,270 @@
+/*
+ * r8a7743 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation; of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A7743_CLK_OSC,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_USB_EXTAL,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL3,
+	CLK_PLL1_DIV2,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",	CLK_EXTAL),
+	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+	/* Core Clock Outputs */
+	DEF_BASE("lb",	 R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
+	DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
+	DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
+	DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
+	DEF_BASE("rcan", R8A7743_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
+
+	DEF_FIXED("z",	   R8A7743_CLK_Z,	CLK_PLL0,	    2, 1),
+	DEF_FIXED("zg",    R8A7743_CLK_ZG,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zx",    R8A7743_CLK_ZX,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zs",    R8A7743_CLK_ZS,	CLK_PLL1,	    6, 1),
+	DEF_FIXED("hp",    R8A7743_CLK_HP,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("b",     R8A7743_CLK_B,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("p",     R8A7743_CLK_P,	CLK_PLL1,	   24, 1),
+	DEF_FIXED("cl",    R8A7743_CLK_CL,	CLK_PLL1,	   48, 1),
+	DEF_FIXED("m2",    R8A7743_CLK_M2,	CLK_PLL1,	    8, 1),
+	DEF_FIXED("zb3",   R8A7743_CLK_ZB3,	CLK_PLL3,	    4, 1),
+	DEF_FIXED("zb3d2", R8A7743_CLK_ZB3D2,	CLK_PLL3,	    8, 1),
+	DEF_FIXED("ddr",   R8A7743_CLK_DDR,	CLK_PLL3,	    8, 1),
+	DEF_FIXED("mp",    R8A7743_CLK_MP,	CLK_PLL1_DIV2,     15, 1),
+	DEF_FIXED("cp",    R8A7743_CLK_CP,	CLK_EXTAL,	    2, 1),
+	DEF_FIXED("r",     R8A7743_CLK_R,	CLK_PLL1,	49152, 1),
+	DEF_FIXED("osc",   R8A7743_CLK_OSC,	CLK_PLL1,	12288, 1),
+
+	DEF_DIV6P1("sd2",  R8A7743_CLK_SD2,	CLK_PLL1_DIV2,	0x078),
+	DEF_DIV6P1("sd3",  R8A7743_CLK_SD3,	CLK_PLL1_DIV2,	0x26c),
+	DEF_DIV6P1("mmc0", R8A7743_CLK_MMC0,	CLK_PLL1_DIV2,	0x240),
+};
+
+static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
+	DEF_MOD("msiof0",	    0,	R8A7743_CLK_MP),
+	DEF_MOD("vcp0",		  101,	R8A7743_CLK_ZS),
+	DEF_MOD("vpc0",		  103,	R8A7743_CLK_ZS),
+	DEF_MOD("tmu1",		  111,	R8A7743_CLK_P),
+	DEF_MOD("3dg",		  112,	R8A7743_CLK_ZG),
+	DEF_MOD("2d-dmac",	  115,	R8A7743_CLK_ZS),
+	DEF_MOD("fdp1-1",	  118,	R8A7743_CLK_ZS),
+	DEF_MOD("fdp1-0",	  119,	R8A7743_CLK_ZS),
+	DEF_MOD("tmu3",		  121,	R8A7743_CLK_P),
+	DEF_MOD("tmu2",		  122,	R8A7743_CLK_P),
+	DEF_MOD("cmt0",		  124,	R8A7743_CLK_R),
+	DEF_MOD("tmu0",		  125,	R8A7743_CLK_CP),
+	DEF_MOD("vsp1du1",	  127,	R8A7743_CLK_ZS),
+	DEF_MOD("vsp1du0",	  128,	R8A7743_CLK_ZS),
+	DEF_MOD("vsp1-sy",	  131,	R8A7743_CLK_ZS),
+	DEF_MOD("scifa2",	  202,	R8A7743_CLK_MP),
+	DEF_MOD("scifa1",	  203,	R8A7743_CLK_MP),
+	DEF_MOD("scifa0",	  204,	R8A7743_CLK_MP),
+	DEF_MOD("msiof2",	  205,	R8A7743_CLK_MP),
+	DEF_MOD("scifb0",	  206,	R8A7743_CLK_MP),
+	DEF_MOD("scifb1",	  207,	R8A7743_CLK_MP),
+	DEF_MOD("msiof1",	  208,	R8A7743_CLK_MP),
+	DEF_MOD("scifb2",	  216,	R8A7743_CLK_MP),
+	DEF_MOD("sys-dmac1",	  218,	R8A7743_CLK_ZS),
+	DEF_MOD("sys-dmac0",	  219,	R8A7743_CLK_ZS),
+	DEF_MOD("tpu0",		  304,	R8A7743_CLK_CP),
+	DEF_MOD("sdhi3",	  311,	R8A7743_CLK_SD3),
+	DEF_MOD("sdhi2",	  312,	R8A7743_CLK_SD2),
+	DEF_MOD("sdhi0",	  314,	R8A7743_CLK_SD0),
+	DEF_MOD("mmcif0",	  315,	R8A7743_CLK_MMC0),
+	DEF_MOD("iic0",		  318,	R8A7743_CLK_HP),
+	DEF_MOD("pciec",	  319,	R8A7743_CLK_MP),
+	DEF_MOD("iic1",		  323,	R8A7743_CLK_HP),
+	DEF_MOD("usb3.0",	  328,	R8A7743_CLK_MP),
+	DEF_MOD("cmt1",		  329,	R8A7743_CLK_R),
+	DEF_MOD("usbhs-dmac0",	  330,	R8A7743_CLK_HP),
+	DEF_MOD("usbhs-dmac1",	  331,	R8A7743_CLK_HP),
+	DEF_MOD("irqc",		  407,	R8A7743_CLK_CP),
+	DEF_MOD("intc-sys",	  408,	R8A7743_CLK_ZS),
+	DEF_MOD("audio-dmac1",	  501,	R8A7743_CLK_HP),
+	DEF_MOD("audio-dmac0",	  502,	R8A7743_CLK_HP),
+	DEF_MOD("thermal",	  522,	CLK_EXTAL),
+	DEF_MOD("pwm",		  523,	R8A7743_CLK_P),
+	DEF_MOD("usb-ehci",	  703,	R8A7743_CLK_MP),
+	DEF_MOD("usbhs",	  704,	R8A7743_CLK_HP),
+	DEF_MOD("hscif2",	  713,	R8A7743_CLK_ZS),
+	DEF_MOD("scif5",	  714,	R8A7743_CLK_P),
+	DEF_MOD("scif4",	  715,	R8A7743_CLK_P),
+	DEF_MOD("hscif1",	  716,	R8A7743_CLK_ZS),
+	DEF_MOD("hscif0",	  717,	R8A7743_CLK_ZS),
+	DEF_MOD("scif3",	  718,	R8A7743_CLK_P),
+	DEF_MOD("scif2",	  719,	R8A7743_CLK_P),
+	DEF_MOD("scif1",	  720,	R8A7743_CLK_P),
+	DEF_MOD("scif0",	  721,	R8A7743_CLK_P),
+	DEF_MOD("du1",		  723,	R8A7743_CLK_ZX),
+	DEF_MOD("du0",		  724,	R8A7743_CLK_ZX),
+	DEF_MOD("lvds0",	  726,	R8A7743_CLK_ZX),
+	DEF_MOD("ipmmu-sgx",	  800,	R8A7743_CLK_ZX),
+	DEF_MOD("vin2",		  809,	R8A7743_CLK_ZG),
+	DEF_MOD("vin1",		  810,	R8A7743_CLK_ZG),
+	DEF_MOD("vin0",		  811,	R8A7743_CLK_ZG),
+	DEF_MOD("etheravb",	  812,	R8A7743_CLK_HP),
+	DEF_MOD("ether",	  813,	R8A7743_CLK_P),
+	DEF_MOD("sata1",	  814,	R8A7743_CLK_ZS),
+	DEF_MOD("sata0",	  815,	R8A7743_CLK_ZS),
+	DEF_MOD("gpio7",	  904,	R8A7743_CLK_CP),
+	DEF_MOD("gpio6",	  905,	R8A7743_CLK_CP),
+	DEF_MOD("gpio5",	  907,	R8A7743_CLK_CP),
+	DEF_MOD("gpio4",	  908,	R8A7743_CLK_CP),
+	DEF_MOD("gpio3",	  909,	R8A7743_CLK_CP),
+	DEF_MOD("gpio2",	  910,	R8A7743_CLK_CP),
+	DEF_MOD("gpio1",	  911,	R8A7743_CLK_CP),
+	DEF_MOD("gpio0",	  912,	R8A7743_CLK_CP),
+	DEF_MOD("can1",		  915,	R8A7743_CLK_P),
+	DEF_MOD("can0",		  916,	R8A7743_CLK_P),
+	DEF_MOD("qspi_mod",	  917,	R8A7743_CLK_QSPI),
+	DEF_MOD("i2c5",		  925,	R8A7743_CLK_HP),
+	DEF_MOD("iicdvfs",	  926,	R8A7743_CLK_CP),
+	DEF_MOD("i2c4",		  927,	R8A7743_CLK_HP),
+	DEF_MOD("i2c3",		  928,	R8A7743_CLK_HP),
+	DEF_MOD("i2c2",		  929,	R8A7743_CLK_HP),
+	DEF_MOD("i2c1",		  930,	R8A7743_CLK_HP),
+	DEF_MOD("i2c0",		  931,	R8A7743_CLK_HP),
+	DEF_MOD("ssi-all",	 1005,	R8A7743_CLK_P),
+	DEF_MOD("ssi9",		 1006,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi8",		 1007,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi7",		 1008,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi6",		 1009,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi5",		 1010,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi4",		 1011,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi3",		 1012,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi2",		 1013,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi1",		 1014,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi0",		 1015,	MOD_CLK_ID(1005)),
+	DEF_MOD("scu-all",	 1017,	R8A7743_CLK_P),
+	DEF_MOD("scu-dvc1",	 1018,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-dvc0",	 1019,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu1-mix1", 1020,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu0-mix0", 1021,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src9",	 1022,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src8",	 1023,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src7",	 1024,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src6",	 1025,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src5",	 1026,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src4",	 1027,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src3",	 1028,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src2",	 1029,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src1",	 1030,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src0",	 1031,	MOD_CLK_ID(1017)),
+	DEF_MOD("scifa3",	 1106,	R8A7743_CLK_MP),
+	DEF_MOD("scifa4",	 1107,	R8A7743_CLK_MP),
+	DEF_MOD("scifa5",	 1108,	R8A7743_CLK_MP),
+};
+
+static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
+	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ *    MD	EXTAL		PLL0	PLL1	PLL3
+ * 14 13 19	(MHz)		*1	*1
+ *---------------------------------------------------
+ * 0  0  0	15		x172/2	x208/2	x106
+ * 0  0  1	15		x172/2	x208/2	x88
+ * 0  1  0	20		x130/2	x156/2	x80
+ * 0  1  1	20		x130/2	x156/2	x66
+ * 1  0  0	26 / 2		x200/2	x240/2	x122
+ * 1  0  1	26 / 2		x200/2	x240/2	x102
+ * 1  1  0	30 / 2		x172/2	x208/2	x106
+ * 1  1  1	30 / 2		x172/2	x208/2	x88
+ *
+ * *1 :	Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
+					 (((md) & BIT(13)) >> 12) | \
+					 (((md) & BIT(19)) >> 19))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+	/* EXTAL div	PLL1 mult	PLL3 mult */
+	{ 1,		208,		106,	},
+	{ 1,		208,		88,	},
+	{ 1,		156,		80,	},
+	{ 1,		156,		66,	},
+	{ 2,		240,		122,	},
+	{ 2,		240,		102,	},
+	{ 2,		208,		106,	},
+	{ 2,		208,		88,	},
+};
+
+static int __init r8a7743_cpg_mssr_init(struct device *dev)
+{
+	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+	u32 cpg_mode;
+	int error;
+
+	error = rcar_rst_read_mode_pins(&cpg_mode);
+	if (error)
+		return error;
+
+	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+	return rcar_gen2_cpg_init(cpg_pll_config);
+}
+
+const struct cpg_mssr_info r8a7743_cpg_mssr_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r8a7743_core_clks,
+	.num_core_clks = ARRAY_SIZE(r8a7743_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r8a7743_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r8a7743_mod_clks),
+	.num_hw_mod_clks = 12 * 32,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r8a7743_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r8a7743_crit_mod_clks),
+
+	/* Callbacks */
+	.init = r8a7743_cpg_mssr_init,
+	.cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
Index: renesas/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- renesas.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ renesas/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -503,6 +503,12 @@ static int __init cpg_mssr_add_clk_domai
 }
 
 static const struct of_device_id cpg_mssr_match[] = {
+#ifdef CONFIG_ARCH_R8A7743
+	{
+		.compatible = "renesas,r8a7743-cpg-mssr",
+		.data = &r8a7743_cpg_mssr_info,
+	},
+#endif
 #ifdef CONFIG_ARCH_R8A7795
 	{
 		.compatible = "renesas,r8a7795-cpg-mssr",
Index: renesas/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- renesas.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ renesas/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -130,6 +130,7 @@ struct cpg_mssr_info {
 					struct clk **clks, void __iomem *base);
 };
 
+extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
 #endif

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* [PATCH v5 2/2] clk: renesas: cpg-mssr: add R8A7743 support
@ 2016-11-02 21:59     ` Sergei Shtylyov
  0 siblings, 0 replies; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-02 21:59 UTC (permalink / raw)
  To: mturquette, linux-clk, sboyd, robh+dt, mark.rutland, devicetree
  Cc: linux-renesas-soc, horms+renesas

Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
<geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
Changes in version 5:
- describe the Z clock as PLL0/VCO divided by 2.

Changes in version 4:
- made use of the new RST  driver's API to read the mode pins;
- cleaned  up the table copied from the manual, fixed the manual reference.

Changes in version 3:
- exchanged  Audio-DMAC0/1  entries in r8a7743_mod_clks[];
- renamed the I2C6 entry to IICDVFS;
- fixed the comment to the INTC-SYS entry in r8a7743_crit_mod_clks[];
- removed the useless EXTAL divisor check from r8a7743_cpg_mssr_init();
- added Rob's ACK and Geert's tag.

Changes in version 2:
- documented the R8A7743 device tree binding;
- fixed whitespace errors/warnings reported by checkpatch.pl;
- used  tabs instead of spaces for indentation;
- fixed the PLL3 column name in the PLL table.

 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt |    4 
 drivers/clk/renesas/Kconfig                                  |    1 
 drivers/clk/renesas/Makefile                                 |    1 
 drivers/clk/renesas/r8a7743-cpg-mssr.c                       |  270 +++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c                       |    6 
 drivers/clk/renesas/renesas-cpg-mssr.h                       |    1 
 6 files changed, 282 insertions(+), 1 deletion(-)

Index: renesas/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ renesas/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,6 +13,7 @@ They provide the following functionaliti
 
 Required Properties:
   - compatible: Must be one of:
+      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
 
@@ -22,7 +23,8 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
-      - "extal" (r8a7795, r8a7796)
+      - "extal" (r8a7743, r8a7795, r8a7796)
+      - "usb_extal" (r8a7743)
       - "extalr" (r8a7795, r8a7796)
 
   - #clock-cells: Must be 2
Index: renesas/drivers/clk/renesas/Kconfig
===================================================================
--- renesas.orig/drivers/clk/renesas/Kconfig
+++ renesas/drivers/clk/renesas/Kconfig
@@ -1,5 +1,6 @@
 config CLK_RENESAS_CPG_MSSR
 	bool
+	default y if ARCH_R8A7743
 	default y if ARCH_R8A7795
 	default y if ARCH_R8A7796
 
Index: renesas/drivers/clk/renesas/Makefile
===================================================================
--- renesas.orig/drivers/clk/renesas/Makefile
+++ renesas/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o
 obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7743)		+= r8a7743-cpg-mssr.o rcar-gen2-cpg.o
 obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-div6.o
Index: renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
===================================================================
--- /dev/null
+++ renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -0,0 +1,270 @@
+/*
+ * r8a7743 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation; of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A7743_CLK_OSC,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_USB_EXTAL,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL3,
+	CLK_PLL1_DIV2,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",	CLK_EXTAL),
+	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+	/* Core Clock Outputs */
+	DEF_BASE("lb",	 R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
+	DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
+	DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
+	DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
+	DEF_BASE("rcan", R8A7743_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
+
+	DEF_FIXED("z",	   R8A7743_CLK_Z,	CLK_PLL0,	    2, 1),
+	DEF_FIXED("zg",    R8A7743_CLK_ZG,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zx",    R8A7743_CLK_ZX,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zs",    R8A7743_CLK_ZS,	CLK_PLL1,	    6, 1),
+	DEF_FIXED("hp",    R8A7743_CLK_HP,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("b",     R8A7743_CLK_B,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("p",     R8A7743_CLK_P,	CLK_PLL1,	   24, 1),
+	DEF_FIXED("cl",    R8A7743_CLK_CL,	CLK_PLL1,	   48, 1),
+	DEF_FIXED("m2",    R8A7743_CLK_M2,	CLK_PLL1,	    8, 1),
+	DEF_FIXED("zb3",   R8A7743_CLK_ZB3,	CLK_PLL3,	    4, 1),
+	DEF_FIXED("zb3d2", R8A7743_CLK_ZB3D2,	CLK_PLL3,	    8, 1),
+	DEF_FIXED("ddr",   R8A7743_CLK_DDR,	CLK_PLL3,	    8, 1),
+	DEF_FIXED("mp",    R8A7743_CLK_MP,	CLK_PLL1_DIV2,     15, 1),
+	DEF_FIXED("cp",    R8A7743_CLK_CP,	CLK_EXTAL,	    2, 1),
+	DEF_FIXED("r",     R8A7743_CLK_R,	CLK_PLL1,	49152, 1),
+	DEF_FIXED("osc",   R8A7743_CLK_OSC,	CLK_PLL1,	12288, 1),
+
+	DEF_DIV6P1("sd2",  R8A7743_CLK_SD2,	CLK_PLL1_DIV2,	0x078),
+	DEF_DIV6P1("sd3",  R8A7743_CLK_SD3,	CLK_PLL1_DIV2,	0x26c),
+	DEF_DIV6P1("mmc0", R8A7743_CLK_MMC0,	CLK_PLL1_DIV2,	0x240),
+};
+
+static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
+	DEF_MOD("msiof0",	    0,	R8A7743_CLK_MP),
+	DEF_MOD("vcp0",		  101,	R8A7743_CLK_ZS),
+	DEF_MOD("vpc0",		  103,	R8A7743_CLK_ZS),
+	DEF_MOD("tmu1",		  111,	R8A7743_CLK_P),
+	DEF_MOD("3dg",		  112,	R8A7743_CLK_ZG),
+	DEF_MOD("2d-dmac",	  115,	R8A7743_CLK_ZS),
+	DEF_MOD("fdp1-1",	  118,	R8A7743_CLK_ZS),
+	DEF_MOD("fdp1-0",	  119,	R8A7743_CLK_ZS),
+	DEF_MOD("tmu3",		  121,	R8A7743_CLK_P),
+	DEF_MOD("tmu2",		  122,	R8A7743_CLK_P),
+	DEF_MOD("cmt0",		  124,	R8A7743_CLK_R),
+	DEF_MOD("tmu0",		  125,	R8A7743_CLK_CP),
+	DEF_MOD("vsp1du1",	  127,	R8A7743_CLK_ZS),
+	DEF_MOD("vsp1du0",	  128,	R8A7743_CLK_ZS),
+	DEF_MOD("vsp1-sy",	  131,	R8A7743_CLK_ZS),
+	DEF_MOD("scifa2",	  202,	R8A7743_CLK_MP),
+	DEF_MOD("scifa1",	  203,	R8A7743_CLK_MP),
+	DEF_MOD("scifa0",	  204,	R8A7743_CLK_MP),
+	DEF_MOD("msiof2",	  205,	R8A7743_CLK_MP),
+	DEF_MOD("scifb0",	  206,	R8A7743_CLK_MP),
+	DEF_MOD("scifb1",	  207,	R8A7743_CLK_MP),
+	DEF_MOD("msiof1",	  208,	R8A7743_CLK_MP),
+	DEF_MOD("scifb2",	  216,	R8A7743_CLK_MP),
+	DEF_MOD("sys-dmac1",	  218,	R8A7743_CLK_ZS),
+	DEF_MOD("sys-dmac0",	  219,	R8A7743_CLK_ZS),
+	DEF_MOD("tpu0",		  304,	R8A7743_CLK_CP),
+	DEF_MOD("sdhi3",	  311,	R8A7743_CLK_SD3),
+	DEF_MOD("sdhi2",	  312,	R8A7743_CLK_SD2),
+	DEF_MOD("sdhi0",	  314,	R8A7743_CLK_SD0),
+	DEF_MOD("mmcif0",	  315,	R8A7743_CLK_MMC0),
+	DEF_MOD("iic0",		  318,	R8A7743_CLK_HP),
+	DEF_MOD("pciec",	  319,	R8A7743_CLK_MP),
+	DEF_MOD("iic1",		  323,	R8A7743_CLK_HP),
+	DEF_MOD("usb3.0",	  328,	R8A7743_CLK_MP),
+	DEF_MOD("cmt1",		  329,	R8A7743_CLK_R),
+	DEF_MOD("usbhs-dmac0",	  330,	R8A7743_CLK_HP),
+	DEF_MOD("usbhs-dmac1",	  331,	R8A7743_CLK_HP),
+	DEF_MOD("irqc",		  407,	R8A7743_CLK_CP),
+	DEF_MOD("intc-sys",	  408,	R8A7743_CLK_ZS),
+	DEF_MOD("audio-dmac1",	  501,	R8A7743_CLK_HP),
+	DEF_MOD("audio-dmac0",	  502,	R8A7743_CLK_HP),
+	DEF_MOD("thermal",	  522,	CLK_EXTAL),
+	DEF_MOD("pwm",		  523,	R8A7743_CLK_P),
+	DEF_MOD("usb-ehci",	  703,	R8A7743_CLK_MP),
+	DEF_MOD("usbhs",	  704,	R8A7743_CLK_HP),
+	DEF_MOD("hscif2",	  713,	R8A7743_CLK_ZS),
+	DEF_MOD("scif5",	  714,	R8A7743_CLK_P),
+	DEF_MOD("scif4",	  715,	R8A7743_CLK_P),
+	DEF_MOD("hscif1",	  716,	R8A7743_CLK_ZS),
+	DEF_MOD("hscif0",	  717,	R8A7743_CLK_ZS),
+	DEF_MOD("scif3",	  718,	R8A7743_CLK_P),
+	DEF_MOD("scif2",	  719,	R8A7743_CLK_P),
+	DEF_MOD("scif1",	  720,	R8A7743_CLK_P),
+	DEF_MOD("scif0",	  721,	R8A7743_CLK_P),
+	DEF_MOD("du1",		  723,	R8A7743_CLK_ZX),
+	DEF_MOD("du0",		  724,	R8A7743_CLK_ZX),
+	DEF_MOD("lvds0",	  726,	R8A7743_CLK_ZX),
+	DEF_MOD("ipmmu-sgx",	  800,	R8A7743_CLK_ZX),
+	DEF_MOD("vin2",		  809,	R8A7743_CLK_ZG),
+	DEF_MOD("vin1",		  810,	R8A7743_CLK_ZG),
+	DEF_MOD("vin0",		  811,	R8A7743_CLK_ZG),
+	DEF_MOD("etheravb",	  812,	R8A7743_CLK_HP),
+	DEF_MOD("ether",	  813,	R8A7743_CLK_P),
+	DEF_MOD("sata1",	  814,	R8A7743_CLK_ZS),
+	DEF_MOD("sata0",	  815,	R8A7743_CLK_ZS),
+	DEF_MOD("gpio7",	  904,	R8A7743_CLK_CP),
+	DEF_MOD("gpio6",	  905,	R8A7743_CLK_CP),
+	DEF_MOD("gpio5",	  907,	R8A7743_CLK_CP),
+	DEF_MOD("gpio4",	  908,	R8A7743_CLK_CP),
+	DEF_MOD("gpio3",	  909,	R8A7743_CLK_CP),
+	DEF_MOD("gpio2",	  910,	R8A7743_CLK_CP),
+	DEF_MOD("gpio1",	  911,	R8A7743_CLK_CP),
+	DEF_MOD("gpio0",	  912,	R8A7743_CLK_CP),
+	DEF_MOD("can1",		  915,	R8A7743_CLK_P),
+	DEF_MOD("can0",		  916,	R8A7743_CLK_P),
+	DEF_MOD("qspi_mod",	  917,	R8A7743_CLK_QSPI),
+	DEF_MOD("i2c5",		  925,	R8A7743_CLK_HP),
+	DEF_MOD("iicdvfs",	  926,	R8A7743_CLK_CP),
+	DEF_MOD("i2c4",		  927,	R8A7743_CLK_HP),
+	DEF_MOD("i2c3",		  928,	R8A7743_CLK_HP),
+	DEF_MOD("i2c2",		  929,	R8A7743_CLK_HP),
+	DEF_MOD("i2c1",		  930,	R8A7743_CLK_HP),
+	DEF_MOD("i2c0",		  931,	R8A7743_CLK_HP),
+	DEF_MOD("ssi-all",	 1005,	R8A7743_CLK_P),
+	DEF_MOD("ssi9",		 1006,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi8",		 1007,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi7",		 1008,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi6",		 1009,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi5",		 1010,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi4",		 1011,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi3",		 1012,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi2",		 1013,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi1",		 1014,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi0",		 1015,	MOD_CLK_ID(1005)),
+	DEF_MOD("scu-all",	 1017,	R8A7743_CLK_P),
+	DEF_MOD("scu-dvc1",	 1018,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-dvc0",	 1019,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu1-mix1", 1020,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu0-mix0", 1021,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src9",	 1022,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src8",	 1023,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src7",	 1024,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src6",	 1025,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src5",	 1026,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src4",	 1027,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src3",	 1028,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src2",	 1029,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src1",	 1030,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src0",	 1031,	MOD_CLK_ID(1017)),
+	DEF_MOD("scifa3",	 1106,	R8A7743_CLK_MP),
+	DEF_MOD("scifa4",	 1107,	R8A7743_CLK_MP),
+	DEF_MOD("scifa5",	 1108,	R8A7743_CLK_MP),
+};
+
+static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
+	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ *    MD	EXTAL		PLL0	PLL1	PLL3
+ * 14 13 19	(MHz)		*1	*1
+ *---------------------------------------------------
+ * 0  0  0	15		x172/2	x208/2	x106
+ * 0  0  1	15		x172/2	x208/2	x88
+ * 0  1  0	20		x130/2	x156/2	x80
+ * 0  1  1	20		x130/2	x156/2	x66
+ * 1  0  0	26 / 2		x200/2	x240/2	x122
+ * 1  0  1	26 / 2		x200/2	x240/2	x102
+ * 1  1  0	30 / 2		x172/2	x208/2	x106
+ * 1  1  1	30 / 2		x172/2	x208/2	x88
+ *
+ * *1 :	Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
+					 (((md) & BIT(13)) >> 12) | \
+					 (((md) & BIT(19)) >> 19))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+	/* EXTAL div	PLL1 mult	PLL3 mult */
+	{ 1,		208,		106,	},
+	{ 1,		208,		88,	},
+	{ 1,		156,		80,	},
+	{ 1,		156,		66,	},
+	{ 2,		240,		122,	},
+	{ 2,		240,		102,	},
+	{ 2,		208,		106,	},
+	{ 2,		208,		88,	},
+};
+
+static int __init r8a7743_cpg_mssr_init(struct device *dev)
+{
+	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+	u32 cpg_mode;
+	int error;
+
+	error = rcar_rst_read_mode_pins(&cpg_mode);
+	if (error)
+		return error;
+
+	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+	return rcar_gen2_cpg_init(cpg_pll_config);
+}
+
+const struct cpg_mssr_info r8a7743_cpg_mssr_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r8a7743_core_clks,
+	.num_core_clks = ARRAY_SIZE(r8a7743_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r8a7743_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r8a7743_mod_clks),
+	.num_hw_mod_clks = 12 * 32,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r8a7743_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r8a7743_crit_mod_clks),
+
+	/* Callbacks */
+	.init = r8a7743_cpg_mssr_init,
+	.cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
Index: renesas/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- renesas.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ renesas/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -503,6 +503,12 @@ static int __init cpg_mssr_add_clk_domai
 }
 
 static const struct of_device_id cpg_mssr_match[] = {
+#ifdef CONFIG_ARCH_R8A7743
+	{
+		.compatible = "renesas,r8a7743-cpg-mssr",
+		.data = &r8a7743_cpg_mssr_info,
+	},
+#endif
 #ifdef CONFIG_ARCH_R8A7795
 	{
 		.compatible = "renesas,r8a7795-cpg-mssr",
Index: renesas/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- renesas.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ renesas/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -130,6 +130,7 @@ struct cpg_mssr_info {
 					struct clk **clks, void __iomem *base);
 };
 
+extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
 #endif

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 2/2] clk: renesas: cpg-mssr: add R8A7743 support
  2016-11-02 21:59     ` Sergei Shtylyov
  (?)
@ 2016-11-07 10:09     ` Geert Uytterhoeven
  2016-11-07 10:35       ` Sergei Shtylyov
  -1 siblings, 1 reply; 10+ messages in thread
From: Geert Uytterhoeven @ 2016-11-07 10:09 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Michael Turquette, linux-clk, Stephen Boyd, Rob Herring,
	Mark Rutland, devicetree, Linux-Renesas, Simon Horman

Hi Sergei,

On Wed, Nov 2, 2016 at 10:59 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
> <geert+renesas@glider.be>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 5:
> - describe the Z clock as PLL0/VCO divided by 2.

Why did you do that?

> --- /dev/null
> +++ renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
> @@ -0,0 +1,270 @@

> +       DEF_FIXED("z",     R8A7743_CLK_Z,       CLK_PLL0,           2, 1),

FTR, previous version had

       DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,     CLK_PLL0),

which made the "z" clock configurable.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 2/2] clk: renesas: cpg-mssr: add R8A7743 support
  2016-11-07 10:09     ` Geert Uytterhoeven
@ 2016-11-07 10:35       ` Sergei Shtylyov
  0 siblings, 0 replies; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-07 10:35 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Michael Turquette, linux-clk, Stephen Boyd, Rob Herring,
	Mark Rutland, devicetree, Linux-Renesas, Simon Horman

Hello.

On 11/7/2016 1:09 PM, Geert Uytterhoeven wrote:

>> Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
>> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
>> (and RZ/G) code.
>>
>> Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
>> <geert+renesas@glider.be>.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>> ---
>> Changes in version 5:
>> - describe the Z clock as PLL0/VCO divided by 2.
>
> Why did you do that?

    I did it because I removed the divisor-by-2 from PLL0.

>> --- /dev/null
>> +++ renesas/drivers/clk/renesas/r8a7743-cpg-mssr.c
>> @@ -0,0 +1,270 @@
>
>> +       DEF_FIXED("z",     R8A7743_CLK_Z,       CLK_PLL0,           2, 1),
>
> FTR, previous version had
>
>        DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,     CLK_PLL0),
>
> which made the "z" clock configurable.

     I see your point -- I should have included the divisor-by-2 into the 
common R-Car gen2 driver code instead...

> Gr{oetje,eeting}s,
>
>                         Geert

MBR, Sergei


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v5 1/2] ARM: shmobile: r8a7743: add CPG clock index macros
  2016-11-02 21:57 ` [PATCH v5 1/2] ARM: shmobile: r8a7743: add CPG clock index macros Sergei Shtylyov
@ 2016-11-07 18:40   ` Geert Uytterhoeven
  0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2016-11-07 18:40 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Rob Herring, Mark Rutland, devicetree, Michael Turquette,
	linux-clk, Stephen Boyd, Linux-Renesas, Simon Horman

On Wed, Nov 2, 2016 at 10:57 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add macros usable by  the device tree sources to reference the R8A7743 CPG
> clocks  by index. The data comes from the  table 7.2b in the revision 0.50
> of the RZ/G Series User's Manual.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Applied and included in second clk-renesas-for-v4.10 pull request.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v6] clk: renesas: cpg-mssr: add R8A7743 support
  2016-11-02 21:53 ` Sergei Shtylyov
                   ` (2 preceding siblings ...)
  (?)
@ 2016-11-08 21:21 ` Sergei Shtylyov
  2016-11-10 12:52   ` Geert Uytterhoeven
  -1 siblings, 1 reply; 10+ messages in thread
From: Sergei Shtylyov @ 2016-11-08 21:21 UTC (permalink / raw)
  To: mturquette, linux-clk, sboyd, robh+dt, mark.rutland, devicetree
  Cc: linux-renesas-soc, horms+renesas

Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
<geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

---
This patch is against the 'clk-next' branch of CLK group's 'linux.git' repo.
It depends on the common R-Car gen2 (and RZ/G) support just posted.

Changes in version 6:
- passed the PLL0 divisor to rcar_gen2_cpg_init();
- undid  the version 5 changes.

Changes in version 5:
- described the Z clock as PLL0/VCO divided by 2.

Changes in version 4:
- made use of the new RST  driver's API to read the mode pins;
- cleaned  up the table copied from the manual, fixed the manual reference.

Changes in version 3:
- exchanged  Audio-DMAC0/1  entries in r8a7743_mod_clks[];
- renamed the I2C6 entry to IICDVFS;
- fixed the comment to the INTC-SYS entry in r8a7743_crit_mod_clks[];
- removed the useless EXTAL divisor check from r8a7743_cpg_mssr_init();
- added Rob's ACK and Geert's tag.

Changes in version 2:
- documented the R8A7743 device tree binding;
- fixed whitespace errors/warnings reported by checkpatch.pl;
- used  tabs instead of spaces for indentation;
- fixed the PLL3 column name in the PLL table.

 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt |    4 
 drivers/clk/renesas/Kconfig                                  |    1 
 drivers/clk/renesas/Makefile                                 |    1 
 drivers/clk/renesas/r8a7743-cpg-mssr.c                       |  270 +++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c                       |    6 
 drivers/clk/renesas/renesas-cpg-mssr.h                       |    1 
 6 files changed, 282 insertions(+), 1 deletion(-)

Index: linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
--- linux.orig/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,6 +13,7 @@ They provide the following functionaliti
 
 Required Properties:
   - compatible: Must be one of:
+      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
 
@@ -22,7 +23,8 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
-      - "extal" (r8a7795, r8a7796)
+      - "extal" (r8a7743, r8a7795, r8a7796)
+      - "usb_extal" (r8a7743)
       - "extalr" (r8a7795, r8a7796)
 
   - #clock-cells: Must be 2
Index: linux/drivers/clk/renesas/Kconfig
===================================================================
--- linux.orig/drivers/clk/renesas/Kconfig
+++ linux/drivers/clk/renesas/Kconfig
@@ -1,5 +1,6 @@
 config CLK_RENESAS_CPG_MSSR
 	bool
+	default y if ARCH_R8A7743
 	default y if ARCH_R8A7795
 	default y if ARCH_R8A7796
 
Index: linux/drivers/clk/renesas/Makefile
===================================================================
--- linux.orig/drivers/clk/renesas/Makefile
+++ linux/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o
 obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7743)		+= r8a7743-cpg-mssr.o rcar-gen2-cpg.o
 obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-div6.o
Index: linux/drivers/clk/renesas/r8a7743-cpg-mssr.c
===================================================================
--- /dev/null
+++ linux/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -0,0 +1,270 @@
+/*
+ * r8a7743 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation; of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A7743_CLK_OSC,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_USB_EXTAL,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL3,
+	CLK_PLL1_DIV2,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",	CLK_EXTAL),
+	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+	/* Core Clock Outputs */
+	DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,     CLK_PLL0),
+	DEF_BASE("lb",	 R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),
+	DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
+	DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
+	DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
+	DEF_BASE("rcan", R8A7743_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
+
+	DEF_FIXED("zg",    R8A7743_CLK_ZG,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zx",    R8A7743_CLK_ZX,	CLK_PLL1,	    3, 1),
+	DEF_FIXED("zs",    R8A7743_CLK_ZS,	CLK_PLL1,	    6, 1),
+	DEF_FIXED("hp",    R8A7743_CLK_HP,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("b",     R8A7743_CLK_B,	CLK_PLL1,	   12, 1),
+	DEF_FIXED("p",     R8A7743_CLK_P,	CLK_PLL1,	   24, 1),
+	DEF_FIXED("cl",    R8A7743_CLK_CL,	CLK_PLL1,	   48, 1),
+	DEF_FIXED("m2",    R8A7743_CLK_M2,	CLK_PLL1,	    8, 1),
+	DEF_FIXED("zb3",   R8A7743_CLK_ZB3,	CLK_PLL3,	    4, 1),
+	DEF_FIXED("zb3d2", R8A7743_CLK_ZB3D2,	CLK_PLL3,	    8, 1),
+	DEF_FIXED("ddr",   R8A7743_CLK_DDR,	CLK_PLL3,	    8, 1),
+	DEF_FIXED("mp",    R8A7743_CLK_MP,	CLK_PLL1_DIV2,     15, 1),
+	DEF_FIXED("cp",    R8A7743_CLK_CP,	CLK_EXTAL,	    2, 1),
+	DEF_FIXED("r",     R8A7743_CLK_R,	CLK_PLL1,	49152, 1),
+	DEF_FIXED("osc",   R8A7743_CLK_OSC,	CLK_PLL1,	12288, 1),
+
+	DEF_DIV6P1("sd2",  R8A7743_CLK_SD2,	CLK_PLL1_DIV2,	0x078),
+	DEF_DIV6P1("sd3",  R8A7743_CLK_SD3,	CLK_PLL1_DIV2,	0x26c),
+	DEF_DIV6P1("mmc0", R8A7743_CLK_MMC0,	CLK_PLL1_DIV2,	0x240),
+};
+
+static const struct mssr_mod_clk r8a7743_mod_clks[] __initconst = {
+	DEF_MOD("msiof0",	    0,	R8A7743_CLK_MP),
+	DEF_MOD("vcp0",		  101,	R8A7743_CLK_ZS),
+	DEF_MOD("vpc0",		  103,	R8A7743_CLK_ZS),
+	DEF_MOD("tmu1",		  111,	R8A7743_CLK_P),
+	DEF_MOD("3dg",		  112,	R8A7743_CLK_ZG),
+	DEF_MOD("2d-dmac",	  115,	R8A7743_CLK_ZS),
+	DEF_MOD("fdp1-1",	  118,	R8A7743_CLK_ZS),
+	DEF_MOD("fdp1-0",	  119,	R8A7743_CLK_ZS),
+	DEF_MOD("tmu3",		  121,	R8A7743_CLK_P),
+	DEF_MOD("tmu2",		  122,	R8A7743_CLK_P),
+	DEF_MOD("cmt0",		  124,	R8A7743_CLK_R),
+	DEF_MOD("tmu0",		  125,	R8A7743_CLK_CP),
+	DEF_MOD("vsp1du1",	  127,	R8A7743_CLK_ZS),
+	DEF_MOD("vsp1du0",	  128,	R8A7743_CLK_ZS),
+	DEF_MOD("vsp1-sy",	  131,	R8A7743_CLK_ZS),
+	DEF_MOD("scifa2",	  202,	R8A7743_CLK_MP),
+	DEF_MOD("scifa1",	  203,	R8A7743_CLK_MP),
+	DEF_MOD("scifa0",	  204,	R8A7743_CLK_MP),
+	DEF_MOD("msiof2",	  205,	R8A7743_CLK_MP),
+	DEF_MOD("scifb0",	  206,	R8A7743_CLK_MP),
+	DEF_MOD("scifb1",	  207,	R8A7743_CLK_MP),
+	DEF_MOD("msiof1",	  208,	R8A7743_CLK_MP),
+	DEF_MOD("scifb2",	  216,	R8A7743_CLK_MP),
+	DEF_MOD("sys-dmac1",	  218,	R8A7743_CLK_ZS),
+	DEF_MOD("sys-dmac0",	  219,	R8A7743_CLK_ZS),
+	DEF_MOD("tpu0",		  304,	R8A7743_CLK_CP),
+	DEF_MOD("sdhi3",	  311,	R8A7743_CLK_SD3),
+	DEF_MOD("sdhi2",	  312,	R8A7743_CLK_SD2),
+	DEF_MOD("sdhi0",	  314,	R8A7743_CLK_SD0),
+	DEF_MOD("mmcif0",	  315,	R8A7743_CLK_MMC0),
+	DEF_MOD("iic0",		  318,	R8A7743_CLK_HP),
+	DEF_MOD("pciec",	  319,	R8A7743_CLK_MP),
+	DEF_MOD("iic1",		  323,	R8A7743_CLK_HP),
+	DEF_MOD("usb3.0",	  328,	R8A7743_CLK_MP),
+	DEF_MOD("cmt1",		  329,	R8A7743_CLK_R),
+	DEF_MOD("usbhs-dmac0",	  330,	R8A7743_CLK_HP),
+	DEF_MOD("usbhs-dmac1",	  331,	R8A7743_CLK_HP),
+	DEF_MOD("irqc",		  407,	R8A7743_CLK_CP),
+	DEF_MOD("intc-sys",	  408,	R8A7743_CLK_ZS),
+	DEF_MOD("audio-dmac1",	  501,	R8A7743_CLK_HP),
+	DEF_MOD("audio-dmac0",	  502,	R8A7743_CLK_HP),
+	DEF_MOD("thermal",	  522,	CLK_EXTAL),
+	DEF_MOD("pwm",		  523,	R8A7743_CLK_P),
+	DEF_MOD("usb-ehci",	  703,	R8A7743_CLK_MP),
+	DEF_MOD("usbhs",	  704,	R8A7743_CLK_HP),
+	DEF_MOD("hscif2",	  713,	R8A7743_CLK_ZS),
+	DEF_MOD("scif5",	  714,	R8A7743_CLK_P),
+	DEF_MOD("scif4",	  715,	R8A7743_CLK_P),
+	DEF_MOD("hscif1",	  716,	R8A7743_CLK_ZS),
+	DEF_MOD("hscif0",	  717,	R8A7743_CLK_ZS),
+	DEF_MOD("scif3",	  718,	R8A7743_CLK_P),
+	DEF_MOD("scif2",	  719,	R8A7743_CLK_P),
+	DEF_MOD("scif1",	  720,	R8A7743_CLK_P),
+	DEF_MOD("scif0",	  721,	R8A7743_CLK_P),
+	DEF_MOD("du1",		  723,	R8A7743_CLK_ZX),
+	DEF_MOD("du0",		  724,	R8A7743_CLK_ZX),
+	DEF_MOD("lvds0",	  726,	R8A7743_CLK_ZX),
+	DEF_MOD("ipmmu-sgx",	  800,	R8A7743_CLK_ZX),
+	DEF_MOD("vin2",		  809,	R8A7743_CLK_ZG),
+	DEF_MOD("vin1",		  810,	R8A7743_CLK_ZG),
+	DEF_MOD("vin0",		  811,	R8A7743_CLK_ZG),
+	DEF_MOD("etheravb",	  812,	R8A7743_CLK_HP),
+	DEF_MOD("ether",	  813,	R8A7743_CLK_P),
+	DEF_MOD("sata1",	  814,	R8A7743_CLK_ZS),
+	DEF_MOD("sata0",	  815,	R8A7743_CLK_ZS),
+	DEF_MOD("gpio7",	  904,	R8A7743_CLK_CP),
+	DEF_MOD("gpio6",	  905,	R8A7743_CLK_CP),
+	DEF_MOD("gpio5",	  907,	R8A7743_CLK_CP),
+	DEF_MOD("gpio4",	  908,	R8A7743_CLK_CP),
+	DEF_MOD("gpio3",	  909,	R8A7743_CLK_CP),
+	DEF_MOD("gpio2",	  910,	R8A7743_CLK_CP),
+	DEF_MOD("gpio1",	  911,	R8A7743_CLK_CP),
+	DEF_MOD("gpio0",	  912,	R8A7743_CLK_CP),
+	DEF_MOD("can1",		  915,	R8A7743_CLK_P),
+	DEF_MOD("can0",		  916,	R8A7743_CLK_P),
+	DEF_MOD("qspi_mod",	  917,	R8A7743_CLK_QSPI),
+	DEF_MOD("i2c5",		  925,	R8A7743_CLK_HP),
+	DEF_MOD("iicdvfs",	  926,	R8A7743_CLK_CP),
+	DEF_MOD("i2c4",		  927,	R8A7743_CLK_HP),
+	DEF_MOD("i2c3",		  928,	R8A7743_CLK_HP),
+	DEF_MOD("i2c2",		  929,	R8A7743_CLK_HP),
+	DEF_MOD("i2c1",		  930,	R8A7743_CLK_HP),
+	DEF_MOD("i2c0",		  931,	R8A7743_CLK_HP),
+	DEF_MOD("ssi-all",	 1005,	R8A7743_CLK_P),
+	DEF_MOD("ssi9",		 1006,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi8",		 1007,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi7",		 1008,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi6",		 1009,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi5",		 1010,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi4",		 1011,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi3",		 1012,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi2",		 1013,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi1",		 1014,	MOD_CLK_ID(1005)),
+	DEF_MOD("ssi0",		 1015,	MOD_CLK_ID(1005)),
+	DEF_MOD("scu-all",	 1017,	R8A7743_CLK_P),
+	DEF_MOD("scu-dvc1",	 1018,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-dvc0",	 1019,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu1-mix1", 1020,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-ctu0-mix0", 1021,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src9",	 1022,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src8",	 1023,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src7",	 1024,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src6",	 1025,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src5",	 1026,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src4",	 1027,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src3",	 1028,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src2",	 1029,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src1",	 1030,	MOD_CLK_ID(1017)),
+	DEF_MOD("scu-src0",	 1031,	MOD_CLK_ID(1017)),
+	DEF_MOD("scifa3",	 1106,	R8A7743_CLK_MP),
+	DEF_MOD("scifa4",	 1107,	R8A7743_CLK_MP),
+	DEF_MOD("scifa5",	 1108,	R8A7743_CLK_MP),
+};
+
+static const unsigned int r8a7743_crit_mod_clks[] __initconst = {
+	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ *    MD	EXTAL		PLL0	PLL1	PLL3
+ * 14 13 19	(MHz)		*1	*1
+ *---------------------------------------------------
+ * 0  0  0	15		x172/2	x208/2	x106
+ * 0  0  1	15		x172/2	x208/2	x88
+ * 0  1  0	20		x130/2	x156/2	x80
+ * 0  1  1	20		x130/2	x156/2	x66
+ * 1  0  0	26 / 2		x200/2	x240/2	x122
+ * 1  0  1	26 / 2		x200/2	x240/2	x102
+ * 1  1  0	30 / 2		x172/2	x208/2	x106
+ * 1  1  1	30 / 2		x172/2	x208/2	x88
+ *
+ * *1 :	Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
+					 (((md) & BIT(13)) >> 12) | \
+					 (((md) & BIT(19)) >> 19))
+
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+	/* EXTAL div	PLL1 mult	PLL3 mult */
+	{ 1,		208,		106,	},
+	{ 1,		208,		88,	},
+	{ 1,		156,		80,	},
+	{ 1,		156,		66,	},
+	{ 2,		240,		122,	},
+	{ 2,		240,		102,	},
+	{ 2,		208,		106,	},
+	{ 2,		208,		88,	},
+};
+
+static int __init r8a7743_cpg_mssr_init(struct device *dev)
+{
+	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+	u32 cpg_mode;
+	int error;
+
+	error = rcar_rst_read_mode_pins(&cpg_mode);
+	if (error)
+		return error;
+
+	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+	return rcar_gen2_cpg_init(cpg_pll_config, 2);
+}
+
+const struct cpg_mssr_info r8a7743_cpg_mssr_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r8a7743_core_clks,
+	.num_core_clks = ARRAY_SIZE(r8a7743_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r8a7743_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r8a7743_mod_clks),
+	.num_hw_mod_clks = 12 * 32,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r8a7743_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r8a7743_crit_mod_clks),
+
+	/* Callbacks */
+	.init = r8a7743_cpg_mssr_init,
+	.cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
Index: linux/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
--- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.c
+++ linux/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -503,6 +503,12 @@ static int __init cpg_mssr_add_clk_domai
 }
 
 static const struct of_device_id cpg_mssr_match[] = {
+#ifdef CONFIG_ARCH_R8A7743
+	{
+		.compatible = "renesas,r8a7743-cpg-mssr",
+		.data = &r8a7743_cpg_mssr_info,
+	},
+#endif
 #ifdef CONFIG_ARCH_R8A7795
 	{
 		.compatible = "renesas,r8a7795-cpg-mssr",
Index: linux/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
--- linux.orig/drivers/clk/renesas/renesas-cpg-mssr.h
+++ linux/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -130,6 +130,7 @@ struct cpg_mssr_info {
 					struct clk **clks, void __iomem *base);
 };
 
+extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
 #endif

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v6] clk: renesas: cpg-mssr: add R8A7743 support
  2016-11-08 21:21 ` [PATCH v6] " Sergei Shtylyov
@ 2016-11-10 12:52   ` Geert Uytterhoeven
  0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2016-11-10 12:52 UTC (permalink / raw)
  To: Sergei Shtylyov
  Cc: Michael Turquette, linux-clk, Stephen Boyd, Rob Herring,
	Mark Rutland, devicetree, Linux-Renesas, Simon Horman

Hi Sergei,

On Tue, Nov 8, 2016 at 10:21 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add RZ/G1M (R8A7743) Clock  Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
> <geert+renesas@glider.be>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> This patch is against the 'clk-next' branch of CLK group's 'linux.git' repo.
> It depends on the common R-Car gen2 (and RZ/G) support just posted.
>
> Changes in version 6:
> - passed the PLL0 divisor to rcar_gen2_cpg_init();
> - undid  the version 5 changes.

Thanks!

Will queue with the following trivial changes:
  - pass cpg_mode to rcar_gen2_cpg_init(),
  - sort clock names in DT bindings,
  - reformat tables for easier comparison with other clock drivers.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-11-10 12:52 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-02 21:53 [PATCH v5 0/2] Renesas R8A7743 CPG/MSSR clock support Sergei Shtylyov
2016-11-02 21:53 ` Sergei Shtylyov
2016-11-02 21:57 ` [PATCH v5 1/2] ARM: shmobile: r8a7743: add CPG clock index macros Sergei Shtylyov
2016-11-07 18:40   ` Geert Uytterhoeven
     [not found] ` <1737840.BeMyoUTlpl-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-11-02 21:59   ` [PATCH v5 2/2] clk: renesas: cpg-mssr: add R8A7743 support Sergei Shtylyov
2016-11-02 21:59     ` Sergei Shtylyov
2016-11-07 10:09     ` Geert Uytterhoeven
2016-11-07 10:35       ` Sergei Shtylyov
2016-11-08 21:21 ` [PATCH v6] " Sergei Shtylyov
2016-11-10 12:52   ` Geert Uytterhoeven

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