[RFC PATCH v2 0/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[RFC PATCH v2 0/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[Jocelyn Falempe]

This series adds DMA and IRQ for the mgag200 driver.
Unfortunately the DMA doesn't make the driver faster.
But it's still a big improvement regarding CPU usage and latency.

CPU usage goes from 100% of 1 CPU to 3% (using top and refreshing the screen continuously).

top without DMA, and a bash script to refresh the screen continuously
    PID S  %CPU     TIME+ COMMAND
   1536 R 100.0   4:02.78 kworker/1:0+events
   1612 S   3.0   0:03.82 bash
     16 I   0.3   0:01.56 rcu_preempt
   1467 I   0.3   0:00.11 kworker/u64:1-events_unbound
   3650 R   0.3   0:00.02 top

top with DMA, and the same bash script:
    PID S  %CPU     TIME+ COMMAND
   1335 D   3.0   0:01.26 kworker/2:0+events
   1486 S   0.3   0:00.14 bash
   1846 R   0.3   0:00.03 top
      1 S   0.0   0:01.87 systemd
      2 S   0.0   0:00.00 kthreadd

Latency, measured with cyclictest -s -l 10000:
Without DMA:
# /dev/cpu_dma_latency set to 0us
policy: other/other: loadavg: 1.52 0.52 0.33 3/358 2025          
T: 0 ( 1977) P: 0 I:1000 C:  10000 Min:      7 Act:   56 Avg:   85 Max:    2542

With DMA:
# /dev/cpu_dma_latency set to 0us
policy: other/other: loadavg: 1.27 0.48 0.18 2/363 2498          
T: 0 ( 2403) P: 0 I:1000 C:  10000 Min:      8 Act:   62 Avg:   59 Max:     339

Last benchmark is glxgears. It's still software rendering, but on my 2 core CPU,
freeing one CPU constantly doing memcpy(), allows it to draw more frames.
Without DMA:
415 frames in 5.0 seconds = 82.973 FPS
356 frames in 5.0 seconds = 71.167 FPS
with DMA:
717 frames in 5.0 seconds = 143.343 FPS
720 frames in 5.0 seconds = 143.993 FPS

Regarding the implementation:
The driver uses primary DMA to send drawing engine commands, and secondary DMA to send the pixels to an ILOAD command.
You can directly program the ILOAD command, and use Primary DMA to send the pixels, but in this case, you can't use the softrap interrupt to wait for the DMA completion.
The pixels are copied from the gem framebuffer to the DMA buffer, but as system memory is much faster than VRAM, it has a negligible impact.

DMA buffer size:
On my test machine (x86_64), I can't allocate more than 4MB of DMA coherent memory, and the framebuffer is 5MB.
So the driver has to cut it into small chunks when the full framebuffer is refreshed.
My implementation tries to allocate 4MB, and then smaller allocation until it succeeds.
The DMA GEM framework tries to allocate the whole framebuffer at once, so it fails for resolutions higher than 1024x768x32.
So I stick with SHMEM, and that extra memcpy.

Pixel width:
I tested this in 16 bits per pixels RGB565 and 32 bits per pixels (XRGB8888).
I didn't find a userspace able to use 24 bits (RGB888), Xorg uses XRGB8888 when specifying
"DefaultDepth" to 24.

I think the added complexity is low, as it only adds ~400 lines, less than 10% of the whole mgag200 driver (~5000 lines).

 drivers/gpu/drm/mgag200/Makefile          |   3 +-
 drivers/gpu/drm/mgag200/mgag200_dma.c     | 237 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/mgag200/mgag200_drv.c     |  40 +++++++
 drivers/gpu/drm/mgag200/mgag200_drv.h     |  29 +++++
 drivers/gpu/drm/mgag200/mgag200_g200.c    |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200eh.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200eh3.c |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200er.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200ev.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200ew3.c |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200se.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200wb.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_mode.c    |  84 ++++----------
 drivers/gpu/drm/mgag200/mgag200_reg.h     |  30 ++++-
 14 files changed, 393 insertions(+), 62 deletions(-)

v2:
 - Better explain scale and offset simplifications.
 - Move all damage handling to mgag200_dma.c
 - Move all dma-related variables to struct mga_dma.
 - Remove the fallback, DMA should always work.
 - Fix the warning reported by the kernel test bot.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>

[PATCH v2 1/4] drm/mgag200: Rename constant MGAREG_Status to MGAREG_STATUS

[Jocelyn Falempe]

From: Thomas Zimmermann <tzimmermann@suse.de>

Register constants are upper case. Fix MGAREG_Status accordingly.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
---
 drivers/gpu/drm/mgag200/mgag200_mode.c | 6 +++---
 drivers/gpu/drm/mgag200/mgag200_reg.h  | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 0a5aaf78172a..9a24b9c00745 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -109,12 +109,12 @@ static inline void mga_wait_vsync(struct mga_device *mdev)
 	unsigned int status = 0;
 
 	do {
-		status = RREG32(MGAREG_Status);
+		status = RREG32(MGAREG_STATUS);
 	} while ((status & 0x08) && time_before(jiffies, timeout));
 	timeout = jiffies + HZ/10;
 	status = 0;
 	do {
-		status = RREG32(MGAREG_Status);
+		status = RREG32(MGAREG_STATUS);
 	} while (!(status & 0x08) && time_before(jiffies, timeout));
 }
 
@@ -123,7 +123,7 @@ static inline void mga_wait_busy(struct mga_device *mdev)
 	unsigned long timeout = jiffies + HZ;
 	unsigned int status = 0;
 	do {
-		status = RREG8(MGAREG_Status + 2);
+		status = RREG8(MGAREG_STATUS + 2);
 	} while ((status & 0x01) && time_before(jiffies, timeout));
 }
 
diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h
index 1019ffd6c260..aa73463674e4 100644
--- a/drivers/gpu/drm/mgag200/mgag200_reg.h
+++ b/drivers/gpu/drm/mgag200/mgag200_reg.h
@@ -102,7 +102,7 @@
 #define MGAREG_EXEC		0x0100
 
 #define	MGAREG_FIFOSTATUS	0x1e10
-#define	MGAREG_Status		0x1e14
+#define	MGAREG_STATUS		0x1e14
 #define MGAREG_CACHEFLUSH       0x1fff
 #define	MGAREG_ICLEAR		0x1e18
 #define	MGAREG_IEN		0x1e1c

base-commit: 457391b0380335d5e9a5babdec90ac53928b23b4
-- 
2.40.1

[PATCH v2 2/4] drm/mgag200: Simplify offset and scale computation.

[Jocelyn Falempe]

bppshift variable introduces a lot of complexity, and can be removed.
From the Matrox documentation, scale is the number of byte per pixels - 1,
And offset is pitch (in bits) / 128 (or pitch (in bytes) / 16).
The old formula gives the same results, but is harder to understand.

No functional changes.

offset:
16bit: (bppshift = 1)
offset = width >> (4 - bppshift) => width / 8 => pitch / 16

24bit:  (bppshift = 0)
offset = (width * 3) >> (4 - bppshift)  => width * 3 / 16 => pitch / 16

32bit:  (bppshift = 2)
offset = width >> (4 - bppshift) => width / 4 => pitch / 16

scale:
16bit:
scale = (1 << bppshift) - 1 => 1
24bit:
scale = ((1 << bppshift) * 3) - 1 => 2
32bit:
scale = (1 << bppshift) - 1 => 3

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
---
 drivers/gpu/drm/mgag200/mgag200_mode.c | 63 +++++++-------------------
 1 file changed, 16 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 9a24b9c00745..7d8c65372ac4 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -280,30 +280,16 @@ void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mod
 	WREG8(MGA_MISC_OUT, misc);
 }
 
-static u8 mgag200_get_bpp_shift(const struct drm_format_info *format)
-{
-	static const u8 bpp_shift[] = {0, 1, 0, 2};
-
-	return bpp_shift[format->cpp[0] - 1];
-}
-
 /*
  * Calculates the HW offset value from the framebuffer's pitch. The
  * offset is a multiple of the pixel size and depends on the display
- * format.
+ * format. With width in pixels and pitch in bytes, the formula is:
+ * offset = width * bpp / 128 = pitch / 16
  */
 static u32 mgag200_calculate_offset(struct mga_device *mdev,
 				    const struct drm_framebuffer *fb)
 {
-	u32 offset = fb->pitches[0] / fb->format->cpp[0];
-	u8 bppshift = mgag200_get_bpp_shift(fb->format);
-
-	if (fb->format->cpp[0] * 8 == 24)
-		offset = (offset * 3) >> (4 - bppshift);
-	else
-		offset = offset >> (4 - bppshift);
-
-	return offset;
+	return fb->pitches[0] >> 4;
 }
 
 static void mgag200_set_offset(struct mga_device *mdev,
@@ -326,48 +312,25 @@ static void mgag200_set_offset(struct mga_device *mdev,
 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format)
 {
 	struct drm_device *dev = &mdev->base;
-	unsigned int bpp, bppshift, scale;
+	unsigned int scale;
 	u8 crtcext3, xmulctrl;
 
-	bpp = format->cpp[0] * 8;
-
-	bppshift = mgag200_get_bpp_shift(format);
-	switch (bpp) {
-	case 24:
-		scale = ((1 << bppshift) * 3) - 1;
-		break;
-	default:
-		scale = (1 << bppshift) - 1;
-		break;
-	}
-
-	RREG_ECRT(3, crtcext3);
-
-	switch (bpp) {
-	case 8:
-		xmulctrl = MGA1064_MUL_CTL_8bits;
-		break;
-	case 16:
-		if (format->depth == 15)
-			xmulctrl = MGA1064_MUL_CTL_15bits;
-		else
-			xmulctrl = MGA1064_MUL_CTL_16bits;
+	switch (format->format) {
+	case DRM_FORMAT_RGB565:
+		xmulctrl = MGA1064_MUL_CTL_16bits;
 		break;
-	case 24:
+	case DRM_FORMAT_RGB888:
 		xmulctrl = MGA1064_MUL_CTL_24bits;
 		break;
-	case 32:
+	case DRM_FORMAT_XRGB8888:
 		xmulctrl = MGA1064_MUL_CTL_32_24bits;
 		break;
 	default:
 		/* BUG: We should have caught this problem already. */
-		drm_WARN_ON(dev, "invalid format depth\n");
+		drm_WARN_ON(dev, "invalid drm format\n");
 		return;
 	}
 
-	crtcext3 &= ~GENMASK(2, 0);
-	crtcext3 |= scale;
-
 	WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
 
 	WREG_GFX(0, 0x00);
@@ -383,6 +346,12 @@ void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_in
 	WREG_GFX(7, 0x0f);
 	WREG_GFX(8, 0x0f);
 
+	/* scale is the number of bytes per pixels - 1 */
+	scale = format->cpp[0] - 1;
+
+	RREG_ECRT(3, crtcext3);
+	crtcext3 &= ~GENMASK(2, 0);
+	crtcext3 |= scale;
 	WREG_ECRT(3, crtcext3);
 }
 
-- 
2.40.1

[PATCH v2 3/4] drm/mgag200: Add IRQ support

[Jocelyn Falempe]

Register irq, and enable the softrap irq.
This patch has no functional impact since softrap
irq can't be triggered without DMA.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
---
 drivers/gpu/drm/mgag200/mgag200_drv.c | 38 +++++++++++++++++++++++++++
 drivers/gpu/drm/mgag200/mgag200_reg.h |  3 +++
 2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c
index 976f0ab2006b..a5851dcc6bdd 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -110,12 +110,41 @@ resource_size_t mgag200_device_probe_vram(struct mga_device *mdev)
 	return mgag200_probe_vram(mdev->vram, resource_size(mdev->vram_res));
 }
 
+static irqreturn_t mgag200_driver_irq_handler(int irq, void *arg)
+{
+	struct mga_device *mdev = (struct mga_device *) arg;
+	u32 status;
+
+	status = RREG32(MGAREG_STATUS);
+
+	if (status & MGAIRQ_SOFTRAP) {
+		WREG32(MGAREG_ICLEAR, MGAIRQ_SOFTRAP);
+		return IRQ_HANDLED;
+	}
+	return IRQ_NONE;
+}
+
+static void mgag200_init_irq(struct mga_device *mdev)
+{
+	/* Disable *all* interrupts */
+	WREG32(MGAREG_IEN, 0);
+	/* Clear bits if they're already high */
+	WREG32(MGAREG_ICLEAR, 0xf);
+}
+
+static void mgag200_enable_irq(struct mga_device *mdev)
+{
+	/* Enable only Softrap IRQ */
+	WREG32(MGAREG_IEN, MGAIRQ_SOFTRAP);
+}
+
 int mgag200_device_preinit(struct mga_device *mdev)
 {
 	struct drm_device *dev = &mdev->base;
 	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	resource_size_t start, len;
 	struct resource *res;
+	int ret;
 
 	/* BAR 1 contains registers */
 
@@ -153,6 +182,13 @@ int mgag200_device_preinit(struct mga_device *mdev)
 	if (!mdev->vram)
 		return -ENOMEM;
 
+	mgag200_init_irq(mdev);
+	ret = devm_request_irq(dev->dev, pdev->irq, mgag200_driver_irq_handler,
+			       IRQF_SHARED, "mgag200_irq", mdev);
+	if (ret < 0) {
+		drm_err(dev, "devm_request_irq(VRAM) failed %d\n", ret);
+		return -ENXIO;
+	}
 	return 0;
 }
 
@@ -184,6 +220,8 @@ int mgag200_device_init(struct mga_device *mdev,
 		MGAREG_MISC_HIGH_PG_SEL;
 	WREG8(MGA_MISC_OUT, misc);
 
+	mgag200_enable_irq(mdev);
+
 	mutex_unlock(&mdev->rmmio_lock);
 
 	return 0;
diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h
index aa73463674e4..748c8e18e938 100644
--- a/drivers/gpu/drm/mgag200/mgag200_reg.h
+++ b/drivers/gpu/drm/mgag200/mgag200_reg.h
@@ -107,6 +107,9 @@
 #define	MGAREG_ICLEAR		0x1e18
 #define	MGAREG_IEN		0x1e1c
 
+/* same bit shift for MGAREG_IEN, MGAREG_ICLEAR and MGAREG_STATUS */
+#define MGAIRQ_SOFTRAP		BIT(0)
+
 #define	MGAREG_VCOUNT		0x1e20
 
 #define	MGAREG_Reset		0x1e40
-- 
2.40.1

[PATCH v2 4/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[Jocelyn Falempe]

Even if the transfer is not faster, it brings significant
improvement in latencies and CPU usage.

CPU usage drops from 100% of one core to 3% when continuously
refreshing the screen.

The primary DMA is used to send commands (register write), and
the secondary DMA to send the pixel data.
It uses the ILOAD command (chapter 4.5.7 in G200 specification),
which allows to load an image, or a part of an image from system
memory to VRAM.
The last command sent, is a softrap command, which triggers an IRQ
when the DMA transfer is complete.
For 16bits and 24bits pixel width, each line is padded to make sure,
the DMA transfer is a multiple of 32bits. The padded bytes won't be
drawn on the screen, so they don't need to be initialized.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
---
 drivers/gpu/drm/mgag200/Makefile          |   3 +-
 drivers/gpu/drm/mgag200/mgag200_dma.c     | 237 ++++++++++++++++++++++
 drivers/gpu/drm/mgag200/mgag200_drv.c     |   4 +-
 drivers/gpu/drm/mgag200/mgag200_drv.h     |  29 +++
 drivers/gpu/drm/mgag200/mgag200_g200.c    |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200eh.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200eh3.c |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200er.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200ev.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200ew3.c |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200se.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_g200wb.c  |   4 +
 drivers/gpu/drm/mgag200/mgag200_mode.c    |  15 +-
 drivers/gpu/drm/mgag200/mgag200_reg.h     |  25 +++
 14 files changed, 333 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/mgag200/mgag200_dma.c

diff --git a/drivers/gpu/drm/mgag200/Makefile b/drivers/gpu/drm/mgag200/Makefile
index 182e224c460d..96e23dc5572c 100644
--- a/drivers/gpu/drm/mgag200/Makefile
+++ b/drivers/gpu/drm/mgag200/Makefile
@@ -11,6 +11,7 @@ mgag200-y := \
 	mgag200_g200se.o \
 	mgag200_g200wb.o \
 	mgag200_i2c.o \
-	mgag200_mode.o
+	mgag200_mode.o \
+	mgag200_dma.o
 
 obj-$(CONFIG_DRM_MGAG200) += mgag200.o
diff --git a/drivers/gpu/drm/mgag200/mgag200_dma.c b/drivers/gpu/drm/mgag200/mgag200_dma.c
new file mode 100644
index 000000000000..7e9b59ef08d9
--- /dev/null
+++ b/drivers/gpu/drm/mgag200/mgag200_dma.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2023 Red Hat
+ *
+ * Authors: Jocelyn Falempe
+ *
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/iosys-map.h>
+#include <linux/wait.h>
+
+#include <drm/drm_framebuffer.h>
+
+#include "mgag200_drv.h"
+#include "mgag200_reg.h"
+
+/* Maximum number of command block for one DMA transfer
+ * iload should only use 4 blocks
+ */
+#define MGA_MAX_CMD		50
+
+#define MGA_DMA_SIZE		(4 * 1024 * 1024)
+#define MGA_MIN_DMA_SIZE	(64 * 1024)
+
+/*
+ * Allocate coherent buffers for DMA transfer.
+ * We need two buffers, one for the commands, and one for the data.
+ */
+int mgag200_dma_init(struct mga_device *mdev)
+{
+	struct drm_device *dev = &mdev->base;
+	struct mga_dma *dma = &mdev->dma;
+	int size;
+	/* Allocate the command buffer */
+	dma->cmd = dmam_alloc_coherent(dev->dev, MGA_MAX_CMD * sizeof(*dma->cmd),
+					&dma->cmd_handle, GFP_KERNEL);
+
+	if (!dma->cmd) {
+		drm_err(dev, "DMA command buffer allocation failed\n");
+		return -ENOMEM;
+	}
+
+	for (size = MGA_DMA_SIZE; size >= MGA_MIN_DMA_SIZE; size = size >> 1) {
+		dma->buf = dmam_alloc_coherent(dev->dev, size, &dma->handle, GFP_KERNEL);
+		if (dma->buf)
+			break;
+	}
+	if (!dma->buf) {
+		drm_err(dev, "DMA data buffer allocation failed\n");
+		return -ENOMEM;
+	}
+	dma->size = size;
+	drm_info(dev, "Using DMA with a %dk data buffer\n", size / 1024);
+
+	init_waitqueue_head(&dma->waitq);
+	return 0;
+}
+
+/*
+ * Matrox uses a command block to program the hardware through DMA.
+ * Each command is a register write, and each block contains 4 commands
+ * packed in 5 dwords(u32).
+ * First dword is the 4 register index (8bit) to write for the 4 commands,
+ * followed by the four values to be written.
+ */
+static void mgag200_dma_add_block(struct mga_device *mdev,
+			   u32 reg0, u32 val0,
+			   u32 reg1, u32 val1,
+			   u32 reg2, u32 val2,
+			   u32 reg3, u32 val3)
+{
+	if (mdev->dma.cmd_idx >= MGA_MAX_CMD) {
+		pr_err("mgag200: exceeding the DMA command buffer size\n");
+		return;
+	}
+
+	mdev->dma.cmd[mdev->dma.cmd_idx] = (struct mga_cmd_block) {
+		.cmd = DMAREG(reg0) | DMAREG(reg1) << 8 | DMAREG(reg2) << 16 | DMAREG(reg3) << 24,
+		.v0 = val0,
+		.v1 = val1,
+		.v2 = val2,
+		.v3 = val3};
+	mdev->dma.cmd_idx++;
+}
+
+static void mgag200_dma_run_cmd(struct mga_device *mdev)
+{
+	struct drm_device *dev = &mdev->base;
+	u32 primend;
+
+	/* Add a last block to trigger the softrap interrupt */
+	mgag200_dma_add_block(mdev,
+			MGAREG_DMAPAD, 0,
+			MGAREG_DMAPAD, 0,
+			MGAREG_DMAPAD, 0,
+			MGAREG_SOFTRAP, 0);
+
+	primend = mdev->dma.cmd_handle + mdev->dma.cmd_idx * sizeof(struct mga_cmd_block);
+
+	// Use primary DMA to send the commands
+	WREG32(MGAREG_PRIMADDR, (u32) mdev->dma.cmd_handle);
+	mdev->dma.in_use = 1;
+	WREG32(MGAREG_PRIMEND, primend);
+
+	wait_event_timeout(mdev->dma.waitq, mdev->dma.in_use == 0, HZ);
+
+	if (mdev->dma.in_use) {
+		drm_err(dev, "DMA transfer timed out\n");
+		/* something goes wrong, reset the DMA engine */
+		WREG8(MGAREG_OPMODE, MGAOPM_DMA_BLIT);
+		mdev->dma.in_use = 0;
+	}
+
+	/* reset command index to start a new sequence */
+	mdev->dma.cmd_idx = 0;
+}
+
+/*
+ * ILOAD allows to load an image from system memory to the VRAM, and with FXBNDRY, YDST and YDSTLEN,
+ * you can transfer a rectangle, so it's perfect when used with a damage clip.
+ */
+static void mgag200_iload_cmd(struct mga_device *mdev, int x, int y, int width, int height,
+			      int width_padded, int cpp)
+{
+	int size = width_padded * height;
+	u32 iload;
+
+	iload = MGADWG_ILOAD | MGADWG_SGNZERO | MGADWG_SHIFTZERO | MGADWG_REPLACE | MGADWG_CLIPDIS
+		| MGADWG_BFCOL;
+
+	mgag200_dma_add_block(mdev,
+		MGAREG_DWGCTL, iload,
+		MGAREG_FXBNDRY, (((x + width - 1) << 16) | x),
+		MGAREG_AR0, (width_padded / cpp) - 1,
+		MGAREG_AR3, 0);
+
+	mgag200_dma_add_block(mdev,
+		MGAREG_AR5, 0,
+		MGAREG_YDST, y,
+		MGAREG_DMAPAD, 0,
+		MGAREG_DMAPAD, 0);
+
+	mgag200_dma_add_block(mdev,
+		MGAREG_DMAPAD, 0,
+		MGAREG_LEN | MGAREG_EXEC, height,
+		MGAREG_SECADDR, mdev->dma.handle | 1,
+		/* Writing SECEND should always be the last command of a block */
+		MGAREG_SECEND, mdev->dma.handle + size);
+}
+
+static void mgag200_dma_copy(struct mga_device *mdev, const void *src, u32 pitch,
+				struct drm_rect *clip, int cpp)
+{
+	int i;
+	int width = drm_rect_width(clip);
+	int height = drm_rect_height(clip);
+
+	/* pad each line to 32bits boundaries see section 4.5.7 of G200 Specification */
+	int width_padded = round_up(width * cpp, 4);
+
+	for (i = 0; i < height; i++)
+		memcpy(mdev->dma.buf + width_padded * i,
+		       src + (((clip->y1 + i) * pitch) + clip->x1 * cpp),
+		       width * cpp);
+
+	mgag200_iload_cmd(mdev, clip->x1, clip->y1, width, height, width_padded, cpp);
+	mgag200_dma_run_cmd(mdev);
+}
+
+/*
+ * If the DMA coherent buffer is smaller than damage rectangle, we need to
+ * split it into multiple DMA transfers.
+ */
+void mgag200_dma_damage(struct mga_device *mdev, const struct iosys_map *vmap,
+			struct drm_framebuffer *fb, struct drm_rect *clip)
+{
+	u32 pitch = fb->pitches[0];
+	const void *src = vmap[0].vaddr;
+	struct drm_rect subclip;
+	int y1;
+	int lines;
+	int cpp = fb->format->cpp[0];
+
+	/* Number of lines that fit in one DMA buffer */
+	lines = min(drm_rect_height(clip), (int) mdev->dma.size / (drm_rect_width(clip) * cpp));
+
+	subclip.x1 = clip->x1;
+	subclip.x2 = clip->x2;
+
+	for (y1 = clip->y1; y1 < clip->y2; y1 += lines) {
+		subclip.y1 = y1;
+		subclip.y2 = min(clip->y2, y1 + lines);
+		mgag200_dma_copy(mdev, src, pitch, &subclip, cpp);
+	}
+}
+
+/*
+ * Setup the drawing engine (DWG) registers
+ * Color format, framebuffer width, ...
+ * This must be done before using any DWGCTL command
+ */
+void mgag200_dma_dwg_setup(struct mga_device *mdev, struct drm_framebuffer *fb)
+{
+	u32 maccess;
+
+	drm_dbg(&mdev->base, "Setup DWG with %dx%d %p4cc\n",
+		fb->width, fb->height, &fb->format->format);
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_RGB565:
+		maccess = MGAMAC_PW16;
+		break;
+	case DRM_FORMAT_RGB888:
+		maccess = MGAMAC_PW24;
+		break;
+	case DRM_FORMAT_XRGB8888:
+		maccess = MGAMAC_PW32;
+		break;
+	}
+	WREG32(MGAREG_MACCESS, maccess);
+
+	/* Framebuffer width in pixel */
+	WREG32(MGAREG_PITCH, fb->width);
+
+	/* Sane default value for the drawing engine registers */
+	WREG32(MGAREG_DSTORG, 0);
+	WREG32(MGAREG_YDSTORG, 0);
+	WREG32(MGAREG_SRCORG, 0);
+	WREG32(MGAREG_CXBNDRY, 0x0FFF0000);
+	WREG32(MGAREG_YTOP, 0);
+	WREG32(MGAREG_YBOT, 0x00FFFFFF);
+
+	/* Activate blit mode DMA, only write the low part of the register */
+	WREG8(MGAREG_OPMODE, MGAOPM_DMA_BLIT);
+}
+
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c
index a5851dcc6bdd..07f34e4df1b0 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -119,6 +119,8 @@ static irqreturn_t mgag200_driver_irq_handler(int irq, void *arg)
 
 	if (status & MGAIRQ_SOFTRAP) {
 		WREG32(MGAREG_ICLEAR, MGAIRQ_SOFTRAP);
+		mdev->dma.in_use = 0;
+		wake_up(&mdev->dma.waitq);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
@@ -187,7 +189,7 @@ int mgag200_device_preinit(struct mga_device *mdev)
 			       IRQF_SHARED, "mgag200_irq", mdev);
 	if (ret < 0) {
 		drm_err(dev, "devm_request_irq(VRAM) failed %d\n", ret);
-		return -ENXIO;
+		return ret;
 	}
 	return 0;
 }
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h
index 9e604dbb8e44..af69f61a11b7 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.h
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.h
@@ -277,6 +277,27 @@ struct mgag200_device_funcs {
 	void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
 };
 
+struct mga_cmd_block {
+	u32 cmd;
+	u32 v0;
+	u32 v1;
+	u32 v2;
+	u32 v3;
+} __packed;
+
+struct mga_dma {
+	void *buf;
+	size_t size;
+	dma_addr_t handle;
+
+	struct mga_cmd_block *cmd;
+	int cmd_idx;
+	dma_addr_t cmd_handle;
+
+	wait_queue_head_t waitq;
+	int in_use;
+};
+
 struct mga_device {
 	struct drm_device base;
 
@@ -291,6 +312,8 @@ struct mga_device {
 	void __iomem			*vram;
 	resource_size_t			vram_available;
 
+	struct mga_dma dma;
+
 	struct drm_plane primary_plane;
 	struct drm_crtc crtc;
 	struct drm_encoder encoder;
@@ -443,4 +466,10 @@ void mgag200_bmc_enable_vidrst(struct mga_device *mdev);
 				/* mgag200_i2c.c */
 int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c);
 
+/* mgag200_dma.c */
+int mgag200_dma_init(struct mga_device *mdev);
+void mgag200_dma_damage(struct mga_device *mdev, const struct iosys_map *vmap,
+			struct drm_framebuffer *fb, struct drm_rect *clip);
+void mgag200_dma_dwg_setup(struct mga_device *mdev, struct drm_framebuffer *fb);
+
 #endif				/* __MGAG200_DRV_H__ */
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200.c b/drivers/gpu/drm/mgag200/mgag200_g200.c
index bf5d7fe525a3..4e972518733a 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200.c
@@ -424,6 +424,10 @@ struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct
 
 	mgag200_g200_init_refclk(g200);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200_device_info,
 				  &mgag200_g200_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh.c b/drivers/gpu/drm/mgag200/mgag200_g200eh.c
index fad62453a91d..6628b891118d 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200eh.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200eh.c
@@ -296,6 +296,10 @@ struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const stru
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200eh_device_info,
 				  &mgag200_g200eh_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
index 0f7d8112cd49..35219fbe364f 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
@@ -201,6 +201,10 @@ struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev,
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200eh3_device_info,
 				  &mgag200_g200eh3_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200er.c b/drivers/gpu/drm/mgag200/mgag200_g200er.c
index bce267e0f7de..fc6df2ffd99d 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200er.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200er.c
@@ -330,6 +330,10 @@ struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, const stru
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200er_device_info,
 				  &mgag200_g200er_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ev.c b/drivers/gpu/drm/mgag200/mgag200_g200ev.c
index ac957f42abe1..190c358aba7e 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200ev.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200ev.c
@@ -335,6 +335,10 @@ struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const stru
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200ev_device_info,
 				  &mgag200_g200ev_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
index 170934414d7d..5de7ccbc575c 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
@@ -221,6 +221,10 @@ struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev,
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200ew3_device_info,
 				  &mgag200_g200ew3_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c
index bd6e573c9a1a..3edb930598dd 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200se.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c
@@ -506,6 +506,10 @@ struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const stru
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_g200se_init_unique_rev_id(g200se);
 	if (ret)
 		return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/mgag200/mgag200_g200wb.c b/drivers/gpu/drm/mgag200/mgag200_g200wb.c
index 9baa727ac6f9..6e731da89a5f 100644
--- a/drivers/gpu/drm/mgag200/mgag200_g200wb.c
+++ b/drivers/gpu/drm/mgag200/mgag200_g200wb.c
@@ -345,6 +345,10 @@ struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const stru
 	if (ret)
 		return ERR_PTR(ret);
 
+	ret = mgag200_dma_init(mdev);
+	if (ret)
+		return ERR_PTR(ret);
+
 	ret = mgag200_device_init(mdev, &mgag200_g200wb_device_info,
 				  &mgag200_g200wb_device_funcs);
 	if (ret)
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 7d8c65372ac4..adfc61428df6 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -398,15 +398,6 @@ static void mgag200_disable_display(struct mga_device *mdev)
 	WREG_ECRT(0x01, crtcext1);
 }
 
-static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap,
-				  struct drm_framebuffer *fb, struct drm_rect *clip)
-{
-	struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram);
-
-	iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
-	drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip);
-}
-
 /*
  * Primary plane
  */
@@ -475,9 +466,13 @@ void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
 	if (!fb)
 		return;
 
+	if (!old_plane_state->fb || fb->format != old_plane_state->fb->format
+	    || fb->width != old_plane_state->fb->width)
+		mgag200_dma_dwg_setup(mdev, fb);
+
 	drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
 	drm_atomic_for_each_plane_damage(&iter, &damage) {
-		mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage);
+		mgag200_dma_damage(mdev, shadow_plane_state->data, fb, &damage);
 	}
 
 	/* Always scanout image at VRAM offset 0 */
diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h
index 748c8e18e938..256ac92dae56 100644
--- a/drivers/gpu/drm/mgag200/mgag200_reg.h
+++ b/drivers/gpu/drm/mgag200/mgag200_reg.h
@@ -116,6 +116,9 @@
 
 #define	MGAREG_OPMODE		0x1e54
 
+#define MGAREG_PRIMADDR		0x1e58
+#define MGAREG_PRIMEND		0x1e5c
+
 /* Warp Registers */
 #define MGAREG_WIADDR           0x1dc0
 #define MGAREG_WIADDR2          0x1dd8
@@ -200,6 +203,8 @@
 
 /* See table on 4-43 for bop ALU operations */
 
+#define MGADWG_REPLACE	(0xC << 16)
+
 /* See table on 4-44 for translucidity masks */
 
 #define MGADWG_BMONOLEF		( 0x00 << 25 )
@@ -218,6 +223,8 @@
 
 #define MGADWG_PATTERN		( 0x01 << 29 )
 #define MGADWG_TRANSC		( 0x01 << 30 )
+#define MGADWG_CLIPDIS		( 0x01 << 31 )
+
 #define MGAREG_MISC_WRITE	0x3c2
 #define MGAREG_MISC_READ	0x3cc
 #define MGAREG_MEM_MISC_WRITE       0x1fc2
@@ -605,6 +612,9 @@
 #    define MGA_TC2_SELECT_TMU1                 (0x80000000)
 #define MGAREG_TEXTRANS		0x2c34
 #define MGAREG_TEXTRANSHIGH	0x2c38
+#define MGAREG_SECADDR		0x2c40
+#define MGAREG_SECEND		0x2c44
+#define MGAREG_SOFTRAP		0x2c48
 #define MGAREG_TEXFILTER	0x2c58
 #    define MGA_MIN_NRST                        (0x00000000)
 #    define MGA_MIN_BILIN                       (0x00000002)
@@ -691,4 +701,19 @@
 #define MGA_AGP2XPLL_ENABLE		0x1
 #define MGA_AGP2XPLL_DISABLE		0x0
 
+
+#define DWGREG0		0x1c00
+#define DWGREG0_END	0x1dff
+#define DWGREG1		0x2c00
+#define DWGREG1_END	0x2dff
+
+/* These macros convert register address to the 8 bit command index used with DMA
+ * It remaps 0x1c00-0x1dff to 0x00-0x7f (REG0)
+ * and 0x2c00-0x2dff to 0x80-0xff (REG1)
+ */
+#define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
+#define DMAREG0(r)	((u8)((r - DWGREG0) >> 2))
+#define DMAREG1(r)	((u8)(((r - DWGREG1) >> 2) | 0x80))
+#define DMAREG(r)	(ISREG0((r)) ? DMAREG0((r)) : DMAREG1((r)))
+
 #endif
-- 
2.40.1

Re: [PATCH v2 4/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[Thomas Zimmermann]

[-- Attachment #1.1: Type: text/plain, Size: 21287 bytes --]

Hi Jocelyn

Am 31.05.23 um 11:21 schrieb Jocelyn Falempe:
> Even if the transfer is not faster, it brings significant
> improvement in latencies and CPU usage.
> 
> CPU usage drops from 100% of one core to 3% when continuously
> refreshing the screen.

I tried your patchset on a HP Proliant server with a G200EH. I can see 
that the CPU usage goes down, but the time until the screen update 
reaches the hardware's video memory has increased significantly.

Any display update that is more than just moving the mouse results in 
tearing. I can see how the individial scanlines are updated from top to 
bottom. That takes ~1 sec per full frame. So this patch renders the 
display from slow to barely usable.

Best regards
Thomas

> 
> The primary DMA is used to send commands (register write), and
> the secondary DMA to send the pixel data.
> It uses the ILOAD command (chapter 4.5.7 in G200 specification),
> which allows to load an image, or a part of an image from system
> memory to VRAM.
> The last command sent, is a softrap command, which triggers an IRQ
> when the DMA transfer is complete.
> For 16bits and 24bits pixel width, each line is padded to make sure,
> the DMA transfer is a multiple of 32bits. The padded bytes won't be
> drawn on the screen, so they don't need to be initialized.
> 
> Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
> ---
>   drivers/gpu/drm/mgag200/Makefile          |   3 +-
>   drivers/gpu/drm/mgag200/mgag200_dma.c     | 237 ++++++++++++++++++++++
>   drivers/gpu/drm/mgag200/mgag200_drv.c     |   4 +-
>   drivers/gpu/drm/mgag200/mgag200_drv.h     |  29 +++
>   drivers/gpu/drm/mgag200/mgag200_g200.c    |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200eh.c  |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200eh3.c |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200er.c  |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200ev.c  |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200ew3.c |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200se.c  |   4 +
>   drivers/gpu/drm/mgag200/mgag200_g200wb.c  |   4 +
>   drivers/gpu/drm/mgag200/mgag200_mode.c    |  15 +-
>   drivers/gpu/drm/mgag200/mgag200_reg.h     |  25 +++
>   14 files changed, 333 insertions(+), 12 deletions(-)
>   create mode 100644 drivers/gpu/drm/mgag200/mgag200_dma.c
> 
> diff --git a/drivers/gpu/drm/mgag200/Makefile b/drivers/gpu/drm/mgag200/Makefile
> index 182e224c460d..96e23dc5572c 100644
> --- a/drivers/gpu/drm/mgag200/Makefile
> +++ b/drivers/gpu/drm/mgag200/Makefile
> @@ -11,6 +11,7 @@ mgag200-y := \
>   	mgag200_g200se.o \
>   	mgag200_g200wb.o \
>   	mgag200_i2c.o \
> -	mgag200_mode.o
> +	mgag200_mode.o \
> +	mgag200_dma.o
>   
>   obj-$(CONFIG_DRM_MGAG200) += mgag200.o
> diff --git a/drivers/gpu/drm/mgag200/mgag200_dma.c b/drivers/gpu/drm/mgag200/mgag200_dma.c
> new file mode 100644
> index 000000000000..7e9b59ef08d9
> --- /dev/null
> +++ b/drivers/gpu/drm/mgag200/mgag200_dma.c
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2023 Red Hat
> + *
> + * Authors: Jocelyn Falempe
> + *
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/iosys-map.h>
> +#include <linux/wait.h>
> +
> +#include <drm/drm_framebuffer.h>
> +
> +#include "mgag200_drv.h"
> +#include "mgag200_reg.h"
> +
> +/* Maximum number of command block for one DMA transfer
> + * iload should only use 4 blocks
> + */
> +#define MGA_MAX_CMD		50
> +
> +#define MGA_DMA_SIZE		(4 * 1024 * 1024)
> +#define MGA_MIN_DMA_SIZE	(64 * 1024)
> +
> +/*
> + * Allocate coherent buffers for DMA transfer.
> + * We need two buffers, one for the commands, and one for the data.
> + */
> +int mgag200_dma_init(struct mga_device *mdev)
> +{
> +	struct drm_device *dev = &mdev->base;
> +	struct mga_dma *dma = &mdev->dma;
> +	int size;
> +	/* Allocate the command buffer */
> +	dma->cmd = dmam_alloc_coherent(dev->dev, MGA_MAX_CMD * sizeof(*dma->cmd),
> +					&dma->cmd_handle, GFP_KERNEL);
> +
> +	if (!dma->cmd) {
> +		drm_err(dev, "DMA command buffer allocation failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	for (size = MGA_DMA_SIZE; size >= MGA_MIN_DMA_SIZE; size = size >> 1) {
> +		dma->buf = dmam_alloc_coherent(dev->dev, size, &dma->handle, GFP_KERNEL);
> +		if (dma->buf)
> +			break;
> +	}
> +	if (!dma->buf) {
> +		drm_err(dev, "DMA data buffer allocation failed\n");
> +		return -ENOMEM;
> +	}
> +	dma->size = size;
> +	drm_info(dev, "Using DMA with a %dk data buffer\n", size / 1024);
> +
> +	init_waitqueue_head(&dma->waitq);
> +	return 0;
> +}
> +
> +/*
> + * Matrox uses a command block to program the hardware through DMA.
> + * Each command is a register write, and each block contains 4 commands
> + * packed in 5 dwords(u32).
> + * First dword is the 4 register index (8bit) to write for the 4 commands,
> + * followed by the four values to be written.
> + */
> +static void mgag200_dma_add_block(struct mga_device *mdev,
> +			   u32 reg0, u32 val0,
> +			   u32 reg1, u32 val1,
> +			   u32 reg2, u32 val2,
> +			   u32 reg3, u32 val3)
> +{
> +	if (mdev->dma.cmd_idx >= MGA_MAX_CMD) {
> +		pr_err("mgag200: exceeding the DMA command buffer size\n");
> +		return;
> +	}
> +
> +	mdev->dma.cmd[mdev->dma.cmd_idx] = (struct mga_cmd_block) {
> +		.cmd = DMAREG(reg0) | DMAREG(reg1) << 8 | DMAREG(reg2) << 16 | DMAREG(reg3) << 24,
> +		.v0 = val0,
> +		.v1 = val1,
> +		.v2 = val2,
> +		.v3 = val3};
> +	mdev->dma.cmd_idx++;
> +}
> +
> +static void mgag200_dma_run_cmd(struct mga_device *mdev)
> +{
> +	struct drm_device *dev = &mdev->base;
> +	u32 primend;
> +
> +	/* Add a last block to trigger the softrap interrupt */
> +	mgag200_dma_add_block(mdev,
> +			MGAREG_DMAPAD, 0,
> +			MGAREG_DMAPAD, 0,
> +			MGAREG_DMAPAD, 0,
> +			MGAREG_SOFTRAP, 0);
> +
> +	primend = mdev->dma.cmd_handle + mdev->dma.cmd_idx * sizeof(struct mga_cmd_block);
> +
> +	// Use primary DMA to send the commands
> +	WREG32(MGAREG_PRIMADDR, (u32) mdev->dma.cmd_handle);
> +	mdev->dma.in_use = 1;
> +	WREG32(MGAREG_PRIMEND, primend);
> +
> +	wait_event_timeout(mdev->dma.waitq, mdev->dma.in_use == 0, HZ);
> +
> +	if (mdev->dma.in_use) {
> +		drm_err(dev, "DMA transfer timed out\n");
> +		/* something goes wrong, reset the DMA engine */
> +		WREG8(MGAREG_OPMODE, MGAOPM_DMA_BLIT);
> +		mdev->dma.in_use = 0;
> +	}
> +
> +	/* reset command index to start a new sequence */
> +	mdev->dma.cmd_idx = 0;
> +}
> +
> +/*
> + * ILOAD allows to load an image from system memory to the VRAM, and with FXBNDRY, YDST and YDSTLEN,
> + * you can transfer a rectangle, so it's perfect when used with a damage clip.
> + */
> +static void mgag200_iload_cmd(struct mga_device *mdev, int x, int y, int width, int height,
> +			      int width_padded, int cpp)
> +{
> +	int size = width_padded * height;
> +	u32 iload;
> +
> +	iload = MGADWG_ILOAD | MGADWG_SGNZERO | MGADWG_SHIFTZERO | MGADWG_REPLACE | MGADWG_CLIPDIS
> +		| MGADWG_BFCOL;
> +
> +	mgag200_dma_add_block(mdev,
> +		MGAREG_DWGCTL, iload,
> +		MGAREG_FXBNDRY, (((x + width - 1) << 16) | x),
> +		MGAREG_AR0, (width_padded / cpp) - 1,
> +		MGAREG_AR3, 0);
> +
> +	mgag200_dma_add_block(mdev,
> +		MGAREG_AR5, 0,
> +		MGAREG_YDST, y,
> +		MGAREG_DMAPAD, 0,
> +		MGAREG_DMAPAD, 0);
> +
> +	mgag200_dma_add_block(mdev,
> +		MGAREG_DMAPAD, 0,
> +		MGAREG_LEN | MGAREG_EXEC, height,
> +		MGAREG_SECADDR, mdev->dma.handle | 1,
> +		/* Writing SECEND should always be the last command of a block */
> +		MGAREG_SECEND, mdev->dma.handle + size);
> +}
> +
> +static void mgag200_dma_copy(struct mga_device *mdev, const void *src, u32 pitch,
> +				struct drm_rect *clip, int cpp)
> +{
> +	int i;
> +	int width = drm_rect_width(clip);
> +	int height = drm_rect_height(clip);
> +
> +	/* pad each line to 32bits boundaries see section 4.5.7 of G200 Specification */
> +	int width_padded = round_up(width * cpp, 4);
> +
> +	for (i = 0; i < height; i++)
> +		memcpy(mdev->dma.buf + width_padded * i,
> +		       src + (((clip->y1 + i) * pitch) + clip->x1 * cpp),
> +		       width * cpp);
> +
> +	mgag200_iload_cmd(mdev, clip->x1, clip->y1, width, height, width_padded, cpp);
> +	mgag200_dma_run_cmd(mdev);
> +}
> +
> +/*
> + * If the DMA coherent buffer is smaller than damage rectangle, we need to
> + * split it into multiple DMA transfers.
> + */
> +void mgag200_dma_damage(struct mga_device *mdev, const struct iosys_map *vmap,
> +			struct drm_framebuffer *fb, struct drm_rect *clip)
> +{
> +	u32 pitch = fb->pitches[0];
> +	const void *src = vmap[0].vaddr;
> +	struct drm_rect subclip;
> +	int y1;
> +	int lines;
> +	int cpp = fb->format->cpp[0];
> +
> +	/* Number of lines that fit in one DMA buffer */
> +	lines = min(drm_rect_height(clip), (int) mdev->dma.size / (drm_rect_width(clip) * cpp));
> +
> +	subclip.x1 = clip->x1;
> +	subclip.x2 = clip->x2;
> +
> +	for (y1 = clip->y1; y1 < clip->y2; y1 += lines) {
> +		subclip.y1 = y1;
> +		subclip.y2 = min(clip->y2, y1 + lines);
> +		mgag200_dma_copy(mdev, src, pitch, &subclip, cpp);
> +	}
> +}
> +
> +/*
> + * Setup the drawing engine (DWG) registers
> + * Color format, framebuffer width, ...
> + * This must be done before using any DWGCTL command
> + */
> +void mgag200_dma_dwg_setup(struct mga_device *mdev, struct drm_framebuffer *fb)
> +{
> +	u32 maccess;
> +
> +	drm_dbg(&mdev->base, "Setup DWG with %dx%d %p4cc\n",
> +		fb->width, fb->height, &fb->format->format);
> +
> +	switch (fb->format->format) {
> +	case DRM_FORMAT_RGB565:
> +		maccess = MGAMAC_PW16;
> +		break;
> +	case DRM_FORMAT_RGB888:
> +		maccess = MGAMAC_PW24;
> +		break;
> +	case DRM_FORMAT_XRGB8888:
> +		maccess = MGAMAC_PW32;
> +		break;
> +	}
> +	WREG32(MGAREG_MACCESS, maccess);
> +
> +	/* Framebuffer width in pixel */
> +	WREG32(MGAREG_PITCH, fb->width);
> +
> +	/* Sane default value for the drawing engine registers */
> +	WREG32(MGAREG_DSTORG, 0);
> +	WREG32(MGAREG_YDSTORG, 0);
> +	WREG32(MGAREG_SRCORG, 0);
> +	WREG32(MGAREG_CXBNDRY, 0x0FFF0000);
> +	WREG32(MGAREG_YTOP, 0);
> +	WREG32(MGAREG_YBOT, 0x00FFFFFF);
> +
> +	/* Activate blit mode DMA, only write the low part of the register */
> +	WREG8(MGAREG_OPMODE, MGAOPM_DMA_BLIT);
> +}
> +
> diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c
> index a5851dcc6bdd..07f34e4df1b0 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_drv.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
> @@ -119,6 +119,8 @@ static irqreturn_t mgag200_driver_irq_handler(int irq, void *arg)
>   
>   	if (status & MGAIRQ_SOFTRAP) {
>   		WREG32(MGAREG_ICLEAR, MGAIRQ_SOFTRAP);
> +		mdev->dma.in_use = 0;
> +		wake_up(&mdev->dma.waitq);
>   		return IRQ_HANDLED;
>   	}
>   	return IRQ_NONE;
> @@ -187,7 +189,7 @@ int mgag200_device_preinit(struct mga_device *mdev)
>   			       IRQF_SHARED, "mgag200_irq", mdev);
>   	if (ret < 0) {
>   		drm_err(dev, "devm_request_irq(VRAM) failed %d\n", ret);
> -		return -ENXIO;
> +		return ret;
>   	}
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h
> index 9e604dbb8e44..af69f61a11b7 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_drv.h
> +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h
> @@ -277,6 +277,27 @@ struct mgag200_device_funcs {
>   	void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
>   };
>   
> +struct mga_cmd_block {
> +	u32 cmd;
> +	u32 v0;
> +	u32 v1;
> +	u32 v2;
> +	u32 v3;
> +} __packed;
> +
> +struct mga_dma {
> +	void *buf;
> +	size_t size;
> +	dma_addr_t handle;
> +
> +	struct mga_cmd_block *cmd;
> +	int cmd_idx;
> +	dma_addr_t cmd_handle;
> +
> +	wait_queue_head_t waitq;
> +	int in_use;
> +};
> +
>   struct mga_device {
>   	struct drm_device base;
>   
> @@ -291,6 +312,8 @@ struct mga_device {
>   	void __iomem			*vram;
>   	resource_size_t			vram_available;
>   
> +	struct mga_dma dma;
> +
>   	struct drm_plane primary_plane;
>   	struct drm_crtc crtc;
>   	struct drm_encoder encoder;
> @@ -443,4 +466,10 @@ void mgag200_bmc_enable_vidrst(struct mga_device *mdev);
>   				/* mgag200_i2c.c */
>   int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c);
>   
> +/* mgag200_dma.c */
> +int mgag200_dma_init(struct mga_device *mdev);
> +void mgag200_dma_damage(struct mga_device *mdev, const struct iosys_map *vmap,
> +			struct drm_framebuffer *fb, struct drm_rect *clip);
> +void mgag200_dma_dwg_setup(struct mga_device *mdev, struct drm_framebuffer *fb);
> +
>   #endif				/* __MGAG200_DRV_H__ */
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200.c b/drivers/gpu/drm/mgag200/mgag200_g200.c
> index bf5d7fe525a3..4e972518733a 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200.c
> @@ -424,6 +424,10 @@ struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct
>   
>   	mgag200_g200_init_refclk(g200);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200_device_info,
>   				  &mgag200_g200_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh.c b/drivers/gpu/drm/mgag200/mgag200_g200eh.c
> index fad62453a91d..6628b891118d 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200eh.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh.c
> @@ -296,6 +296,10 @@ struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev, const stru
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200eh_device_info,
>   				  &mgag200_g200eh_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
> index 0f7d8112cd49..35219fbe364f 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
> @@ -201,6 +201,10 @@ struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev,
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200eh3_device_info,
>   				  &mgag200_g200eh3_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200er.c b/drivers/gpu/drm/mgag200/mgag200_g200er.c
> index bce267e0f7de..fc6df2ffd99d 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200er.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200er.c
> @@ -330,6 +330,10 @@ struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev, const stru
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200er_device_info,
>   				  &mgag200_g200er_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ev.c b/drivers/gpu/drm/mgag200/mgag200_g200ev.c
> index ac957f42abe1..190c358aba7e 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200ev.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200ev.c
> @@ -335,6 +335,10 @@ struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const stru
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200ev_device_info,
>   				  &mgag200_g200ev_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
> index 170934414d7d..5de7ccbc575c 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
> @@ -221,6 +221,10 @@ struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev,
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200ew3_device_info,
>   				  &mgag200_g200ew3_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c b/drivers/gpu/drm/mgag200/mgag200_g200se.c
> index bd6e573c9a1a..3edb930598dd 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c
> @@ -506,6 +506,10 @@ struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const stru
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_g200se_init_unique_rev_id(g200se);
>   	if (ret)
>   		return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200wb.c b/drivers/gpu/drm/mgag200/mgag200_g200wb.c
> index 9baa727ac6f9..6e731da89a5f 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_g200wb.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_g200wb.c
> @@ -345,6 +345,10 @@ struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const stru
>   	if (ret)
>   		return ERR_PTR(ret);
>   
> +	ret = mgag200_dma_init(mdev);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
>   	ret = mgag200_device_init(mdev, &mgag200_g200wb_device_info,
>   				  &mgag200_g200wb_device_funcs);
>   	if (ret)
> diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
> index 7d8c65372ac4..adfc61428df6 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_mode.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
> @@ -398,15 +398,6 @@ static void mgag200_disable_display(struct mga_device *mdev)
>   	WREG_ECRT(0x01, crtcext1);
>   }
>   
> -static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap,
> -				  struct drm_framebuffer *fb, struct drm_rect *clip)
> -{
> -	struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram);
> -
> -	iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
> -	drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip);
> -}
> -
>   /*
>    * Primary plane
>    */
> @@ -475,9 +466,13 @@ void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
>   	if (!fb)
>   		return;
>   
> +	if (!old_plane_state->fb || fb->format != old_plane_state->fb->format
> +	    || fb->width != old_plane_state->fb->width)
> +		mgag200_dma_dwg_setup(mdev, fb);
> +
>   	drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
>   	drm_atomic_for_each_plane_damage(&iter, &damage) {
> -		mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage);
> +		mgag200_dma_damage(mdev, shadow_plane_state->data, fb, &damage);
>   	}
>   
>   	/* Always scanout image at VRAM offset 0 */
> diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h
> index 748c8e18e938..256ac92dae56 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_reg.h
> +++ b/drivers/gpu/drm/mgag200/mgag200_reg.h
> @@ -116,6 +116,9 @@
>   
>   #define	MGAREG_OPMODE		0x1e54
>   
> +#define MGAREG_PRIMADDR		0x1e58
> +#define MGAREG_PRIMEND		0x1e5c
> +
>   /* Warp Registers */
>   #define MGAREG_WIADDR           0x1dc0
>   #define MGAREG_WIADDR2          0x1dd8
> @@ -200,6 +203,8 @@
>   
>   /* See table on 4-43 for bop ALU operations */
>   
> +#define MGADWG_REPLACE	(0xC << 16)
> +
>   /* See table on 4-44 for translucidity masks */
>   
>   #define MGADWG_BMONOLEF		( 0x00 << 25 )
> @@ -218,6 +223,8 @@
>   
>   #define MGADWG_PATTERN		( 0x01 << 29 )
>   #define MGADWG_TRANSC		( 0x01 << 30 )
> +#define MGADWG_CLIPDIS		( 0x01 << 31 )
> +
>   #define MGAREG_MISC_WRITE	0x3c2
>   #define MGAREG_MISC_READ	0x3cc
>   #define MGAREG_MEM_MISC_WRITE       0x1fc2
> @@ -605,6 +612,9 @@
>   #    define MGA_TC2_SELECT_TMU1                 (0x80000000)
>   #define MGAREG_TEXTRANS		0x2c34
>   #define MGAREG_TEXTRANSHIGH	0x2c38
> +#define MGAREG_SECADDR		0x2c40
> +#define MGAREG_SECEND		0x2c44
> +#define MGAREG_SOFTRAP		0x2c48
>   #define MGAREG_TEXFILTER	0x2c58
>   #    define MGA_MIN_NRST                        (0x00000000)
>   #    define MGA_MIN_BILIN                       (0x00000002)
> @@ -691,4 +701,19 @@
>   #define MGA_AGP2XPLL_ENABLE		0x1
>   #define MGA_AGP2XPLL_DISABLE		0x0
>   
> +
> +#define DWGREG0		0x1c00
> +#define DWGREG0_END	0x1dff
> +#define DWGREG1		0x2c00
> +#define DWGREG1_END	0x2dff
> +
> +/* These macros convert register address to the 8 bit command index used with DMA
> + * It remaps 0x1c00-0x1dff to 0x00-0x7f (REG0)
> + * and 0x2c00-0x2dff to 0x80-0xff (REG1)
> + */
> +#define ISREG0(r)	(r >= DWGREG0 && r <= DWGREG0_END)
> +#define DMAREG0(r)	((u8)((r - DWGREG0) >> 2))
> +#define DMAREG1(r)	((u8)(((r - DWGREG1) >> 2) | 0x80))
> +#define DMAREG(r)	(ISREG0((r)) ? DMAREG0((r)) : DMAREG1((r)))
> +
>   #endif

-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)

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Re: [PATCH v2 4/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[Jocelyn Falempe]

On 15/06/2023 16:24, Thomas Zimmermann wrote:
> Hi Jocelyn
> 
> Am 31.05.23 um 11:21 schrieb Jocelyn Falempe:
>> Even if the transfer is not faster, it brings significant
>> improvement in latencies and CPU usage.
>>
>> CPU usage drops from 100% of one core to 3% when continuously
>> refreshing the screen.
> 
> I tried your patchset on a HP Proliant server with a G200EH. I can see 
> that the CPU usage goes down, but the time until the screen update 
> reaches the hardware's video memory has increased significantly.

Thanks for taking time to test it.
Can you check if there is something in the dmesg ?

The 1s looks suspicious, if the IRQ is not working, there is a 1s 
timeout, which can explain why it will display only one frame per 
second. (logs should be filled with "DMA transfer timed out")

I will see if I can get access to a G200EH, and if I can reproduce this.

Best regards,

-- 

Jocelyn

> 
> Any display update that is more than just moving the mouse results in 
> tearing. I can see how the individial scanlines are updated from top to 
> bottom. That takes ~1 sec per full frame. So this patch renders the 
> display from slow to barely usable.
> 
> Best regards
> Thomas
> 
>>
>> The primary DMA is used to send commands (register write), and
>> the secondary DMA to send the pixel data.
>> It uses the ILOAD command (chapter 4.5.7 in G200 specification),
>> which allows to load an image, or a part of an image from system
>> memory to VRAM.
>> The last command sent, is a softrap command, which triggers an IRQ
>> when the DMA transfer is complete.
>> For 16bits and 24bits pixel width, each line is padded to make sure,
>> the DMA transfer is a multiple of 32bits. The padded bytes won't be
>> drawn on the screen, so they don't need to be initialized.
>>
>> Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
>> ---
>>   drivers/gpu/drm/mgag200/Makefile          |   3 +-
>>   drivers/gpu/drm/mgag200/mgag200_dma.c     | 237 ++++++++++++++++++++++
>>   drivers/gpu/drm/mgag200/mgag200_drv.c     |   4 +-
>>   drivers/gpu/drm/mgag200/mgag200_drv.h     |  29 +++
>>   drivers/gpu/drm/mgag200/mgag200_g200.c    |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200eh.c  |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200eh3.c |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200er.c  |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200ev.c  |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200ew3.c |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200se.c  |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_g200wb.c  |   4 +
>>   drivers/gpu/drm/mgag200/mgag200_mode.c    |  15 +-
>>   drivers/gpu/drm/mgag200/mgag200_reg.h     |  25 +++
>>   14 files changed, 333 insertions(+), 12 deletions(-)
>>   create mode 100644 drivers/gpu/drm/mgag200/mgag200_dma.c
>>
>> diff --git a/drivers/gpu/drm/mgag200/Makefile 
>> b/drivers/gpu/drm/mgag200/Makefile
>> index 182e224c460d..96e23dc5572c 100644
>> --- a/drivers/gpu/drm/mgag200/Makefile
>> +++ b/drivers/gpu/drm/mgag200/Makefile
>> @@ -11,6 +11,7 @@ mgag200-y := \
>>       mgag200_g200se.o \
>>       mgag200_g200wb.o \
>>       mgag200_i2c.o \
>> -    mgag200_mode.o
>> +    mgag200_mode.o \
>> +    mgag200_dma.o
>>   obj-$(CONFIG_DRM_MGAG200) += mgag200.o
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_dma.c 
>> b/drivers/gpu/drm/mgag200/mgag200_dma.c
>> new file mode 100644
>> index 000000000000..7e9b59ef08d9
>> --- /dev/null
>> +++ b/drivers/gpu/drm/mgag200/mgag200_dma.c
>> @@ -0,0 +1,237 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright 2023 Red Hat
>> + *
>> + * Authors: Jocelyn Falempe
>> + *
>> + */
>> +
>> +#include <linux/dma-mapping.h>
>> +#include <linux/iosys-map.h>
>> +#include <linux/wait.h>
>> +
>> +#include <drm/drm_framebuffer.h>
>> +
>> +#include "mgag200_drv.h"
>> +#include "mgag200_reg.h"
>> +
>> +/* Maximum number of command block for one DMA transfer
>> + * iload should only use 4 blocks
>> + */
>> +#define MGA_MAX_CMD        50
>> +
>> +#define MGA_DMA_SIZE        (4 * 1024 * 1024)
>> +#define MGA_MIN_DMA_SIZE    (64 * 1024)
>> +
>> +/*
>> + * Allocate coherent buffers for DMA transfer.
>> + * We need two buffers, one for the commands, and one for the data.
>> + */
>> +int mgag200_dma_init(struct mga_device *mdev)
>> +{
>> +    struct drm_device *dev = &mdev->base;
>> +    struct mga_dma *dma = &mdev->dma;
>> +    int size;
>> +    /* Allocate the command buffer */
>> +    dma->cmd = dmam_alloc_coherent(dev->dev, MGA_MAX_CMD * 
>> sizeof(*dma->cmd),
>> +                    &dma->cmd_handle, GFP_KERNEL);
>> +
>> +    if (!dma->cmd) {
>> +        drm_err(dev, "DMA command buffer allocation failed\n");
>> +        return -ENOMEM;
>> +    }
>> +
>> +    for (size = MGA_DMA_SIZE; size >= MGA_MIN_DMA_SIZE; size = size 
>> >> 1) {
>> +        dma->buf = dmam_alloc_coherent(dev->dev, size, &dma->handle, 
>> GFP_KERNEL);
>> +        if (dma->buf)
>> +            break;
>> +    }
>> +    if (!dma->buf) {
>> +        drm_err(dev, "DMA data buffer allocation failed\n");
>> +        return -ENOMEM;
>> +    }
>> +    dma->size = size;
>> +    drm_info(dev, "Using DMA with a %dk data buffer\n", size / 1024);
>> +
>> +    init_waitqueue_head(&dma->waitq);
>> +    return 0;
>> +}
>> +
>> +/*
>> + * Matrox uses a command block to program the hardware through DMA.
>> + * Each command is a register write, and each block contains 4 commands
>> + * packed in 5 dwords(u32).
>> + * First dword is the 4 register index (8bit) to write for the 4 
>> commands,
>> + * followed by the four values to be written.
>> + */
>> +static void mgag200_dma_add_block(struct mga_device *mdev,
>> +               u32 reg0, u32 val0,
>> +               u32 reg1, u32 val1,
>> +               u32 reg2, u32 val2,
>> +               u32 reg3, u32 val3)
>> +{
>> +    if (mdev->dma.cmd_idx >= MGA_MAX_CMD) {
>> +        pr_err("mgag200: exceeding the DMA command buffer size\n");
>> +        return;
>> +    }
>> +
>> +    mdev->dma.cmd[mdev->dma.cmd_idx] = (struct mga_cmd_block) {
>> +        .cmd = DMAREG(reg0) | DMAREG(reg1) << 8 | DMAREG(reg2) << 16 
>> | DMAREG(reg3) << 24,
>> +        .v0 = val0,
>> +        .v1 = val1,
>> +        .v2 = val2,
>> +        .v3 = val3};
>> +    mdev->dma.cmd_idx++;
>> +}
>> +
>> +static void mgag200_dma_run_cmd(struct mga_device *mdev)
>> +{
>> +    struct drm_device *dev = &mdev->base;
>> +    u32 primend;
>> +
>> +    /* Add a last block to trigger the softrap interrupt */
>> +    mgag200_dma_add_block(mdev,
>> +            MGAREG_DMAPAD, 0,
>> +            MGAREG_DMAPAD, 0,
>> +            MGAREG_DMAPAD, 0,
>> +            MGAREG_SOFTRAP, 0);
>> +
>> +    primend = mdev->dma.cmd_handle + mdev->dma.cmd_idx * 
>> sizeof(struct mga_cmd_block);
>> +
>> +    // Use primary DMA to send the commands
>> +    WREG32(MGAREG_PRIMADDR, (u32) mdev->dma.cmd_handle);
>> +    mdev->dma.in_use = 1;
>> +    WREG32(MGAREG_PRIMEND, primend);
>> +
>> +    wait_event_timeout(mdev->dma.waitq, mdev->dma.in_use == 0, HZ);
>> +
>> +    if (mdev->dma.in_use) {
>> +        drm_err(dev, "DMA transfer timed out\n");
>> +        /* something goes wrong, reset the DMA engine */
>> +        WREG8(MGAREG_OPMODE, MGAOPM_DMA_BLIT);
>> +        mdev->dma.in_use = 0;
>> +    }
>> +
>> +    /* reset command index to start a new sequence */
>> +    mdev->dma.cmd_idx = 0;
>> +}
>> +
>> +/*
>> + * ILOAD allows to load an image from system memory to the VRAM, and 
>> with FXBNDRY, YDST and YDSTLEN,
>> + * you can transfer a rectangle, so it's perfect when used with a 
>> damage clip.
>> + */
>> +static void mgag200_iload_cmd(struct mga_device *mdev, int x, int y, 
>> int width, int height,
>> +                  int width_padded, int cpp)
>> +{
>> +    int size = width_padded * height;
>> +    u32 iload;
>> +
>> +    iload = MGADWG_ILOAD | MGADWG_SGNZERO | MGADWG_SHIFTZERO | 
>> MGADWG_REPLACE | MGADWG_CLIPDIS
>> +        | MGADWG_BFCOL;
>> +
>> +    mgag200_dma_add_block(mdev,
>> +        MGAREG_DWGCTL, iload,
>> +        MGAREG_FXBNDRY, (((x + width - 1) << 16) | x),
>> +        MGAREG_AR0, (width_padded / cpp) - 1,
>> +        MGAREG_AR3, 0);
>> +
>> +    mgag200_dma_add_block(mdev,
>> +        MGAREG_AR5, 0,
>> +        MGAREG_YDST, y,
>> +        MGAREG_DMAPAD, 0,
>> +        MGAREG_DMAPAD, 0);
>> +
>> +    mgag200_dma_add_block(mdev,
>> +        MGAREG_DMAPAD, 0,
>> +        MGAREG_LEN | MGAREG_EXEC, height,
>> +        MGAREG_SECADDR, mdev->dma.handle | 1,
>> +        /* Writing SECEND should always be the last command of a 
>> block */
>> +        MGAREG_SECEND, mdev->dma.handle + size);
>> +}
>> +
>> +static void mgag200_dma_copy(struct mga_device *mdev, const void 
>> *src, u32 pitch,
>> +                struct drm_rect *clip, int cpp)
>> +{
>> +    int i;
>> +    int width = drm_rect_width(clip);
>> +    int height = drm_rect_height(clip);
>> +
>> +    /* pad each line to 32bits boundaries see section 4.5.7 of G200 
>> Specification */
>> +    int width_padded = round_up(width * cpp, 4);
>> +
>> +    for (i = 0; i < height; i++)
>> +        memcpy(mdev->dma.buf + width_padded * i,
>> +               src + (((clip->y1 + i) * pitch) + clip->x1 * cpp),
>> +               width * cpp);
>> +
>> +    mgag200_iload_cmd(mdev, clip->x1, clip->y1, width, height, 
>> width_padded, cpp);
>> +    mgag200_dma_run_cmd(mdev);
>> +}
>> +
>> +/*
>> + * If the DMA coherent buffer is smaller than damage rectangle, we 
>> need to
>> + * split it into multiple DMA transfers.
>> + */
>> +void mgag200_dma_damage(struct mga_device *mdev, const struct 
>> iosys_map *vmap,
>> +            struct drm_framebuffer *fb, struct drm_rect *clip)
>> +{
>> +    u32 pitch = fb->pitches[0];
>> +    const void *src = vmap[0].vaddr;
>> +    struct drm_rect subclip;
>> +    int y1;
>> +    int lines;
>> +    int cpp = fb->format->cpp[0];
>> +
>> +    /* Number of lines that fit in one DMA buffer */
>> +    lines = min(drm_rect_height(clip), (int) mdev->dma.size / 
>> (drm_rect_width(clip) * cpp));
>> +
>> +    subclip.x1 = clip->x1;
>> +    subclip.x2 = clip->x2;
>> +
>> +    for (y1 = clip->y1; y1 < clip->y2; y1 += lines) {
>> +        subclip.y1 = y1;
>> +        subclip.y2 = min(clip->y2, y1 + lines);
>> +        mgag200_dma_copy(mdev, src, pitch, &subclip, cpp);
>> +    }
>> +}
>> +
>> +/*
>> + * Setup the drawing engine (DWG) registers
>> + * Color format, framebuffer width, ...
>> + * This must be done before using any DWGCTL command
>> + */
>> +void mgag200_dma_dwg_setup(struct mga_device *mdev, struct 
>> drm_framebuffer *fb)
>> +{
>> +    u32 maccess;
>> +
>> +    drm_dbg(&mdev->base, "Setup DWG with %dx%d %p4cc\n",
>> +        fb->width, fb->height, &fb->format->format);
>> +
>> +    switch (fb->format->format) {
>> +    case DRM_FORMAT_RGB565:
>> +        maccess = MGAMAC_PW16;
>> +        break;
>> +    case DRM_FORMAT_RGB888:
>> +        maccess = MGAMAC_PW24;
>> +        break;
>> +    case DRM_FORMAT_XRGB8888:
>> +        maccess = MGAMAC_PW32;
>> +        break;
>> +    }
>> +    WREG32(MGAREG_MACCESS, maccess);
>> +
>> +    /* Framebuffer width in pixel */
>> +    WREG32(MGAREG_PITCH, fb->width);
>> +
>> +    /* Sane default value for the drawing engine registers */
>> +    WREG32(MGAREG_DSTORG, 0);
>> +    WREG32(MGAREG_YDSTORG, 0);
>> +    WREG32(MGAREG_SRCORG, 0);
>> +    WREG32(MGAREG_CXBNDRY, 0x0FFF0000);
>> +    WREG32(MGAREG_YTOP, 0);
>> +    WREG32(MGAREG_YBOT, 0x00FFFFFF);
>> +
>> +    /* Activate blit mode DMA, only write the low part of the 
>> register */
>> +    WREG8(MGAREG_OPMODE, MGAOPM_DMA_BLIT);
>> +}
>> +
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c 
>> b/drivers/gpu/drm/mgag200/mgag200_drv.c
>> index a5851dcc6bdd..07f34e4df1b0 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_drv.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
>> @@ -119,6 +119,8 @@ static irqreturn_t mgag200_driver_irq_handler(int 
>> irq, void *arg)
>>       if (status & MGAIRQ_SOFTRAP) {
>>           WREG32(MGAREG_ICLEAR, MGAIRQ_SOFTRAP);
>> +        mdev->dma.in_use = 0;
>> +        wake_up(&mdev->dma.waitq);
>>           return IRQ_HANDLED;
>>       }
>>       return IRQ_NONE;
>> @@ -187,7 +189,7 @@ int mgag200_device_preinit(struct mga_device *mdev)
>>                      IRQF_SHARED, "mgag200_irq", mdev);
>>       if (ret < 0) {
>>           drm_err(dev, "devm_request_irq(VRAM) failed %d\n", ret);
>> -        return -ENXIO;
>> +        return ret;
>>       }
>>       return 0;
>>   }
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h 
>> b/drivers/gpu/drm/mgag200/mgag200_drv.h
>> index 9e604dbb8e44..af69f61a11b7 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_drv.h
>> +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h
>> @@ -277,6 +277,27 @@ struct mgag200_device_funcs {
>>       void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct 
>> drm_atomic_state *old_state);
>>   };
>> +struct mga_cmd_block {
>> +    u32 cmd;
>> +    u32 v0;
>> +    u32 v1;
>> +    u32 v2;
>> +    u32 v3;
>> +} __packed;
>> +
>> +struct mga_dma {
>> +    void *buf;
>> +    size_t size;
>> +    dma_addr_t handle;
>> +
>> +    struct mga_cmd_block *cmd;
>> +    int cmd_idx;
>> +    dma_addr_t cmd_handle;
>> +
>> +    wait_queue_head_t waitq;
>> +    int in_use;
>> +};
>> +
>>   struct mga_device {
>>       struct drm_device base;
>> @@ -291,6 +312,8 @@ struct mga_device {
>>       void __iomem            *vram;
>>       resource_size_t            vram_available;
>> +    struct mga_dma dma;
>> +
>>       struct drm_plane primary_plane;
>>       struct drm_crtc crtc;
>>       struct drm_encoder encoder;
>> @@ -443,4 +466,10 @@ void mgag200_bmc_enable_vidrst(struct mga_device 
>> *mdev);
>>                   /* mgag200_i2c.c */
>>   int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan 
>> *i2c);
>> +/* mgag200_dma.c */
>> +int mgag200_dma_init(struct mga_device *mdev);
>> +void mgag200_dma_damage(struct mga_device *mdev, const struct 
>> iosys_map *vmap,
>> +            struct drm_framebuffer *fb, struct drm_rect *clip);
>> +void mgag200_dma_dwg_setup(struct mga_device *mdev, struct 
>> drm_framebuffer *fb);
>> +
>>   #endif                /* __MGAG200_DRV_H__ */
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200.c
>> index bf5d7fe525a3..4e972518733a 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200.c
>> @@ -424,6 +424,10 @@ struct mga_device 
>> *mgag200_g200_device_create(struct pci_dev *pdev, const struct
>>       mgag200_g200_init_refclk(g200);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200_device_info,
>>                     &mgag200_g200_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200eh.c
>> index fad62453a91d..6628b891118d 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200eh.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh.c
>> @@ -296,6 +296,10 @@ struct mga_device 
>> *mgag200_g200eh_device_create(struct pci_dev *pdev, const stru
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200eh_device_info,
>>                     &mgag200_g200eh_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
>> index 0f7d8112cd49..35219fbe364f 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200eh3.c
>> @@ -201,6 +201,10 @@ struct mga_device 
>> *mgag200_g200eh3_device_create(struct pci_dev *pdev,
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200eh3_device_info,
>>                     &mgag200_g200eh3_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200er.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200er.c
>> index bce267e0f7de..fc6df2ffd99d 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200er.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200er.c
>> @@ -330,6 +330,10 @@ struct mga_device 
>> *mgag200_g200er_device_create(struct pci_dev *pdev, const stru
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200er_device_info,
>>                     &mgag200_g200er_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ev.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200ev.c
>> index ac957f42abe1..190c358aba7e 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200ev.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200ev.c
>> @@ -335,6 +335,10 @@ struct mga_device 
>> *mgag200_g200ev_device_create(struct pci_dev *pdev, const stru
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200ev_device_info,
>>                     &mgag200_g200ev_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
>> index 170934414d7d..5de7ccbc575c 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200ew3.c
>> @@ -221,6 +221,10 @@ struct mga_device 
>> *mgag200_g200ew3_device_create(struct pci_dev *pdev,
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200ew3_device_info,
>>                     &mgag200_g200ew3_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200se.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200se.c
>> index bd6e573c9a1a..3edb930598dd 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200se.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200se.c
>> @@ -506,6 +506,10 @@ struct mga_device 
>> *mgag200_g200se_device_create(struct pci_dev *pdev, const stru
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_g200se_init_unique_rev_id(g200se);
>>       if (ret)
>>           return ERR_PTR(ret);
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_g200wb.c 
>> b/drivers/gpu/drm/mgag200/mgag200_g200wb.c
>> index 9baa727ac6f9..6e731da89a5f 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_g200wb.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_g200wb.c
>> @@ -345,6 +345,10 @@ struct mga_device 
>> *mgag200_g200wb_device_create(struct pci_dev *pdev, const stru
>>       if (ret)
>>           return ERR_PTR(ret);
>> +    ret = mgag200_dma_init(mdev);
>> +    if (ret)
>> +        return ERR_PTR(ret);
>> +
>>       ret = mgag200_device_init(mdev, &mgag200_g200wb_device_info,
>>                     &mgag200_g200wb_device_funcs);
>>       if (ret)
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c 
>> b/drivers/gpu/drm/mgag200/mgag200_mode.c
>> index 7d8c65372ac4..adfc61428df6 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_mode.c
>> +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
>> @@ -398,15 +398,6 @@ static void mgag200_disable_display(struct 
>> mga_device *mdev)
>>       WREG_ECRT(0x01, crtcext1);
>>   }
>> -static void mgag200_handle_damage(struct mga_device *mdev, const 
>> struct iosys_map *vmap,
>> -                  struct drm_framebuffer *fb, struct drm_rect *clip)
>> -{
>> -    struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram);
>> -
>> -    iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], 
>> fb->format, clip));
>> -    drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip);
>> -}
>> -
>>   /*
>>    * Primary plane
>>    */
>> @@ -475,9 +466,13 @@ void 
>> mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
>>       if (!fb)
>>           return;
>> +    if (!old_plane_state->fb || fb->format != 
>> old_plane_state->fb->format
>> +        || fb->width != old_plane_state->fb->width)
>> +        mgag200_dma_dwg_setup(mdev, fb);
>> +
>>       drm_atomic_helper_damage_iter_init(&iter, old_plane_state, 
>> plane_state);
>>       drm_atomic_for_each_plane_damage(&iter, &damage) {
>> -        mgag200_handle_damage(mdev, shadow_plane_state->data, fb, 
>> &damage);
>> +        mgag200_dma_damage(mdev, shadow_plane_state->data, fb, &damage);
>>       }
>>       /* Always scanout image at VRAM offset 0 */
>> diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h 
>> b/drivers/gpu/drm/mgag200/mgag200_reg.h
>> index 748c8e18e938..256ac92dae56 100644
>> --- a/drivers/gpu/drm/mgag200/mgag200_reg.h
>> +++ b/drivers/gpu/drm/mgag200/mgag200_reg.h
>> @@ -116,6 +116,9 @@
>>   #define    MGAREG_OPMODE        0x1e54
>> +#define MGAREG_PRIMADDR        0x1e58
>> +#define MGAREG_PRIMEND        0x1e5c
>> +
>>   /* Warp Registers */
>>   #define MGAREG_WIADDR           0x1dc0
>>   #define MGAREG_WIADDR2          0x1dd8
>> @@ -200,6 +203,8 @@
>>   /* See table on 4-43 for bop ALU operations */
>> +#define MGADWG_REPLACE    (0xC << 16)
>> +
>>   /* See table on 4-44 for translucidity masks */
>>   #define MGADWG_BMONOLEF        ( 0x00 << 25 )
>> @@ -218,6 +223,8 @@
>>   #define MGADWG_PATTERN        ( 0x01 << 29 )
>>   #define MGADWG_TRANSC        ( 0x01 << 30 )
>> +#define MGADWG_CLIPDIS        ( 0x01 << 31 )
>> +
>>   #define MGAREG_MISC_WRITE    0x3c2
>>   #define MGAREG_MISC_READ    0x3cc
>>   #define MGAREG_MEM_MISC_WRITE       0x1fc2
>> @@ -605,6 +612,9 @@
>>   #    define MGA_TC2_SELECT_TMU1                 (0x80000000)
>>   #define MGAREG_TEXTRANS        0x2c34
>>   #define MGAREG_TEXTRANSHIGH    0x2c38
>> +#define MGAREG_SECADDR        0x2c40
>> +#define MGAREG_SECEND        0x2c44
>> +#define MGAREG_SOFTRAP        0x2c48
>>   #define MGAREG_TEXFILTER    0x2c58
>>   #    define MGA_MIN_NRST                        (0x00000000)
>>   #    define MGA_MIN_BILIN                       (0x00000002)
>> @@ -691,4 +701,19 @@
>>   #define MGA_AGP2XPLL_ENABLE        0x1
>>   #define MGA_AGP2XPLL_DISABLE        0x0
>> +
>> +#define DWGREG0        0x1c00
>> +#define DWGREG0_END    0x1dff
>> +#define DWGREG1        0x2c00
>> +#define DWGREG1_END    0x2dff
>> +
>> +/* These macros convert register address to the 8 bit command index 
>> used with DMA
>> + * It remaps 0x1c00-0x1dff to 0x00-0x7f (REG0)
>> + * and 0x2c00-0x2dff to 0x80-0xff (REG1)
>> + */
>> +#define ISREG0(r)    (r >= DWGREG0 && r <= DWGREG0_END)
>> +#define DMAREG0(r)    ((u8)((r - DWGREG0) >> 2))
>> +#define DMAREG1(r)    ((u8)(((r - DWGREG1) >> 2) | 0x80))
>> +#define DMAREG(r)    (ISREG0((r)) ? DMAREG0((r)) : DMAREG1((r)))
>> +
>>   #endif
> 

Re: [PATCH v2 4/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[Thomas Zimmermann]

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Hi

Am 15.06.23 um 19:15 schrieb Jocelyn Falempe:
> On 15/06/2023 16:24, Thomas Zimmermann wrote:
>> Hi Jocelyn
>>
>> Am 31.05.23 um 11:21 schrieb Jocelyn Falempe:
>>> Even if the transfer is not faster, it brings significant
>>> improvement in latencies and CPU usage.
>>>
>>> CPU usage drops from 100% of one core to 3% when continuously
>>> refreshing the screen.
>>
>> I tried your patchset on a HP Proliant server with a G200EH. I can see 
>> that the CPU usage goes down, but the time until the screen update 
>> reaches the hardware's video memory has increased significantly.
> 
> Thanks for taking time to test it.
> Can you check if there is something in the dmesg ?
> 
> The 1s looks suspicious, if the IRQ is not working, there is a 1s 
> timeout, which can explain why it will display only one frame per 
> second. (logs should be filled with "DMA transfer timed out")

No, I don't see that error. I also verified that the IRQ handler is 
running. It runs on each update AFAICT.

When I'm doing full-screen scrolling on the kernel console I can see the 
scanlines being updated from top to bottom. This indicates to me that 
the actual copying takes time or interferes with the scanout.

Best regards
Thomas

> 
> I will see if I can get access to a G200EH, and if I can reproduce this.
> 
> Best regards,
> 

-- 
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)

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Re: [PATCH v2 4/4] drm/mgag200: Use DMA to copy the framebuffer to the VRAM

[Jocelyn Falempe]

On 16/06/2023 10:08, Thomas Zimmermann wrote:
> Hi
> 
> Am 15.06.23 um 19:15 schrieb Jocelyn Falempe:
>> On 15/06/2023 16:24, Thomas Zimmermann wrote:
>>> Hi Jocelyn
>>>
>>> Am 31.05.23 um 11:21 schrieb Jocelyn Falempe:
>>>> Even if the transfer is not faster, it brings significant
>>>> improvement in latencies and CPU usage.
>>>>
>>>> CPU usage drops from 100% of one core to 3% when continuously
>>>> refreshing the screen.
>>>
>>> I tried your patchset on a HP Proliant server with a G200EH. I can 
>>> see that the CPU usage goes down, but the time until the screen 
>>> update reaches the hardware's video memory has increased significantly.
>>
>> Thanks for taking time to test it.
>> Can you check if there is something in the dmesg ?
>>
>> The 1s looks suspicious, if the IRQ is not working, there is a 1s 
>> timeout, which can explain why it will display only one frame per 
>> second. (logs should be filled with "DMA transfer timed out")
> 
> No, I don't see that error. I also verified that the IRQ handler is 
> running. It runs on each update AFAICT.
> 
> When I'm doing full-screen scrolling on the kernel console I can see the 
> scanlines being updated from top to bottom. This indicates to me that 
> the actual copying takes time or interferes with the scanout.
> 
> Best regards
> Thomas
> 
>>
>> I will see if I can get access to a G200EH, and if I can reproduce this.
>>
>> Best regards,
>>
> 

I reproduced the issue on G200EH, and there is the same problem on 
G200eR2 [102b:0534], G200eW3 [102b:0536], G200eH3 [102b:0538]
On these severs, DMA is between 2x and 10x slower than memcpy().
I didn't find a setting in Matrox register, that has an effect on this.
At this point, I think the problem may lie in the PCIe <-> PCI bridge.

I also tested on a MGA G200e [102b:0522] where the IRQ is not working at 
all.

So it looks like I've done the development on one of the few models, 
where the DMA is not completely broken.

So let's abandon this, as most hardware can't handle DMA with acceptable 
performance, and some have even broken IRQ.

Here is my complete test results:

Dell T310 G200WB [102b:0532]:
MGA memcpy: x 1280, y 1024, time: 124832 us
MGA iload: x 1280, y 1024, time: 123794 us
With PCI burst enabled (OPTION enhmemacc set to 1 and HEADER cacheline 
set to 0x08)
MGA iload: x 1280, y 1024, time : 51880 us

HP dl160 Gen8 G200EH [102b:0533]:
MGA memcpy: x 1024, y 768, time: 31542 us
MGA iload: x 1024, y 768, time: 312638 us

Dell pem520  G200eR2 [102b:0534]:
MGA memcpy: x 1280, y 1024, time : 30156 us
IRQ not working

Dell per640 G200eW3 [102b:0536]:
MGA memcpy: x 1024, y 768, time : 15586 us
MGA iload: x 1024, y 768, time : 60900 us

HP dl120 gen10 G200eH3 [102b:0538] (rev 02):
MGA memcpy: x 1024, y 768, time : 22539 us
MGA iload: x 1024, y 768, time : 38324 us

HP dl180 G200e [102b:0522] (rev 02)
MGA memcpy: x 1024, y 768, time : 35749 us
MGA iload busywait: x 1024, y 768, time : 137079 us
IRQ not working

Best regards,

-- 

Jocelyn