From: Ludovic BARRE <ludovic.barre@st.com> To: Marek Vasut <marek.vasut@gmail.com>, Cyrille Pitchen <cyrille.pitchen@atmel.com> Cc: David Woodhouse <dwmw2@infradead.org>, Brian Norris <computersforpeace@gmail.com>, Boris Brezillon <boris.brezillon@free-electrons.com>, Richard Weinberger <richard@nod.at>, Alexandre Torgue <alexandre.torgue@st.com>, Rob Herring <robh+dt@kernel.org>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: Re: [PATCH 2/2] mtd: spi-nor: add driver for STM32 quad spi flash controller Date: Wed, 29 Mar 2017 18:38:56 +0200 [thread overview] Message-ID: <d785a279-362c-3693-d318-08ef43af7ad4@st.com> (raw) In-Reply-To: <0e7da44f-c41b-de15-62c3-7509e556f623@gmail.com> On 03/29/2017 03:57 PM, Marek Vasut wrote: > On 03/29/2017 03:35 PM, Ludovic BARRE wrote: > > [...] > >>>>>> + writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | >>>>>> CR_SSHIFT >>>>>> + | CR_EN, qspi->io_base + QUADSPI_CR); >>>>>> + >>>>>> + /* a minimum fsize must be set to sent the command id */ >>>>>> + flash->fsize = 25; >>>>> I don't understand why this is needed and the comment doesn't make >>>>> sense. Please fix. >>>> fsize field defines the size of external memory. >>> What external memory ? Unclear >> oops, fsize field defined the size of "flash memory" in stm32 qspi >> controller. > Errr, now I am totally lost :) Is that some internal SPI NOR ? Shouldn't > the size be coming from DT or something ? > >> Number of bytes in Flash memory = 2 ^[FSIZE+1]. >> To sent a nor cmd this field must be set (hardware issue), >> but before "spi_nor_scan" the size of flash nor is not know. >> So I set a temporary value (workaround). > Is it needed before the scan ? yes it's needed before scan (fix a "stm32 qspi controller" issue) sorry, I try to reformulate: The nor flash (external component like micron n25q128a13 or spansion s25fl512s ...) is connected to stm32 by classic spi-nor interface cs, clock and 1/2/4 IO lines. the stm32 microprocessor has a dedicated controller to manage spi-nor interface, it's stm32 qspi. In stm32 qspi controller there is a register with fsize field which define the size of nor flash (n25q128a13 or s25fl512s...). fsize can't be null, else the stm32 qspi controller doesn't send spi-nor command. it's "stm32 qspi controller" issue. Before the "spi_nor_scan" the size of nor flash (n25q128a13 or s25fl512s...) is not know. So we set a temporary value just to discover the nor flash with "spi_nor_scan". After we can set the right value (mtd->size) in fsize. >> After "spi_nor_scan" the fsize is overwritten by the right value >> flash->fsize = __fls(mtd->size) - 1; >>>> Normaly, this field is used only for memory map mode, >>>> but in fact is check in indirect mode. >>>> So while flash scan "spi_nor_scan": >>>> -I can't let 0. >>>> -I not know yet the size of flash. >>>> So I fix a temporary value >>>> >>>> I will update my comment >>> Please do, also please consider that I'm reading the comment and I >>> barely have any clue about this hardware , so make sure I can >>> understand it. >>> >>>>>> + ret = spi_nor_scan(&flash->nor, NULL, flash_read); >>>>>> + if (ret) { >>>>>> + dev_err(qspi->dev, "device scan failed\n"); >>>>>> + return ret; >>>>>> + } >>>>>> + >>>>>> + flash->fsize = __fls(mtd->size) - 1; >>>>>> + >>>>>> + writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR); >>>>>> + >>>>>> + ret = mtd_device_register(mtd, NULL, 0); >>>>>> + if (ret) { >>>>>> + dev_err(qspi->dev, "mtd device parse failed\n"); >>>>>> + return ret; >>>>>> + } >>>>>> + >>>>>> + dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n", >>>>>> + qspi->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, >>>>>> width); >>>>>> + >>>>>> + return 0; >>>>>> +} >>>>> [...] >>>>> >
WARNING: multiple messages have this Message-ID (diff)
From: Ludovic BARRE <ludovic.barre-qxv4g6HH51o@public.gmane.org> To: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Cyrille Pitchen <cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org> Cc: David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>, Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>, Richard Weinberger <richard-/L3Ra7n9ekc@public.gmane.org>, Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: Re: [PATCH 2/2] mtd: spi-nor: add driver for STM32 quad spi flash controller Date: Wed, 29 Mar 2017 18:38:56 +0200 [thread overview] Message-ID: <d785a279-362c-3693-d318-08ef43af7ad4@st.com> (raw) In-Reply-To: <0e7da44f-c41b-de15-62c3-7509e556f623-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> On 03/29/2017 03:57 PM, Marek Vasut wrote: > On 03/29/2017 03:35 PM, Ludovic BARRE wrote: > > [...] > >>>>>> + writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | >>>>>> CR_SSHIFT >>>>>> + | CR_EN, qspi->io_base + QUADSPI_CR); >>>>>> + >>>>>> + /* a minimum fsize must be set to sent the command id */ >>>>>> + flash->fsize = 25; >>>>> I don't understand why this is needed and the comment doesn't make >>>>> sense. Please fix. >>>> fsize field defines the size of external memory. >>> What external memory ? Unclear >> oops, fsize field defined the size of "flash memory" in stm32 qspi >> controller. > Errr, now I am totally lost :) Is that some internal SPI NOR ? Shouldn't > the size be coming from DT or something ? > >> Number of bytes in Flash memory = 2 ^[FSIZE+1]. >> To sent a nor cmd this field must be set (hardware issue), >> but before "spi_nor_scan" the size of flash nor is not know. >> So I set a temporary value (workaround). > Is it needed before the scan ? yes it's needed before scan (fix a "stm32 qspi controller" issue) sorry, I try to reformulate: The nor flash (external component like micron n25q128a13 or spansion s25fl512s ...) is connected to stm32 by classic spi-nor interface cs, clock and 1/2/4 IO lines. the stm32 microprocessor has a dedicated controller to manage spi-nor interface, it's stm32 qspi. In stm32 qspi controller there is a register with fsize field which define the size of nor flash (n25q128a13 or s25fl512s...). fsize can't be null, else the stm32 qspi controller doesn't send spi-nor command. it's "stm32 qspi controller" issue. Before the "spi_nor_scan" the size of nor flash (n25q128a13 or s25fl512s...) is not know. So we set a temporary value just to discover the nor flash with "spi_nor_scan". After we can set the right value (mtd->size) in fsize. >> After "spi_nor_scan" the fsize is overwritten by the right value >> flash->fsize = __fls(mtd->size) - 1; >>>> Normaly, this field is used only for memory map mode, >>>> but in fact is check in indirect mode. >>>> So while flash scan "spi_nor_scan": >>>> -I can't let 0. >>>> -I not know yet the size of flash. >>>> So I fix a temporary value >>>> >>>> I will update my comment >>> Please do, also please consider that I'm reading the comment and I >>> barely have any clue about this hardware , so make sure I can >>> understand it. >>> >>>>>> + ret = spi_nor_scan(&flash->nor, NULL, flash_read); >>>>>> + if (ret) { >>>>>> + dev_err(qspi->dev, "device scan failed\n"); >>>>>> + return ret; >>>>>> + } >>>>>> + >>>>>> + flash->fsize = __fls(mtd->size) - 1; >>>>>> + >>>>>> + writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR); >>>>>> + >>>>>> + ret = mtd_device_register(mtd, NULL, 0); >>>>>> + if (ret) { >>>>>> + dev_err(qspi->dev, "mtd device parse failed\n"); >>>>>> + return ret; >>>>>> + } >>>>>> + >>>>>> + dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n", >>>>>> + qspi->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, >>>>>> width); >>>>>> + >>>>>> + return 0; >>>>>> +} >>>>> [...] >>>>> > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2017-03-29 16:40 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-27 12:54 [PATCH 0/2] mtd: spi-nor: add stm32 qspi driver Ludovic Barre 2017-03-27 12:54 ` Ludovic Barre 2017-03-27 12:54 ` [PATCH 1/2] dt-bindings: Document the STM32 QSPI bindings Ludovic Barre 2017-03-27 12:54 ` Ludovic Barre 2017-03-27 12:54 ` [PATCH 2/2] mtd: spi-nor: add driver for STM32 quad spi flash controller Ludovic Barre 2017-03-27 12:54 ` Ludovic Barre 2017-03-29 10:54 ` Marek Vasut 2017-03-29 10:54 ` Marek Vasut 2017-03-29 12:24 ` Ludovic BARRE 2017-03-29 12:24 ` Ludovic BARRE 2017-03-29 13:09 ` Marek Vasut 2017-03-29 13:09 ` Marek Vasut 2017-03-29 13:35 ` Ludovic BARRE 2017-03-29 13:35 ` Ludovic BARRE 2017-03-29 13:57 ` Marek Vasut 2017-03-29 16:38 ` Ludovic BARRE [this message] 2017-03-29 16:38 ` Ludovic BARRE 2017-03-30 10:17 ` Marek Vasut 2017-03-30 10:17 ` Marek Vasut 2017-03-29 16:51 ` [PATCH 0/2] mtd: spi-nor: add stm32 qspi driver Cyrille Pitchen 2017-03-29 16:51 ` Cyrille Pitchen 2017-03-30 7:31 ` Ludovic BARRE 2017-03-30 7:31 ` Ludovic BARRE 2017-03-30 10:15 ` Marek Vasut 2017-03-30 10:15 ` Marek Vasut 2017-04-05 16:20 ` Ludovic BARRE 2017-04-05 16:20 ` Ludovic BARRE 2017-04-06 20:07 ` Cyrille Pitchen 2017-04-06 20:07 ` Cyrille Pitchen
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