i82975x chip location correction

* i82975x chip location correction
@ 2010-01-29  9:33 Arvind R
  2010-02-12  5:07 ` Doug Thompson
  2010-02-21  4:26 ` [SPAM] Support for Intel 5500 chipset & 5500&5600 CPU caohe
  0 siblings, 2 replies; 4+ messages in thread
From: Arvind R @ 2010-01-29  9:33 UTC (permalink / raw)
  To: bluesmoke-devel


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This is a patch I've been using for quite some time now and have luckily
verified on an errant system. Surprised that it has not made it upstream.
Since I saw some posts on misreporting of chip rows, etc. I'm sending this
again.

diff -Nru a/drivers/edac/i82975x_edac.c b/drivers/edac/i82975x_edac.c

--- a/drivers/edac/i82975x_edac.c   2009-09-10 03:43:59.000000000 +0530
+++ b/drivers/edac/i82975x_edac.c   2010-01-29 14:44:00.000000000 +0530
@@ -279,6 +279,7 @@
        struct i82975x_error_info *info, int handle_errors)
 {
    int row, multi_chan, chan;
+   unsigned long offst;

    multi_chan = mci->csrows[0].nr_channels - 1;

@@ -294,16 +295,17 @@
    }

    chan = info->eap & 1;
+   offst = (info->eap & ~0x7f) & ((1 << PAGE_SHIFT) - 1);
    info->eap >>= 1;
    if (info->xeap )
        info->eap |= 0x80000000;
-   info->eap >>= PAGE_SHIFT;
+   info->eap >>= (PAGE_SHIFT - 1);
    row = edac_mc_find_csrow_by_page(mci, info->eap);

    if (info->errsts & 0x0002)
-       edac_mc_handle_ue(mci, info->eap, 0, row, "i82975x UE");
+       edac_mc_handle_ue(mci, info->eap, offst , row, "i82975x UE");
    else
-       edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
+       edac_mc_handle_ce(mci, info->eap, offst, info->derrsyn, row,
                multi_chan ? chan : 0,
                "i82975x CE");

@@ -339,6 +341,7 @@
        drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
        dualch = dualch && (drb[row][0] == drb[row][1]);
    }
+   debugf3("%s(): Mode %s\n", __func__, dualch ? "Symmetric" :
"Asymmetric");
    return dualch;
 }

@@ -383,19 +386,21 @@

        value = readb(mch_window + I82975X_DRB + index +
                    ((index >= 4) ? 0x80 : 0));
-       cumul_size = value;
+       cumul_size = value & ~3;
        cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
        debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
            cumul_size);
-       if (cumul_size == last_cumul_size)
+       if (cumul_size == last_cumul_size)  {
+           csrow->nr_pages = 0;
            continue;   /* not populated */
+       }

        csrow->first_page = last_cumul_size;
        csrow->last_page = cumul_size - 1;
        csrow->nr_pages = cumul_size - last_cumul_size;
        last_cumul_size = cumul_size;
        csrow->grain = 1 << 7;  /* I82975X_EAP has 128B resolution */
-       csrow->mtype = MEM_DDR; /* i82975x supports only DDR2 */
+       csrow->mtype = MEM_DDR2; /* i82975x supports only DDR2 */
        csrow->dtype = i82975x_dram_type(mch_window, index);
        csrow->edac_mode = EDAC_SECDED; /* only supported */
    }
@@ -516,18 +521,20 @@

    debugf3("%s(): init mci\n", __func__);
    mci->dev = &pdev->dev;
-   mci->mtype_cap = MEM_FLAG_DDR;
+   mci->mtype_cap = MEM_FLAG_DDR2;
    mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
    mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
    mci->mod_name = EDAC_MOD_STR;
    mci->mod_ver = I82975X_REVISION;
    mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
+   mci->dev_name = pci_name(pdev);
    mci->edac_check = i82975x_check;
    mci->ctl_page_to_phys = NULL;
    debugf3("%s(): init pvt\n", __func__);
    pvt = (struct i82975x_pvt *) mci->pvt_info;
    pvt->mch_window = mch_window;
    i82975x_init_csrows(mci, pdev, mch_window);
+   mci->scrub_mode = SCRUB_SW_SRC;
    i82975x_get_error_info(mci, &discard);  /* clear counters */

    /* finalize this instance of memory controller with edac core */
@@ -665,7 +672,7 @@
 module_exit(i82975x_exit);

 MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Arvind R. <arvind@acarlab.com>");
+MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");

 module_param(edac_op_state, int, 0444);

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