* [Qemu-devel] [PATCH v1 4/8] s390x/tcg: add instruction flags for floating point instructions
2018-08-22 7:57 [Qemu-devel] [PATCH v1 0/8] s390x/tcg: instruction flags and AFP registers David Hildenbrand
` (2 preceding siblings ...)
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 3/8] s390x/tcg: support flags for instructions David Hildenbrand
@ 2018-08-22 7:57 ` David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 5/8] s390x/tcg: check for AFP-register, BFP and DFP data exceptions David Hildenbrand
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: David Hildenbrand @ 2018-08-22 7:57 UTC (permalink / raw)
To: qemu-s390x
Cc: qemu-devel, Richard Henderson, Alexander Graf, Cornelia Huck,
Thomas Huth, David Hildenbrand
These flags allow us to later on detect if a DATA program interrupt
is to be injected, and which DXC (1,2,3) is to be used.
Interestingly, some support FP instructions are considered as HFP
instructions (I assume simply because they were available very early).
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 254 ++++++++++++++++++-------------------
target/s390x/translate.c | 8 ++
2 files changed, 135 insertions(+), 127 deletions(-)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ff4a6ceaf5..506c3de1d7 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -32,11 +32,11 @@
C(0xb9e8, AGRK, RRF_a, DO, r2, r3, r1, 0, add, adds64)
C(0xe308, AG, RXY_a, Z, r1, m2_64, r1, 0, add, adds64)
C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64)
- C(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32)
- C(0xb31a, ADBR, RRE, Z, f1_o, f2_o, f1, 0, adb, f64)
- C(0xb34a, AXBR, RRE, Z, 0, x2_o, x1, 0, axb, f128)
- C(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32)
- C(0xed1a, ADB, RXE, Z, f1_o, m2_64, f1, 0, adb, f64)
+ F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP)
+ F(0xb31a, ADBR, RRE, Z, f1_o, f2_o, f1, 0, adb, f64, IF_BFP)
+ F(0xb34a, AXBR, RRE, Z, 0, x2_o, x1, 0, axb, f128, IF_BFP)
+ F(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32, IF_BFP)
+ F(0xed1a, ADB, RXE, Z, f1_o, m2_64, f1, 0, adb, f64, IF_BFP)
/* ADD HIGH */
C(0xb9c8, AHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, adds32)
C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32)
@@ -151,7 +151,7 @@
C(0xb241, CKSM, RRE, Z, r1_o, ra2, new, r1_32, cksm, 0)
/* COPY SIGN */
- C(0xb372, CPSDR, RRF_b, FPSSH, f3_o, f2_o, f1, 0, cps, 0)
+ F(0xb372, CPSDR, RRF_b, FPSSH, f3_o, f2_o, f1, 0, cps, 0, IF_HFP1 | IF_HFP2 | IF_HFP3)
/* COMPARE */
C(0x1900, CR, RR_a, Z, r1_o, r2_o, 0, 0, 0, cmps32)
@@ -161,17 +161,17 @@
C(0xb930, CGFR, RRE, Z, r1_o, r2_32s, 0, 0, 0, cmps64)
C(0xe320, CG, RXY_a, Z, r1_o, m2_64, 0, 0, 0, cmps64)
C(0xe330, CGF, RXY_a, Z, r1_o, m2_32s, 0, 0, 0, cmps64)
- C(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0)
- C(0xb319, CDBR, RRE, Z, f1_o, f2_o, 0, 0, cdb, 0)
- C(0xb349, CXBR, RRE, Z, x1_o, x2_o, 0, 0, cxb, 0)
- C(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0)
- C(0xed19, CDB, RXE, Z, f1_o, m2_64, 0, 0, cdb, 0)
+ F(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0, IF_BFP)
+ F(0xb319, CDBR, RRE, Z, f1_o, f2_o, 0, 0, cdb, 0, IF_BFP)
+ F(0xb349, CXBR, RRE, Z, x1_o, x2_o, 0, 0, cxb, 0, IF_BFP)
+ F(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0, IF_BFP)
+ F(0xed19, CDB, RXE, Z, f1_o, m2_64, 0, 0, cdb, 0, IF_BFP)
/* COMPARE AND SIGNAL */
- C(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0)
- C(0xb318, KDBR, RRE, Z, f1_o, f2_o, 0, 0, kdb, 0)
- C(0xb348, KXBR, RRE, Z, x1_o, x2_o, 0, 0, kxb, 0)
- C(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0)
- C(0xed18, KDB, RXE, Z, f1_o, m2_64, 0, 0, kdb, 0)
+ F(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0, IF_BFP)
+ F(0xb318, KDBR, RRE, Z, f1_o, f2_o, 0, 0, kdb, 0, IF_BFP)
+ F(0xb348, KXBR, RRE, Z, x1_o, x2_o, 0, 0, kxb, 0, IF_BFP)
+ F(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0, IF_BFP)
+ F(0xed18, KDB, RXE, Z, f1_o, m2_64, 0, 0, kdb, 0, IF_BFP)
/* COMPARE IMMEDIATE */
C(0xc20d, CFI, RIL_a, EI, r1, i2, 0, 0, 0, cmps32)
C(0xc20c, CGFI, RIL_a, EI, r1, i2, 0, 0, 0, cmps64)
@@ -288,33 +288,33 @@
C(0x4e00, CVD, RX_a, Z, r1_o, a2, 0, 0, cvd, 0)
C(0xe326, CVDY, RXY_a, LD, r1_o, a2, 0, 0, cvd, 0)
/* CONVERT TO FIXED */
- C(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0)
- C(0xb399, CFDBR, RRF_e, Z, 0, f2_o, new, r1_32, cfdb, 0)
- C(0xb39a, CFXBR, RRF_e, Z, 0, x2_o, new, r1_32, cfxb, 0)
- C(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0)
- C(0xb3a9, CGDBR, RRF_e, Z, 0, f2_o, r1, 0, cgdb, 0)
- C(0xb3aa, CGXBR, RRF_e, Z, 0, x2_o, r1, 0, cgxb, 0)
+ F(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0, IF_BFP)
+ F(0xb399, CFDBR, RRF_e, Z, 0, f2_o, new, r1_32, cfdb, 0, IF_BFP)
+ F(0xb39a, CFXBR, RRF_e, Z, 0, x2_o, new, r1_32, cfxb, 0, IF_BFP)
+ F(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0, IF_BFP)
+ F(0xb3a9, CGDBR, RRF_e, Z, 0, f2_o, r1, 0, cgdb, 0, IF_BFP)
+ F(0xb3aa, CGXBR, RRF_e, Z, 0, x2_o, r1, 0, cgxb, 0, IF_BFP)
/* CONVERT FROM FIXED */
- C(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0)
- C(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, f1, 0, cdgb, 0)
- C(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, x1, 0, cxgb, 0)
- C(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0)
- C(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, f1, 0, cdgb, 0)
- C(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, x1, 0, cxgb, 0)
+ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP)
+ F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, f1, 0, cdgb, 0, IF_BFP)
+ F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, x1, 0, cxgb, 0, IF_BFP)
+ F(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0, IF_BFP)
+ F(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, f1, 0, cdgb, 0, IF_BFP)
+ F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, x1, 0, cxgb, 0, IF_BFP)
/* CONVERT TO LOGICAL */
- C(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0)
- C(0xb39d, CLFDBR, RRF_e, FPE, 0, f2_o, new, r1_32, clfdb, 0)
- C(0xb39e, CLFXBR, RRF_e, FPE, 0, x2_o, new, r1_32, clfxb, 0)
- C(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0)
- C(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2_o, r1, 0, clgdb, 0)
- C(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2_o, r1, 0, clgxb, 0)
+ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP)
+ F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2_o, new, r1_32, clfdb, 0, IF_BFP)
+ F(0xb39e, CLFXBR, RRF_e, FPE, 0, x2_o, new, r1_32, clfxb, 0, IF_BFP)
+ F(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0, IF_BFP)
+ F(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2_o, r1, 0, clgdb, 0, IF_BFP)
+ F(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2_o, r1, 0, clgxb, 0, IF_BFP)
/* CONVERT FROM LOGICAL */
- C(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0)
- C(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, f1, 0, cdlgb, 0)
- C(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, x1, 0, cxlgb, 0)
- C(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0)
- C(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, f1, 0, cdlgb, 0)
- C(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, x1, 0, cxlgb, 0)
+ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP)
+ F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, f1, 0, cdlgb, 0, IF_BFP)
+ F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, x1, 0, cxlgb, 0, IF_BFP)
+ F(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0, IF_BFP)
+ F(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, f1, 0, cdlgb, 0, IF_BFP)
+ F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, x1, 0, cxlgb, 0, IF_BFP)
/* CONVERT UTF-8 TO UTF-16 */
D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12)
@@ -332,11 +332,11 @@
/* DIVIDE */
C(0x1d00, DR, RR_a, Z, r1_D32, r2_32s, new_P, r1_P32, divs32, 0)
C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, 0)
- C(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0)
- C(0xb31d, DDBR, RRE, Z, f1_o, f2_o, f1, 0, ddb, 0)
- C(0xb34d, DXBR, RRE, Z, 0, x2_o, x1, 0, dxb, 0)
- C(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0)
- C(0xed1d, DDB, RXE, Z, f1_o, m2_64, f1, 0, ddb, 0)
+ F(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0, IF_BFP)
+ F(0xb31d, DDBR, RRE, Z, f1_o, f2_o, f1, 0, ddb, 0, IF_BFP)
+ F(0xb34d, DXBR, RRE, Z, 0, x2_o, x1, 0, dxb, 0, IF_BFP)
+ F(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0, IF_BFP)
+ F(0xed1d, DDB, RXE, Z, f1_o, m2_64, f1, 0, ddb, 0, IF_BFP)
/* DIVIDE LOGICAL */
C(0xb997, DLR, RRE, Z, r1_D32, r2_32u, new_P, r1_P32, divu32, 0)
C(0xe397, DL, RXY_a, Z, r1_D32, m2_32u, new_P, r1_P32, divu32, 0)
@@ -375,7 +375,7 @@
/* EXTRACT CPU TIME */
C(0xc801, ECTG, SSF, ECT, 0, 0, 0, 0, ectg, 0)
/* EXTRACT FPC */
- C(0xb38c, EFPC, RRE, Z, 0, 0, new, r1_32, efpc, 0)
+ F(0xb38c, EFPC, RRE, Z, 0, 0, new, r1_32, efpc, 0, IF_BFP)
/* EXTRACT PSW */
C(0xb98d, EPSW, RRE, Z, 0, 0, 0, 0, epsw, 0)
@@ -407,13 +407,13 @@
C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0)
C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0)
C(0xe314, LGF, RXY_a, Z, 0, a2, r1, 0, ld32s, 0)
- C(0x2800, LDR, RR_a, Z, 0, f2_o, 0, f1, mov2, 0)
- C(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0)
- C(0xed65, LDY, RXY_a, LD, 0, m2_64, 0, f1, mov2, 0)
- C(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0)
- C(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0)
- C(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0)
- C(0xb365, LXR, RRE, Z, 0, x2_o, 0, x1, movx, 0)
+ F(0x2800, LDR, RR_a, Z, 0, f2_o, 0, f1, mov2, 0, IF_HFP1 | IF_HFP2)
+ F(0x6800, LD, RX_a, Z, 0, m2_64, 0, f1, mov2, 0, IF_HFP1)
+ F(0xed65, LDY, RXY_a, LD, 0, m2_64, 0, f1, mov2, 0, IF_HFP1)
+ F(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0, IF_HFP1 | IF_HFP2)
+ F(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0, IF_HFP1)
+ F(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0, IF_HFP1)
+ F(0xb365, LXR, RRE, Z, 0, x2_o, 0, x1, movx, 0, IF_HFP1)
/* LOAD IMMEDIATE */
C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0)
/* LOAD RELATIVE LONG */
@@ -450,9 +450,9 @@
C(0xe312, LT, RXY_a, EI, 0, a2, new, r1_32, ld32s, s64)
C(0xe302, LTG, RXY_a, EI, 0, a2, r1, 0, ld64, s64)
C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64)
- C(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32)
- C(0xb312, LTDBR, RRE, Z, 0, f2_o, 0, f1, mov2, f64)
- C(0xb342, LTXBR, RRE, Z, 0, x2_o, 0, x1, movx, f128)
+ F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP)
+ F(0xb312, LTDBR, RRE, Z, 0, f2_o, 0, f1, mov2, f64, IF_BFP)
+ F(0xb342, LTXBR, RRE, Z, 0, x2_o, 0, x1, movx, f128, IF_BFP)
/* LOAD AND TRAP */
C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)
C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0)
@@ -472,10 +472,10 @@
C(0x1300, LCR, RR_a, Z, 0, r2, new, r1_32, neg, neg32)
C(0xb903, LCGR, RRE, Z, 0, r2, r1, 0, neg, neg64)
C(0xb913, LCGFR, RRE, Z, 0, r2_32s, r1, 0, neg, neg64)
- C(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32)
- C(0xb313, LCDBR, RRE, Z, 0, f2_o, f1, 0, negf64, f64)
- C(0xb343, LCXBR, RRE, Z, 0, x2_o, x1, 0, negf128, f128)
- C(0xb373, LCDFR, RRE, FPSSH, 0, f2_o, f1, 0, negf64, 0)
+ F(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32, IF_BFP)
+ F(0xb313, LCDBR, RRE, Z, 0, f2_o, f1, 0, negf64, f64, IF_BFP)
+ F(0xb343, LCXBR, RRE, Z, 0, x2_o, x1, 0, negf128, f128, IF_BFP)
+ F(0xb373, LCDFR, RRE, FPSSH, 0, f2_o, f1, 0, negf64, 0, IF_HFP1 | IF_HFP2)
/* LOAD HALFWORD */
C(0xb927, LHR, RRE, EI, 0, r2_16s, 0, r1_32, mov2, 0)
C(0xb907, LGHR, RRE, EI, 0, r2_16s, 0, r1, mov2, 0)
@@ -532,17 +532,17 @@
C(0xe39c, LLGTAT, RXY_a, LAT, 0, m2_32u, r1, 0, llgtat, 0)
/* LOAD FPR FROM GR */
- C(0xb3c1, LDGR, RRE, FPRGR, 0, r2_o, 0, f1, mov2, 0)
+ F(0xb3c1, LDGR, RRE, FPRGR, 0, r2_o, 0, f1, mov2, 0, IF_HFP1)
/* LOAD GR FROM FPR */
- C(0xb3cd, LGDR, RRE, FPRGR, 0, f2_o, 0, r1, mov2, 0)
+ F(0xb3cd, LGDR, RRE, FPRGR, 0, f2_o, 0, r1, mov2, 0, IF_HFP2)
/* LOAD NEGATIVE */
C(0x1100, LNR, RR_a, Z, 0, r2_32s, new, r1_32, nabs, nabs32)
C(0xb901, LNGR, RRE, Z, 0, r2, r1, 0, nabs, nabs64)
C(0xb911, LNGFR, RRE, Z, 0, r2_32s, r1, 0, nabs, nabs64)
- C(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32)
- C(0xb311, LNDBR, RRE, Z, 0, f2_o, f1, 0, nabsf64, f64)
- C(0xb341, LNXBR, RRE, Z, 0, x2_o, x1, 0, nabsf128, f128)
- C(0xb371, LNDFR, RRE, FPSSH, 0, f2_o, f1, 0, nabsf64, 0)
+ F(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32, IF_BFP)
+ F(0xb311, LNDBR, RRE, Z, 0, f2_o, f1, 0, nabsf64, f64, IF_BFP)
+ F(0xb341, LNXBR, RRE, Z, 0, x2_o, x1, 0, nabsf128, f128, IF_BFP)
+ F(0xb371, LNDFR, RRE, FPSSH, 0, f2_o, f1, 0, nabsf64, 0, IF_HFP1 | IF_HFP2)
/* LOAD ON CONDITION */
C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0)
C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
@@ -564,10 +564,10 @@
C(0x1000, LPR, RR_a, Z, 0, r2_32s, new, r1_32, abs, abs32)
C(0xb900, LPGR, RRE, Z, 0, r2, r1, 0, abs, abs64)
C(0xb910, LPGFR, RRE, Z, 0, r2_32s, r1, 0, abs, abs64)
- C(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32)
- C(0xb310, LPDBR, RRE, Z, 0, f2_o, f1, 0, absf64, f64)
- C(0xb340, LPXBR, RRE, Z, 0, x2_o, x1, 0, absf128, f128)
- C(0xb370, LPDFR, RRE, FPSSH, 0, f2_o, f1, 0, absf64, 0)
+ F(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32, IF_BFP)
+ F(0xb310, LPDBR, RRE, Z, 0, f2_o, f1, 0, absf64, f64, IF_BFP)
+ F(0xb340, LPXBR, RRE, Z, 0, x2_o, x1, 0, absf128, f128, IF_BFP)
+ F(0xb370, LPDFR, RRE, FPSSH, 0, f2_o, f1, 0, absf64, 0, IF_HFP1 | IF_HFP2)
/* LOAD REVERSED */
C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0)
C(0xb90f, LRVGR, RRE, Z, 0, r2_o, r1, 0, rev64, 0)
@@ -575,30 +575,30 @@
C(0xe31e, LRV, RXY_a, Z, 0, m2_32u, new, r1_32, rev32, 0)
C(0xe30f, LRVG, RXY_a, Z, 0, m2_64, r1, 0, rev64, 0)
/* LOAD ZERO */
- C(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0)
- C(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0)
- C(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0)
+ F(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0, IF_HFP1)
+ F(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0, IF_HFP1)
+ F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0, IF_HFP1)
/* LOAD FPC */
- C(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0)
+ F(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0, IF_BFP)
/* LOAD FPC AND SIGNAL */
- C(0xb2bd, LFAS, S, IEEEE_SIM, 0, m2_32u, 0, 0, sfas, 0)
+ F(0xb2bd, LFAS, S, IEEEE_SIM, 0, m2_32u, 0, 0, sfas, 0, IF_DFP)
/* LOAD FP INTEGER */
- C(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0)
- C(0xb35f, FIDBR, RRF_e, Z, 0, f2_o, f1, 0, fidb, 0)
- C(0xb347, FIXBR, RRF_e, Z, 0, x2_o, x1, 0, fixb, 0)
+ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP)
+ F(0xb35f, FIDBR, RRF_e, Z, 0, f2_o, f1, 0, fidb, 0, IF_BFP)
+ F(0xb347, FIXBR, RRF_e, Z, 0, x2_o, x1, 0, fixb, 0, IF_BFP)
/* LOAD LENGTHENED */
- C(0xb304, LDEBR, RRE, Z, 0, e2, f1, 0, ldeb, 0)
- C(0xb305, LXDBR, RRE, Z, 0, f2_o, x1, 0, lxdb, 0)
- C(0xb306, LXEBR, RRE, Z, 0, e2, x1, 0, lxeb, 0)
- C(0xed04, LDEB, RXE, Z, 0, m2_32u, f1, 0, ldeb, 0)
- C(0xed05, LXDB, RXE, Z, 0, m2_64, x1, 0, lxdb, 0)
- C(0xed06, LXEB, RXE, Z, 0, m2_32u, x1, 0, lxeb, 0)
+ F(0xb304, LDEBR, RRE, Z, 0, e2, f1, 0, ldeb, 0, IF_BFP)
+ F(0xb305, LXDBR, RRE, Z, 0, f2_o, x1, 0, lxdb, 0, IF_BFP)
+ F(0xb306, LXEBR, RRE, Z, 0, e2, x1, 0, lxeb, 0, IF_BFP)
+ F(0xed04, LDEB, RXE, Z, 0, m2_32u, f1, 0, ldeb, 0, IF_BFP)
+ F(0xed05, LXDB, RXE, Z, 0, m2_64, x1, 0, lxdb, 0, IF_BFP)
+ F(0xed06, LXEB, RXE, Z, 0, m2_32u, x1, 0, lxeb, 0, IF_BFP)
/* LOAD ROUNDED */
- C(0xb344, LEDBR, RRE, Z, 0, f2_o, new, e1, ledb, 0)
- C(0xb345, LDXBR, RRE, Z, 0, x2_o, f1, 0, ldxb, 0)
- C(0xb346, LEXBR, RRE, Z, 0, x2_o, new, e1, lexb, 0)
+ F(0xb344, LEDBR, RRE, Z, 0, f2_o, new, e1, ledb, 0, IF_BFP)
+ F(0xb345, LDXBR, RRE, Z, 0, x2_o, f1, 0, ldxb, 0, IF_BFP)
+ F(0xb346, LEXBR, RRE, Z, 0, x2_o, new, e1, lexb, 0, IF_BFP)
/* LOAD MULTIPLE */
C(0x9800, LM, RS_a, Z, 0, a2, 0, 0, lm32, 0)
@@ -644,15 +644,15 @@
C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0)
C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
C(0xe35c, MFY, RXY_a, GIE, r1p1_32s, m2_32s, new, r1_D32, mul, 0)
- C(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0)
- C(0xb31c, MDBR, RRE, Z, f1_o, f2_o, f1, 0, mdb, 0)
- C(0xb34c, MXBR, RRE, Z, 0, x2_o, x1, 0, mxb, 0)
- C(0xb30c, MDEBR, RRE, Z, f1_o, e2, f1, 0, mdeb, 0)
- C(0xb307, MXDBR, RRE, Z, 0, f2_o, x1, 0, mxdb, 0)
- C(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0)
- C(0xed1c, MDB, RXE, Z, f1_o, m2_64, f1, 0, mdb, 0)
- C(0xed0c, MDEB, RXE, Z, f1_o, m2_32u, f1, 0, mdeb, 0)
- C(0xed07, MXDB, RXE, Z, 0, m2_64, x1, 0, mxdb, 0)
+ F(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0, IF_BFP)
+ F(0xb31c, MDBR, RRE, Z, f1_o, f2_o, f1, 0, mdb, 0, IF_BFP)
+ F(0xb34c, MXBR, RRE, Z, 0, x2_o, x1, 0, mxb, 0, IF_BFP)
+ F(0xb30c, MDEBR, RRE, Z, f1_o, e2, f1, 0, mdeb, 0, IF_BFP)
+ F(0xb307, MXDBR, RRE, Z, 0, f2_o, x1, 0, mxdb, 0, IF_BFP)
+ F(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0, IF_BFP)
+ F(0xed1c, MDB, RXE, Z, f1_o, m2_64, f1, 0, mdb, 0, IF_BFP)
+ F(0xed0c, MDEB, RXE, Z, f1_o, m2_32u, f1, 0, mdeb, 0, IF_BFP)
+ F(0xed07, MXDB, RXE, Z, 0, m2_64, x1, 0, mxdb, 0, IF_BFP)
/* MULTIPLY HALFWORD */
C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0)
C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0)
@@ -677,15 +677,15 @@
C(0xc200, MSGFI, RIL_a, GIE, r1_o, i2, r1, 0, mul, 0)
/* MULTIPLY AND ADD */
- C(0xb30e, MAEBR, RRD, Z, e1, e2, new, e1, maeb, 0)
- C(0xb31e, MADBR, RRD, Z, f1_o, f2_o, f1, 0, madb, 0)
- C(0xed0e, MAEB, RXF, Z, e1, m2_32u, new, e1, maeb, 0)
- C(0xed1e, MADB, RXF, Z, f1_o, m2_64, f1, 0, madb, 0)
+ F(0xb30e, MAEBR, RRD, Z, e1, e2, new, e1, maeb, 0, IF_BFP)
+ F(0xb31e, MADBR, RRD, Z, f1_o, f2_o, f1, 0, madb, 0, IF_BFP)
+ F(0xed0e, MAEB, RXF, Z, e1, m2_32u, new, e1, maeb, 0, IF_BFP)
+ F(0xed1e, MADB, RXF, Z, f1_o, m2_64, f1, 0, madb, 0, IF_BFP)
/* MULTIPLY AND SUBTRACT */
- C(0xb30f, MSEBR, RRD, Z, e1, e2, new, e1, mseb, 0)
- C(0xb31f, MSDBR, RRD, Z, f1_o, f2_o, f1, 0, msdb, 0)
- C(0xed0f, MSEB, RXF, Z, e1, m2_32u, new, e1, mseb, 0)
- C(0xed1f, MSDB, RXF, Z, f1_o, m2_64, f1, 0, msdb, 0)
+ F(0xb30f, MSEBR, RRD, Z, e1, e2, new, e1, mseb, 0, IF_BFP)
+ F(0xb31f, MSDBR, RRD, Z, f1_o, f2_o, f1, 0, msdb, 0, IF_BFP)
+ F(0xed0f, MSEB, RXF, Z, e1, m2_32u, new, e1, mseb, 0, IF_BFP)
+ F(0xed1f, MSDB, RXF, Z, f1_o, m2_64, f1, 0, msdb, 0, IF_BFP)
/* OR */
C(0x1600, OR, RR_a, Z, r1, r2, new, r1_32, or, nz32)
@@ -752,14 +752,14 @@
D(0x010d, SAM31, E, Z, 0, 0, 0, 0, sam, 0, 1)
D(0x010e, SAM64, E, Z, 0, 0, 0, 0, sam, 0, 3)
/* SET FPC */
- C(0xb384, SFPC, RRE, Z, 0, r1_o, 0, 0, sfpc, 0)
+ F(0xb384, SFPC, RRE, Z, 0, r1_o, 0, 0, sfpc, 0, IF_BFP)
/* SET FPC AND SIGNAL */
- C(0xb385, SFASR, RRE, IEEEE_SIM, 0, r1_o, 0, 0, sfas, 0)
+ F(0xb385, SFASR, RRE, IEEEE_SIM, 0, r1_o, 0, 0, sfas, 0, IF_DFP)
/* SET BFP ROUNDING MODE */
- C(0xb299, SRNM, S, Z, 0, 0, 0, 0, srnm, 0)
- C(0xb2b8, SRNMB, S, FPE, 0, 0, 0, 0, srnm, 0)
+ F(0xb299, SRNM, S, Z, 0, 0, 0, 0, srnm, 0, IF_BFP)
+ F(0xb2b8, SRNMB, S, FPE, 0, 0, 0, 0, srnm, 0, IF_BFP)
/* SET DFP ROUNDING MODE */
- C(0xb2b9, SRNMT, S, DFPR, 0, 0, 0, 0, srnm, 0)
+ F(0xb2b9, SRNMT, S, DFPR, 0, 0, 0, 0, srnm, 0, IF_DFP)
/* SET PROGRAM MASK */
C(0x0400, SPM, RR_a, Z, r1, 0, 0, 0, spm, 0)
@@ -789,20 +789,20 @@
C(0x8c00, SRDL, RS_a, Z, r1_D32, sh64, new, r1_D32, srl, 0)
/* SQUARE ROOT */
- C(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0)
- C(0xb315, SQDBR, RRE, Z, 0, f2_o, f1, 0, sqdb, 0)
- C(0xb316, SQXBR, RRE, Z, 0, x2_o, x1, 0, sqxb, 0)
- C(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0)
- C(0xed15, SQDB, RXE, Z, 0, m2_64, f1, 0, sqdb, 0)
+ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP)
+ F(0xb315, SQDBR, RRE, Z, 0, f2_o, f1, 0, sqdb, 0, IF_BFP)
+ F(0xb316, SQXBR, RRE, Z, 0, x2_o, x1, 0, sqxb, 0, IF_BFP)
+ F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP)
+ F(0xed15, SQDB, RXE, Z, 0, m2_64, f1, 0, sqdb, 0, IF_BFP)
/* STORE */
C(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0)
C(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0)
C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0)
- C(0x6000, STD, RX_a, Z, f1_o, a2, 0, 0, st64, 0)
- C(0xed67, STDY, RXY_a, LD, f1_o, a2, 0, 0, st64, 0)
- C(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0)
- C(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0)
+ F(0x6000, STD, RX_a, Z, f1_o, a2, 0, 0, st64, 0, IF_HFP1)
+ F(0xed67, STDY, RXY_a, LD, f1_o, a2, 0, 0, st64, 0, IF_HFP1)
+ F(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, IF_HFP1)
+ F(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, IF_HFP1)
/* STORE RELATIVE LONG */
C(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0)
C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0)
@@ -837,7 +837,7 @@
/* STORE FACILITY LIST EXTENDED */
C(0xb2b0, STFLE, S, SFLE, 0, a2, 0, 0, stfle, 0)
/* STORE FPC */
- C(0xb29c, STFPC, S, Z, 0, a2, new, m2_32, efpc, 0)
+ F(0xb29c, STFPC, S, Z, 0, a2, new, m2_32, efpc, 0, IF_BFP)
/* STORE MULTIPLE */
D(0x9000, STM, RS_a, Z, 0, a2, 0, 0, stm, 0, 4)
@@ -861,11 +861,11 @@
C(0xb9e9, SGRK, RRF_a, DO, r2, r3, r1, 0, sub, subs64)
C(0xe309, SG, RXY_a, Z, r1, m2_64, r1, 0, sub, subs64)
C(0xe319, SGF, RXY_a, Z, r1, m2_32s, r1, 0, sub, subs64)
- C(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32)
- C(0xb31b, SDBR, RRE, Z, f1_o, f2_o, f1, 0, sdb, f64)
- C(0xb34b, SXBR, RRE, Z, 0, x2_o, x1, 0, sxb, f128)
- C(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32)
- C(0xed1b, SDB, RXE, Z, f1_o, m2_64, f1, 0, sdb, f64)
+ F(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32, IF_BFP)
+ F(0xb31b, SDBR, RRE, Z, f1_o, f2_o, f1, 0, sdb, f64, IF_BFP)
+ F(0xb34b, SXBR, RRE, Z, 0, x2_o, x1, 0, sxb, f128, IF_BFP)
+ F(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32, IF_BFP)
+ F(0xed1b, SDB, RXE, Z, f1_o, m2_64, f1, 0, sdb, f64, IF_BFP)
/* SUBTRACT HALFWORD */
C(0x4b00, SH, RX_a, Z, r1, m2_16s, new, r1_32, sub, subs32)
C(0xe37b, SHY, RXY_a, LD, r1, m2_16s, new, r1_32, sub, subs32)
@@ -904,9 +904,9 @@
C(0x9300, TS, S, Z, 0, a2, 0, 0, ts, 0)
/* TEST DATA CLASS */
- C(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0)
- C(0xed11, TCDB, RXE, Z, f1_o, a2, 0, 0, tcdb, 0)
- C(0xed12, TCXB, RXE, Z, x1_o, a2, 0, 0, tcxb, 0)
+ F(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0, IF_BFP)
+ F(0xed11, TCDB, RXE, Z, f1_o, a2, 0, 0, tcdb, 0, IF_BFP)
+ F(0xed12, TCXB, RXE, Z, x1_o, a2, 0, 0, tcxb, 0, IF_BFP)
/* TEST DECIMAL */
C(0xebc0, TP, RSL, E2, la1, 0, 0, 0, tp, 0)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index e9cbeb2a1b..8322c81e90 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1112,6 +1112,14 @@ typedef struct {
/* We are exiting the TB to the main loop. */
#define DISAS_PC_STALE_NOCHAIN DISAS_TARGET_4
+
+/* Instruction flags */
+#define IF_HFP1 0x0001 /* r1 points at fp reg for HFP instructions */
+#define IF_HFP2 0x0002 /* r2 points at fp reg for HFP instructions */
+#define IF_HFP3 0x0004 /* r3 points at fp reg for HFP instructions */
+#define IF_BFP 0x0008 /* binary floating point instruction */
+#define IF_DFP 0x0010 /* decimal floating point instruction */
+
struct DisasInsn {
unsigned opc:16;
unsigned flags:16;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Qemu-devel] [PATCH v1 6/8] s390x/tcg: handle privileged instructions via flags
2018-08-22 7:57 [Qemu-devel] [PATCH v1 0/8] s390x/tcg: instruction flags and AFP registers David Hildenbrand
` (4 preceding siblings ...)
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 5/8] s390x/tcg: check for AFP-register, BFP and DFP data exceptions David Hildenbrand
@ 2018-08-22 7:57 ` David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 7/8] s390x/tcg: fix FP register pair checks David Hildenbrand
2018-08-22 7:57 ` [Qemu-devel] [PATCH v1 8/8] s390x/tcg: refactor specification checking David Hildenbrand
7 siblings, 0 replies; 14+ messages in thread
From: David Hildenbrand @ 2018-08-22 7:57 UTC (permalink / raw)
To: qemu-s390x
Cc: qemu-devel, Richard Henderson, Alexander Graf, Cornelia Huck,
Thomas Huth, David Hildenbrand
Let's check this also at a central place.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 138 ++++++++++++++++++-------------------
target/s390x/translate.c | 83 ++--------------------
2 files changed, 76 insertions(+), 145 deletions(-)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 506c3de1d7..fe52d7b81c 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -961,126 +961,126 @@
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
- D(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL)
- D(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_TEQ)
+ E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
+ E(0xb98a, CSPG, RRE, DAT_ENH, r1_o, ra2, r1_P, 0, csp, 0, MO_TEQ, IF_PRIV)
/* DIAGNOSE (KVM hypercall) */
- C(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0)
+ F(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0, IF_PRIV)
/* INSERT STORAGE KEY EXTENDED */
- C(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0)
+ F(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0, IF_PRIV)
/* INVALIDATE DAT TABLE ENTRY */
- C(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0)
+ F(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0, IF_PRIV)
/* INVALIDATE PAGE TABLE ENTRY */
- C(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0)
+ F(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0, IF_PRIV)
/* LOAD CONTROL */
- C(0xb700, LCTL, RS_a, Z, 0, a2, 0, 0, lctl, 0)
- C(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0)
+ F(0xb700, LCTL, RS_a, Z, 0, a2, 0, 0, lctl, 0, IF_PRIV)
+ F(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0, IF_PRIV)
/* LOAD PROGRAM PARAMETER */
- C(0xb280, LPP, S, LPP, 0, m2_64, 0, 0, lpp, 0)
+ F(0xb280, LPP, S, LPP, 0, m2_64, 0, 0, lpp, 0, IF_PRIV)
/* LOAD PSW */
- C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0)
+ F(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0, IF_PRIV)
/* LOAD PSW EXTENDED */
- C(0xb2b2, LPSWE, S, Z, 0, a2, 0, 0, lpswe, 0)
+ F(0xb2b2, LPSWE, S, Z, 0, a2, 0, 0, lpswe, 0, IF_PRIV)
/* LOAD REAL ADDRESS */
- C(0xb100, LRA, RX_a, Z, 0, a2, r1, 0, lra, 0)
- C(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0)
- C(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0)
+ F(0xb100, LRA, RX_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV)
+ F(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0, IF_PRIV)
+ F(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0, IF_PRIV)
/* LOAD USING REAL ADDRESS */
- C(0xb24b, LURA, RRE, Z, 0, r2, new, r1_32, lura, 0)
- C(0xb905, LURAG, RRE, Z, 0, r2, r1, 0, lurag, 0)
+ F(0xb24b, LURA, RRE, Z, 0, r2, new, r1_32, lura, 0, IF_PRIV)
+ F(0xb905, LURAG, RRE, Z, 0, r2, r1, 0, lurag, 0, IF_PRIV)
/* MOVE TO PRIMARY */
- C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0)
+ F(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0, IF_PRIV)
/* MOVE TO SECONDARY */
- C(0xdb00, MVCS, SS_d, Z, la1, a2, 0, 0, mvcs, 0)
+ F(0xdb00, MVCS, SS_d, Z, la1, a2, 0, 0, mvcs, 0, IF_PRIV)
/* PURGE TLB */
- C(0xb20d, PTLB, S, Z, 0, 0, 0, 0, ptlb, 0)
+ F(0xb20d, PTLB, S, Z, 0, 0, 0, 0, ptlb, 0, IF_PRIV)
/* RESET REFERENCE BIT EXTENDED */
- C(0xb22a, RRBE, RRE, Z, 0, r2_o, 0, 0, rrbe, 0)
+ F(0xb22a, RRBE, RRE, Z, 0, r2_o, 0, 0, rrbe, 0, IF_PRIV)
/* SERVICE CALL LOGICAL PROCESSOR (PV hypercall) */
- C(0xb220, SERVC, RRE, Z, r1_o, r2_o, 0, 0, servc, 0)
+ F(0xb220, SERVC, RRE, Z, r1_o, r2_o, 0, 0, servc, 0, IF_PRIV)
/* SET ADDRESS SPACE CONTROL FAST */
- C(0xb279, SACF, S, Z, 0, a2, 0, 0, sacf, 0)
+ F(0xb279, SACF, S, Z, 0, a2, 0, 0, sacf, 0, IF_PRIV)
/* SET CLOCK */
- C(0xb204, SCK, S, Z, la2, 0, 0, 0, sck, 0)
+ F(0xb204, SCK, S, Z, la2, 0, 0, 0, sck, 0, IF_PRIV)
/* SET CLOCK COMPARATOR */
- C(0xb206, SCKC, S, Z, 0, m2_64a, 0, 0, sckc, 0)
+ F(0xb206, SCKC, S, Z, 0, m2_64a, 0, 0, sckc, 0, IF_PRIV)
/* SET CLOCK PROGRAMMABLE FIELD */
- C(0x0107, SCKPF, E, Z, 0, 0, 0, 0, sckpf, 0)
+ F(0x0107, SCKPF, E, Z, 0, 0, 0, 0, sckpf, 0, IF_PRIV)
/* SET CPU TIMER */
- C(0xb208, SPT, S, Z, 0, m2_64a, 0, 0, spt, 0)
+ F(0xb208, SPT, S, Z, 0, m2_64a, 0, 0, spt, 0, IF_PRIV)
/* SET PREFIX */
- C(0xb210, SPX, S, Z, 0, m2_32ua, 0, 0, spx, 0)
+ F(0xb210, SPX, S, Z, 0, m2_32ua, 0, 0, spx, 0, IF_PRIV)
/* SET PSW KEY FROM ADDRESS */
- C(0xb20a, SPKA, S, Z, 0, a2, 0, 0, spka, 0)
+ F(0xb20a, SPKA, S, Z, 0, a2, 0, 0, spka, 0, IF_PRIV)
/* SET STORAGE KEY EXTENDED */
- C(0xb22b, SSKE, RRF_c, Z, r1_o, r2_o, 0, 0, sske, 0)
+ F(0xb22b, SSKE, RRF_c, Z, r1_o, r2_o, 0, 0, sske, 0, IF_PRIV)
/* SET SYSTEM MASK */
- C(0x8000, SSM, S, Z, 0, m2_8u, 0, 0, ssm, 0)
+ F(0x8000, SSM, S, Z, 0, m2_8u, 0, 0, ssm, 0, IF_PRIV)
/* SIGNAL PROCESSOR */
- C(0xae00, SIGP, RS_a, Z, 0, a2, 0, 0, sigp, 0)
+ F(0xae00, SIGP, RS_a, Z, 0, a2, 0, 0, sigp, 0, IF_PRIV)
/* STORE CLOCK */
C(0xb205, STCK, S, Z, la2, 0, new, m1_64, stck, 0)
C(0xb27c, STCKF, S, SCF, la2, 0, new, m1_64, stck, 0)
/* STORE CLOCK EXTENDED */
C(0xb278, STCKE, S, Z, 0, a2, 0, 0, stcke, 0)
/* STORE CLOCK COMPARATOR */
- C(0xb207, STCKC, S, Z, la2, 0, new, m1_64a, stckc, 0)
+ F(0xb207, STCKC, S, Z, la2, 0, new, m1_64a, stckc, 0, IF_PRIV)
/* STORE CONTROL */
- C(0xb600, STCTL, RS_a, Z, 0, a2, 0, 0, stctl, 0)
- C(0xeb25, STCTG, RSY_a, Z, 0, a2, 0, 0, stctg, 0)
+ F(0xb600, STCTL, RS_a, Z, 0, a2, 0, 0, stctl, 0, IF_PRIV)
+ F(0xeb25, STCTG, RSY_a, Z, 0, a2, 0, 0, stctg, 0, IF_PRIV)
/* STORE CPU ADDRESS */
- C(0xb212, STAP, S, Z, la2, 0, new, m1_16a, stap, 0)
+ F(0xb212, STAP, S, Z, la2, 0, new, m1_16a, stap, 0, IF_PRIV)
/* STORE CPU ID */
- C(0xb202, STIDP, S, Z, la2, 0, new, m1_64a, stidp, 0)
+ F(0xb202, STIDP, S, Z, la2, 0, new, m1_64a, stidp, 0, IF_PRIV)
/* STORE CPU TIMER */
- C(0xb209, STPT, S, Z, la2, 0, new, m1_64a, stpt, 0)
+ F(0xb209, STPT, S, Z, la2, 0, new, m1_64a, stpt, 0, IF_PRIV)
/* STORE FACILITY LIST */
- C(0xb2b1, STFL, S, Z, 0, 0, 0, 0, stfl, 0)
+ F(0xb2b1, STFL, S, Z, 0, 0, 0, 0, stfl, 0, IF_PRIV)
/* STORE PREFIX */
- C(0xb211, STPX, S, Z, la2, 0, new, m1_32a, stpx, 0)
+ F(0xb211, STPX, S, Z, la2, 0, new, m1_32a, stpx, 0, IF_PRIV)
/* STORE SYSTEM INFORMATION */
- C(0xb27d, STSI, S, Z, 0, a2, 0, 0, stsi, 0)
+ F(0xb27d, STSI, S, Z, 0, a2, 0, 0, stsi, 0, IF_PRIV)
/* STORE THEN AND SYSTEM MASK */
- C(0xac00, STNSM, SI, Z, la1, 0, 0, 0, stnosm, 0)
+ F(0xac00, STNSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV)
/* STORE THEN OR SYSTEM MASK */
- C(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0)
+ F(0xad00, STOSM, SI, Z, la1, 0, 0, 0, stnosm, 0, IF_PRIV)
/* STORE USING REAL ADDRESS */
- C(0xb246, STURA, RRE, Z, r1_o, r2_o, 0, 0, stura, 0)
- C(0xb925, STURG, RRE, Z, r1_o, r2_o, 0, 0, sturg, 0)
+ F(0xb246, STURA, RRE, Z, r1_o, r2_o, 0, 0, stura, 0, IF_PRIV)
+ F(0xb925, STURG, RRE, Z, r1_o, r2_o, 0, 0, sturg, 0, IF_PRIV)
/* TEST BLOCK */
- C(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0)
+ F(0xb22c, TB, RRE, Z, 0, r2_o, 0, 0, testblock, 0, IF_PRIV)
/* TEST PROTECTION */
C(0xe501, TPROT, SSE, Z, la1, a2, 0, 0, tprot, 0)
/* CCW I/O Instructions */
- C(0xb276, XSCH, S, Z, 0, 0, 0, 0, xsch, 0)
- C(0xb230, CSCH, S, Z, 0, 0, 0, 0, csch, 0)
- C(0xb231, HSCH, S, Z, 0, 0, 0, 0, hsch, 0)
- C(0xb232, MSCH, S, Z, 0, insn, 0, 0, msch, 0)
- C(0xb23b, RCHP, S, Z, 0, 0, 0, 0, rchp, 0)
- C(0xb238, RSCH, S, Z, 0, 0, 0, 0, rsch, 0)
- C(0xb237, SAL, S, Z, 0, 0, 0, 0, sal, 0)
- C(0xb23c, SCHM, S, Z, 0, insn, 0, 0, schm, 0)
- C(0xb274, SIGA, S, Z, 0, 0, 0, 0, siga, 0)
- C(0xb23a, STCPS, S, Z, 0, 0, 0, 0, stcps, 0)
- C(0xb233, SSCH, S, Z, 0, insn, 0, 0, ssch, 0)
- C(0xb239, STCRW, S, Z, 0, insn, 0, 0, stcrw, 0)
- C(0xb234, STSCH, S, Z, 0, insn, 0, 0, stsch, 0)
- C(0xb236, TPI , S, Z, la2, 0, 0, 0, tpi, 0)
- C(0xb235, TSCH, S, Z, 0, insn, 0, 0, tsch, 0)
+ F(0xb276, XSCH, S, Z, 0, 0, 0, 0, xsch, 0, IF_PRIV)
+ F(0xb230, CSCH, S, Z, 0, 0, 0, 0, csch, 0, IF_PRIV)
+ F(0xb231, HSCH, S, Z, 0, 0, 0, 0, hsch, 0, IF_PRIV)
+ F(0xb232, MSCH, S, Z, 0, insn, 0, 0, msch, 0, IF_PRIV)
+ F(0xb23b, RCHP, S, Z, 0, 0, 0, 0, rchp, 0, IF_PRIV)
+ F(0xb238, RSCH, S, Z, 0, 0, 0, 0, rsch, 0, IF_PRIV)
+ F(0xb237, SAL, S, Z, 0, 0, 0, 0, sal, 0, IF_PRIV)
+ F(0xb23c, SCHM, S, Z, 0, insn, 0, 0, schm, 0, IF_PRIV)
+ F(0xb274, SIGA, S, Z, 0, 0, 0, 0, siga, 0, IF_PRIV)
+ F(0xb23a, STCPS, S, Z, 0, 0, 0, 0, stcps, 0, IF_PRIV)
+ F(0xb233, SSCH, S, Z, 0, insn, 0, 0, ssch, 0, IF_PRIV)
+ F(0xb239, STCRW, S, Z, 0, insn, 0, 0, stcrw, 0, IF_PRIV)
+ F(0xb234, STSCH, S, Z, 0, insn, 0, 0, stsch, 0, IF_PRIV)
+ F(0xb236, TPI , S, Z, la2, 0, 0, 0, tpi, 0, IF_PRIV)
+ F(0xb235, TSCH, S, Z, 0, insn, 0, 0, tsch, 0, IF_PRIV)
/* ??? Not listed in PoO ninth edition, but there's a linux driver that
uses it: "A CHSC subchannel is usually present on LPAR only." */
- C(0xb25f, CHSC, RRE, Z, 0, insn, 0, 0, chsc, 0)
+ F(0xb25f, CHSC, RRE, Z, 0, insn, 0, 0, chsc, 0, IF_PRIV)
/* zPCI Instructions */
/* None of these instructions are documented in the PoP, so this is all
based upon target/s390x/kvm.c and Linux code and likely incomplete */
- C(0xebd0, PCISTB, RSY_a, PCI, la2, 0, 0, 0, pcistb, 0)
- C(0xebd1, SIC, RSY_a, AIS, r1, r3, 0, 0, sic, 0)
- C(0xb9a0, CLP, RRF_c, PCI, 0, 0, 0, 0, clp, 0)
- C(0xb9d0, PCISTG, RRE, PCI, 0, 0, 0, 0, pcistg, 0)
- C(0xb9d2, PCILG, RRE, PCI, 0, 0, 0, 0, pcilg, 0)
- C(0xb9d3, RPCIT, RRE, PCI, 0, 0, 0, 0, rpcit, 0)
- C(0xe3d0, MPCIFC, RXY_a, PCI, la2, 0, 0, 0, mpcifc, 0)
- C(0xe3d4, STPCIFC, RXY_a, PCI, la2, 0, 0, 0, stpcifc, 0)
+ F(0xebd0, PCISTB, RSY_a, PCI, la2, 0, 0, 0, pcistb, 0, IF_PRIV)
+ F(0xebd1, SIC, RSY_a, AIS, r1, r3, 0, 0, sic, 0, IF_PRIV)
+ F(0xb9a0, CLP, RRF_c, PCI, 0, 0, 0, 0, clp, 0, IF_PRIV)
+ F(0xb9d0, PCISTG, RRE, PCI, 0, 0, 0, 0, pcistg, 0, IF_PRIV)
+ F(0xb9d2, PCILG, RRE, PCI, 0, 0, 0, 0, pcilg, 0, IF_PRIV)
+ F(0xb9d3, RPCIT, RRE, PCI, 0, 0, 0, 0, rpcit, 0, IF_PRIV)
+ F(0xe3d0, MPCIFC, RXY_a, PCI, la2, 0, 0, 0, mpcifc, 0, IF_PRIV)
+ F(0xe3d4, STPCIFC, RXY_a, PCI, la2, 0, 0, 0, stpcifc, 0, IF_PRIV)
#endif /* CONFIG_USER_ONLY */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a0c834ebb9..1ca6ef45a1 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -320,15 +320,6 @@ static inline void gen_trap(DisasContext *s)
gen_data_exception(0xff);
}
-#ifndef CONFIG_USER_ONLY
-static void check_privileged(DisasContext *s)
-{
- if (s->base.tb->flags & FLAG_MASK_PSTATE) {
- gen_program_exception(s, PGM_PRIVILEGED);
- }
-}
-#endif
-
static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
{
TCGv_i64 tmp = tcg_temp_new_i64();
@@ -1119,6 +1110,7 @@ typedef struct {
#define IF_HFP3 0x0004 /* r3 points at fp reg for HFP instructions */
#define IF_BFP 0x0008 /* binary floating point instruction */
#define IF_DFP 0x0010 /* decimal floating point instruction */
+#define IF_PRIV 0x0020 /* priviledged instruction */
struct DisasInsn {
unsigned opc:16;
@@ -2046,7 +2038,6 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
/* Note that in1 = R1 (zero-extended expected value),
out = R1 (original reg), out2 = R1+1 (new value). */
- check_privileged(s);
addr = tcg_temp_new_i64();
old = tcg_temp_new_i64();
tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE));
@@ -2170,7 +2161,6 @@ static DisasJumpType op_diag(DisasContext *s, DisasOps *o)
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
TCGv_i32 func_code = tcg_const_i32(get_field(s->fields, i2));
- check_privileged(s);
gen_helper_diag(cpu_env, r1, r3, func_code);
tcg_temp_free_i32(func_code);
@@ -2434,7 +2424,6 @@ static DisasJumpType op_idte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
- check_privileged(s);
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
m4 = tcg_const_i32(get_field(s->fields, m4));
} else {
@@ -2449,7 +2438,6 @@ static DisasJumpType op_ipte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
- check_privileged(s);
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
m4 = tcg_const_i32(get_field(s->fields, m4));
} else {
@@ -2462,7 +2450,6 @@ static DisasJumpType op_ipte(DisasContext *s, DisasOps *o)
static DisasJumpType op_iske(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_iske(o->out, cpu_env, o->in2);
return DISAS_NEXT;
}
@@ -2761,7 +2748,6 @@ static DisasJumpType op_lctl(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- check_privileged(s);
gen_helper_lctl(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
@@ -2773,7 +2759,6 @@ static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- check_privileged(s);
gen_helper_lctlg(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
@@ -2783,7 +2768,6 @@ static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o)
static DisasJumpType op_lra(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_lra(o->out, cpu_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -2791,8 +2775,6 @@ static DisasJumpType op_lra(DisasContext *s, DisasOps *o)
static DisasJumpType op_lpp(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
-
tcg_gen_st_i64(o->in2, cpu_env, offsetof(CPUS390XState, pp));
return DISAS_NEXT;
}
@@ -2801,7 +2783,6 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1, t2;
- check_privileged(s);
per_breaking_event(s);
t1 = tcg_temp_new_i64();
@@ -2821,7 +2802,6 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
{
TCGv_i64 t1, t2;
- check_privileged(s);
per_breaking_event(s);
t1 = tcg_temp_new_i64();
@@ -3019,14 +2999,12 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_lura(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_lura(o->out, cpu_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_lurag(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_lurag(o->out, cpu_env, o->in2);
return DISAS_NEXT;
}
@@ -3185,7 +3163,6 @@ static DisasJumpType op_mvcos(DisasContext *s, DisasOps *o)
static DisasJumpType op_mvcp(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, l1);
- check_privileged(s);
gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -3194,7 +3171,6 @@ static DisasJumpType op_mvcp(DisasContext *s, DisasOps *o)
static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, l1);
- check_privileged(s);
gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -3480,7 +3456,6 @@ static DisasJumpType op_popcnt(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_ptlb(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_ptlb(cpu_env);
return DISAS_NEXT;
}
@@ -3671,7 +3646,6 @@ static DisasJumpType op_rll64(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_rrbe(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_rrbe(cc_op, cpu_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -3679,7 +3653,6 @@ static DisasJumpType op_rrbe(DisasContext *s, DisasOps *o)
static DisasJumpType op_sacf(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sacf(cpu_env, o->in2);
/* Addressing mode has changed, so end the block. */
return DISAS_PC_STALE;
@@ -3769,7 +3742,6 @@ static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_servc(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
set_cc_static(s);
return DISAS_NEXT;
@@ -3779,7 +3751,6 @@ static DisasJumpType op_sigp(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- check_privileged(s);
gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3);
set_cc_static(s);
tcg_temp_free_i32(r1);
@@ -3961,7 +3932,6 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_spka(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
tcg_gen_shri_i64(o->in2, o->in2, 4);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
return DISAS_NEXT;
@@ -3969,14 +3939,12 @@ static DisasJumpType op_spka(DisasContext *s, DisasOps *o)
static DisasJumpType op_sske(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sske(cpu_env, o->in1, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_ssm(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
/* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
return DISAS_PC_STALE_NOCHAIN;
@@ -3984,7 +3952,6 @@ static DisasJumpType op_ssm(DisasContext *s, DisasOps *o)
static DisasJumpType op_stap(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, core_id));
return DISAS_NEXT;
}
@@ -4026,7 +3993,6 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
static DisasJumpType op_sck(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEQ | MO_ALIGN);
gen_helper_sck(cc_op, cpu_env, o->in1);
set_cc_static(s);
@@ -4035,21 +4001,18 @@ static DisasJumpType op_sck(DisasContext *s, DisasOps *o)
static DisasJumpType op_sckc(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sckc(cpu_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_sckpf(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sckpf(cpu_env, regs[0]);
return DISAS_NEXT;
}
static DisasJumpType op_stckc(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stckc(o->out, cpu_env);
return DISAS_NEXT;
}
@@ -4058,7 +4021,6 @@ static DisasJumpType op_stctg(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- check_privileged(s);
gen_helper_stctg(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
@@ -4069,7 +4031,6 @@ static DisasJumpType op_stctl(DisasContext *s, DisasOps *o)
{
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- check_privileged(s);
gen_helper_stctl(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
@@ -4078,35 +4039,30 @@ static DisasJumpType op_stctl(DisasContext *s, DisasOps *o)
static DisasJumpType op_stidp(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid));
return DISAS_NEXT;
}
static DisasJumpType op_spt(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_spt(cpu_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_stfl(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stfl(cpu_env);
return DISAS_NEXT;
}
static DisasJumpType op_stpt(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stpt(o->out, cpu_env);
return DISAS_NEXT;
}
static DisasJumpType op_stsi(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
set_cc_static(s);
return DISAS_NEXT;
@@ -4114,14 +4070,12 @@ static DisasJumpType op_stsi(DisasContext *s, DisasOps *o)
static DisasJumpType op_spx(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_spx(cpu_env, o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_xsch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_xsch(cpu_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
@@ -4129,7 +4083,6 @@ static DisasJumpType op_xsch(DisasContext *s, DisasOps *o)
static DisasJumpType op_csch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_csch(cpu_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
@@ -4137,7 +4090,6 @@ static DisasJumpType op_csch(DisasContext *s, DisasOps *o)
static DisasJumpType op_hsch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_hsch(cpu_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
@@ -4145,7 +4097,6 @@ static DisasJumpType op_hsch(DisasContext *s, DisasOps *o)
static DisasJumpType op_msch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_msch(cpu_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4153,7 +4104,6 @@ static DisasJumpType op_msch(DisasContext *s, DisasOps *o)
static DisasJumpType op_rchp(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_rchp(cpu_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
@@ -4161,7 +4111,6 @@ static DisasJumpType op_rchp(DisasContext *s, DisasOps *o)
static DisasJumpType op_rsch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_rsch(cpu_env, regs[1]);
set_cc_static(s);
return DISAS_NEXT;
@@ -4169,21 +4118,18 @@ static DisasJumpType op_rsch(DisasContext *s, DisasOps *o)
static DisasJumpType op_sal(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sal(cpu_env, regs[1]);
return DISAS_NEXT;
}
static DisasJumpType op_schm(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_schm(cpu_env, regs[1], regs[2], o->in2);
return DISAS_NEXT;
}
static DisasJumpType op_siga(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
/* From KVM code: Not provided, set CC = 3 for subchannel not operational */
gen_op_movi_cc(s, 3);
return DISAS_NEXT;
@@ -4191,14 +4137,12 @@ static DisasJumpType op_siga(DisasContext *s, DisasOps *o)
static DisasJumpType op_stcps(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
/* The instruction is suppressed if not provided. */
return DISAS_NEXT;
}
static DisasJumpType op_ssch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_ssch(cpu_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4206,7 +4150,6 @@ static DisasJumpType op_ssch(DisasContext *s, DisasOps *o)
static DisasJumpType op_stsch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stsch(cpu_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4214,7 +4157,6 @@ static DisasJumpType op_stsch(DisasContext *s, DisasOps *o)
static DisasJumpType op_stcrw(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stcrw(cpu_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4222,7 +4164,6 @@ static DisasJumpType op_stcrw(DisasContext *s, DisasOps *o)
static DisasJumpType op_tpi(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_tpi(cc_op, cpu_env, o->addr1);
set_cc_static(s);
return DISAS_NEXT;
@@ -4230,7 +4171,6 @@ static DisasJumpType op_tpi(DisasContext *s, DisasOps *o)
static DisasJumpType op_tsch(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_tsch(cpu_env, regs[1], o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4238,7 +4178,6 @@ static DisasJumpType op_tsch(DisasContext *s, DisasOps *o)
static DisasJumpType op_chsc(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_chsc(cpu_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4246,7 +4185,6 @@ static DisasJumpType op_chsc(DisasContext *s, DisasOps *o)
static DisasJumpType op_stpx(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
return DISAS_NEXT;
@@ -4257,8 +4195,6 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
uint64_t i2 = get_field(s->fields, i2);
TCGv_i64 t;
- check_privileged(s);
-
/* It is important to do what the instruction name says: STORE THEN.
If we let the output hook perform the store then if we fault and
restart, we'll have the wrong SYSTEM MASK in place. */
@@ -4280,14 +4216,12 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_stura(cpu_env, o->in2, o->in1);
return DISAS_NEXT;
}
static DisasJumpType op_sturg(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sturg(cpu_env, o->in2, o->in1);
return DISAS_NEXT;
}
@@ -4553,7 +4487,6 @@ static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o)
static DisasJumpType op_testblock(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_testblock(cc_op, cpu_env, o->in2);
set_cc_static(s);
return DISAS_NEXT;
@@ -4811,7 +4744,6 @@ static DisasJumpType op_clp(DisasContext *s, DisasOps *o)
{
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
- check_privileged(s);
gen_helper_clp(cpu_env, r2);
tcg_temp_free_i32(r2);
set_cc_static(s);
@@ -4823,7 +4755,6 @@ static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o)
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
- check_privileged(s);
gen_helper_pcilg(cpu_env, r1, r2);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
@@ -4836,7 +4767,6 @@ static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o)
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
- check_privileged(s);
gen_helper_pcistg(cpu_env, r1, r2);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
@@ -4849,7 +4779,6 @@ static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o)
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
- check_privileged(s);
gen_helper_stpcifc(cpu_env, r1, o->addr1, ar);
tcg_temp_free_i32(ar);
tcg_temp_free_i32(r1);
@@ -4859,7 +4788,6 @@ static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o)
static DisasJumpType op_sic(DisasContext *s, DisasOps *o)
{
- check_privileged(s);
gen_helper_sic(cpu_env, o->in1, o->in2);
return DISAS_NEXT;
}
@@ -4869,7 +4797,6 @@ static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o)
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
- check_privileged(s);
gen_helper_rpcit(cpu_env, r1, r2);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r2);
@@ -4883,7 +4810,6 @@ static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o)
TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
- check_privileged(s);
gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar);
tcg_temp_free_i32(ar);
tcg_temp_free_i32(r1);
@@ -4897,7 +4823,6 @@ static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
- check_privileged(s);
gen_helper_mpcifc(cpu_env, r1, o->addr1, ar);
tcg_temp_free_i32(ar);
tcg_temp_free_i32(r1);
@@ -6088,6 +6013,12 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
/* process flags */
if (insn->flags) {
+ /* priviledged instruction */
+ if ((s->base.tb->flags & FLAG_MASK_PSTATE) && (insn->flags & IF_PRIV)) {
+ gen_program_exception(s, PGM_PRIVILEGED);
+ return DISAS_NORETURN;
+ }
+
/* if AFP is not enabled, instructions and registers are forbidden */
if (!(s->base.tb->flags & FLAG_MASK_AFP)) {
uint8_t dxc = 0;
--
2.17.1
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