* [PATCH] sabre: increase number of PCI bus IRQs from 32 to 64
@ 2020-10-11 8:13 Mark Cave-Ayland
2020-10-21 9:27 ` Mark Cave-Ayland
0 siblings, 1 reply; 4+ messages in thread
From: Mark Cave-Ayland @ 2020-10-11 8:13 UTC (permalink / raw)
To: qemu-devel, atar4qemu
The rework of the sabre IRQs in commit 6864fa3897 "sun4u: update PCI topology to
include simba PCI bridges" changed the IRQ routing so that both PCI and legacy
OBIO IRQs are routed through the sabre PCI host bridge to the CPU.
Unfortunately this commit failed to increase the number of PCI bus IRQs
accordingly meaning that access to the legacy IRQs OBIO (irqnum >= 0x20) would
overflow the PCI bus IRQ array causing strange failures running qemu-system-sparc64
in NetBSD.
Reported-by: Harold Gutch <logix@foobar.franken.de>
Fixes: https://bugs.launchpad.net/qemu/+bug/1838658
Fixes: 6864fa3897 ("sun4u: update PCI topology to include simba PCI bridges")
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/pci-host/sabre.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
index 5ac6283623..ffdba1d865 100644
--- a/hw/pci-host/sabre.c
+++ b/hw/pci-host/sabre.c
@@ -396,7 +396,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
pci_sabre_set_irq, pci_sabre_map_irq, s,
&s->pci_mmio,
&s->pci_ioport,
- 0, 32, TYPE_PCI_BUS);
+ 0, 0x40, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] sabre: increase number of PCI bus IRQs from 32 to 64
2020-10-11 8:13 [PATCH] sabre: increase number of PCI bus IRQs from 32 to 64 Mark Cave-Ayland
@ 2020-10-21 9:27 ` Mark Cave-Ayland
2020-10-24 20:41 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 4+ messages in thread
From: Mark Cave-Ayland @ 2020-10-21 9:27 UTC (permalink / raw)
To: qemu-devel, atar4qemu
On 11/10/2020 09:13, Mark Cave-Ayland wrote:
> The rework of the sabre IRQs in commit 6864fa3897 "sun4u: update PCI topology to
> include simba PCI bridges" changed the IRQ routing so that both PCI and legacy
> OBIO IRQs are routed through the sabre PCI host bridge to the CPU.
>
> Unfortunately this commit failed to increase the number of PCI bus IRQs
> accordingly meaning that access to the legacy IRQs OBIO (irqnum >= 0x20) would
> overflow the PCI bus IRQ array causing strange failures running qemu-system-sparc64
> in NetBSD.
>
> Reported-by: Harold Gutch <logix@foobar.franken.de>
> Fixes: https://bugs.launchpad.net/qemu/+bug/1838658
> Fixes: 6864fa3897 ("sun4u: update PCI topology to include simba PCI bridges")
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> hw/pci-host/sabre.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
> index 5ac6283623..ffdba1d865 100644
> --- a/hw/pci-host/sabre.c
> +++ b/hw/pci-host/sabre.c
> @@ -396,7 +396,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
> pci_sabre_set_irq, pci_sabre_map_irq, s,
> &s->pci_mmio,
> &s->pci_ioport,
> - 0, 32, TYPE_PCI_BUS);
> + 0, 0x40, TYPE_PCI_BUS);
>
> pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
Applied to my qemu-sparc branch.
ATB,
Mark.
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] sabre: increase number of PCI bus IRQs from 32 to 64
2020-10-21 9:27 ` Mark Cave-Ayland
@ 2020-10-24 20:41 ` Philippe Mathieu-Daudé
2020-10-25 10:59 ` Mark Cave-Ayland
0 siblings, 1 reply; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-24 20:41 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, atar4qemu
On 10/21/20 11:27 AM, Mark Cave-Ayland wrote:
> On 11/10/2020 09:13, Mark Cave-Ayland wrote:
>
>> The rework of the sabre IRQs in commit 6864fa3897 "sun4u: update PCI
>> topology to
>> include simba PCI bridges" changed the IRQ routing so that both PCI
>> and legacy
>> OBIO IRQs are routed through the sabre PCI host bridge to the CPU.
>>
>> Unfortunately this commit failed to increase the number of PCI bus IRQs
>> accordingly meaning that access to the legacy IRQs OBIO (irqnum >=
>> 0x20) would
>> overflow the PCI bus IRQ array causing strange failures running
>> qemu-system-sparc64
>> in NetBSD.
>>
>> Reported-by: Harold Gutch <logix@foobar.franken.de>
>> Fixes: https://bugs.launchpad.net/qemu/+bug/1838658
>> Fixes: 6864fa3897 ("sun4u: update PCI topology to include simba PCI
>> bridges")
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>> hw/pci-host/sabre.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
>> index 5ac6283623..ffdba1d865 100644
>> --- a/hw/pci-host/sabre.c
>> +++ b/hw/pci-host/sabre.c
>> @@ -396,7 +396,7 @@ static void sabre_realize(DeviceState *dev, Error
>> **errp)
>> pci_sabre_set_irq,
>> pci_sabre_map_irq, s,
>> &s->pci_mmio,
>> &s->pci_ioport,
>> - 0, 32, TYPE_PCI_BUS);
>> + 0, 0x40, TYPE_PCI_BUS);
>> pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
>
> Applied to my qemu-sparc branch.
FWIW I spent some time looking at this, and your patch is indeed
the simplest fix in the current state of this model.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
>
> ATB,
>
> Mark.
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] sabre: increase number of PCI bus IRQs from 32 to 64
2020-10-24 20:41 ` Philippe Mathieu-Daudé
@ 2020-10-25 10:59 ` Mark Cave-Ayland
0 siblings, 0 replies; 4+ messages in thread
From: Mark Cave-Ayland @ 2020-10-25 10:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel, atar4qemu
On 24/10/2020 21:41, Philippe Mathieu-Daudé wrote:
> On 10/21/20 11:27 AM, Mark Cave-Ayland wrote:
>> On 11/10/2020 09:13, Mark Cave-Ayland wrote:
>>
>>> The rework of the sabre IRQs in commit 6864fa3897 "sun4u: update PCI topology to
>>> include simba PCI bridges" changed the IRQ routing so that both PCI and legacy
>>> OBIO IRQs are routed through the sabre PCI host bridge to the CPU.
>>>
>>> Unfortunately this commit failed to increase the number of PCI bus IRQs
>>> accordingly meaning that access to the legacy IRQs OBIO (irqnum >= 0x20) would
>>> overflow the PCI bus IRQ array causing strange failures running qemu-system-sparc64
>>> in NetBSD.
>>>
>>> Reported-by: Harold Gutch <logix@foobar.franken.de>
>>> Fixes: https://bugs.launchpad.net/qemu/+bug/1838658
>>> Fixes: 6864fa3897 ("sun4u: update PCI topology to include simba PCI bridges")
>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> ---
>>> hw/pci-host/sabre.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c
>>> index 5ac6283623..ffdba1d865 100644
>>> --- a/hw/pci-host/sabre.c
>>> +++ b/hw/pci-host/sabre.c
>>> @@ -396,7 +396,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
>>> pci_sabre_set_irq, pci_sabre_map_irq, s,
>>> &s->pci_mmio,
>>> &s->pci_ioport,
>>> - 0, 32, TYPE_PCI_BUS);
>>> + 0, 0x40, TYPE_PCI_BUS);
>>> pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
>>
>> Applied to my qemu-sparc branch.
>
> FWIW I spent some time looking at this, and your patch is indeed
> the simplest fix in the current state of this model.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks! I'll add the tag to my pending PR.
ATB,
Mark.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-10-25 11:02 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-11 8:13 [PATCH] sabre: increase number of PCI bus IRQs from 32 to 64 Mark Cave-Ayland
2020-10-21 9:27 ` Mark Cave-Ayland
2020-10-24 20:41 ` Philippe Mathieu-Daudé
2020-10-25 10:59 ` Mark Cave-Ayland
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.