[PATCH 1/9] clk: imx8mp: Add EQoS MAC clock

[PATCH 1/9] clk: imx8mp: Add EQoS MAC clock

[Marek Vasut]

Add clock for the DWMAC EQoS block. This is used among other things
to configure the MII clock via DM CLK.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index ffbc1d1ba9f..6dda0403e35 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
 					 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 					 "audio_pll2_out", "sys_pll1_133m", };
 
+static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+					     "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
+					     "video_pll1_out", "clk_ext4", };
+
+static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+						   "clk_ext1", "clk_ext2", "clk_ext3",
+						   "clk_ext4", "video_pll1_out", };
+
 static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
 					   "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 					   "audio_pll2_out", "sys_pll1_100m", };
@@ -250,6 +258,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
 	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
 	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
+	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
+	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
 	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
 	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
 	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
@@ -292,10 +302,13 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
+	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
 	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
 	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
 	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
 	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
+	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
 	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
 	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
 	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
-- 
2.39.0

[PATCH 2/9] net: dwc_eth_qos: Drop bogus return after goto

[Marek Vasut]

The return is never triggered due to the goto just above it.
Drop it. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 drivers/net/dwc_eth_qos.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index afc47b56ff5..44d05908894 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1373,7 +1373,6 @@ static int eqos_probe_resources_tegra186(struct udevice *dev)
 	if (ret) {
 		pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
 		goto err_free_clk_rx;
-		return ret;
 	}
 
 	ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
-- 
2.39.0

[PATCH 3/9] net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32

[Marek Vasut]

The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 drivers/net/dwc_eth_qos.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 44d05908894..cd2def4ba21 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1502,9 +1502,6 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
 		clk_free(&eqos->clk_ck);
 #endif
 
-	if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
-		dm_gpio_free(dev, &eqos->phy_reset_gpio);
-
 	debug("%s: OK\n", __func__);
 	return 0;
 }
-- 
2.39.0

[PATCH 4/9] net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC

[Marek Vasut]

The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.

Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 drivers/net/dwc_eth_qos.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index cd2def4ba21..d488bd0c288 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev)
 
 	eqos->reg_access_ok = true;
 
+	/*
+	 * Assert the SWR first, the actually reset the MAC and to latch in
+	 * e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
+	 */
+	setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
+
 	ret = wait_for_bit_le32(&eqos->dma_regs->mode,
 				EQOS_DMA_MODE_SWR, false,
 				eqos->config->swr_wait, false);
-- 
2.39.0

[PATCH 5/9] net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus

[Marek Vasut]

The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.

The adjustment here is modeled after STM32MP15xx clock handling
in this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c |  41 --------
 drivers/net/dwc_eth_qos_imx.c          | 130 +++++++++++++++++++++++--
 2 files changed, 120 insertions(+), 51 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 64ad57e9b39..494bfbedc8c 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -872,47 +872,6 @@ int set_clk_eqos(enum enet_freq type)
 
 	return 0;
 }
-
-int imx_eqos_txclk_set_rate(ulong rate)
-{
-	u32 val;
-	u32 eqos_post_div;
-
-	/* disable the clock first */
-	clock_enable(CCGR_QOS_ETHENET, 0);
-	clock_enable(CCGR_SDMA2, 0);
-
-	switch (rate) {
-	case 125000000:
-		eqos_post_div = 1;
-		break;
-	case 25000000:
-		eqos_post_div = 125000000 / 25000000;
-		break;
-	case 2500000:
-		eqos_post_div = 125000000 / 2500000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
-	val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
-	val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-	       CLK_ROOT_POST_DIV(eqos_post_div - 1);
-	clock_set_target_val(ENET_QOS_CLK_ROOT, val);
-
-	/* enable clock */
-	clock_enable(CCGR_QOS_ETHENET, 1);
-	clock_enable(CCGR_SDMA2, 1);
-
-	return 0;
-}
-
-u32 imx_get_eqos_csr_clk(void)
-{
-	return get_root_clk(ENET_AXI_CLK_ROOT);
-}
 #endif
 
 #ifdef CONFIG_FEC_MXC
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 42cb164ad14..d0b7ef75c26 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -32,20 +32,18 @@ __weak u32 imx_get_eqos_csr_clk(void)
 	return 100 * 1000000;
 }
 
-__weak int imx_eqos_txclk_set_rate(unsigned long rate)
-{
-	return 0;
-}
-
 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
 {
-	return imx_get_eqos_csr_clk();
+	struct eqos_priv *eqos = dev_get_priv(dev);
+
+	return clk_get_rate(&eqos->clk_master_bus);
 }
 
 static int eqos_probe_resources_imx(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
 	phy_interface_t interface;
+	int ret;
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
@@ -56,6 +54,118 @@ static int eqos_probe_resources_imx(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
+
+	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
+	if (ret) {
+		pr_err("clk_get_by_name(master_bus) failed: %d", ret);
+		goto err_probe;
+	}
+
+	ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
+	if (ret) {
+		pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
+		goto err_free_clk_master_bus;
+	}
+
+	ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
+	if (ret) {
+		pr_err("clk_get_by_name(tx) failed: %d", ret);
+		goto err_free_clk_ptp_ref;
+	}
+
+	ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck);
+	if (ret) {
+		pr_err("clk_get_by_name(pclk) failed: %d", ret);
+		goto err_free_clk_tx;
+	}
+
+	debug("%s: OK\n", __func__);
+	return 0;
+
+err_free_clk_tx:
+	clk_free(&eqos->clk_tx);
+err_free_clk_ptp_ref:
+	clk_free(&eqos->clk_ptp_ref);
+err_free_clk_master_bus:
+	clk_free(&eqos->clk_master_bus);
+err_probe:
+
+	debug("%s: returns %d\n", __func__, ret);
+	return ret;
+}
+
+static int eqos_remove_resources_imx(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	clk_free(&eqos->clk_ck);
+	clk_free(&eqos->clk_tx);
+	clk_free(&eqos->clk_ptp_ref);
+	clk_free(&eqos->clk_master_bus);
+
+	debug("%s: OK\n", __func__);
+	return 0;
+}
+
+static int eqos_start_clks_imx(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	int ret;
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	ret = clk_enable(&eqos->clk_master_bus);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_master_bus) failed: %d", ret);
+		goto err;
+	}
+
+	ret = clk_enable(&eqos->clk_ptp_ref);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
+		goto err_disable_clk_master_bus;
+	}
+
+	ret = clk_enable(&eqos->clk_tx);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_tx) failed: %d", ret);
+		goto err_disable_clk_ptp_ref;
+	}
+
+	ret = clk_enable(&eqos->clk_ck);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_ck) failed: %d", ret);
+		goto err_disable_clk_tx;
+	}
+
+	debug("%s: OK\n", __func__);
+	return 0;
+
+err_disable_clk_tx:
+	clk_disable(&eqos->clk_tx);
+err_disable_clk_ptp_ref:
+	clk_disable(&eqos->clk_ptp_ref);
+err_disable_clk_master_bus:
+	clk_disable(&eqos->clk_master_bus);
+err:
+	debug("%s: FAILED: %d\n", __func__, ret);
+	return ret;
+}
+
+static int eqos_stop_clks_imx(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	clk_disable(&eqos->clk_ck);
+	clk_disable(&eqos->clk_tx);
+	clk_disable(&eqos->clk_ptp_ref);
+	clk_disable(&eqos->clk_master_bus);
+
 	debug("%s: OK\n", __func__);
 	return 0;
 }
@@ -83,7 +193,7 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	ret = imx_eqos_txclk_set_rate(rate);
+	ret = clk_set_rate(&eqos->clk_tx, rate);
 	if (ret < 0) {
 		pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
 		return ret;
@@ -107,11 +217,11 @@ static struct eqos_ops eqos_imx_ops = {
 	.eqos_inval_buffer = eqos_inval_buffer_generic,
 	.eqos_flush_buffer = eqos_flush_buffer_generic,
 	.eqos_probe_resources = eqos_probe_resources_imx,
-	.eqos_remove_resources = eqos_null_ops,
+	.eqos_remove_resources = eqos_remove_resources_imx,
 	.eqos_stop_resets = eqos_null_ops,
 	.eqos_start_resets = eqos_null_ops,
-	.eqos_stop_clks = eqos_null_ops,
-	.eqos_start_clks = eqos_null_ops,
+	.eqos_stop_clks = eqos_stop_clks_imx,
+	.eqos_start_clks = eqos_start_clks_imx,
 	.eqos_calibrate_pads = eqos_null_ops,
 	.eqos_disable_calibration = eqos_null_ops,
 	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
-- 
2.39.0

[PATCH 6/9] net: dwc_eth_qos: Add i.MX8M Plus RMII support

[Marek Vasut]

With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.

The board DT requires the following adjustments to EQoS node:
  phy-mode = "rmii";
  assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
  			<&clk IMX8MP_SYS_PLL2_100M>,
  			<&clk IMX8MP_SYS_PLL2_50M>;
  assigned-clock-rates = <0>, <100000000>, <50000000>;

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 drivers/net/dwc_eth_qos_imx.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index d0b7ef75c26..55080257623 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -178,21 +178,25 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
-	switch (eqos->phy->speed) {
-	case SPEED_1000:
-		rate = 125 * 1000 * 1000;
-		break;
-	case SPEED_100:
-		rate = 25 * 1000 * 1000;
-		break;
-	case SPEED_10:
-		rate = 2.5 * 1000 * 1000;
-		break;
-	default:
+	if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
+		rate = 5000;	/* 5000 kHz = 5 MHz */
+	else
+		rate = 2500;	/* 2500 kHz = 2.5 MHz */
+
+	if (eqos->phy->speed == SPEED_1000 &&
+	    eqos->phy->interface == PHY_INTERFACE_MODE_RGMII) {
+		rate *= 50;	/* Use 50x base rate i.e. 125 MHz */
+	} else if (eqos->phy->speed == SPEED_100) {
+		rate *= 10;	/* Use 10x base rate */
+	} else if (eqos->phy->speed == SPEED_10) {
+		rate *= 1;	/* Use base rate */
+	} else {
 		pr_err("invalid speed %d", eqos->phy->speed);
 		return -EINVAL;
 	}
 
+	rate *= 1000;	/* clk_set_rate() operates in Hz */
+
 	ret = clk_set_rate(&eqos->clk_tx, rate);
 	if (ret < 0) {
 		pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
-- 
2.39.0

[PATCH 7/9] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus

[Marek Vasut]

Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h |  8 ++++-
 arch/arm/mach-imx/imx8m/clock_imx8mm.c     | 37 ++++++++++++++++++++++
 drivers/net/dwc_eth_qos_imx.c              |  4 +++
 3 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 20f4699a12b..88e7f7dc557 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -85,7 +85,13 @@
 #define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
 #define DDR_CSD1_BASE_ADDR	0x40000000
 
-#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN		BIT(21)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL	BIT(20)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN		BIT(19)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK	GENMASK(18, 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII	(0 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII	(1 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII	(4 << 16)
 #define FEC_QUIRK_ENET_MAC
 
 #define CAAM_ARB_BASE_ADDR              (0x00100000)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 494bfbedc8c..069087c2cfd 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -15,6 +15,7 @@
 #include <errno.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -872,6 +873,42 @@ int set_clk_eqos(enum enet_freq type)
 
 	return 0;
 }
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	clrbits_le32(&gpr->gpr[1],
+		     IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
+		     IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+		     IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+		     IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
+
+	switch (interface_type) {
+	case PHY_INTERFACE_MODE_MII:
+		setbits_le32(&gpr->gpr[1],
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		setbits_le32(&gpr->gpr[1],
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+		setbits_le32(&gpr->gpr[1],
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+			     IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
 #endif
 
 #ifdef CONFIG_FEC_MXC
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 55080257623..f8f4cbc0257 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -54,6 +54,10 @@ static int eqos_probe_resources_imx(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	ret = board_interface_eth_init(dev, interface);
+	if (ret)
+		return -EINVAL;
+
 	eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
 	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
-- 
2.39.0

[PATCH 8/9] arm64: dts: imx8mp: Drop EQoS clock workaround

[Marek Vasut]

The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/imx8mp-dhcom-u-boot.dtsi                | 6 ------
 arch/arm/dts/imx8mp-evk-u-boot.dtsi                  | 6 ------
 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 6 ------
 arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi        | 6 ------
 arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi      | 6 ------
 5 files changed, 30 deletions(-)

diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
index ae838caebcf..ea6ab9f2e17 100644
--- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -33,12 +33,6 @@
 	u-boot,dm-spl;
 };
 
-&eqos {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
 &gpio1 {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index f43eb6238d0..cd0fb815c79 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -131,12 +131,6 @@
 	u-boot,dm-spl;
 };
 
-&eqos {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
 &ethphy0 {
 	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 	reset-delay-us = <15000>;
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
index 342c523b0c5..3e48cf8ec5c 100644
--- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -130,12 +130,6 @@
 	u-boot,dm-spl;
 };
 
-&eqos {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
 &ethphy0 {
 	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 	reset-delay-us = <15000>;
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
index d8721124526..849950fe026 100644
--- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
@@ -20,12 +20,6 @@
 	};
 };
 
-&eqos {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
 &ethphy0 {
 	reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
 	reset-delay-us = <1000>;
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
index 8a4cdc717d2..5f021d17230 100644
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
@@ -39,12 +39,6 @@
 	u-boot,dm-spl;
 };
 
-&eqos {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-parents;
-	/delete-property/ assigned-clock-rates;
-};
-
 &gpio1 {
 	u-boot,dm-spl;
 };
-- 
2.39.0

[PATCH 9/9] arm64: imx8mp: Drop EQoS GPR[1] board workaround

[Marek Vasut]

The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc: u-boot@lists.denx.de
---
 .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c         | 17 +----------------
 .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 14 --------------
 board/engicam/imx8mp/icore_mx8mp.c              | 16 ----------------
 board/freescale/imx8mp_evk/imx8mp_evk.c         | 17 -----------------
 board/gateworks/venice/venice.c                 | 15 ---------------
 board/msc/sm2s_imx8mp/sm2s_imx8mp.c             | 15 ---------------
 board/toradex/verdin-imx8mp/verdin-imx8mp.c     | 16 ----------------
 7 files changed, 1 insertion(+), 109 deletions(-)

diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index aa9687f7a9d..4c3fb6cbe35 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -113,7 +113,7 @@ static const iomux_v3_cfg_t eqos_rst_pads[] = {
 	MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static void setup_iomux_eqos(void)
+static int setup_eqos(void)
 {
 	imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
 					 ARRAY_SIZE(eqos_rst_pads));
@@ -124,21 +124,6 @@ static void setup_iomux_eqos(void)
 	gpio_direction_output(EQOS_RST_PAD, 1);
 	mdelay(100);
 }
-
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	setup_iomux_eqos();
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
 #endif /* CONFIG_DWC_ETH_QOS */
 
 int board_phy_config(struct phy_device *phydev)
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index e83dd52c3a6..319ea6e93c5 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -37,19 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
 	return 0;
 }
 
-static void setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* Set INTF as RGMII, enable RGMII TXC clock. */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	set_clk_eqos(ENET_125MHZ);
-}
-
 static void setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
@@ -128,7 +115,6 @@ int dh_setup_mac_address(void)
 
 int board_init(void)
 {
-	setup_eqos();
 	setup_fec();
 	return 0;
 }
diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c
index b309a12df08..b80513c7957 100644
--- a/board/engicam/imx8mp/icore_mx8mp.c
+++ b/board/engicam/imx8mp/icore_mx8mp.c
@@ -34,19 +34,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 #if CONFIG_IS_ENABLED(NET)
 int board_phy_config(struct phy_device *phydev)
 {
@@ -61,9 +48,6 @@ int board_init(void)
 	if (CONFIG_IS_ENABLED(FEC_MXC))
 		setup_fec();
 
-	if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
-		setup_eqos();
-
 	return 0;
 }
 
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 8971a827df3..0fefdafadfa 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -29,19 +29,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 #if CONFIG_IS_ENABLED(NET)
 int board_phy_config(struct phy_device *phydev)
 {
@@ -59,10 +46,6 @@ int board_init(void)
 		setup_fec();
 	}
 
-	if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
-		ret = setup_eqos();
-	}
-
 	return ret;
 }
 
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index c4d86c26a9b..bc8937b366c 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -58,19 +58,6 @@ static int setup_fec(void)
 	return 0;
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
 	unsigned short val;
@@ -115,8 +102,6 @@ int board_init(void)
 
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
-	if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
-		setup_eqos();
 
 	return 0;
 }
diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c
index 3913c4f2427..6ccbf02db06 100644
--- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c
+++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c
@@ -30,19 +30,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
 	if (phydev->drv->config)
@@ -54,7 +41,5 @@ int board_init(void)
 {
 	setup_fec();
 
-	setup_eqos();
-
 	return 0;
 }
diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
index 9c2e44a1229..5490d3ed44a 100644
--- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c
+++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c
@@ -49,19 +49,6 @@ static void setup_fec(void)
 	setbits_le32(&gpr->gpr[1], BIT(22));
 }
 
-static int setup_eqos(void)
-{
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-	/* set INTF as RGMII, enable RGMII TXC clock */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-	setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-	return set_clk_eqos(ENET_125MHZ);
-}
-
 #if IS_ENABLED(CONFIG_NET)
 int board_phy_config(struct phy_device *phydev)
 {
@@ -78,9 +65,6 @@ int board_init(void)
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
 
-	if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
-		ret = setup_eqos();
-
 	return ret;
 }
 
-- 
2.39.0

Re: [PATCH 1/9] clk: imx8mp: Add EQoS MAC clock

[Sean Anderson]

On 1/19/23 16:44, Marek Vasut wrote:
> Add clock for the DWMAC EQoS block. This is used among other things
> to configure the MII clock via DM CLK.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>   drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index ffbc1d1ba9f..6dda0403e35 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
>   					 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
>   					 "audio_pll2_out", "sys_pll1_133m", };
>   
> +static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
> +					     "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
> +					     "video_pll1_out", "clk_ext4", };
> +
> +static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
> +						   "clk_ext1", "clk_ext2", "clk_ext3",
> +						   "clk_ext4", "video_pll1_out", };
> +
>   static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
>   					   "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
>   					   "audio_pll2_out", "sys_pll1_100m", };
> @@ -250,6 +258,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
>   	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
>   	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
>   	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
> +	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
> +	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
>   	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
>   	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
>   	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
> @@ -292,10 +302,13 @@ static int imx8mp_clk_probe(struct udevice *dev)
>   	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
>   	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
>   	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> +	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
> +	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
>   	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
>   	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
>   	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
>   	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
> +	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
>   	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
>   	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
>   	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));

Acked-by: Sean Anderson <seanga2@gmail.com>

Re: [PATCH 5/9] net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus

[Sean Anderson]

On 1/19/23 16:44, Marek Vasut wrote:
> The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
> architecture code. Replace that with DM clock instead. This way,
> the driver claims all its required clock, enables and disables
> them, and even gets the CSR clock rate and sets the TX clock rate,
> without any need of architecture specific register fiddling. Drop
> the architecture specific code while at it too.
> 
> The adjustment here is modeled after STM32MP15xx clock handling
> in this driver.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>   arch/arm/mach-imx/imx8m/clock_imx8mm.c |  41 --------
>   drivers/net/dwc_eth_qos_imx.c          | 130 +++++++++++++++++++++++--
>   2 files changed, 120 insertions(+), 51 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 64ad57e9b39..494bfbedc8c 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -872,47 +872,6 @@ int set_clk_eqos(enum enet_freq type)
>   
>   	return 0;
>   }
> -
> -int imx_eqos_txclk_set_rate(ulong rate)
> -{
> -	u32 val;
> -	u32 eqos_post_div;
> -
> -	/* disable the clock first */
> -	clock_enable(CCGR_QOS_ETHENET, 0);
> -	clock_enable(CCGR_SDMA2, 0);
> -
> -	switch (rate) {
> -	case 125000000:
> -		eqos_post_div = 1;
> -		break;
> -	case 25000000:
> -		eqos_post_div = 125000000 / 25000000;
> -		break;
> -	case 2500000:
> -		eqos_post_div = 125000000 / 2500000;
> -		break;
> -	default:
> -		return -EINVAL;
> -	}
> -
> -	clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
> -	val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
> -	val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
> -	       CLK_ROOT_POST_DIV(eqos_post_div - 1);
> -	clock_set_target_val(ENET_QOS_CLK_ROOT, val);
> -
> -	/* enable clock */
> -	clock_enable(CCGR_QOS_ETHENET, 1);
> -	clock_enable(CCGR_SDMA2, 1);
> -
> -	return 0;
> -}
> -
> -u32 imx_get_eqos_csr_clk(void)
> -{
> -	return get_root_clk(ENET_AXI_CLK_ROOT);
> -}
>   #endif
>   
>   #ifdef CONFIG_FEC_MXC
> diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
> index 42cb164ad14..d0b7ef75c26 100644
> --- a/drivers/net/dwc_eth_qos_imx.c
> +++ b/drivers/net/dwc_eth_qos_imx.c
> @@ -32,20 +32,18 @@ __weak u32 imx_get_eqos_csr_clk(void)
>   	return 100 * 1000000;
>   }
>   
> -__weak int imx_eqos_txclk_set_rate(unsigned long rate)
> -{
> -	return 0;
> -}
> -
>   static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
>   {
> -	return imx_get_eqos_csr_clk();
> +	struct eqos_priv *eqos = dev_get_priv(dev);
> +
> +	return clk_get_rate(&eqos->clk_master_bus);
>   }
>   
>   static int eqos_probe_resources_imx(struct udevice *dev)
>   {
>   	struct eqos_priv *eqos = dev_get_priv(dev);
>   	phy_interface_t interface;
> +	int ret;
>   
>   	debug("%s(dev=%p):\n", __func__, dev);
>   
> @@ -56,6 +54,118 @@ static int eqos_probe_resources_imx(struct udevice *dev)
>   		return -EINVAL;
>   	}
>   
> +	eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
> +
> +	ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
> +	if (ret) {
> +		pr_err("clk_get_by_name(master_bus) failed: %d", ret);

These should all be dev_dbg.

> +		goto err_probe;
> +	}
> +
> +	ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
> +	if (ret) {
> +		pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
> +		goto err_free_clk_master_bus;
> +	}
> +
> +	ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
> +	if (ret) {
> +		pr_err("clk_get_by_name(tx) failed: %d", ret);
> +		goto err_free_clk_ptp_ref;
> +	}
> +
> +	ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck);
> +	if (ret) {
> +		pr_err("clk_get_by_name(pclk) failed: %d", ret);
> +		goto err_free_clk_tx;
> +	}
> +
> +	debug("%s: OK\n", __func__);
> +	return 0;
> +
> +err_free_clk_tx:
> +	clk_free(&eqos->clk_tx);
> +err_free_clk_ptp_ref:
> +	clk_free(&eqos->clk_ptp_ref);
> +err_free_clk_master_bus:
> +	clk_free(&eqos->clk_master_bus);
> +err_probe:
> +
> +	debug("%s: returns %d\n", __func__, ret);
> +	return ret;
> +}
> +
> +static int eqos_remove_resources_imx(struct udevice *dev)
> +{
> +	struct eqos_priv *eqos = dev_get_priv(dev);
> +
> +	debug("%s(dev=%p):\n", __func__, dev);
> +
> +	clk_free(&eqos->clk_ck);
> +	clk_free(&eqos->clk_tx);
> +	clk_free(&eqos->clk_ptp_ref);
> +	clk_free(&eqos->clk_master_bus);
> +
> +	debug("%s: OK\n", __func__);
> +	return 0;
> +}
> +
> +static int eqos_start_clks_imx(struct udevice *dev)
> +{
> +	struct eqos_priv *eqos = dev_get_priv(dev);
> +	int ret;
> +
> +	debug("%s(dev=%p):\n", __func__, dev);
> +
> +	ret = clk_enable(&eqos->clk_master_bus);
> +	if (ret < 0) {
> +		pr_err("clk_enable(clk_master_bus) failed: %d", ret);

ditto

> +		goto err;
> +	}
> +
> +	ret = clk_enable(&eqos->clk_ptp_ref);
> +	if (ret < 0) {
> +		pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
> +		goto err_disable_clk_master_bus;
> +	}
> +
> +	ret = clk_enable(&eqos->clk_tx);
> +	if (ret < 0) {
> +		pr_err("clk_enable(clk_tx) failed: %d", ret);
> +		goto err_disable_clk_ptp_ref;
> +	}
> +
> +	ret = clk_enable(&eqos->clk_ck);
> +	if (ret < 0) {
> +		pr_err("clk_enable(clk_ck) failed: %d", ret);
> +		goto err_disable_clk_tx;
> +	}
> +
> +	debug("%s: OK\n", __func__);
> +	return 0;
> +
> +err_disable_clk_tx:
> +	clk_disable(&eqos->clk_tx);
> +err_disable_clk_ptp_ref:
> +	clk_disable(&eqos->clk_ptp_ref);
> +err_disable_clk_master_bus:
> +	clk_disable(&eqos->clk_master_bus);
> +err:
> +	debug("%s: FAILED: %d\n", __func__, ret);

ditto

> +	return ret;
> +}
> +
> +static int eqos_stop_clks_imx(struct udevice *dev)
> +{
> +	struct eqos_priv *eqos = dev_get_priv(dev);
> +
> +	debug("%s(dev=%p):\n", __func__, dev);
> +
> +	clk_disable(&eqos->clk_ck);
> +	clk_disable(&eqos->clk_tx);
> +	clk_disable(&eqos->clk_ptp_ref);
> +	clk_disable(&eqos->clk_master_bus);
> +
>   	debug("%s: OK\n", __func__);
>   	return 0;
>   }
> @@ -83,7 +193,7 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
>   		return -EINVAL;
>   	}
>   
> -	ret = imx_eqos_txclk_set_rate(rate);
> +	ret = clk_set_rate(&eqos->clk_tx, rate);
>   	if (ret < 0) {
>   		pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
>   		return ret;
> @@ -107,11 +217,11 @@ static struct eqos_ops eqos_imx_ops = {
>   	.eqos_inval_buffer = eqos_inval_buffer_generic,
>   	.eqos_flush_buffer = eqos_flush_buffer_generic,
>   	.eqos_probe_resources = eqos_probe_resources_imx,
> -	.eqos_remove_resources = eqos_null_ops,
> +	.eqos_remove_resources = eqos_remove_resources_imx,
>   	.eqos_stop_resets = eqos_null_ops,
>   	.eqos_start_resets = eqos_null_ops,
> -	.eqos_stop_clks = eqos_null_ops,
> -	.eqos_start_clks = eqos_null_ops,
> +	.eqos_stop_clks = eqos_stop_clks_imx,
> +	.eqos_start_clks = eqos_start_clks_imx,
>   	.eqos_calibrate_pads = eqos_null_ops,
>   	.eqos_disable_calibration = eqos_null_ops,
>   	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,

Anyway, this looks fine other than the debug stuff.

--Sean

Re: [PATCH 1/9] clk: imx8mp: Add EQoS MAC clock

[Stefano Babic]

Hi Marek,

not related to this patch, but to the whole series. I have applied it to 
my test (master-next) branch and I ran CI, this series breaks 3 boards.

	https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/565207

Can you fix it into a V2 ?

Best regards,
Stefano

On 19.01.23 22:44, Marek Vasut wrote:
> Add clock for the DWMAC EQoS block. This is used among other things
> to configure the MII clock via DM CLK.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>   drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++
>   1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index ffbc1d1ba9f..6dda0403e35 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
>   					 "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
>   					 "audio_pll2_out", "sys_pll1_133m", };
>   
> +static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
> +					     "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
> +					     "video_pll1_out", "clk_ext4", };
> +
> +static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
> +						   "clk_ext1", "clk_ext2", "clk_ext3",
> +						   "clk_ext4", "video_pll1_out", };
> +
>   static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
>   					   "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
>   					   "audio_pll2_out", "sys_pll1_100m", };
> @@ -250,6 +258,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
>   	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
>   	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
>   	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
> +	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
> +	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
>   	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
>   	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
>   	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
> @@ -292,10 +302,13 @@ static int imx8mp_clk_probe(struct udevice *dev)
>   	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
>   	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
>   	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
> +	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
> +	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
>   	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
>   	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
>   	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
>   	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
> +	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
>   	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
>   	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
>   	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

Re: [PATCH 2/9] net: dwc_eth_qos: Drop bogus return after goto

[Ramon Fried]

On Thu, Jan 19, 2023 at 11:45 PM Marek Vasut <marex@denx.de> wrote:
>
> The return is never triggered due to the goto just above it.
> Drop it. No functional change.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>  drivers/net/dwc_eth_qos.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index afc47b56ff5..44d05908894 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1373,7 +1373,6 @@ static int eqos_probe_resources_tegra186(struct udevice *dev)
>         if (ret) {
>                 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
>                 goto err_free_clk_rx;
> -               return ret;
>         }
>
>         ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
> --
> 2.39.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 3/9] net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32

[Ramon Fried]

On Thu, Jan 19, 2023 at 11:45 PM Marek Vasut <marex@denx.de> wrote:
>
> The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
> pointer is never valid. This is because only tegra186 ever claims the
> phy_reset_gpio, all other platforms use the PHY framework to reset the
> PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>  drivers/net/dwc_eth_qos.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 44d05908894..cd2def4ba21 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1502,9 +1502,6 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
>                 clk_free(&eqos->clk_ck);
>  #endif
>
> -       if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
> -               dm_gpio_free(dev, &eqos->phy_reset_gpio);
> -
>         debug("%s: OK\n", __func__);
>         return 0;
>  }
> --
> 2.39.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 4/9] net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC

[Ramon Fried]

On Thu, Jan 19, 2023 at 11:45 PM Marek Vasut <marex@denx.de> wrote:
>
> The driver currently only waits for DMA_MODE SWR bit to clear itself.
> This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
> before IOMUX GPR[1] content is latched into the MAC and used. Without
> the proper reset, the i.MX8M Plus MAC variant does not take the value
> in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
> interface mode from RGMII to any other.
>
> Since proper reset is desired in general to put the block into defined
> state, always assert the DMA_MODE SWR bit before waiting for the bit
> to clear itself.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>  drivers/net/dwc_eth_qos.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index cd2def4ba21..d488bd0c288 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev)
>
>         eqos->reg_access_ok = true;
>
> +       /*
> +        * Assert the SWR first, the actually reset the MAC and to latch in
> +        * e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
> +        */
> +       setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
> +
>         ret = wait_for_bit_le32(&eqos->dma_regs->mode,
>                                 EQOS_DMA_MODE_SWR, false,
>                                 eqos->config->swr_wait, false);
> --
> 2.39.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 6/9] net: dwc_eth_qos: Add i.MX8M Plus RMII support

[Ramon Fried]

On Thu, Jan 19, 2023 at 11:45 PM Marek Vasut <marex@denx.de> wrote:
>
> With DM clock support in place, it is easy to add RMII support into the
> MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
> the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.
>
> The board DT requires the following adjustments to EQoS node:
>   phy-mode = "rmii";
>   assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
>                         <&clk IMX8MP_SYS_PLL2_100M>,
>                         <&clk IMX8MP_SYS_PLL2_50M>;
>   assigned-clock-rates = <0>, <100000000>, <50000000>;
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>  drivers/net/dwc_eth_qos_imx.c | 26 +++++++++++++++-----------
>  1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
> index d0b7ef75c26..55080257623 100644
> --- a/drivers/net/dwc_eth_qos_imx.c
> +++ b/drivers/net/dwc_eth_qos_imx.c
> @@ -178,21 +178,25 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
>
>         debug("%s(dev=%p):\n", __func__, dev);
>
> -       switch (eqos->phy->speed) {
> -       case SPEED_1000:
> -               rate = 125 * 1000 * 1000;
> -               break;
> -       case SPEED_100:
> -               rate = 25 * 1000 * 1000;
> -               break;
> -       case SPEED_10:
> -               rate = 2.5 * 1000 * 1000;
> -               break;
> -       default:
> +       if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
> +               rate = 5000;    /* 5000 kHz = 5 MHz */
> +       else
> +               rate = 2500;    /* 2500 kHz = 2.5 MHz */
> +
> +       if (eqos->phy->speed == SPEED_1000 &&
> +           eqos->phy->interface == PHY_INTERFACE_MODE_RGMII) {
> +               rate *= 50;     /* Use 50x base rate i.e. 125 MHz */
> +       } else if (eqos->phy->speed == SPEED_100) {
> +               rate *= 10;     /* Use 10x base rate */
> +       } else if (eqos->phy->speed == SPEED_10) {
> +               rate *= 1;      /* Use base rate */
> +       } else {
>                 pr_err("invalid speed %d", eqos->phy->speed);
>                 return -EINVAL;
>         }
>
> +       rate *= 1000;   /* clk_set_rate() operates in Hz */
> +
>         ret = clk_set_rate(&eqos->clk_tx, rate);
>         if (ret < 0) {
>                 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
> --
> 2.39.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 7/9] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus

[Ramon Fried]

On Thu, Jan 19, 2023 at 11:45 PM Marek Vasut <marex@denx.de> wrote:
>
> Implement common board_interface_eth_init() and call it from the DWMAC
> driver to configure IOMUXC GPR[1] register according to the PHY mode
> obtained from DT. This supports all three interface modes supported by
> the i.MX8M Plus DWMAC and supersedes current board-side configuration
> of the same IOMUX GPR[1] duplicated in the board files.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Lukasz Majewski <lukma@denx.de>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ramon Fried <rfried.dev@gmail.com>
> Cc: Sean Anderson <seanga2@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Cc: u-boot@lists.denx.de
> ---
>  arch/arm/include/asm/arch-imx8m/imx-regs.h |  8 ++++-
>  arch/arm/mach-imx/imx8m/clock_imx8mm.c     | 37 ++++++++++++++++++++++
>  drivers/net/dwc_eth_qos_imx.c              |  4 +++
>  3 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> index 20f4699a12b..88e7f7dc557 100644
> --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> @@ -85,7 +85,13 @@
>  #define DDRC_IPS_BASE_ADDR(X)  (0x3d400000 + ((X) * 0x2000000))
>  #define DDR_CSD1_BASE_ADDR     0x40000000
>
> -#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN          BIT(21)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL    BIT(20)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN                BIT(19)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK     GENMASK(18, 16)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII      (0 << 16)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII    (1 << 16)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII     (4 << 16)
>  #define FEC_QUIRK_ENET_MAC
>
>  #define CAAM_ARB_BASE_ADDR              (0x00100000)
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 494bfbedc8c..069087c2cfd 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -15,6 +15,7 @@
>  #include <errno.h>
>  #include <linux/bitops.h>
>  #include <linux/delay.h>
> +#include <phy.h>
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> @@ -872,6 +873,42 @@ int set_clk_eqos(enum enet_freq type)
>
>         return 0;
>  }
> +
> +int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
> +{
> +       struct iomuxc_gpr_base_regs *gpr =
> +               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> +       clrbits_le32(&gpr->gpr[1],
> +                    IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
> +                    IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
> +                    IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
> +                    IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
> +
> +       switch (interface_type) {
> +       case PHY_INTERFACE_MODE_MII:
> +               setbits_le32(&gpr->gpr[1],
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
> +               break;
> +       case PHY_INTERFACE_MODE_RMII:
> +               setbits_le32(&gpr->gpr[1],
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
> +               break;
> +       case PHY_INTERFACE_MODE_RGMII:
> +               setbits_le32(&gpr->gpr[1],
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
> +                            IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
> +               break;
> +       default:
> +               return -EINVAL;
> +       }
> +
> +       return 0;
> +}
>  #endif
>
>  #ifdef CONFIG_FEC_MXC
> diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
> index 55080257623..f8f4cbc0257 100644
> --- a/drivers/net/dwc_eth_qos_imx.c
> +++ b/drivers/net/dwc_eth_qos_imx.c
> @@ -54,6 +54,10 @@ static int eqos_probe_resources_imx(struct udevice *dev)
>                 return -EINVAL;
>         }
>
> +       ret = board_interface_eth_init(dev, interface);
> +       if (ret)
> +               return -EINVAL;
> +
>         eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
>
>         ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
> --
> 2.39.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>