* [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
@ 2021-12-22 22:35 ` Matthew Brost
0 siblings, 0 replies; 14+ messages in thread
From: Matthew Brost @ 2021-12-22 22:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: john.c.harrison
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for the existing (hopefully soon deprecated) bonding interface.
We perma-pin these execlists contexts to align with GuC implementation.
v2:
(John Harrison)
- Drop siblings array as num_siblings must be 1
v3:
(John Harrison)
- Drop single submission
v4:
(John Harrison)
- Actually drop single submission
- Use IS_ERR check on return value from intel_context_create
- Set last request to NULL on unpin
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++++--
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
5 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cad3f0b2be9e..b0d2d81fc3b3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
struct intel_engine_cs **siblings = NULL;
intel_engine_mask_t prev_mask;
- /* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(&to_gt(i915)->uc)))
- return -ENODEV;
-
if (get_user(slot, &ext->engine_index))
return -EFAULT;
@@ -583,6 +579,13 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
if (get_user(num_siblings, &ext->num_siblings))
return -EFAULT;
+ if (!intel_uc_uses_guc_submission(&to_gt(i915)->uc) &&
+ num_siblings != 1) {
+ drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
if (slot >= set->num_engines) {
drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
slot, set->num_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index ba083d800a08..5d0ec7c49b6a 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
__i915_active_acquire(&ce->active);
- if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
+ intel_context_is_parallel(ce))
return 0;
/* Preallocate tracking nodes */
@@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
* Callers responsibility to validate that this function is used
* correctly but we use GEM_BUG_ON here ensure that they do.
*/
- GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
GEM_BUG_ON(intel_context_is_pinned(parent));
GEM_BUG_ON(intel_context_is_child(parent));
GEM_BUG_ON(intel_context_is_pinned(child));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index a69df5e9e77a..be56d0b41892 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2599,6 +2599,43 @@ static void execlists_context_cancel_request(struct intel_context *ce,
current->comm);
}
+static struct intel_context *
+execlists_create_parallel(struct intel_engine_cs **engines,
+ unsigned int num_siblings,
+ unsigned int width)
+{
+ struct intel_context *parent = NULL, *ce, *err;
+ int i;
+
+ GEM_BUG_ON(num_siblings != 1);
+
+ for (i = 0; i < width; ++i) {
+ ce = intel_context_create(engines[i]);
+ if (IS_ERR(ce)) {
+ err = ce;
+ goto unwind;
+ }
+
+ if (i == 0)
+ parent = ce;
+ else
+ intel_context_bind_parent_child(parent, ce);
+ }
+
+ parent->parallel.fence_context = dma_fence_context_alloc(1);
+
+ intel_context_set_nopreempt(parent);
+ for_each_child(parent, ce)
+ intel_context_set_nopreempt(ce);
+
+ return parent;
+
+unwind:
+ if (parent)
+ intel_context_put(parent);
+ return err;
+}
+
static const struct intel_context_ops execlists_context_ops = {
.flags = COPS_HAS_INFLIGHT,
@@ -2617,6 +2654,7 @@ static const struct intel_context_ops execlists_context_ops = {
.reset = lrc_reset,
.destroy = lrc_destroy,
+ .create_parallel = execlists_create_parallel,
.create_virtual = execlists_create_virtual,
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3489599e4de..84456ffeb4cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1065,6 +1065,10 @@ lrc_pin(struct intel_context *ce,
void lrc_unpin(struct intel_context *ce)
{
+ if (unlikely(ce->parallel.last_rq)) {
+ i915_request_put(ce->parallel.last_rq);
+ ce->parallel.last_rq = NULL;
+ }
check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e7517206af82..0a03a30e4c6d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3248,8 +3248,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
GEM_BUG_ON(!intel_context_is_parent(ce));
GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
- if (ce->parallel.last_rq)
- i915_request_put(ce->parallel.last_rq);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
@ 2021-12-22 22:35 ` Matthew Brost
0 siblings, 0 replies; 14+ messages in thread
From: Matthew Brost @ 2021-12-22 22:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for the existing (hopefully soon deprecated) bonding interface.
We perma-pin these execlists contexts to align with GuC implementation.
v2:
(John Harrison)
- Drop siblings array as num_siblings must be 1
v3:
(John Harrison)
- Drop single submission
v4:
(John Harrison)
- Actually drop single submission
- Use IS_ERR check on return value from intel_context_create
- Set last request to NULL on unpin
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++++--
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
5 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cad3f0b2be9e..b0d2d81fc3b3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
struct intel_engine_cs **siblings = NULL;
intel_engine_mask_t prev_mask;
- /* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(&to_gt(i915)->uc)))
- return -ENODEV;
-
if (get_user(slot, &ext->engine_index))
return -EFAULT;
@@ -583,6 +579,13 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
if (get_user(num_siblings, &ext->num_siblings))
return -EFAULT;
+ if (!intel_uc_uses_guc_submission(&to_gt(i915)->uc) &&
+ num_siblings != 1) {
+ drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
if (slot >= set->num_engines) {
drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
slot, set->num_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index ba083d800a08..5d0ec7c49b6a 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
__i915_active_acquire(&ce->active);
- if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
+ intel_context_is_parallel(ce))
return 0;
/* Preallocate tracking nodes */
@@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
* Callers responsibility to validate that this function is used
* correctly but we use GEM_BUG_ON here ensure that they do.
*/
- GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
GEM_BUG_ON(intel_context_is_pinned(parent));
GEM_BUG_ON(intel_context_is_child(parent));
GEM_BUG_ON(intel_context_is_pinned(child));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index a69df5e9e77a..be56d0b41892 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2599,6 +2599,43 @@ static void execlists_context_cancel_request(struct intel_context *ce,
current->comm);
}
+static struct intel_context *
+execlists_create_parallel(struct intel_engine_cs **engines,
+ unsigned int num_siblings,
+ unsigned int width)
+{
+ struct intel_context *parent = NULL, *ce, *err;
+ int i;
+
+ GEM_BUG_ON(num_siblings != 1);
+
+ for (i = 0; i < width; ++i) {
+ ce = intel_context_create(engines[i]);
+ if (IS_ERR(ce)) {
+ err = ce;
+ goto unwind;
+ }
+
+ if (i == 0)
+ parent = ce;
+ else
+ intel_context_bind_parent_child(parent, ce);
+ }
+
+ parent->parallel.fence_context = dma_fence_context_alloc(1);
+
+ intel_context_set_nopreempt(parent);
+ for_each_child(parent, ce)
+ intel_context_set_nopreempt(ce);
+
+ return parent;
+
+unwind:
+ if (parent)
+ intel_context_put(parent);
+ return err;
+}
+
static const struct intel_context_ops execlists_context_ops = {
.flags = COPS_HAS_INFLIGHT,
@@ -2617,6 +2654,7 @@ static const struct intel_context_ops execlists_context_ops = {
.reset = lrc_reset,
.destroy = lrc_destroy,
+ .create_parallel = execlists_create_parallel,
.create_virtual = execlists_create_virtual,
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3489599e4de..84456ffeb4cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1065,6 +1065,10 @@ lrc_pin(struct intel_context *ce,
void lrc_unpin(struct intel_context *ce)
{
+ if (unlikely(ce->parallel.last_rq)) {
+ i915_request_put(ce->parallel.last_rq);
+ ce->parallel.last_rq = NULL;
+ }
check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e7517206af82..0a03a30e4c6d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3248,8 +3248,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
GEM_BUG_ON(!intel_context_is_parent(ce));
GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
- if (ce->parallel.last_rq)
- i915_request_put(ce->parallel.last_rq);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Weak parallel submission support for execlists (rev3)
2021-12-22 22:35 ` [Intel-gfx] " Matthew Brost
(?)
@ 2021-12-22 23:36 ` Patchwork
-1 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-12-22 23:36 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8048 bytes --]
== Series Details ==
Series: drm/i915/execlists: Weak parallel submission support for execlists (rev3)
URL : https://patchwork.freedesktop.org/series/96088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11029 -> Patchwork_21899
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/index.html
Participating hosts (43 -> 38)
------------------------------
Additional (2): fi-kbl-soraka fi-icl-u2
Missing (7): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_21899 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][3] -> [INCOMPLETE][4] ([i915#4006])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +25 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-tgl-u2: [PASS][6] -> [FAIL][7] ([i915#1888])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/fi-tgl-u2/igt@gem_exec_suspend@basic-s0@smem.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-tgl-u2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][9] ([i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886] / [i915#2291])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109278]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109285])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][17] -> [DMESG-WARN][18] ([i915#4269])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][20] -> [FAIL][21] ([i915#4547])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][22] ([i915#3301])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][23] ([i915#4312])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-skl-6600u/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][24] ([i915#2722] / [i915#4312])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][25] ([i915#3921]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11029 -> Patchwork_21899
CI-20190529: 20190529
CI_DRM_11029: ed49e39bdb15ee9721b96022cde454ffa045d621 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6317: 704a1a42db2fad72c382e95c9da200b5bde5e5fc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21899: b7b9cf98477fc928bcef85ea8b32087b60116c16 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b7b9cf98477f drm/i915/execlists: Weak parallel submission support for execlists
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/index.html
[-- Attachment #2: Type: text/html, Size: 9755 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-12-22 22:35 ` [Intel-gfx] " Matthew Brost
@ 2021-12-23 0:54 ` John Harrison
-1 siblings, 0 replies; 14+ messages in thread
From: John Harrison @ 2021-12-23 0:54 UTC (permalink / raw)
To: Matthew Brost, intel-gfx, dri-devel
On 12/22/2021 14:35, Matthew Brost wrote:
> A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> execlists. Doing as little as possible to support this interface for
> execlists - basically just passing submit fences between each request
> generated and virtual engines are not allowed. This is on par with what
> is there for the existing (hopefully soon deprecated) bonding interface.
>
> We perma-pin these execlists contexts to align with GuC implementation.
>
> v2:
> (John Harrison)
> - Drop siblings array as num_siblings must be 1
> v3:
> (John Harrison)
> - Drop single submission
> v4:
> (John Harrison)
> - Actually drop single submission
> - Use IS_ERR check on return value from intel_context_create
> - Set last request to NULL on unpin
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++++--
> drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> .../drm/i915/gt/intel_execlists_submission.c | 38 +++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> 5 files changed, 51 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index cad3f0b2be9e..b0d2d81fc3b3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> struct intel_engine_cs **siblings = NULL;
> intel_engine_mask_t prev_mask;
>
> - /* FIXME: This is NIY for execlists */
> - if (!(intel_uc_uses_guc_submission(&to_gt(i915)->uc)))
> - return -ENODEV;
> -
> if (get_user(slot, &ext->engine_index))
> return -EFAULT;
>
> @@ -583,6 +579,13 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> if (get_user(num_siblings, &ext->num_siblings))
> return -EFAULT;
>
> + if (!intel_uc_uses_guc_submission(&to_gt(i915)->uc) &&
> + num_siblings != 1) {
> + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> + num_siblings);
> + return -EINVAL;
> + }
> +
> if (slot >= set->num_engines) {
> drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> slot, set->num_engines);
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index ba083d800a08..5d0ec7c49b6a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
>
> __i915_active_acquire(&ce->active);
>
> - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> + intel_context_is_parallel(ce))
> return 0;
>
> /* Preallocate tracking nodes */
> @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> * Callers responsibility to validate that this function is used
> * correctly but we use GEM_BUG_ON here ensure that they do.
> */
> - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> GEM_BUG_ON(intel_context_is_pinned(parent));
> GEM_BUG_ON(intel_context_is_child(parent));
> GEM_BUG_ON(intel_context_is_pinned(child));
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index a69df5e9e77a..be56d0b41892 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2599,6 +2599,43 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> current->comm);
> }
>
> +static struct intel_context *
> +execlists_create_parallel(struct intel_engine_cs **engines,
> + unsigned int num_siblings,
> + unsigned int width)
> +{
> + struct intel_context *parent = NULL, *ce, *err;
> + int i;
> +
> + GEM_BUG_ON(num_siblings != 1);
> +
> + for (i = 0; i < width; ++i) {
> + ce = intel_context_create(engines[i]);
> + if (IS_ERR(ce)) {
> + err = ce;
Could get rid of 'err' and just say 'return ce;' at the end of 'unwind:'.
Either way:
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> + goto unwind;
> + }
> +
> + if (i == 0)
> + parent = ce;
> + else
> + intel_context_bind_parent_child(parent, ce);
> + }
> +
> + parent->parallel.fence_context = dma_fence_context_alloc(1);
> +
> + intel_context_set_nopreempt(parent);
> + for_each_child(parent, ce)
> + intel_context_set_nopreempt(ce);
> +
> + return parent;
> +
> +unwind:
> + if (parent)
> + intel_context_put(parent);
> + return err;
> +}
> +
> static const struct intel_context_ops execlists_context_ops = {
> .flags = COPS_HAS_INFLIGHT,
>
> @@ -2617,6 +2654,7 @@ static const struct intel_context_ops execlists_context_ops = {
> .reset = lrc_reset,
> .destroy = lrc_destroy,
>
> + .create_parallel = execlists_create_parallel,
> .create_virtual = execlists_create_virtual,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b3489599e4de..84456ffeb4cd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1065,6 +1065,10 @@ lrc_pin(struct intel_context *ce,
>
> void lrc_unpin(struct intel_context *ce)
> {
> + if (unlikely(ce->parallel.last_rq)) {
> + i915_request_put(ce->parallel.last_rq);
> + ce->parallel.last_rq = NULL;
> + }
> check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> ce->engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index e7517206af82..0a03a30e4c6d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -3248,8 +3248,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> GEM_BUG_ON(!intel_context_is_parent(ce));
> GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
>
> - if (ce->parallel.last_rq)
> - i915_request_put(ce->parallel.last_rq);
> unpin_guc_id(guc, ce);
> lrc_unpin(ce);
> }
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
@ 2021-12-23 0:54 ` John Harrison
0 siblings, 0 replies; 14+ messages in thread
From: John Harrison @ 2021-12-23 0:54 UTC (permalink / raw)
To: Matthew Brost, intel-gfx, dri-devel
On 12/22/2021 14:35, Matthew Brost wrote:
> A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> execlists. Doing as little as possible to support this interface for
> execlists - basically just passing submit fences between each request
> generated and virtual engines are not allowed. This is on par with what
> is there for the existing (hopefully soon deprecated) bonding interface.
>
> We perma-pin these execlists contexts to align with GuC implementation.
>
> v2:
> (John Harrison)
> - Drop siblings array as num_siblings must be 1
> v3:
> (John Harrison)
> - Drop single submission
> v4:
> (John Harrison)
> - Actually drop single submission
> - Use IS_ERR check on return value from intel_context_create
> - Set last request to NULL on unpin
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++++--
> drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> .../drm/i915/gt/intel_execlists_submission.c | 38 +++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> 5 files changed, 51 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index cad3f0b2be9e..b0d2d81fc3b3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> struct intel_engine_cs **siblings = NULL;
> intel_engine_mask_t prev_mask;
>
> - /* FIXME: This is NIY for execlists */
> - if (!(intel_uc_uses_guc_submission(&to_gt(i915)->uc)))
> - return -ENODEV;
> -
> if (get_user(slot, &ext->engine_index))
> return -EFAULT;
>
> @@ -583,6 +579,13 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> if (get_user(num_siblings, &ext->num_siblings))
> return -EFAULT;
>
> + if (!intel_uc_uses_guc_submission(&to_gt(i915)->uc) &&
> + num_siblings != 1) {
> + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> + num_siblings);
> + return -EINVAL;
> + }
> +
> if (slot >= set->num_engines) {
> drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> slot, set->num_engines);
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index ba083d800a08..5d0ec7c49b6a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
>
> __i915_active_acquire(&ce->active);
>
> - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> + intel_context_is_parallel(ce))
> return 0;
>
> /* Preallocate tracking nodes */
> @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> * Callers responsibility to validate that this function is used
> * correctly but we use GEM_BUG_ON here ensure that they do.
> */
> - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> GEM_BUG_ON(intel_context_is_pinned(parent));
> GEM_BUG_ON(intel_context_is_child(parent));
> GEM_BUG_ON(intel_context_is_pinned(child));
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index a69df5e9e77a..be56d0b41892 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2599,6 +2599,43 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> current->comm);
> }
>
> +static struct intel_context *
> +execlists_create_parallel(struct intel_engine_cs **engines,
> + unsigned int num_siblings,
> + unsigned int width)
> +{
> + struct intel_context *parent = NULL, *ce, *err;
> + int i;
> +
> + GEM_BUG_ON(num_siblings != 1);
> +
> + for (i = 0; i < width; ++i) {
> + ce = intel_context_create(engines[i]);
> + if (IS_ERR(ce)) {
> + err = ce;
Could get rid of 'err' and just say 'return ce;' at the end of 'unwind:'.
Either way:
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> + goto unwind;
> + }
> +
> + if (i == 0)
> + parent = ce;
> + else
> + intel_context_bind_parent_child(parent, ce);
> + }
> +
> + parent->parallel.fence_context = dma_fence_context_alloc(1);
> +
> + intel_context_set_nopreempt(parent);
> + for_each_child(parent, ce)
> + intel_context_set_nopreempt(ce);
> +
> + return parent;
> +
> +unwind:
> + if (parent)
> + intel_context_put(parent);
> + return err;
> +}
> +
> static const struct intel_context_ops execlists_context_ops = {
> .flags = COPS_HAS_INFLIGHT,
>
> @@ -2617,6 +2654,7 @@ static const struct intel_context_ops execlists_context_ops = {
> .reset = lrc_reset,
> .destroy = lrc_destroy,
>
> + .create_parallel = execlists_create_parallel,
> .create_virtual = execlists_create_virtual,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b3489599e4de..84456ffeb4cd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1065,6 +1065,10 @@ lrc_pin(struct intel_context *ce,
>
> void lrc_unpin(struct intel_context *ce)
> {
> + if (unlikely(ce->parallel.last_rq)) {
> + i915_request_put(ce->parallel.last_rq);
> + ce->parallel.last_rq = NULL;
> + }
> check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> ce->engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index e7517206af82..0a03a30e4c6d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -3248,8 +3248,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> GEM_BUG_ON(!intel_context_is_parent(ce));
> GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
>
> - if (ce->parallel.last_rq)
> - i915_request_put(ce->parallel.last_rq);
> unpin_guc_id(guc, ce);
> lrc_unpin(ce);
> }
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Weak parallel submission support for execlists (rev3)
2021-12-22 22:35 ` [Intel-gfx] " Matthew Brost
` (2 preceding siblings ...)
(?)
@ 2021-12-23 2:29 ` Patchwork
-1 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-12-23 2:29 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30296 bytes --]
== Series Details ==
Series: drm/i915/execlists: Weak parallel submission support for execlists (rev3)
URL : https://patchwork.freedesktop.org/series/96088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11029_full -> Patchwork_21899_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_21899_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21899_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21899_full:
### IGT changes ###
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][1] ([i915#232]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-tglb5/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][3] ([i915#4525]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
- shard-tglb: [SKIP][5] ([i915#4525]) -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-tglb3/igt@gem_exec_balancer@parallel-ordering.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb8/igt@gem_exec_balancer@parallel-ordering.html
- shard-kbl: [SKIP][7] ([fdo#109271]) -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-kbl3/igt@gem_exec_balancer@parallel-ordering.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl6/igt@gem_exec_balancer@parallel-ordering.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling}:
- shard-glk: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling}:
- shard-iclb: [PASS][11] -> [SKIP][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
Known issues
------------
Here are the changes found in Patchwork_21899_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][13], [FAIL][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37]) ([i915#4386]) -> ([PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl1/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl1/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl1/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl1/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl2/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl2/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl4/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl4/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl4/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl4/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl8/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl8/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl1/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl1/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl1/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl2/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl2/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl2/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl4/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl4/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl4/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl4/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl7/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl7/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl7/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl8/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl8/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][63] ([i915#3002])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/igt@gem_create@create-massive.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][64] ([i915#4547])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][65] -> [FAIL][66] ([i915#2842])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][67] -> [FAIL][68] ([i915#2842])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-glk7/igt@gem_exec_fair@basic-none@vcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][69] -> [FAIL][70] ([i915#2842])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][71] -> [FAIL][72] ([i915#2842]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@basic:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#4613])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#4613])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl3/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][75] ([fdo#111656])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@gem_mmap_gtt@coherency.html
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109292])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@gem_mmap_gtt@coherency.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#4270])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@gem_pxp@reject-modify-context-protection-on.html
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#4270])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109312])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@gem_softpin@evict-snoop.html
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109312])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@access-control:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#3297]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb6/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#3297])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen3_render_tiledy_blits:
- shard-tglb: NOTRUN -> [SKIP][83] ([fdo#109289]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb7/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][84] -> [DMESG-WARN][85] ([i915#1436] / [i915#716])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-glk4/igt@gen9_exec_parse@allowed-all.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][86] ([i915#2856])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@gen9_exec_parse@secure-batches.html
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#2856])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][88] -> [FAIL][89] ([i915#454])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#1937])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109506] / [i915#2411])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109293] / [fdo#109506])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_pm_sseu@full-enable:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#4387])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@i915_pm_sseu@full-enable.html
- shard-iclb: NOTRUN -> [SKIP][94] ([i915#4387])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-unsupported:
- shard-tglb: NOTRUN -> [SKIP][95] ([fdo#109302])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb7/igt@i915_query@query-topology-unsupported.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][96] -> [DMESG-WARN][97] ([i915#180]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@i915_suspend@forcewake:
- shard-skl: [PASS][98] -> [INCOMPLETE][99] ([i915#636])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-skl9/igt@i915_suspend@forcewake.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl4/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][100] ([fdo#111614]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_big_fb@linear-8bpp-rotate-270.html
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#110725] / [fdo#111614]) +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#3886]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109278] / [i915#3886]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#3689] / [i915#3886])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#3886]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][106] ([i915#3689]) +3 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][107] ([fdo#111615] / [i915#3689])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb6/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271]) +28 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl1/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@plane-scaling:
- shard-apl: NOTRUN -> [SKIP][109] ([fdo#109271]) +47 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl6/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-iclb: NOTRUN -> [SKIP][110] ([fdo#109284] / [fdo#111827])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@vga-hpd:
- shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271] / [fdo#111827]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl3/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-d-degamma:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109278] / [i915#1149])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_color@pipe-d-degamma.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271] / [fdo#111827]) +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl1/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][114] ([fdo#109271] / [fdo#111827]) +5 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-tglb: NOTRUN -> [SKIP][116] ([fdo#109284] / [fdo#111827]) +3 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb6/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][117] ([i915#3319])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109278] / [fdo#109279]) +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][119] ([i915#3359]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][120] -> [INCOMPLETE][121] ([i915#3614])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][122] ([fdo#109279] / [i915#3359]) +4 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-iclb: NOTRUN -> [SKIP][123] ([fdo#109274] / [fdo#109278])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-tglb: NOTRUN -> [SKIP][124] ([fdo#111825]) +15 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][125] ([fdo#109274]) +2 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][126] -> [DMESG-WARN][127] ([i915#180]) +5 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-iclb: [PASS][128] -> [DMESG-WARN][129] ([i915#2867])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb8/igt@kms_flip@flip-vs-suspend@c-edp1.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1:
- shard-glk: [PASS][130] -> [FAIL][131] ([i915#2122])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-glk2/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-glk6/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][132] -> [FAIL][133] ([i915#2122]) +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-skl3/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl3/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: NOTRUN -> [SKIP][134] ([fdo#109271]) +35 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][135] ([fdo#109280]) +4 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][136] ([i915#1187])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_hdr@static-toggle-dpms.html
- shard-iclb: NOTRUN -> [SKIP][137] ([i915#1187])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#533])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#533])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][140] ([i915#132] / [i915#3467]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@kms_psr@psr2_cursor_mmap_gtt.html
- shard-iclb: NOTRUN -> [SKIP][141] ([fdo#109441])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][142] -> [SKIP][143] ([fdo#109441]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglb: NOTRUN -> [SKIP][144] ([fdo#111615]) +3 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_vblank@pipe-d-ts-continuation-idle-hang:
- shard-iclb: NOTRUN -> [SKIP][145] ([fdo#109278]) +10 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@kms_vblank@pipe-d-ts-continuation-idle-hang.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][146] ([fdo#109271] / [i915#2437])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-apl3/igt@kms_writeback@writeback-fb-id.html
- shard-kbl: NOTRUN -> [SKIP][147] ([fdo#109271] / [i915#2437])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl3/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][148] ([i915#2530])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
- shard-tglb: NOTRUN -> [SKIP][149] ([i915#2530])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][150] -> [FAIL][151] ([i915#1542])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-skl3/igt@perf@polling-parameterized.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl3/igt@perf@polling-parameterized.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][152] -> [FAIL][153] ([i915#1722])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-skl10/igt@perf@polling-small-buf.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-skl7/igt@perf@polling-small-buf.html
* igt@perf_pmu@event-wait@rcs0:
- shard-iclb: NOTRUN -> [SKIP][154] ([fdo#112283])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@perf_pmu@event-wait@rcs0.html
- shard-tglb: NOTRUN -> [SKIP][155] ([fdo#112283])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@perf_pmu@event-wait@rcs0.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][156] ([fdo#109291])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb5/igt@prime_nv_pcopy@test3_1.html
- shard-iclb: NOTRUN -> [SKIP][157] ([fdo#109291])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb1/igt@prime_nv_pcopy@test3_1.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][158] ([fdo#109271] / [i915#2994])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl1/igt@sysfs_clients@fair-3.html
- shard-tglb: NOTRUN -> [SKIP][159] ([i915#2994])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-tglb6/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][160] ([i915#658]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-iclb5/igt@feature_discovery@psr2.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_exec_balancer@parallel:
- shard-kbl: [SKIP][162] ([fdo#109271]) -> [PASS][163] +5 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-kbl4/igt@gem_exec_balancer@parallel.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/shard-kbl7/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-tglb: [SKIP][164] ([i915#4525]) -> [PASS][165] +6 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11029/shard-
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21899/index.html
[-- Attachment #2: Type: text/html, Size: 33786 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-12-06 20:01 ` John Harrison
@ 2021-12-22 22:21 ` Matthew Brost
0 siblings, 0 replies; 14+ messages in thread
From: Matthew Brost @ 2021-12-22 22:21 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel
On Mon, Dec 06, 2021 at 12:01:04PM -0800, John Harrison wrote:
> On 11/11/2021 13:20, Matthew Brost wrote:
> > A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> > execlists. Doing as little as possible to support this interface for
> > execlists - basically just passing submit fences between each request
> > generated and virtual engines are not allowed. This is on par with what
> > is there for the existing (hopefully soon deprecated) bonding interface.
> >
> > We perma-pin these execlists contexts to align with GuC implementation.
> >
> > v2:
> > (John Harrison)
> > - Drop siblings array as num_siblings must be 1
> > v3:
> > (John Harrison)
> > - Drop single submission
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
> > drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> > .../drm/i915/gt/intel_execlists_submission.c | 40 +++++++++++++++++++
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> > 5 files changed, 50 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index ebd775cb1661c..d7bf6c8f70b7b 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> > struct intel_engine_cs **siblings = NULL;
> > intel_engine_mask_t prev_mask;
> > - /* FIXME: This is NIY for execlists */
> > - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> > - return -ENODEV;
> > -
> > if (get_user(slot, &ext->engine_index))
> > return -EFAULT;
> > @@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> > if (get_user(num_siblings, &ext->num_siblings))
> > return -EFAULT;
> > + if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
> > + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> > + num_siblings);
> > + return -EINVAL;
> > + }
> > +
> > if (slot >= set->num_engines) {
> > drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> > slot, set->num_engines);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> > index 5634d14052bc9..1bec92e1d8e63 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
> > __i915_active_acquire(&ce->active);
> > - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> > + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> > + intel_context_is_parallel(ce))
> > return 0;
> > /* Preallocate tracking nodes */
> > @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> > * Callers responsibility to validate that this function is used
> > * correctly but we use GEM_BUG_ON here ensure that they do.
> > */
> > - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> > GEM_BUG_ON(intel_context_is_pinned(parent));
> > GEM_BUG_ON(intel_context_is_child(parent));
> > GEM_BUG_ON(intel_context_is_pinned(child));
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index ca03880fa7e49..5fd49ee47096d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -2598,6 +2598,45 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> > current->comm);
> > }
> > +static struct intel_context *
> > +execlists_create_parallel(struct intel_engine_cs **engines,
> > + unsigned int num_siblings,
> > + unsigned int width)
> > +{
> > + struct intel_context *parent = NULL, *ce, *err;
> > + int i;
> > +
> > + GEM_BUG_ON(num_siblings != 1);
> > +
> > + for (i = 0; i < width; ++i) {
> > + ce = intel_context_create(engines[i]);
> > + if (!ce) {
> > + err = ERR_PTR(-ENOMEM);
> intel_context_create already checks for null and returns -ENOMEM. This needs
> to check for IS_ERR(ce).
>
Yep.
> > + goto unwind;
> > + }
> > +
> > + if (i == 0)
> > + parent = ce;
> > + else
> > + intel_context_bind_parent_child(parent, ce);
> > + }
> > +
> > + parent->parallel.fence_context = dma_fence_context_alloc(1);
> > +
> > + intel_context_set_nopreempt(parent);
> > + for_each_child(parent, ce) {
> > + intel_context_set_nopreempt(ce);
> > + intel_context_set_single_submission(ce);
> I thought the single submission thing wasn't wanted anymore?
>
Yep.
> > + }
> > +
> > + return parent;
> > +
> > +unwind:
> > + if (parent)
> > + intel_context_put(parent);
> > + return err;
> > +}
> > +
> > static const struct intel_context_ops execlists_context_ops = {
> > .flags = COPS_HAS_INFLIGHT,
> > @@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
> > .reset = lrc_reset,
> > .destroy = lrc_destroy,
> > + .create_parallel = execlists_create_parallel,
> > .create_virtual = execlists_create_virtual,
> > };
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 56156cf18c413..70f4b309522d3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
> > void lrc_unpin(struct intel_context *ce)
> > {
> > + if (unlikely(ce->parallel.last_rq))
> > + i915_request_put(ce->parallel.last_rq);
> Should set this to null after to prevent the possibility of a double put?
>
Not needed as parallel contexts are perma-pinnned and only unpinned
once in their lifetime.
That being said, will set it to NULL anyways to be safe.
Matt
> John.
>
> > check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> > ce->engine);
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 5cc49c0b38897..cd1784953d679 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -3235,8 +3235,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> > GEM_BUG_ON(!intel_context_is_parent(ce));
> > GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
> > - if (ce->parallel.last_rq)
> > - i915_request_put(ce->parallel.last_rq);
> > unpin_guc_id(guc, ce);
> > lrc_unpin(ce);
> > }
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-11-11 21:20 [PATCH] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
@ 2021-12-06 20:01 ` John Harrison
2021-12-22 22:21 ` Matthew Brost
0 siblings, 1 reply; 14+ messages in thread
From: John Harrison @ 2021-12-06 20:01 UTC (permalink / raw)
To: Matthew Brost, intel-gfx, dri-devel
On 11/11/2021 13:20, Matthew Brost wrote:
> A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> execlists. Doing as little as possible to support this interface for
> execlists - basically just passing submit fences between each request
> generated and virtual engines are not allowed. This is on par with what
> is there for the existing (hopefully soon deprecated) bonding interface.
>
> We perma-pin these execlists contexts to align with GuC implementation.
>
> v2:
> (John Harrison)
> - Drop siblings array as num_siblings must be 1
> v3:
> (John Harrison)
> - Drop single submission
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
> drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> .../drm/i915/gt/intel_execlists_submission.c | 40 +++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> 5 files changed, 50 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ebd775cb1661c..d7bf6c8f70b7b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> struct intel_engine_cs **siblings = NULL;
> intel_engine_mask_t prev_mask;
>
> - /* FIXME: This is NIY for execlists */
> - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> - return -ENODEV;
> -
> if (get_user(slot, &ext->engine_index))
> return -EFAULT;
>
> @@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> if (get_user(num_siblings, &ext->num_siblings))
> return -EFAULT;
>
> + if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
> + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> + num_siblings);
> + return -EINVAL;
> + }
> +
> if (slot >= set->num_engines) {
> drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> slot, set->num_engines);
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 5634d14052bc9..1bec92e1d8e63 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
>
> __i915_active_acquire(&ce->active);
>
> - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> + intel_context_is_parallel(ce))
> return 0;
>
> /* Preallocate tracking nodes */
> @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> * Callers responsibility to validate that this function is used
> * correctly but we use GEM_BUG_ON here ensure that they do.
> */
> - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> GEM_BUG_ON(intel_context_is_pinned(parent));
> GEM_BUG_ON(intel_context_is_child(parent));
> GEM_BUG_ON(intel_context_is_pinned(child));
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index ca03880fa7e49..5fd49ee47096d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2598,6 +2598,45 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> current->comm);
> }
>
> +static struct intel_context *
> +execlists_create_parallel(struct intel_engine_cs **engines,
> + unsigned int num_siblings,
> + unsigned int width)
> +{
> + struct intel_context *parent = NULL, *ce, *err;
> + int i;
> +
> + GEM_BUG_ON(num_siblings != 1);
> +
> + for (i = 0; i < width; ++i) {
> + ce = intel_context_create(engines[i]);
> + if (!ce) {
> + err = ERR_PTR(-ENOMEM);
intel_context_create already checks for null and returns -ENOMEM. This
needs to check for IS_ERR(ce).
> + goto unwind;
> + }
> +
> + if (i == 0)
> + parent = ce;
> + else
> + intel_context_bind_parent_child(parent, ce);
> + }
> +
> + parent->parallel.fence_context = dma_fence_context_alloc(1);
> +
> + intel_context_set_nopreempt(parent);
> + for_each_child(parent, ce) {
> + intel_context_set_nopreempt(ce);
> + intel_context_set_single_submission(ce);
I thought the single submission thing wasn't wanted anymore?
> + }
> +
> + return parent;
> +
> +unwind:
> + if (parent)
> + intel_context_put(parent);
> + return err;
> +}
> +
> static const struct intel_context_ops execlists_context_ops = {
> .flags = COPS_HAS_INFLIGHT,
>
> @@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
> .reset = lrc_reset,
> .destroy = lrc_destroy,
>
> + .create_parallel = execlists_create_parallel,
> .create_virtual = execlists_create_virtual,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 56156cf18c413..70f4b309522d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
>
> void lrc_unpin(struct intel_context *ce)
> {
> + if (unlikely(ce->parallel.last_rq))
> + i915_request_put(ce->parallel.last_rq);
Should set this to null after to prevent the possibility of a double put?
John.
> check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> ce->engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 5cc49c0b38897..cd1784953d679 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -3235,8 +3235,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> GEM_BUG_ON(!intel_context_is_parent(ce));
> GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
>
> - if (ce->parallel.last_rq)
> - i915_request_put(ce->parallel.last_rq);
> unpin_guc_id(guc, ce);
> lrc_unpin(ce);
> }
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
@ 2021-11-11 21:20 Matthew Brost
2021-12-06 20:01 ` John Harrison
0 siblings, 1 reply; 14+ messages in thread
From: Matthew Brost @ 2021-11-11 21:20 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: john.c.harrison
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for the existing (hopefully soon deprecated) bonding interface.
We perma-pin these execlists contexts to align with GuC implementation.
v2:
(John Harrison)
- Drop siblings array as num_siblings must be 1
v3:
(John Harrison)
- Drop single submission
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 40 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
5 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ebd775cb1661c..d7bf6c8f70b7b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
struct intel_engine_cs **siblings = NULL;
intel_engine_mask_t prev_mask;
- /* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
- return -ENODEV;
-
if (get_user(slot, &ext->engine_index))
return -EFAULT;
@@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
if (get_user(num_siblings, &ext->num_siblings))
return -EFAULT;
+ if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
+ drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
if (slot >= set->num_engines) {
drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
slot, set->num_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 5634d14052bc9..1bec92e1d8e63 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
__i915_active_acquire(&ce->active);
- if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
+ intel_context_is_parallel(ce))
return 0;
/* Preallocate tracking nodes */
@@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
* Callers responsibility to validate that this function is used
* correctly but we use GEM_BUG_ON here ensure that they do.
*/
- GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
GEM_BUG_ON(intel_context_is_pinned(parent));
GEM_BUG_ON(intel_context_is_child(parent));
GEM_BUG_ON(intel_context_is_pinned(child));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index ca03880fa7e49..5fd49ee47096d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2598,6 +2598,45 @@ static void execlists_context_cancel_request(struct intel_context *ce,
current->comm);
}
+static struct intel_context *
+execlists_create_parallel(struct intel_engine_cs **engines,
+ unsigned int num_siblings,
+ unsigned int width)
+{
+ struct intel_context *parent = NULL, *ce, *err;
+ int i;
+
+ GEM_BUG_ON(num_siblings != 1);
+
+ for (i = 0; i < width; ++i) {
+ ce = intel_context_create(engines[i]);
+ if (!ce) {
+ err = ERR_PTR(-ENOMEM);
+ goto unwind;
+ }
+
+ if (i == 0)
+ parent = ce;
+ else
+ intel_context_bind_parent_child(parent, ce);
+ }
+
+ parent->parallel.fence_context = dma_fence_context_alloc(1);
+
+ intel_context_set_nopreempt(parent);
+ for_each_child(parent, ce) {
+ intel_context_set_nopreempt(ce);
+ intel_context_set_single_submission(ce);
+ }
+
+ return parent;
+
+unwind:
+ if (parent)
+ intel_context_put(parent);
+ return err;
+}
+
static const struct intel_context_ops execlists_context_ops = {
.flags = COPS_HAS_INFLIGHT,
@@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
.reset = lrc_reset,
.destroy = lrc_destroy,
+ .create_parallel = execlists_create_parallel,
.create_virtual = execlists_create_virtual,
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 56156cf18c413..70f4b309522d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
void lrc_unpin(struct intel_context *ce)
{
+ if (unlikely(ce->parallel.last_rq))
+ i915_request_put(ce->parallel.last_rq);
check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5cc49c0b38897..cd1784953d679 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3235,8 +3235,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
GEM_BUG_ON(!intel_context_is_parent(ce));
GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
- if (ce->parallel.last_rq)
- i915_request_put(ce->parallel.last_rq);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
}
--
2.33.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-10-27 20:04 ` John Harrison
@ 2021-10-27 20:10 ` Matthew Brost
0 siblings, 0 replies; 14+ messages in thread
From: Matthew Brost @ 2021-10-27 20:10 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel, tvrtko.ursulin, daniele.ceraolospurio
On Wed, Oct 27, 2021 at 01:04:49PM -0700, John Harrison wrote:
> On 10/27/2021 12:17, Matthew Brost wrote:
> > On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> > > On 10/20/2021 14:47, Matthew Brost wrote:
> > > > A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> > > > execlists. Doing as little as possible to support this interface for
> > > > execlists - basically just passing submit fences between each request
> > > > generated and virtual engines are not allowed. This is on par with what
> > > > is there for the existing (hopefully soon deprecated) bonding interface.
> > > >
> > > > We perma-pin these execlists contexts to align with GuC implementation.
> > > >
> > > > v2:
> > > > (John Harrison)
> > > > - Drop siblings array as num_siblings must be 1
> > > >
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
> > > > drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> > > > .../drm/i915/gt/intel_execlists_submission.c | 44 ++++++++++++++++++-
> > > > drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
> > > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> > > > 5 files changed, 52 insertions(+), 10 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > index fb33d0322960..35e87a7d0ea9 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> > > > struct intel_engine_cs **siblings = NULL;
> > > > intel_engine_mask_t prev_mask;
> > > > - /* FIXME: This is NIY for execlists */
> > > > - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> > > > - return -ENODEV;
> > > > -
> > > > if (get_user(slot, &ext->engine_index))
> > > > return -EFAULT;
> > > > @@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> > > > if (get_user(num_siblings, &ext->num_siblings))
> > > > return -EFAULT;
> > > > + if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
> > > > + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> > > > + num_siblings);
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > if (slot >= set->num_engines) {
> > > > drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> > > > slot, set->num_engines);
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> > > > index 5634d14052bc..1bec92e1d8e6 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > > > @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
> > > > __i915_active_acquire(&ce->active);
> > > > - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> > > > + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> > > > + intel_context_is_parallel(ce))
> > > > return 0;
> > > > /* Preallocate tracking nodes */
> > > > @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> > > > * Callers responsibility to validate that this function is used
> > > > * correctly but we use GEM_BUG_ON here ensure that they do.
> > > > */
> > > > - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> > > > GEM_BUG_ON(intel_context_is_pinned(parent));
> > > > GEM_BUG_ON(intel_context_is_child(parent));
> > > > GEM_BUG_ON(intel_context_is_pinned(child));
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > > index bedb80057046..2865b422300d 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > > @@ -927,8 +927,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
> > > > static bool ctx_single_port_submission(const struct intel_context *ce)
> > > > {
> > > > - return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
> > > > - intel_context_force_single_submission(ce));
> > > > + return intel_context_force_single_submission(ce);
> > > I think this is actually going to break GVT.
> > >
> > > Not so much this change here but the whole use of single submission outside
> > > of GVT. It looks like the GVT driver overloads the single submission flag to
> > > tag requests that it owns. If we start using that flag elsewhere when GVT is
> > > active, I think that will cause much confusion within the GVT code.
> > >
> > > The correct fix would be to create a new flag just for GVT usage alongside
> > > the single submission one. GVT would then set both but only check for its
> > > own private flag. The parallel code would obviously only set the existing
> > > single submission flag.
> > >
> > Ok, see below.
> >
> > > > }
> > > > static bool can_merge_ctx(const struct intel_context *prev,
> > > > @@ -2598,6 +2597,46 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> > > > current->comm);
> > > > }
> > > > +static struct intel_context *
> > > > +execlists_create_parallel(struct intel_engine_cs **engines,
> > > > + unsigned int num_siblings,
> > > > + unsigned int width)
> > > > +{
> > > > + struct intel_context *parent = NULL, *ce, *err;
> > > > + int i;
> > > > +
> > > > + GEM_BUG_ON(num_siblings != 1);
> > > > +
> > > > + for (i = 0; i < width; ++i) {
> > > > + ce = intel_context_create(engines[i]);
> > > > + if (!ce) {
> > > > + err = ERR_PTR(-ENOMEM);
> > > > + goto unwind;
> > > > + }
> > > > +
> > > > + if (i == 0)
> > > > + parent = ce;
> > > > + else
> > > > + intel_context_bind_parent_child(parent, ce);
> > > > + }
> > > > +
> > > > + parent->parallel.fence_context = dma_fence_context_alloc(1);
> > > > +
> > > > + intel_context_set_nopreempt(parent);
> > > > + intel_context_set_single_submission(parent);
> > > Can you explain the need for setting single submission?
> > >
> > I think I can actually pull this out. This was needed when I tried to
> > truely implement a guarante that all the parallel requests would be
> > running simultaneously. Couldn't ever to get that working because of the
> > mess that is the execlists scheduler - a simple wait at the head of
> > queue until everyone joined just blew up for whatever reason. I don't
> > believe this servers a purpose anymore, so I'll just drop it.
> >
> > Matt
> Is that not going to be a problem? I thought concurrent execution was a
> fundamental requirement?
>
I don't think so. See the commit message. This implmementation is on par
with the bonding interface - there is no guarantee whatsoever that with
the bonding interface bonded requests actually run at the same time. It
says hopefully these submissions run together. That's what I do in this
patch too for execlists, hence the 'weak' clause in the commit message.
Matt
> John.
>
> >
> > > John.
> > >
> > > > + for_each_child(parent, ce) {
> > > > + intel_context_set_nopreempt(ce);
> > > > + intel_context_set_single_submission(ce);
> > > > + }
> > > > +
> > > > + return parent;
> > > > +
> > > > +unwind:
> > > > + if (parent)
> > > > + intel_context_put(parent);
> > > > + return err;
> > > > +}
> > > > +
> > > > static const struct intel_context_ops execlists_context_ops = {
> > > > .flags = COPS_HAS_INFLIGHT,
> > > > @@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
> > > > .reset = lrc_reset,
> > > > .destroy = lrc_destroy,
> > > > + .create_parallel = execlists_create_parallel,
> > > > .create_virtual = execlists_create_virtual,
> > > > };
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > index 56156cf18c41..70f4b309522d 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > @@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
> > > > void lrc_unpin(struct intel_context *ce)
> > > > {
> > > > + if (unlikely(ce->parallel.last_rq))
> > > > + i915_request_put(ce->parallel.last_rq);
> > > > check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> > > > ce->engine);
> > > > }
> > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > index 1341752dc70e..ddc9a97fcc8f 100644
> > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > @@ -2961,8 +2961,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> > > > GEM_BUG_ON(!intel_context_is_parent(ce));
> > > > GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
> > > > - if (ce->parallel.last_rq)
> > > > - i915_request_put(ce->parallel.last_rq);
> > > > unpin_guc_id(guc, ce);
> > > > lrc_unpin(ce);
> > > > }
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-10-27 19:17 ` Matthew Brost
@ 2021-10-27 20:04 ` John Harrison
2021-10-27 20:10 ` Matthew Brost
0 siblings, 1 reply; 14+ messages in thread
From: John Harrison @ 2021-10-27 20:04 UTC (permalink / raw)
To: Matthew Brost; +Cc: intel-gfx, dri-devel, tvrtko.ursulin, daniele.ceraolospurio
On 10/27/2021 12:17, Matthew Brost wrote:
> On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
>> On 10/20/2021 14:47, Matthew Brost wrote:
>>> A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
>>> execlists. Doing as little as possible to support this interface for
>>> execlists - basically just passing submit fences between each request
>>> generated and virtual engines are not allowed. This is on par with what
>>> is there for the existing (hopefully soon deprecated) bonding interface.
>>>
>>> We perma-pin these execlists contexts to align with GuC implementation.
>>>
>>> v2:
>>> (John Harrison)
>>> - Drop siblings array as num_siblings must be 1
>>>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
>>> drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
>>> .../drm/i915/gt/intel_execlists_submission.c | 44 ++++++++++++++++++-
>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
>>> 5 files changed, 52 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>>> index fb33d0322960..35e87a7d0ea9 100644
>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>>> @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
>>> struct intel_engine_cs **siblings = NULL;
>>> intel_engine_mask_t prev_mask;
>>> - /* FIXME: This is NIY for execlists */
>>> - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
>>> - return -ENODEV;
>>> -
>>> if (get_user(slot, &ext->engine_index))
>>> return -EFAULT;
>>> @@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
>>> if (get_user(num_siblings, &ext->num_siblings))
>>> return -EFAULT;
>>> + if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
>>> + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
>>> + num_siblings);
>>> + return -EINVAL;
>>> + }
>>> +
>>> if (slot >= set->num_engines) {
>>> drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
>>> slot, set->num_engines);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
>>> index 5634d14052bc..1bec92e1d8e6 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_context.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
>>> @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
>>> __i915_active_acquire(&ce->active);
>>> - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
>>> + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
>>> + intel_context_is_parallel(ce))
>>> return 0;
>>> /* Preallocate tracking nodes */
>>> @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
>>> * Callers responsibility to validate that this function is used
>>> * correctly but we use GEM_BUG_ON here ensure that they do.
>>> */
>>> - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
>>> GEM_BUG_ON(intel_context_is_pinned(parent));
>>> GEM_BUG_ON(intel_context_is_child(parent));
>>> GEM_BUG_ON(intel_context_is_pinned(child));
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> index bedb80057046..2865b422300d 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> @@ -927,8 +927,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
>>> static bool ctx_single_port_submission(const struct intel_context *ce)
>>> {
>>> - return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
>>> - intel_context_force_single_submission(ce));
>>> + return intel_context_force_single_submission(ce);
>> I think this is actually going to break GVT.
>>
>> Not so much this change here but the whole use of single submission outside
>> of GVT. It looks like the GVT driver overloads the single submission flag to
>> tag requests that it owns. If we start using that flag elsewhere when GVT is
>> active, I think that will cause much confusion within the GVT code.
>>
>> The correct fix would be to create a new flag just for GVT usage alongside
>> the single submission one. GVT would then set both but only check for its
>> own private flag. The parallel code would obviously only set the existing
>> single submission flag.
>>
> Ok, see below.
>
>>> }
>>> static bool can_merge_ctx(const struct intel_context *prev,
>>> @@ -2598,6 +2597,46 @@ static void execlists_context_cancel_request(struct intel_context *ce,
>>> current->comm);
>>> }
>>> +static struct intel_context *
>>> +execlists_create_parallel(struct intel_engine_cs **engines,
>>> + unsigned int num_siblings,
>>> + unsigned int width)
>>> +{
>>> + struct intel_context *parent = NULL, *ce, *err;
>>> + int i;
>>> +
>>> + GEM_BUG_ON(num_siblings != 1);
>>> +
>>> + for (i = 0; i < width; ++i) {
>>> + ce = intel_context_create(engines[i]);
>>> + if (!ce) {
>>> + err = ERR_PTR(-ENOMEM);
>>> + goto unwind;
>>> + }
>>> +
>>> + if (i == 0)
>>> + parent = ce;
>>> + else
>>> + intel_context_bind_parent_child(parent, ce);
>>> + }
>>> +
>>> + parent->parallel.fence_context = dma_fence_context_alloc(1);
>>> +
>>> + intel_context_set_nopreempt(parent);
>>> + intel_context_set_single_submission(parent);
>> Can you explain the need for setting single submission?
>>
> I think I can actually pull this out. This was needed when I tried to
> truely implement a guarante that all the parallel requests would be
> running simultaneously. Couldn't ever to get that working because of the
> mess that is the execlists scheduler - a simple wait at the head of
> queue until everyone joined just blew up for whatever reason. I don't
> believe this servers a purpose anymore, so I'll just drop it.
>
> Matt
Is that not going to be a problem? I thought concurrent execution was a
fundamental requirement?
John.
>
>> John.
>>
>>> + for_each_child(parent, ce) {
>>> + intel_context_set_nopreempt(ce);
>>> + intel_context_set_single_submission(ce);
>>> + }
>>> +
>>> + return parent;
>>> +
>>> +unwind:
>>> + if (parent)
>>> + intel_context_put(parent);
>>> + return err;
>>> +}
>>> +
>>> static const struct intel_context_ops execlists_context_ops = {
>>> .flags = COPS_HAS_INFLIGHT,
>>> @@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
>>> .reset = lrc_reset,
>>> .destroy = lrc_destroy,
>>> + .create_parallel = execlists_create_parallel,
>>> .create_virtual = execlists_create_virtual,
>>> };
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> index 56156cf18c41..70f4b309522d 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> @@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
>>> void lrc_unpin(struct intel_context *ce)
>>> {
>>> + if (unlikely(ce->parallel.last_rq))
>>> + i915_request_put(ce->parallel.last_rq);
>>> check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
>>> ce->engine);
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> index 1341752dc70e..ddc9a97fcc8f 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> @@ -2961,8 +2961,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
>>> GEM_BUG_ON(!intel_context_is_parent(ce));
>>> GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
>>> - if (ce->parallel.last_rq)
>>> - i915_request_put(ce->parallel.last_rq);
>>> unpin_guc_id(guc, ce);
>>> lrc_unpin(ce);
>>> }
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-10-26 21:58 ` John Harrison
@ 2021-10-27 19:17 ` Matthew Brost
2021-10-27 20:04 ` John Harrison
0 siblings, 1 reply; 14+ messages in thread
From: Matthew Brost @ 2021-10-27 19:17 UTC (permalink / raw)
To: John Harrison; +Cc: intel-gfx, dri-devel, tvrtko.ursulin, daniele.ceraolospurio
On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> On 10/20/2021 14:47, Matthew Brost wrote:
> > A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> > execlists. Doing as little as possible to support this interface for
> > execlists - basically just passing submit fences between each request
> > generated and virtual engines are not allowed. This is on par with what
> > is there for the existing (hopefully soon deprecated) bonding interface.
> >
> > We perma-pin these execlists contexts to align with GuC implementation.
> >
> > v2:
> > (John Harrison)
> > - Drop siblings array as num_siblings must be 1
> >
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
> > drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> > .../drm/i915/gt/intel_execlists_submission.c | 44 ++++++++++++++++++-
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> > 5 files changed, 52 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index fb33d0322960..35e87a7d0ea9 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> > struct intel_engine_cs **siblings = NULL;
> > intel_engine_mask_t prev_mask;
> > - /* FIXME: This is NIY for execlists */
> > - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> > - return -ENODEV;
> > -
> > if (get_user(slot, &ext->engine_index))
> > return -EFAULT;
> > @@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> > if (get_user(num_siblings, &ext->num_siblings))
> > return -EFAULT;
> > + if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
> > + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> > + num_siblings);
> > + return -EINVAL;
> > + }
> > +
> > if (slot >= set->num_engines) {
> > drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> > slot, set->num_engines);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> > index 5634d14052bc..1bec92e1d8e6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
> > __i915_active_acquire(&ce->active);
> > - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> > + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> > + intel_context_is_parallel(ce))
> > return 0;
> > /* Preallocate tracking nodes */
> > @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> > * Callers responsibility to validate that this function is used
> > * correctly but we use GEM_BUG_ON here ensure that they do.
> > */
> > - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> > GEM_BUG_ON(intel_context_is_pinned(parent));
> > GEM_BUG_ON(intel_context_is_child(parent));
> > GEM_BUG_ON(intel_context_is_pinned(child));
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index bedb80057046..2865b422300d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -927,8 +927,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
> > static bool ctx_single_port_submission(const struct intel_context *ce)
> > {
> > - return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
> > - intel_context_force_single_submission(ce));
> > + return intel_context_force_single_submission(ce);
> I think this is actually going to break GVT.
>
> Not so much this change here but the whole use of single submission outside
> of GVT. It looks like the GVT driver overloads the single submission flag to
> tag requests that it owns. If we start using that flag elsewhere when GVT is
> active, I think that will cause much confusion within the GVT code.
>
> The correct fix would be to create a new flag just for GVT usage alongside
> the single submission one. GVT would then set both but only check for its
> own private flag. The parallel code would obviously only set the existing
> single submission flag.
>
Ok, see below.
>
> > }
> > static bool can_merge_ctx(const struct intel_context *prev,
> > @@ -2598,6 +2597,46 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> > current->comm);
> > }
> > +static struct intel_context *
> > +execlists_create_parallel(struct intel_engine_cs **engines,
> > + unsigned int num_siblings,
> > + unsigned int width)
> > +{
> > + struct intel_context *parent = NULL, *ce, *err;
> > + int i;
> > +
> > + GEM_BUG_ON(num_siblings != 1);
> > +
> > + for (i = 0; i < width; ++i) {
> > + ce = intel_context_create(engines[i]);
> > + if (!ce) {
> > + err = ERR_PTR(-ENOMEM);
> > + goto unwind;
> > + }
> > +
> > + if (i == 0)
> > + parent = ce;
> > + else
> > + intel_context_bind_parent_child(parent, ce);
> > + }
> > +
> > + parent->parallel.fence_context = dma_fence_context_alloc(1);
> > +
> > + intel_context_set_nopreempt(parent);
> > + intel_context_set_single_submission(parent);
> Can you explain the need for setting single submission?
>
I think I can actually pull this out. This was needed when I tried to
truely implement a guarante that all the parallel requests would be
running simultaneously. Couldn't ever to get that working because of the
mess that is the execlists scheduler - a simple wait at the head of
queue until everyone joined just blew up for whatever reason. I don't
believe this servers a purpose anymore, so I'll just drop it.
Matt
> John.
>
> > + for_each_child(parent, ce) {
> > + intel_context_set_nopreempt(ce);
> > + intel_context_set_single_submission(ce);
> > + }
> > +
> > + return parent;
> > +
> > +unwind:
> > + if (parent)
> > + intel_context_put(parent);
> > + return err;
> > +}
> > +
> > static const struct intel_context_ops execlists_context_ops = {
> > .flags = COPS_HAS_INFLIGHT,
> > @@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
> > .reset = lrc_reset,
> > .destroy = lrc_destroy,
> > + .create_parallel = execlists_create_parallel,
> > .create_virtual = execlists_create_virtual,
> > };
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 56156cf18c41..70f4b309522d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
> > void lrc_unpin(struct intel_context *ce)
> > {
> > + if (unlikely(ce->parallel.last_rq))
> > + i915_request_put(ce->parallel.last_rq);
> > check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> > ce->engine);
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 1341752dc70e..ddc9a97fcc8f 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -2961,8 +2961,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> > GEM_BUG_ON(!intel_context_is_parent(ce));
> > GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
> > - if (ce->parallel.last_rq)
> > - i915_request_put(ce->parallel.last_rq);
> > unpin_guc_id(guc, ce);
> > lrc_unpin(ce);
> > }
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
2021-10-20 21:47 Matthew Brost
@ 2021-10-26 21:58 ` John Harrison
2021-10-27 19:17 ` Matthew Brost
0 siblings, 1 reply; 14+ messages in thread
From: John Harrison @ 2021-10-26 21:58 UTC (permalink / raw)
To: Matthew Brost, intel-gfx, dri-devel; +Cc: tvrtko.ursulin, daniele.ceraolospurio
On 10/20/2021 14:47, Matthew Brost wrote:
> A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
> execlists. Doing as little as possible to support this interface for
> execlists - basically just passing submit fences between each request
> generated and virtual engines are not allowed. This is on par with what
> is there for the existing (hopefully soon deprecated) bonding interface.
>
> We perma-pin these execlists contexts to align with GuC implementation.
>
> v2:
> (John Harrison)
> - Drop siblings array as num_siblings must be 1
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
> drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> .../drm/i915/gt/intel_execlists_submission.c | 44 ++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> 5 files changed, 52 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index fb33d0322960..35e87a7d0ea9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> struct intel_engine_cs **siblings = NULL;
> intel_engine_mask_t prev_mask;
>
> - /* FIXME: This is NIY for execlists */
> - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> - return -ENODEV;
> -
> if (get_user(slot, &ext->engine_index))
> return -EFAULT;
>
> @@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
> if (get_user(num_siblings, &ext->num_siblings))
> return -EFAULT;
>
> + if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
> + drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
> + num_siblings);
> + return -EINVAL;
> + }
> +
> if (slot >= set->num_engines) {
> drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
> slot, set->num_engines);
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 5634d14052bc..1bec92e1d8e6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
>
> __i915_active_acquire(&ce->active);
>
> - if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
> + if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
> + intel_context_is_parallel(ce))
> return 0;
>
> /* Preallocate tracking nodes */
> @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> * Callers responsibility to validate that this function is used
> * correctly but we use GEM_BUG_ON here ensure that they do.
> */
> - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> GEM_BUG_ON(intel_context_is_pinned(parent));
> GEM_BUG_ON(intel_context_is_child(parent));
> GEM_BUG_ON(intel_context_is_pinned(child));
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index bedb80057046..2865b422300d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -927,8 +927,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
>
> static bool ctx_single_port_submission(const struct intel_context *ce)
> {
> - return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
> - intel_context_force_single_submission(ce));
> + return intel_context_force_single_submission(ce);
I think this is actually going to break GVT.
Not so much this change here but the whole use of single submission
outside of GVT. It looks like the GVT driver overloads the single
submission flag to tag requests that it owns. If we start using that
flag elsewhere when GVT is active, I think that will cause much
confusion within the GVT code.
The correct fix would be to create a new flag just for GVT usage
alongside the single submission one. GVT would then set both but only
check for its own private flag. The parallel code would obviously only
set the existing single submission flag.
> }
>
> static bool can_merge_ctx(const struct intel_context *prev,
> @@ -2598,6 +2597,46 @@ static void execlists_context_cancel_request(struct intel_context *ce,
> current->comm);
> }
>
> +static struct intel_context *
> +execlists_create_parallel(struct intel_engine_cs **engines,
> + unsigned int num_siblings,
> + unsigned int width)
> +{
> + struct intel_context *parent = NULL, *ce, *err;
> + int i;
> +
> + GEM_BUG_ON(num_siblings != 1);
> +
> + for (i = 0; i < width; ++i) {
> + ce = intel_context_create(engines[i]);
> + if (!ce) {
> + err = ERR_PTR(-ENOMEM);
> + goto unwind;
> + }
> +
> + if (i == 0)
> + parent = ce;
> + else
> + intel_context_bind_parent_child(parent, ce);
> + }
> +
> + parent->parallel.fence_context = dma_fence_context_alloc(1);
> +
> + intel_context_set_nopreempt(parent);
> + intel_context_set_single_submission(parent);
Can you explain the need for setting single submission?
John.
> + for_each_child(parent, ce) {
> + intel_context_set_nopreempt(ce);
> + intel_context_set_single_submission(ce);
> + }
> +
> + return parent;
> +
> +unwind:
> + if (parent)
> + intel_context_put(parent);
> + return err;
> +}
> +
> static const struct intel_context_ops execlists_context_ops = {
> .flags = COPS_HAS_INFLIGHT,
>
> @@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
> .reset = lrc_reset,
> .destroy = lrc_destroy,
>
> + .create_parallel = execlists_create_parallel,
> .create_virtual = execlists_create_virtual,
> };
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 56156cf18c41..70f4b309522d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
>
> void lrc_unpin(struct intel_context *ce)
> {
> + if (unlikely(ce->parallel.last_rq))
> + i915_request_put(ce->parallel.last_rq);
> check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
> ce->engine);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 1341752dc70e..ddc9a97fcc8f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -2961,8 +2961,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
> GEM_BUG_ON(!intel_context_is_parent(ce));
> GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
>
> - if (ce->parallel.last_rq)
> - i915_request_put(ce->parallel.last_rq);
> unpin_guc_id(guc, ce);
> lrc_unpin(ce);
> }
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
@ 2021-10-20 21:47 Matthew Brost
2021-10-26 21:58 ` John Harrison
0 siblings, 1 reply; 14+ messages in thread
From: Matthew Brost @ 2021-10-20 21:47 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: tvrtko.ursulin, daniele.ceraolospurio, john.c.harrison
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for the existing (hopefully soon deprecated) bonding interface.
We perma-pin these execlists contexts to align with GuC implementation.
v2:
(John Harrison)
- Drop siblings array as num_siblings must be 1
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 44 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
5 files changed, 52 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fb33d0322960..35e87a7d0ea9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
struct intel_engine_cs **siblings = NULL;
intel_engine_mask_t prev_mask;
- /* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
- return -ENODEV;
-
if (get_user(slot, &ext->engine_index))
return -EFAULT;
@@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
if (get_user(num_siblings, &ext->num_siblings))
return -EFAULT;
+ if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
+ drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC mode\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
if (slot >= set->num_engines) {
drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
slot, set->num_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 5634d14052bc..1bec92e1d8e6 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context *ce)
__i915_active_acquire(&ce->active);
- if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
+ intel_context_is_parallel(ce))
return 0;
/* Preallocate tracking nodes */
@@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context *parent,
* Callers responsibility to validate that this function is used
* correctly but we use GEM_BUG_ON here ensure that they do.
*/
- GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
GEM_BUG_ON(intel_context_is_pinned(parent));
GEM_BUG_ON(intel_context_is_child(parent));
GEM_BUG_ON(intel_context_is_pinned(child));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index bedb80057046..2865b422300d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -927,8 +927,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
static bool ctx_single_port_submission(const struct intel_context *ce)
{
- return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
- intel_context_force_single_submission(ce));
+ return intel_context_force_single_submission(ce);
}
static bool can_merge_ctx(const struct intel_context *prev,
@@ -2598,6 +2597,46 @@ static void execlists_context_cancel_request(struct intel_context *ce,
current->comm);
}
+static struct intel_context *
+execlists_create_parallel(struct intel_engine_cs **engines,
+ unsigned int num_siblings,
+ unsigned int width)
+{
+ struct intel_context *parent = NULL, *ce, *err;
+ int i;
+
+ GEM_BUG_ON(num_siblings != 1);
+
+ for (i = 0; i < width; ++i) {
+ ce = intel_context_create(engines[i]);
+ if (!ce) {
+ err = ERR_PTR(-ENOMEM);
+ goto unwind;
+ }
+
+ if (i == 0)
+ parent = ce;
+ else
+ intel_context_bind_parent_child(parent, ce);
+ }
+
+ parent->parallel.fence_context = dma_fence_context_alloc(1);
+
+ intel_context_set_nopreempt(parent);
+ intel_context_set_single_submission(parent);
+ for_each_child(parent, ce) {
+ intel_context_set_nopreempt(ce);
+ intel_context_set_single_submission(ce);
+ }
+
+ return parent;
+
+unwind:
+ if (parent)
+ intel_context_put(parent);
+ return err;
+}
+
static const struct intel_context_ops execlists_context_ops = {
.flags = COPS_HAS_INFLIGHT,
@@ -2616,6 +2655,7 @@ static const struct intel_context_ops execlists_context_ops = {
.reset = lrc_reset,
.destroy = lrc_destroy,
+ .create_parallel = execlists_create_parallel,
.create_virtual = execlists_create_virtual,
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 56156cf18c41..70f4b309522d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1065,6 +1065,8 @@ lrc_pin(struct intel_context *ce,
void lrc_unpin(struct intel_context *ce)
{
+ if (unlikely(ce->parallel.last_rq))
+ i915_request_put(ce->parallel.last_rq);
check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
ce->engine);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1341752dc70e..ddc9a97fcc8f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2961,8 +2961,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
GEM_BUG_ON(!intel_context_is_parent(ce));
GEM_BUG_ON(!intel_engine_is_virtual(ce->engine));
- if (ce->parallel.last_rq)
- i915_request_put(ce->parallel.last_rq);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-12-23 2:29 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-22 22:35 [PATCH] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-12-22 22:35 ` [Intel-gfx] " Matthew Brost
2021-12-22 23:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Weak parallel submission support for execlists (rev3) Patchwork
2021-12-23 0:54 ` [PATCH] drm/i915/execlists: Weak parallel submission support for execlists John Harrison
2021-12-23 0:54 ` [Intel-gfx] " John Harrison
2021-12-23 2:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Weak parallel submission support for execlists (rev3) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-11-11 21:20 [PATCH] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-12-06 20:01 ` John Harrison
2021-12-22 22:21 ` Matthew Brost
2021-10-20 21:47 Matthew Brost
2021-10-26 21:58 ` John Harrison
2021-10-27 19:17 ` Matthew Brost
2021-10-27 20:04 ` John Harrison
2021-10-27 20:10 ` Matthew Brost
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