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* [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
@ 2018-02-06  0:02 Jackie Li
  2018-02-06  0:02 ` [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
                   ` (6 more replies)
  0 siblings, 7 replies; 26+ messages in thread
From: Jackie Li @ 2018-02-06  0:02 UTC (permalink / raw)
  To: intel-gfx

intel_guc_reg.h should only include definition for GuC registers and
related register bits. Non-register related GuC WOPCM macro definitions
should not be defined in intel_guc_reg.h

This patch creates a better file structure by moving non-register related
GuC WOPCM macro definitions into a new header intel_guc_wopcm.h and moving
GuC WOPCM related functions to a new source file intel_guc_wopcm.c as
future patches will increase the complexity of determining the GuC WOPCM
offset and size.

v8:
 - Fixed naming, coding style issues and typo in commit message (Sagar)
 - Updated commit message to explain why we need create new file for GuC
   WOPCM related code (Chris)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v7)
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/Makefile          |  1 +
 drivers/gpu/drm/i915/intel_guc.c       | 11 --------
 drivers/gpu/drm/i915/intel_guc.h       |  2 +-
 drivers/gpu/drm/i915/intel_guc_reg.h   |  4 ---
 drivers/gpu/drm/i915/intel_guc_wopcm.c | 46 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_guc_wopcm.h | 39 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.c        |  2 +-
 drivers/gpu/drm/i915/intel_uc_fw.c     |  2 +-
 8 files changed, 89 insertions(+), 18 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3bddd8a..1dc9988 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -88,6 +88,7 @@ i915-y += intel_uc.o \
 	  intel_guc_fw.o \
 	  intel_guc_log.o \
 	  intel_guc_submission.o \
+	  intel_guc_wopcm.o \
 	  intel_huc.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 21140cc..9f45e6d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -509,14 +509,3 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 	i915_gem_object_put(obj);
 	return vma;
 }
-
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
-{
-	u32 wopcm_size = GUC_WOPCM_TOP;
-
-	/* On BXT, the top of WOPCM is reserved for RC6 context */
-	if (IS_GEN9_LP(dev_priv))
-		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
-
-	return wopcm_size;
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..9e0a97e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -31,6 +31,7 @@
 #include "intel_guc_ct.h"
 #include "intel_guc_log.h"
 #include "intel_guc_reg.h"
+#include "intel_guc_wopcm.h"
 #include "intel_uc_fw.h"
 #include "i915_vma.h"
 
@@ -130,6 +131,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
 int intel_guc_suspend(struct drm_i915_private *dev_priv);
 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 19a9247..1f52fb8 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -68,7 +68,6 @@
 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
 #define   HUC_LOADING_AGENT_VCR		  (0<<1)
 #define   HUC_LOADING_AGENT_GUC		  (1<<1)
-#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
 #define HUC_STATUS2             _MMIO(0xD3B0)
@@ -76,9 +75,6 @@
 
 /* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
-#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
 
 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
 #define GUC_GGTT_TOP			0xFEE00000
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
new file mode 100644
index 0000000..73be9af
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_guc_wopcm.h"
+#include "i915_drv.h"
+
+/*
+ * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
+ * @guc: intel guc.
+ *
+ * Get the platform specific GuC WOPCM size.
+ *
+ * Return: size of the GuC WOPCM.
+ */
+u32 intel_guc_wopcm_size(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+	u32 size = GUC_WOPCM_TOP;
+
+	/* On BXT, the top of WOPCM is reserved for RC6 context */
+	if (IS_GEN9_LP(i915))
+		size -= BXT_GUC_WOPCM_RC6_RESERVED;
+
+	return size;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
new file mode 100644
index 0000000..53de931
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _INTEL_GUC_WOPCM_H_
+#define _INTEL_GUC_WOPCM_H_
+
+#include <linux/types.h>
+
+struct intel_guc;
+
+#define GUC_WOPCM_OFFSET_VALUE		0x80000	/* 512KB */
+/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
+#define GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
+#define BXT_GUC_WOPCM_RC6_RESERVED	(0x10 << 12)	/* 64KB  */
+
+u32 intel_guc_wopcm_size(struct intel_guc *guc);
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6..1b2831b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -340,7 +340,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	gen9_reset_guc_interrupts(dev_priv);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
 		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
 
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 784eff9..24945cf 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -97,7 +97,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 
 	/* Header and uCode will be loaded to WOPCM */
 	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > intel_guc_wopcm_size(dev_priv)) {
+	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
 		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
 			 intel_uc_fw_type_repr(uc_fw->type));
 		err = -E2BIG;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
@ 2018-02-06  0:02 ` Jackie Li
  2018-02-06  5:21   ` Sagar Arun Kamble
  2018-02-06 10:25   ` Chris Wilson
  2018-02-06  0:02 ` [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size Jackie Li
                   ` (5 subsequent siblings)
  6 siblings, 2 replies; 26+ messages in thread
From: Jackie Li @ 2018-02-06  0:02 UTC (permalink / raw)
  To: intel-gfx

GuC related exported functions should start with "intel_guc_" prefix and
pass intel_guc as the first parameter since its guc related. Current
guc_ggtt_offset() failed to follow this code convention and this is a
problem for future patches that needs to access intel_guc data to verify
the GGTT offset against the GuC WOPCM top.

This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
the related code to pass intel_guc pointer to this function call, so that
we can have a unified coding style for GuC code and also enable the future
patches to get GuC related data from intel_guc to do the offset
verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
intel_guc_regs.h to intel_guc.h since it is not GuC register related
definition.

v8:
 - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
 - Updated commit message to explain to reason and motivation to add
   intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c            | 12 +++++++-----
 drivers/gpu/drm/i915/intel_guc.h            | 14 ++++++++++++--
 drivers/gpu/drm/i915/intel_guc_ads.c        | 25 +++++++++++++------------
 drivers/gpu/drm/i915/intel_guc_ct.c         |  5 +++--
 drivers/gpu/drm/i915/intel_guc_fw.c         |  2 +-
 drivers/gpu/drm/i915/intel_guc_log.c        |  2 +-
 drivers/gpu/drm/i915/intel_guc_reg.h        |  3 ---
 drivers/gpu/drm/i915/intel_guc_submission.c | 10 +++++-----
 drivers/gpu/drm/i915/intel_huc.c            |  6 ++++--
 9 files changed, 46 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 9f45e6d..d9bc2a9 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -269,8 +269,10 @@ void intel_guc_init_params(struct intel_guc *guc)
 
 	/* If GuC submission is enabled, set up additional parameters here */
 	if (USES_GUC_SUBMISSION(dev_priv)) {
-		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
-		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
+		u32 ads = intel_guc_ggtt_offset(guc,
+						guc->ads_vma) >> PAGE_SHIFT;
+		u32 pgs = intel_guc_ggtt_offset(guc,
+						dev_priv->guc.stage_desc_pool);
 		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
 
 		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
@@ -418,7 +420,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
 	data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 	/* any value greater than GUC_POWER_D0 */
 	data[1] = GUC_POWER_D1;
-	data[2] = guc_ggtt_offset(guc->shared_data);
+	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -441,7 +443,7 @@ int intel_guc_reset_engine(struct intel_guc *guc,
 	data[3] = 0;
 	data[4] = 0;
 	data[5] = guc->execbuf_client->stage_id;
-	data[6] = guc_ggtt_offset(guc->shared_data);
+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
@@ -463,7 +465,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
 
 	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 	data[1] = GUC_POWER_D0;
-	data[2] = guc_ggtt_offset(guc->shared_data);
+	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e0a97e..50be6de 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -101,13 +101,23 @@ static inline void intel_guc_notify(struct intel_guc *guc)
 	guc->notify(guc);
 }
 
-/*
+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
+#define GUC_GGTT_TOP	0xFEE00000
+
+/**
+ * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
+ * @guc: intel guc.
+ * @vma: i915 graphics virtual memory area.
+ *
  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ *
+ * Return: GGTT offset that meets the GuC gfx address requirement.
  */
-static inline u32 guc_ggtt_offset(struct i915_vma *vma)
+static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
+					struct i915_vma *vma)
 {
 	u32 offset = i915_ggtt_offset(vma);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
index ac62753..7215594 100644
--- a/drivers/gpu/drm/i915/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/intel_guc_ads.c
@@ -113,17 +113,6 @@ int intel_guc_ads_create(struct intel_guc *guc)
 		blob->reg_state.white_list[engine->guc_id].count = 0;
 	}
 
-	/*
-	 * The GuC requires a "Golden Context" when it reinitialises
-	 * engines after a reset. Here we use the Render ring default
-	 * context, which must already exist and be pinned in the GGTT,
-	 * so its address won't change after we've told the GuC where
-	 * to find it. Note that we have to skip our header (1 page),
-	 * because our GuC shared data is there.
-	 */
-	blob->ads.golden_context_lrca =
-		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
-		skipped_offset;
 
 	/*
 	 * The GuC expects us to exclude the portion of the context image that
@@ -135,11 +124,23 @@ int intel_guc_ads_create(struct intel_guc *guc)
 		blob->ads.eng_state_size[engine->guc_id] =
 			engine->context_size - skipped_size;
 
-	base = guc_ggtt_offset(vma);
+	base = intel_guc_ggtt_offset(guc, vma);
 	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
 	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
 	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
 
+	/*
+	 * The GuC requires a "Golden Context" when it reinitialises
+	 * engines after a reset. Here we use the Render ring default
+	 * context, which must already exist and be pinned in the GGTT,
+	 * so its address won't change after we've told the GuC where
+	 * to find it. Note that we have to skip our header (1 page),
+	 * because our GuC shared data is there.
+	 */
+	vma = dev_priv->kernel_context->engine[RCS].state;
+	blob->ads.golden_context_lrca = intel_guc_ggtt_offset(guc, vma) +
+		skipped_offset;
+
 	kunmap(page);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index 24ad557..0a0d3d5 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -156,7 +156,8 @@ static int ctch_init(struct intel_guc *guc,
 		err = PTR_ERR(blob);
 		goto err_vma;
 	}
-	DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
+	DRM_DEBUG_DRIVER("CT: vma base=%#x\n",
+			 intel_guc_ggtt_offset(guc, ctch->vma));
 
 	/* store pointers to desc and cmds */
 	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
@@ -202,7 +203,7 @@ static int ctch_open(struct intel_guc *guc,
 	}
 
 	/* vma should be already allocated and map'ed */
-	base = guc_ggtt_offset(ctch->vma);
+	base = intel_guc_ggtt_offset(guc, ctch->vma);
 
 	/* (re)initialize descriptors
 	 * cmds buffers are in the second half of the blob page
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index 3b09329..178d339 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -165,7 +165,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
 	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
 
 	/* Set the source address for the new blob */
-	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
+	offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 7b5074e..eca8725 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -638,7 +638,7 @@ int intel_guc_log_create(struct intel_guc *guc)
 		(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
 		(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
 
-	offset = guc_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
+	offset = intel_guc_ggtt_offset(guc, vma) >> PAGE_SHIFT; /* in pages */
 	guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index 1f52fb8..de4f78b 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -76,9 +76,6 @@
 /* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
 
-/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
-#define GUC_GGTT_TOP			0xFEE00000
-
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 1f3a878..c56e4f4 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -375,8 +375,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 		lrc->context_desc = lower_32_bits(ce->lrc_desc);
 
 		/* The state page is after PPHWSP */
-		lrc->ring_lrca =
-			guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
+		lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
+				 LRC_STATE_PN * PAGE_SIZE;
 
 		/* XXX: In direct submission, the GuC wants the HW context id
 		 * here. In proxy submission, it wants the stage id
@@ -384,7 +384,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 		lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
 				(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
 
-		lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
+		lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
 		lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
 		lrc->ring_next_free_location = lrc->ring_begin;
 		lrc->ring_current_tail_pointer_value = 0;
@@ -400,7 +400,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
 	 * The doorbell, process descriptor, and workqueue are all parts
 	 * of the client object, which the GuC will reference via the GGTT
 	 */
-	gfx_addr = guc_ggtt_offset(client->vma);
+	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
 	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
 				client->doorbell_offset;
 	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
@@ -596,7 +596,7 @@ static void inject_preempt_context(struct work_struct *work)
 	data[3] = engine->guc_id;
 	data[4] = guc->execbuf_client->priority;
 	data[5] = guc->execbuf_client->stage_id;
-	data[6] = guc_ggtt_offset(guc->shared_data);
+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 
 	if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
 		execlists_clear_active(&engine->execlists,
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 8ed0518..aed9c1c 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -137,7 +137,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* Set the source address for the uCode */
-	offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
+	offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
+		 huc_fw->header_offset;
 	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 
@@ -213,7 +214,8 @@ int intel_huc_auth(struct intel_huc *huc)
 	}
 
 	ret = intel_guc_auth_huc(guc,
-				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
+				 intel_guc_ggtt_offset(guc, vma) +
+				 huc->fw.rsa_offset);
 	if (ret) {
 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 		goto out;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
  2018-02-06  0:02 ` [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
@ 2018-02-06  0:02 ` Jackie Li
  2018-02-06  6:20   ` Sagar Arun Kamble
  2018-02-06  0:02 ` [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL Jackie Li
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 26+ messages in thread
From: Jackie Li @ 2018-02-06  0:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: Sujaritha Sundaresan

Hardware may have specific restrictions on GuC WOPCM offset and size. On
Gen9, the value of the GuC WOPCM size register needs to be larger than the
value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
will lead to GuC firmware execution failures. So we need add code to verify
the GuC WOPCM offset and size to avoid any GuC failures. On the other hand,
with current static GuC WOPCM offset and size values (512KB for both offset
and size), the GuC WOPCM size verification will fail on Gen9 even if it can
be fixed by lowering the GuC WOPCM offset by calculating its value based on
HuC firmware size (which is likely less than 200KB on Gen9), so that we can
have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
size check.

This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
to verify the GuC WOPCM size aganist the Gen9 hardware restrictions.
Meanwhile, it provides a common way to calculate GuC WOPCM offset and size
based on GuC and HuC firmware sizes for all GuC/HuC enabled platforms.
Currently, GuC WOPCM offset is calculated based on HuC firmware size +
reserved WOPCM size while GuC WOPCM size is set to total WOPCM size - GuC
WOPCM offset - reserved RC6CTX size. In this case, GuC WOPCM offset will be
updated based on the size of HuC firmware while GuC WOPCM size will be set
to use all the remaining WOPCM space.

v2:
 - Removed intel_wopcm_init (Ville/Sagar/Joonas)
 - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
 - Removed unnecessary function calls (Joonas)
 - Init GuC WOPCM partition as soon as firmware fetching is completed

v3:
 - Fixed indentation issues (Chris)
 - Removed layering violation code (Chris/Michal)
 - Created separat files for GuC wopcm code  (Michal)
 - Used inline function to avoid code duplication (Michal)

v4:
 - Preset the GuC WOPCM top during early GuC init (Chris)
 - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed

v5:
 - Moved GuC DMA WOPCM register updating code into intel_guc_wopcm.c
 - Took care of the locking status before writing to GuC DMA
   Write-Once registers. (Joonas)

v6:
 - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)

v8:
 - Updated comments and fixed naming issues (Sagar/Joonas)
 - Updated commit message to include more description about the hardware
   restriction on GuC WOPCM size (Sagar)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
 drivers/gpu/drm/i915/intel_guc.c        |   5 +-
 drivers/gpu/drm/i915/intel_guc.h        |  12 ++--
 drivers/gpu/drm/i915/intel_guc_wopcm.c  | 116 +++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_guc_wopcm.h  |  66 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_huc.c        |   2 +-
 drivers/gpu/drm/i915/intel_uc.c         |  11 ++-
 drivers/gpu/drm/i915/intel_uc_fw.c      |  11 ++-
 drivers/gpu/drm/i915/intel_uc_fw.h      |  16 +++++
 9 files changed, 213 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 648e753..546404e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -312,12 +312,13 @@ __create_hw_context(struct drm_i915_private *dev_priv,
 	ctx->desc_template =
 		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
 
-	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
+	/*
+	 * GuC requires the ring to be placed above GuC WOPCM top. If GuC is not
 	 * present or not in use we still need a small bias as ring wraparound
 	 * at offset 0 sometimes hangs. No idea why.
 	 */
 	if (USES_GUC(dev_priv))
-		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
+		ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;
 	else
 		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
 
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index d9bc2a9..ecd5da2 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -65,6 +65,7 @@ void intel_guc_init_early(struct intel_guc *guc)
 	intel_guc_fw_init_early(guc);
 	intel_guc_ct_init_early(&guc->ct);
 	intel_guc_log_init_early(guc);
+	intel_guc_wopcm_init_early(&guc->wopcm);
 
 	mutex_init(&guc->send_mutex);
 	guc->send = intel_guc_send_nop;
@@ -478,7 +479,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
  * This is a wrapper to create an object for use with the GuC. In order to
  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
  * both some backing storage and a range inside the Global GTT. We must pin
- * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
+ * it in the GGTT somewhere other than than [0, GuC WOPCM top) because that
  * range is reserved inside GuC.
  *
  * Return:	A i915_vma if successful, otherwise an ERR_PTR.
@@ -499,7 +500,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 		goto err;
 
 	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
-			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->wopcm.top);
 	if (ret) {
 		vma = ERR_PTR(ret);
 		goto err;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 50be6de..06f315e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -49,6 +49,7 @@ struct intel_guc {
 	struct intel_uc_fw fw;
 	struct intel_guc_log log;
 	struct intel_guc_ct ct;
+	struct intel_guc_wopcm wopcm;
 
 	/* Log snapshot if GuC errors during load */
 	struct drm_i915_gem_object *load_err_log;
@@ -109,10 +110,10 @@ static inline void intel_guc_notify(struct intel_guc *guc)
  * @guc: intel guc.
  * @vma: i915 graphics virtual memory area.
  *
- * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
- * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
- * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
- * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ * GuC does not allow any gfx GGTT address that falls into range
+ * [0, GuC WOPCM top), which is reserved for Boot ROM, SRAM and WOPCM.
+ * All gfx objects used by GuC is pinned with PIN_OFFSET_BIAS along with
+ * top of WOPCM.
  *
  * Return: GGTT offset that meets the GuC gfx address requirement.
  */
@@ -121,7 +122,8 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
 	u32 offset = i915_ggtt_offset(vma);
 
-	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
+	GEM_BUG_ON(!guc->wopcm.valid);
+	GEM_BUG_ON(offset < guc->wopcm.top);
 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
 	return offset;
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
index 73be9af..1555e79 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -25,22 +25,116 @@
 #include "intel_guc_wopcm.h"
 #include "i915_drv.h"
 
-/*
- * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
+static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	if (IS_GEN9_LP(i915))
+		return BXT_GUC_WOPCM_RC6_RESERVED;
+
+	return 0;
+}
+
+static inline int gen9_guc_wopcm_size_check(struct drm_i915_private *i915)
+{
+	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
+	u32 guc_wopcm_start;
+	u32 delta;
+
+	/*
+	 * GuC WOPCM size is at least 4 bytes larger than the offset from WOPCM
+	 * base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET) due
+	 * to hardware limitation on Gen9.
+	 */
+	guc_wopcm_start = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
+	if (unlikely(guc_wopcm_start > wopcm->size))
+		return -E2BIG;
+
+	delta = wopcm->size - guc_wopcm_start;
+	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
+		return -E2BIG;
+
+	return 0;
+}
+
+static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	if (IS_GEN9(i915))
+		return gen9_guc_wopcm_size_check(i915);
+
+	return 0;
+}
+
+/**
+ * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
  * @guc: intel guc.
+ * @guc_fw_size: size of GuC firmware.
+ * @huc_fw_size: size of HuC firmware.
  *
- * Get the platform specific GuC WOPCM size.
+ * Calculate the GuC WOPCM offset and size based on GuC and HuC firmware sizes.
+ * This function will to set the GuC WOPCM size to the size of maximum WOPCM
+ * available for GuC. This function will also enforce platform dependent
+ * hardware restrictions on GuC WOPCM offset and size. It will fail the GuC
+ * WOPCM init if any of these checks were failed, so that the following GuC
+ * firmware uploading would be aborted.
  *
- * Return: size of the GuC WOPCM.
+ * Return: 0 on success, non-zero error code on failure.
  */
-u32 intel_guc_wopcm_size(struct intel_guc *guc)
+int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
+			 u32 huc_fw_size)
 {
-	struct drm_i915_private *i915 = guc_to_i915(guc);
-	u32 size = GUC_WOPCM_TOP;
+	u32 reserved = guc_reserved_wopcm_size(guc);
+	u32 offset, size, top;
+	int err;
 
-	/* On BXT, the top of WOPCM is reserved for RC6 context */
-	if (IS_GEN9_LP(i915))
-		size -= BXT_GUC_WOPCM_RC6_RESERVED;
+	if (guc->wopcm.valid)
+		return 0;
+
+	if (!guc_fw_size)
+		return -EINVAL;
+
+	if (reserved >= WOPCM_DEFAULT_SIZE)
+		return -E2BIG;
+
+	offset = huc_fw_size + WOPCM_RESERVED_SIZE;
+	if (offset >= WOPCM_DEFAULT_SIZE)
+		return -E2BIG;
+
+	/* Hardware requires GuC WOPCM offset to be 16K aligned. */
+	offset = ALIGN(offset, GUC_WOPCM_OFFSET_ALIGNMENT);
+	if ((offset + reserved) >= WOPCM_DEFAULT_SIZE)
+		return -E2BIG;
+
+	top = WOPCM_DEFAULT_SIZE - offset;
+	size = top - reserved;
+
+	/* GuC WOPCM size must be multiple of 4K pages */
+	size &= PAGE_MASK;
+
+	/*
+	 * GuC firmware size needs to be less than or equal to the size of the
+	 * available GuC WOPCM (total available GuC WOPCM size - reserved size).
+	 * Need extra 8K stack for GuC firmware.
+	 */
+	reserved = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
+	if ((guc_fw_size + reserved) > size)
+		return -E2BIG;
+
+	guc->wopcm.offset = offset;
+	guc->wopcm.size = size;
+	guc->wopcm.top = top;
+
+	/* Check platform specific restrictions */
+	err = guc_wopcm_check_hw_restrictions(guc);
+	if (err)
+		return err;
+
+	guc->wopcm.valid = 1;
+
+	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
+			 offset >> 10, size >> 10, top >> 10);
 
-	return size;
+	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
index 53de931..28e4103 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -29,11 +29,67 @@
 
 struct intel_guc;
 
-#define GUC_WOPCM_OFFSET_VALUE		0x80000	/* 512KB */
-/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
-#define BXT_GUC_WOPCM_RC6_RESERVED	(0x10 << 12)	/* 64KB  */
+/* Default WOPCM size 1MB. */
+#define WOPCM_DEFAULT_SIZE		(0x1 << 20)
+/* The initial 16KB WOPCM is reserved. */
+#define WOPCM_RESERVED_SIZE		(0x4000)
 
-u32 intel_guc_wopcm_size(struct intel_guc *guc);
+/* GUC WOPCM offset needs to be 16KB aligned. */
+#define GUC_WOPCM_OFFSET_ALIGNMENT	(0x4000)
+/* 16KB reserved at the beginning of GuC WOPCM. */
+#define GUC_WOPCM_RESERVED		(0x4000)
+/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
+#define GUC_WOPCM_STACK_RESERVED	(0x2000)
+/* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
+#define BXT_GUC_WOPCM_RC6_RESERVED	(0x6000)
+
+#define GEN9_GUC_WOPCM_DELTA		4
+/**
+ * GuC WOPCM starts at 144KB (GUC_WOPCM_RESERVED + 128KB reserved for GuC
+ * firmware loading) from GuC WOPCM offset on BXT.
+ */
+#define GEN9_GUC_WOPCM_OFFSET		(0x24000)
+
+/**
+ * intel_guc_wopcm - GuC WOPCM related settings.
+ * @offset: GuC WOPCM offset from the WOPCM base.
+ * @size: size of GuC WOPCM for GuC firmware.
+ * @top: start of the non-GuC WOPCM memory.
+ * @valid: whether this structure contains valid (1-valid, 0-invalid) info.
+ *
+ * We simply use this structure to track the GuC use of WOPCM. The layout of
+ * WOPCM would be defined by writing to GuC WOPCM offset and size registers as
+ * shown below.
+ *
+ * +-----------+<-- top
+ * |###########|
+ * +-----------+<-- size (GuC_WOPCM_SIZE register)
+ * | GuC WOPCM |
+ * +-----------+<-- offset (DMA_GUC_WOPCM_OFFSET register)
+ * |###########|
+ * +-----------+<-- WOPCM base
+ */
+struct intel_guc_wopcm {
+	u32 offset;
+	u32 size;
+	u32 top;
+	u32 valid;
+};
+
+/**
+ * intel_guc_wopcm_init_early() - Early initialization of the GuC WOPCM.
+ * @wopcm: GuC WOPCM.
+ *
+ * Setup the GuC WOPCM top to the top of the overall WOPCM. This will guarantee
+ * that the allocation of the GuC accessible objects won't fall into WOPCM when
+ * GuC partition isn't present.
+ *
+ */
+static inline void intel_guc_wopcm_init_early(struct intel_guc_wopcm *wopcm)
+{
+	wopcm->top = WOPCM_DEFAULT_SIZE;
+}
+
+int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_size, u32 huc_size);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index aed9c1c..dc6a6c6 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -206,7 +206,7 @@ int intel_huc_auth(struct intel_huc *huc)
 		return -ENOEXEC;
 
 	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
-				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				PIN_OFFSET_BIAS | guc->wopcm.top);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1b2831b..2292f31 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -283,6 +283,9 @@ void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
 int intel_uc_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
+	struct intel_huc *huc = &dev_priv->huc;
+	u32 guc_fw_size = intel_uc_fw_get_size(&guc->fw);
+	u32 huc_fw_size = intel_uc_fw_get_size(&huc->fw);
 	int ret;
 
 	if (!USES_GUC(dev_priv))
@@ -291,6 +294,10 @@ int intel_uc_init(struct drm_i915_private *dev_priv)
 	if (!HAS_GUC(dev_priv))
 		return -ENODEV;
 
+	ret = intel_guc_wopcm_init(guc, guc_fw_size, huc_fw_size);
+	if (ret)
+		return ret;
+
 	ret = intel_guc_init(guc);
 	if (ret)
 		return ret;
@@ -340,9 +347,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	gen9_reset_guc_interrupts(dev_priv);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
+	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
-		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
+		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
 
 	/* WaEnableuKernelHeaderValidFix:skl */
 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index 24945cf..791263a 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -95,9 +95,13 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
 	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
 
-	/* Header and uCode will be loaded to WOPCM */
+	/*
+	 * Header and uCode will be loaded to WOPCM
+	 * Only check the size against the overall available WOPCM here. Will
+	 * continue to check the size during WOPCM partition calculation.
+	 */
 	size = uc_fw->header_size + uc_fw->ucode_size;
-	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
+	if (size > WOPCM_DEFAULT_SIZE) {
 		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
 			 intel_uc_fw_type_repr(uc_fw->type));
 		err = -E2BIG;
@@ -207,6 +211,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 		       int (*xfer)(struct intel_uc_fw *uc_fw,
 				   struct i915_vma *vma))
 {
+	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
 	struct i915_vma *vma;
 	int err;
 
@@ -230,7 +235,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
 	}
 
 	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
-				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
+				       PIN_OFFSET_BIAS | i915->guc.wopcm.top);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..298d475 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
 	return uc_fw->path != NULL;
 }
 
+/**
+ * intel_uc_fw_get_size() - Get the size of the firmware.
+ * @uc_fw: intel_uc_fw structure.
+ *
+ * Get the size of the firmware that will be placed in WOPCM.
+ *
+ * Return: Zero on invalid firmware status. actual size on success.
+ */
+static inline u32 intel_uc_fw_get_size(struct intel_uc_fw *uc_fw)
+{
+	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
+		return 0;
+
+	return uc_fw->header_size + uc_fw->ucode_size;
+}
+
 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		       struct intel_uc_fw *uc_fw);
 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
  2018-02-06  0:02 ` [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
  2018-02-06  0:02 ` [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size Jackie Li
@ 2018-02-06  0:02 ` Jackie Li
  2018-02-06  6:31   ` Sagar Arun Kamble
  2018-02-06  0:02 ` [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 26+ messages in thread
From: Jackie Li @ 2018-02-06  0:02 UTC (permalink / raw)
  To: intel-gfx

CNL has its own specific reserved GuC WOPCM size and hardware restrictions
on GuC WOPCM size. On CNL A0 and Gen9, there's a hardware restriction that
requires the available GuC WOPCM size to be larger than or equal to HuC
firmware size.

This patch updates GuC WOPCM init code to return the CNL specific reserved
GuC WOPCM size and also adds new verfication code to ensure the available
GuC WOPCM size to be larger than or equal to HuC firmware size on both Gen9
and CNL A0.

v6:
 - Extended HuC FW size check against GuC WOPCM size to all
   Gen9 and CNL A0 platforms

v7:
 - Fixed patch format issues

v8:
 - Renamed variables and functions to avoid ambiguity (Joonas)
 - Updated commit message and comments to be more comprehensive (Sagar)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_wopcm.c | 24 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_guc_wopcm.h |  2 ++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
index 1555e79..3cba9ac 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -32,6 +32,25 @@ static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
 	if (IS_GEN9_LP(i915))
 		return BXT_GUC_WOPCM_RC6_RESERVED;
 
+	if (IS_GEN10(i915))
+		return CNL_GUC_WOPCM_RESERVED;
+
+	return 0;
+}
+
+static inline int guc_wopcm_check_huc_fw_size(struct drm_i915_private *i915)
+{
+	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
+	u32 huc_fw_size = intel_uc_fw_get_size(&i915->huc.fw);
+
+	/*
+	 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
+	 * size to be larger than or equal to HuC firmware size. Otherwise,
+	 * firmware uploading would fail.
+	 */
+	if (unlikely(wopcm->size - GUC_WOPCM_RESERVED < huc_fw_size))
+		return -E2BIG;
+
 	return 0;
 }
 
@@ -54,7 +73,7 @@ static inline int gen9_guc_wopcm_size_check(struct drm_i915_private *i915)
 	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
 		return -E2BIG;
 
-	return 0;
+	return guc_wopcm_check_huc_fw_size(i915);
 }
 
 static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
@@ -64,6 +83,9 @@ static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
 	if (IS_GEN9(i915))
 		return gen9_guc_wopcm_size_check(i915);
 
+	if (IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))
+		return guc_wopcm_check_huc_fw_size(i915);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
index 28e4103..8c71d20a 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -42,6 +42,8 @@ struct intel_guc;
 #define GUC_WOPCM_STACK_RESERVED	(0x2000)
 /* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
 #define BXT_GUC_WOPCM_RC6_RESERVED	(0x6000)
+/* 36KB WOPCM reserved at the end of GuC WOPCM on CNL */
+#define CNL_GUC_WOPCM_RESERVED		(0x9000)
 
 #define GEN9_GUC_WOPCM_DELTA		4
 /**
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (2 preceding siblings ...)
  2018-02-06  0:02 ` [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL Jackie Li
@ 2018-02-06  0:02 ` Jackie Li
  2018-02-06  6:39   ` Sagar Arun Kamble
  2018-02-06 10:29   ` Chris Wilson
  2018-02-06  0:02 ` [PATCH v8 6/6] HAX Enable GuC Submission for CI Jackie Li
                   ` (2 subsequent siblings)
  6 siblings, 2 replies; 26+ messages in thread
From: Jackie Li @ 2018-02-06  0:02 UTC (permalink / raw)
  To: intel-gfx

GuC WOPCM registers are write-once registers. Current driver code accesses
these registers without checking the accessibility to these registers, this
will lead unpredictable driver behaviors if these registers were touch by
other components (such as faulty BIOS code).

This patch moves the GuC WOPCM register updating operations into
intel_guc_wopcm.c and adds checks before and after the write to GuC WOPCM
registers to make sure the driver is in a known state before and after
writing to these write-once registers.

v6:
 - Made sure module reloading won't bug the kernel while doing
   locking status checking

v7:
 - Fixed patch format issues

v8:
 - Fixed coding style issue on register lock bit macro definition (Sagar)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.h       |  2 +-
 drivers/gpu/drm/i915/intel_guc_reg.h   |  2 +
 drivers/gpu/drm/i915/intel_guc_wopcm.c | 93 ++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_guc_wopcm.h |  9 +++-
 drivers/gpu/drm/i915/intel_uc.c        |  5 +-
 5 files changed, 101 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 06f315e..cb1703b 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -122,7 +122,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
 {
 	u32 offset = i915_ggtt_offset(vma);
 
-	GEM_BUG_ON(!guc->wopcm.valid);
+	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
 	GEM_BUG_ON(offset < guc->wopcm.top);
 	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
 
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index de4f78b..18cb2ef 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -66,6 +66,7 @@
 #define   UOS_MOVE			  (1<<4)
 #define   START_DMA			  (1<<0)
 #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
+#define   DMA_GUC_WOPCM_OFFSET_MASK	  (0xffffc000)
 #define   HUC_LOADING_AGENT_VCR		  (0<<1)
 #define   HUC_LOADING_AGENT_GUC		  (1<<1)
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
@@ -75,6 +76,7 @@
 
 /* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
+#define   GUC_WOPCM_REG_LOCKED		  BIT(0)
 
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
index 3cba9ac..8317d9e 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -89,6 +89,55 @@ static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
 	return 0;
 }
 
+static inline bool __reg_locked(struct drm_i915_private *dev_priv,
+				i915_reg_t reg)
+{
+	/* Explicitly cast the return value to bool. */
+	return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);
+}
+
+static inline bool guc_wopcm_locked(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+	bool size_reg_locked = __reg_locked(i915, GUC_WOPCM_SIZE);
+	bool offset_reg_locked = __reg_locked(i915, DMA_GUC_WOPCM_OFFSET);
+
+	return size_reg_locked && offset_reg_locked;
+}
+
+static inline void guc_wopcm_hw_update(struct intel_guc *guc)
+{
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+	/* GuC WOPCM registers should be unlocked at this point. */
+	GEM_BUG_ON(__reg_locked(dev_priv, GUC_WOPCM_SIZE));
+	GEM_BUG_ON(__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
+
+	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
+	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
+		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
+
+	GEM_BUG_ON(!__reg_locked(dev_priv, GUC_WOPCM_SIZE));
+	GEM_BUG_ON(!__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
+}
+
+static inline bool guc_wopcm_regs_valid(struct intel_guc *guc)
+{
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	u32 size, offset;
+	bool guc_loads_huc;
+
+	/* GuC WOPCM size should be always multiple of 4K pages. */
+	size = I915_READ(GUC_WOPCM_SIZE) & PAGE_MASK;
+	offset = I915_READ(DMA_GUC_WOPCM_OFFSET);
+
+	guc_loads_huc = !!(offset & HUC_LOADING_AGENT_GUC);
+	offset &= DMA_GUC_WOPCM_OFFSET_MASK;
+
+	return guc_loads_huc && (size == guc->wopcm.size) &&
+		(offset == guc->wopcm.offset);
+}
+
 /**
  * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
  * @guc: intel guc.
@@ -111,8 +160,7 @@ int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
 	u32 offset, size, top;
 	int err;
 
-	if (guc->wopcm.valid)
-		return 0;
+	GEM_BUG_ON(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID);
 
 	if (!guc_fw_size)
 		return -EINVAL;
@@ -153,10 +201,49 @@ int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
 	if (err)
 		return err;
 
-	guc->wopcm.valid = 1;
+	guc->wopcm.flags |= INTEL_GUC_WOPCM_VALID;
 
 	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
 			 offset >> 10, size >> 10, top >> 10);
 
 	return 0;
 }
+
+/**
+ * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers.
+ * @guc: intel guc.
+ *
+ * Setup the GuC WOPCM size and offset registers with the stored values. It will
+ * also check the registers locking status to determine whether these registers
+ * are unlocked and can be updated.
+ */
+void intel_guc_wopcm_init_hw(struct intel_guc *guc)
+{
+	bool locked = guc_wopcm_locked(guc);
+
+	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
+
+	/*
+	 * Bug if driver hasn't updated the HW Registers and GuC WOPCM has been
+	 * locked. Return directly if WOPCM was locked and we have updated
+	 * the registers.
+	 */
+	if (locked) {
+		/*
+		 * Mark as updated if registers contained correct values.
+		 * This will happen while reloading the driver module without
+		 * rebooting the system.
+		 */
+		if (guc_wopcm_regs_valid(guc))
+			goto out;
+
+		GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_HW_UPDATED));
+		return;
+	}
+
+	/* Always update registers when GuC WOPCM is not locked. */
+	guc_wopcm_hw_update(guc);
+
+out:
+	guc->wopcm.flags |= INTEL_GUC_WOPCM_HW_UPDATED;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
index 8c71d20a..627f7fa 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
@@ -52,12 +52,16 @@ struct intel_guc;
  */
 #define GEN9_GUC_WOPCM_OFFSET		(0x24000)
 
+/* GuC WOPCM flags */
+#define INTEL_GUC_WOPCM_VALID		BIT(0)
+#define INTEL_GUC_WOPCM_HW_UPDATED	BIT(1)
+
 /**
  * intel_guc_wopcm - GuC WOPCM related settings.
  * @offset: GuC WOPCM offset from the WOPCM base.
  * @size: size of GuC WOPCM for GuC firmware.
  * @top: start of the non-GuC WOPCM memory.
- * @valid: whether this structure contains valid (1-valid, 0-invalid) info.
+ * @flags: bitmap of INTEL_GUC_WOPCM_<foo>.
  *
  * We simply use this structure to track the GuC use of WOPCM. The layout of
  * WOPCM would be defined by writing to GuC WOPCM offset and size registers as
@@ -75,7 +79,7 @@ struct intel_guc_wopcm {
 	u32 offset;
 	u32 size;
 	u32 top;
-	u32 valid;
+	u32 flags;
 };
 
 /**
@@ -93,5 +97,6 @@ static inline void intel_guc_wopcm_init_early(struct intel_guc_wopcm *wopcm)
 }
 
 int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_size, u32 huc_size);
+void intel_guc_wopcm_init_hw(struct intel_guc *guc);
 
 #endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2292f31..62e85b5 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -346,10 +346,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 	guc_disable_communication(guc);
 	gen9_reset_guc_interrupts(dev_priv);
 
-	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
-	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
-		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
+	intel_guc_wopcm_init_hw(guc);
 
 	/* WaEnableuKernelHeaderValidFix:skl */
 	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH v8 6/6] HAX Enable GuC Submission for CI
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (3 preceding siblings ...)
  2018-02-06  0:02 ` [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
@ 2018-02-06  0:02 ` Jackie Li
  2018-02-06  0:25 ` ✗ Fi.CI.BAT: failure for series starting with [v8,1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Patchwork
  2018-02-06  5:15 ` [PATCH v8 1/6] " Sagar Arun Kamble
  6 siblings, 0 replies; 26+ messages in thread
From: Jackie Li @ 2018-02-06  0:02 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c     | 2 +-
 drivers/gpu/drm/i915/i915_params.h     | 2 +-
 drivers/gpu/drm/i915/intel_guc_wopcm.c | 6 ++++++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 08108ce..b49ae20 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -152,7 +152,7 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
 i915_param_named_unsafe(enable_guc, int, 0400,
 	"Enable GuC load for GuC submission and/or HuC load. "
 	"Required functionality can be selected using bitmask values. "
-	"(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
+	"(-1=auto [default], 0=disable, 1=GuC submission, 2=HuC load)");
 
 i915_param_named(guc_log_level, int, 0400,
 	"GuC firmware logging level. Requires GuC to be loaded. "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, 0) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
index 8317d9e..bc7e6d9 100644
--- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -160,6 +160,9 @@ int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
 	u32 offset, size, top;
 	int err;
 
+	DRM_DEBUG_DRIVER("guc_fw size %u, huc_fw_size %u\n", guc_fw_size,
+			 huc_fw_size);
+
 	GEM_BUG_ON(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID);
 
 	if (!guc_fw_size)
@@ -221,6 +224,9 @@ void intel_guc_wopcm_init_hw(struct intel_guc *guc)
 {
 	bool locked = guc_wopcm_locked(guc);
 
+	DRM_DEBUG_DRIVER("locked = %s, flags = %#x\n", yesno(locked),
+			 guc->wopcm.flags);
+
 	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
 
 	/*
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 26+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [v8,1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (4 preceding siblings ...)
  2018-02-06  0:02 ` [PATCH v8 6/6] HAX Enable GuC Submission for CI Jackie Li
@ 2018-02-06  0:25 ` Patchwork
  2018-02-06  5:15 ` [PATCH v8 1/6] " Sagar Arun Kamble
  6 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-02-06  0:25 UTC (permalink / raw)
  To: Jackie Li; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v8,1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
URL   : https://patchwork.freedesktop.org/series/37704/
State : failure

== Summary ==

Series 37704v1 series starting with [v8,1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
https://patchwork.freedesktop.org/api/1.0/series/37704/revisions/1/mbox/

Test core_auth:
        Subgroup basic-auth:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test core_prop_blob:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test debugfs_test:
        Subgroup read_all_entries:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test drv_getparams_basic:
        Subgroup basic-eu-total:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-subslice-total:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test drv_hangman:
        Subgroup error-state-basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_basic:
        Subgroup bad-close:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup create-close:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup create-fd-close:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_busy:
        Subgroup basic-busy-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-hang-default:
                pass       -> SKIP       (fi-skl-gvtdvm) fdo#104108 +2
Test gem_close_race:
        Subgroup basic-process:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-threads:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_cpu_reloc:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_cs_tlb:
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_create:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-files:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_exec:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_param:
        Subgroup basic:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_ctx_switch:
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-default-heavy:
                pass       -> SKIP       (fi-skl-gvtdvm)
Test gem_exec_basic:
        Subgroup basic-blt:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-bsd:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-bsd1:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-bsd2:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-render:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup basic-vebox:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-blt:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-bsd:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-bsd1:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-bsd2:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-render:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup gtt-vebox:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-blt:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-bsd:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-bsd1:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-bsd2:
                pass       -> SKIP       (fi-skl-gvtdvm)
        Subgroup readonly-default:
                pass       -> SKIP       (fi-skl-gvtdvm)
WARNING: Long output truncated

89ac14dcb4d010748c1b54dba54885db1a8c13e3 drm-tip: 2018y-02m-05d-19h-08m-24s UTC integration manifest
556959797cc5 HAX Enable GuC Submission for CI
f9010c6453a6 drm/i915/guc: Check the locking status of GuC WOPCM registers
40d3996af281 drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL
17244c9ee12c drm/i915/guc: Implement dynamic GuC WOPCM offset and size
4e030d738cdc drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
7fda8abef3ad drm/i915/guc: Move GuC WOPCM related code into separate files

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7897/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
  2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
                   ` (5 preceding siblings ...)
  2018-02-06  0:25 ` ✗ Fi.CI.BAT: failure for series starting with [v8,1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Patchwork
@ 2018-02-06  5:15 ` Sagar Arun Kamble
  2018-02-06 21:11   ` Michal Wajdeczko
  6 siblings, 1 reply; 26+ messages in thread
From: Sagar Arun Kamble @ 2018-02-06  5:15 UTC (permalink / raw)
  To: Jackie Li, intel-gfx


On 2/6/2018 5:32 AM, Jackie Li wrote:
> intel_guc_reg.h should only include definition for GuC registers and
> related register bits. Non-register related GuC WOPCM macro definitions
> should not be defined in intel_guc_reg.h
>
> This patch creates a better file structure by moving non-register related
> GuC WOPCM macro definitions into a new header intel_guc_wopcm.h and moving
> GuC WOPCM related functions to a new source file intel_guc_wopcm.c as
> future patches will increase the complexity of determining the GuC WOPCM
> offset and size.
>
> v8:
>   - Fixed naming, coding style issues and typo in commit message (Sagar)
>   - Updated commit message to explain why we need create new file for GuC
>     WOPCM related code (Chris)
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v7)
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
Minor change in function comment needed below as per kernel-doc format.
Otherwise, change is good.
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile          |  1 +
>   drivers/gpu/drm/i915/intel_guc.c       | 11 --------
>   drivers/gpu/drm/i915/intel_guc.h       |  2 +-
>   drivers/gpu/drm/i915/intel_guc_reg.h   |  4 ---
>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 46 ++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_guc_wopcm.h | 39 ++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_uc.c        |  2 +-
>   drivers/gpu/drm/i915/intel_uc_fw.c     |  2 +-
>   8 files changed, 89 insertions(+), 18 deletions(-)
>   create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
>   create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 3bddd8a..1dc9988 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -88,6 +88,7 @@ i915-y += intel_uc.o \
>   	  intel_guc_fw.o \
>   	  intel_guc_log.o \
>   	  intel_guc_submission.o \
> +	  intel_guc_wopcm.o \
>   	  intel_huc.o
>   
>   # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 21140cc..9f45e6d 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -509,14 +509,3 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>   	i915_gem_object_put(obj);
>   	return vma;
>   }
> -
> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
> -{
> -	u32 wopcm_size = GUC_WOPCM_TOP;
> -
> -	/* On BXT, the top of WOPCM is reserved for RC6 context */
> -	if (IS_GEN9_LP(dev_priv))
> -		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
> -
> -	return wopcm_size;
> -}
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 52856a9..9e0a97e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -31,6 +31,7 @@
>   #include "intel_guc_ct.h"
>   #include "intel_guc_log.h"
>   #include "intel_guc_reg.h"
> +#include "intel_guc_wopcm.h"
>   #include "intel_uc_fw.h"
>   #include "i915_vma.h"
>   
> @@ -130,6 +131,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
>   int intel_guc_suspend(struct drm_i915_private *dev_priv);
>   int intel_guc_resume(struct drm_i915_private *dev_priv);
>   struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 19a9247..1f52fb8 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -68,7 +68,6 @@
>   #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>   #define   HUC_LOADING_AGENT_VCR		  (0<<1)
>   #define   HUC_LOADING_AGENT_GUC		  (1<<1)
> -#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>   
>   #define HUC_STATUS2             _MMIO(0xD3B0)
> @@ -76,9 +75,6 @@
>   
>   /* Defines WOPCM space available to GuC firmware */
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
> -#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
>   
>   /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
>   #define GUC_GGTT_TOP			0xFEE00000
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> new file mode 100644
> index 0000000..73be9af
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "intel_guc_wopcm.h"
> +#include "i915_drv.h"
> +
> +/*
Should be "/**"
> + * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
> + * @guc: intel guc.
> + *
> + * Get the platform specific GuC WOPCM size.
> + *
> + * Return: size of the GuC WOPCM.
> + */
> +u32 intel_guc_wopcm_size(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +	u32 size = GUC_WOPCM_TOP;
> +
> +	/* On BXT, the top of WOPCM is reserved for RC6 context */
> +	if (IS_GEN9_LP(i915))
> +		size -= BXT_GUC_WOPCM_RC6_RESERVED;
> +
> +	return size;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> new file mode 100644
> index 0000000..53de931
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef _INTEL_GUC_WOPCM_H_
> +#define _INTEL_GUC_WOPCM_H_
> +
> +#include <linux/types.h>
> +
> +struct intel_guc;
> +
> +#define GUC_WOPCM_OFFSET_VALUE		0x80000	/* 512KB */
> +/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> +#define GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
> +#define BXT_GUC_WOPCM_RC6_RESERVED	(0x10 << 12)	/* 64KB  */
> +
> +u32 intel_guc_wopcm_size(struct intel_guc *guc);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 9f1bac6..1b2831b 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -340,7 +340,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>   	gen9_reset_guc_interrupts(dev_priv);
>   
>   	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>   		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
>   
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
> index 784eff9..24945cf 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -97,7 +97,7 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   
>   	/* Header and uCode will be loaded to WOPCM */
>   	size = uc_fw->header_size + uc_fw->ucode_size;
> -	if (size > intel_guc_wopcm_size(dev_priv)) {
> +	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
>   		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
>   			 intel_uc_fw_type_repr(uc_fw->type));
>   		err = -E2BIG;

-- 
Thanks,
Sagar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-02-06  0:02 ` [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
@ 2018-02-06  5:21   ` Sagar Arun Kamble
  2018-02-06 10:25   ` Chris Wilson
  1 sibling, 0 replies; 26+ messages in thread
From: Sagar Arun Kamble @ 2018-02-06  5:21 UTC (permalink / raw)
  To: Jackie Li, intel-gfx



On 2/6/2018 5:32 AM, Jackie Li wrote:
> GuC related exported functions should start with "intel_guc_" prefix and
> pass intel_guc as the first parameter since its guc related. Current
> guc_ggtt_offset() failed to follow this code convention and this is a
> problem for future patches that needs to access intel_guc data to verify
> the GGTT offset against the GuC WOPCM top.
>
> This patch renames the guc_ggtt_offset to intel_guc_ggtt_offset and updates
> the related code to pass intel_guc pointer to this function call, so that
> we can have a unified coding style for GuC code and also enable the future
> patches to get GuC related data from intel_guc to do the offset
> verification. Meanwhile, this patch also moves the GUC_GGTT_TOP from
> intel_guc_regs.h to intel_guc.h since it is not GuC register related
> definition.
>
> v8:
>   - Fixed coding style issues and moved GUC_GGTT_TOP to intel_guc.h (Sagar)
>   - Updated commit message to explain to reason and motivation to add
>     intel_guc as the first parameter of intel_guc_ggtt_offset (Chris)
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc.c            | 12 +++++++-----
>   drivers/gpu/drm/i915/intel_guc.h            | 14 ++++++++++++--
>   drivers/gpu/drm/i915/intel_guc_ads.c        | 25 +++++++++++++------------
>   drivers/gpu/drm/i915/intel_guc_ct.c         |  5 +++--
>   drivers/gpu/drm/i915/intel_guc_fw.c         |  2 +-
>   drivers/gpu/drm/i915/intel_guc_log.c        |  2 +-
>   drivers/gpu/drm/i915/intel_guc_reg.h        |  3 ---
>   drivers/gpu/drm/i915/intel_guc_submission.c | 10 +++++-----
>   drivers/gpu/drm/i915/intel_huc.c            |  6 ++++--
>   9 files changed, 46 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 9f45e6d..d9bc2a9 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -269,8 +269,10 @@ void intel_guc_init_params(struct intel_guc *guc)
>   
>   	/* If GuC submission is enabled, set up additional parameters here */
>   	if (USES_GUC_SUBMISSION(dev_priv)) {
> -		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
> -		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
> +		u32 ads = intel_guc_ggtt_offset(guc,
> +						guc->ads_vma) >> PAGE_SHIFT;
> +		u32 pgs = intel_guc_ggtt_offset(guc,
> +						dev_priv->guc.stage_desc_pool);
>   		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
>   
>   		params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
> @@ -418,7 +420,7 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
>   	data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
>   	/* any value greater than GUC_POWER_D0 */
>   	data[1] = GUC_POWER_D1;
> -	data[2] = guc_ggtt_offset(guc->shared_data);
> +	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>   }
> @@ -441,7 +443,7 @@ int intel_guc_reset_engine(struct intel_guc *guc,
>   	data[3] = 0;
>   	data[4] = 0;
>   	data[5] = guc->execbuf_client->stage_id;
> -	data[6] = guc_ggtt_offset(guc->shared_data);
> +	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>   }
> @@ -463,7 +465,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>   
>   	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
>   	data[1] = GUC_POWER_D0;
> -	data[2] = guc_ggtt_offset(guc->shared_data);
> +	data[2] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>   }
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 9e0a97e..50be6de 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -101,13 +101,23 @@ static inline void intel_guc_notify(struct intel_guc *guc)
>   	guc->notify(guc);
>   }
>   
> -/*
> +/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
> +#define GUC_GGTT_TOP	0xFEE00000
> +
> +/**
> + * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
> + * @guc: intel guc.
> + * @vma: i915 graphics virtual memory area.
> + *
>    * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
>    * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
>    * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
>    * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
> + *
> + * Return: GGTT offset that meets the GuC gfx address requirement.
>    */
> -static inline u32 guc_ggtt_offset(struct i915_vma *vma)
> +static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
> +					struct i915_vma *vma)
>   {
>   	u32 offset = i915_ggtt_offset(vma);
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
> index ac62753..7215594 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.c
> @@ -113,17 +113,6 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   		blob->reg_state.white_list[engine->guc_id].count = 0;
>   	}
>   
> -	/*
> -	 * The GuC requires a "Golden Context" when it reinitialises
> -	 * engines after a reset. Here we use the Render ring default
> -	 * context, which must already exist and be pinned in the GGTT,
> -	 * so its address won't change after we've told the GuC where
> -	 * to find it. Note that we have to skip our header (1 page),
> -	 * because our GuC shared data is there.
> -	 */
> -	blob->ads.golden_context_lrca =
> -		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
> -		skipped_offset;
>   
>   	/*
>   	 * The GuC expects us to exclude the portion of the context image that
> @@ -135,11 +124,23 @@ int intel_guc_ads_create(struct intel_guc *guc)
>   		blob->ads.eng_state_size[engine->guc_id] =
>   			engine->context_size - skipped_size;
>   
> -	base = guc_ggtt_offset(vma);
> +	base = intel_guc_ggtt_offset(guc, vma);
>   	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
>   	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
>   	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
>   
> +	/*
> +	 * The GuC requires a "Golden Context" when it reinitialises
> +	 * engines after a reset. Here we use the Render ring default
> +	 * context, which must already exist and be pinned in the GGTT,
> +	 * so its address won't change after we've told the GuC where
> +	 * to find it. Note that we have to skip our header (1 page),
> +	 * because our GuC shared data is there.
> +	 */
> +	vma = dev_priv->kernel_context->engine[RCS].state;
> +	blob->ads.golden_context_lrca = intel_guc_ggtt_offset(guc, vma) +
> +		skipped_offset;
> +
>   	kunmap(page);
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
> index 24ad557..0a0d3d5 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ct.c
> @@ -156,7 +156,8 @@ static int ctch_init(struct intel_guc *guc,
>   		err = PTR_ERR(blob);
>   		goto err_vma;
>   	}
> -	DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma));
> +	DRM_DEBUG_DRIVER("CT: vma base=%#x\n",
> +			 intel_guc_ggtt_offset(guc, ctch->vma));
>   
>   	/* store pointers to desc and cmds */
>   	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
> @@ -202,7 +203,7 @@ static int ctch_open(struct intel_guc *guc,
>   	}
>   
>   	/* vma should be already allocated and map'ed */
> -	base = guc_ggtt_offset(ctch->vma);
> +	base = intel_guc_ggtt_offset(guc, ctch->vma);
>   
>   	/* (re)initialize descriptors
>   	 * cmds buffers are in the second half of the blob page
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> index 3b09329..178d339 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -165,7 +165,7 @@ static int guc_xfer_ucode(struct intel_guc *guc, struct i915_vma *vma)
>   	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
>   
>   	/* Set the source address for the new blob */
> -	offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
> +	offset = intel_guc_ggtt_offset(guc, vma) + guc_fw->header_offset;
>   	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>   	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
> index 7b5074e..eca8725 100644
> --- a/drivers/gpu/drm/i915/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/intel_guc_log.c
> @@ -638,7 +638,7 @@ int intel_guc_log_create(struct intel_guc *guc)
>   		(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
>   		(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
>   
> -	offset = guc_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */
> +	offset = intel_guc_ggtt_offset(guc, vma) >> PAGE_SHIFT; /* in pages */
>   	guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index 1f52fb8..de4f78b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -76,9 +76,6 @@
>   /* Defines WOPCM space available to GuC firmware */
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
>   
> -/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
> -#define GUC_GGTT_TOP			0xFEE00000
> -
>   #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 1f3a878..c56e4f4 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -375,8 +375,8 @@ static void guc_stage_desc_init(struct intel_guc *guc,
>   		lrc->context_desc = lower_32_bits(ce->lrc_desc);
>   
>   		/* The state page is after PPHWSP */
> -		lrc->ring_lrca =
> -			guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
> +		lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
> +				 LRC_STATE_PN * PAGE_SIZE;
>   
>   		/* XXX: In direct submission, the GuC wants the HW context id
>   		 * here. In proxy submission, it wants the stage id
> @@ -384,7 +384,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
>   		lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
>   				(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
>   
> -		lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
> +		lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
>   		lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
>   		lrc->ring_next_free_location = lrc->ring_begin;
>   		lrc->ring_current_tail_pointer_value = 0;
> @@ -400,7 +400,7 @@ static void guc_stage_desc_init(struct intel_guc *guc,
>   	 * The doorbell, process descriptor, and workqueue are all parts
>   	 * of the client object, which the GuC will reference via the GGTT
>   	 */
> -	gfx_addr = guc_ggtt_offset(client->vma);
> +	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
>   	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
>   				client->doorbell_offset;
>   	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
> @@ -596,7 +596,7 @@ static void inject_preempt_context(struct work_struct *work)
>   	data[3] = engine->guc_id;
>   	data[4] = guc->execbuf_client->priority;
>   	data[5] = guc->execbuf_client->stage_id;
> -	data[6] = guc_ggtt_offset(guc->shared_data);
> +	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>   
>   	if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
>   		execlists_clear_active(&engine->execlists,
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index 8ed0518..aed9c1c 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -137,7 +137,8 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
>   	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>   
>   	/* Set the source address for the uCode */
> -	offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
> +	offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
> +		 huc_fw->header_offset;
>   	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>   	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>   
> @@ -213,7 +214,8 @@ int intel_huc_auth(struct intel_huc *huc)
>   	}
>   
>   	ret = intel_guc_auth_huc(guc,
> -				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
> +				 intel_guc_ggtt_offset(guc, vma) +
> +				 huc->fw.rsa_offset);
>   	if (ret) {
>   		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>   		goto out;

-- 
Thanks,
Sagar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size
  2018-02-06  0:02 ` [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size Jackie Li
@ 2018-02-06  6:20   ` Sagar Arun Kamble
  2018-02-06 22:25     ` Michal Wajdeczko
  0 siblings, 1 reply; 26+ messages in thread
From: Sagar Arun Kamble @ 2018-02-06  6:20 UTC (permalink / raw)
  To: Jackie Li, intel-gfx; +Cc: Sujaritha Sundaresan

change looks good to me. minor updates suggested with r-b.


On 2/6/2018 5:32 AM, Jackie Li wrote:
> Hardware may have specific restrictions on GuC WOPCM offset and size. On
> Gen9, the value of the GuC WOPCM size register needs to be larger than the
> value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
> reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
> will lead to GuC firmware execution failures.
Add below line here?

Second restriction is for Gen9 and Gen10 and it is w.r.t. HuC firmware 
size as per which "GuC WOPCM size - 16K" should
be greater than or equal to HuC firmware size.
> So we need add code to verify
> the GuC WOPCM offset and size to avoid any GuC failures. On the other hand,
> with current static GuC WOPCM offset and size values (512KB for both offset
> and size), the GuC WOPCM size verification will fail on Gen9 even if it can
> be fixed by lowering the GuC WOPCM offset by calculating its value based on
> HuC firmware size (which is likely less than 200KB on Gen9), so that we can
> have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
> size check.
>
> This patch updates the reserved GuC WOPCM size for RC6 context on Gen9 to
> 24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds support
> to verify the GuC WOPCM size aganist the Gen9 hardware restrictions.
> Meanwhile, it provides a common way to calculate GuC WOPCM offset and size
> based on GuC and HuC firmware sizes for all GuC/HuC enabled platforms.
> Currently, GuC WOPCM offset is calculated based on HuC firmware size +
> reserved WOPCM size while GuC WOPCM size is set to total WOPCM size - GuC
> WOPCM offset - reserved RC6CTX size. In this case, GuC WOPCM offset will be
> updated based on the size of HuC firmware while GuC WOPCM size will be set
> to use all the remaining WOPCM space.
>
> v2:
>   - Removed intel_wopcm_init (Ville/Sagar/Joonas)
>   - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
>   - Removed unnecessary function calls (Joonas)
>   - Init GuC WOPCM partition as soon as firmware fetching is completed
>
> v3:
>   - Fixed indentation issues (Chris)
>   - Removed layering violation code (Chris/Michal)
>   - Created separat files for GuC wopcm code  (Michal)
>   - Used inline function to avoid code duplication (Michal)
>
> v4:
>   - Preset the GuC WOPCM top during early GuC init (Chris)
>   - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed
>
> v5:
>   - Moved GuC DMA WOPCM register updating code into intel_guc_wopcm.c
>   - Took care of the locking status before writing to GuC DMA
>     Write-Once registers. (Joonas)
>
> v6:
>   - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)
>
> v8:
>   - Updated comments and fixed naming issues (Sagar/Joonas)
>   - Updated commit message to include more description about the hardware
>     restriction on GuC WOPCM size (Sagar)
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Jackie Li <yaodong.li@intel.com>

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
>   drivers/gpu/drm/i915/intel_guc.c        |   5 +-
>   drivers/gpu/drm/i915/intel_guc.h        |  12 ++--
>   drivers/gpu/drm/i915/intel_guc_wopcm.c  | 116 +++++++++++++++++++++++++++++---
>   drivers/gpu/drm/i915/intel_guc_wopcm.h  |  66 ++++++++++++++++--
>   drivers/gpu/drm/i915/intel_huc.c        |   2 +-
>   drivers/gpu/drm/i915/intel_uc.c         |  11 ++-
>   drivers/gpu/drm/i915/intel_uc_fw.c      |  11 ++-
>   drivers/gpu/drm/i915/intel_uc_fw.h      |  16 +++++
>   9 files changed, 213 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 648e753..546404e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -312,12 +312,13 @@ __create_hw_context(struct drm_i915_private *dev_priv,
>   	ctx->desc_template =
>   		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>   
> -	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
> +	/*
> +	 * GuC requires the ring to be placed above GuC WOPCM top. If GuC is not
>   	 * present or not in use we still need a small bias as ring wraparound
>   	 * at offset 0 sometimes hangs. No idea why.
>   	 */
>   	if (USES_GUC(dev_priv))
> -		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
> +		ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;
>   	else
>   		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index d9bc2a9..ecd5da2 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -65,6 +65,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>   	intel_guc_fw_init_early(guc);
>   	intel_guc_ct_init_early(&guc->ct);
>   	intel_guc_log_init_early(guc);
> +	intel_guc_wopcm_init_early(&guc->wopcm);
>   
>   	mutex_init(&guc->send_mutex);
>   	guc->send = intel_guc_send_nop;
> @@ -478,7 +479,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
>    * This is a wrapper to create an object for use with the GuC. In order to
>    * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
>    * both some backing storage and a range inside the Global GTT. We must pin
> - * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
> + * it in the GGTT somewhere other than than [0, GuC WOPCM top) because that
>    * range is reserved inside GuC.
>    *
>    * Return:	A i915_vma if successful, otherwise an ERR_PTR.
> @@ -499,7 +500,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>   		goto err;
>   
>   	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
> -			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->wopcm.top);
>   	if (ret) {
>   		vma = ERR_PTR(ret);
>   		goto err;
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 50be6de..06f315e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -49,6 +49,7 @@ struct intel_guc {
>   	struct intel_uc_fw fw;
>   	struct intel_guc_log log;
>   	struct intel_guc_ct ct;
> +	struct intel_guc_wopcm wopcm;
>   
>   	/* Log snapshot if GuC errors during load */
>   	struct drm_i915_gem_object *load_err_log;
> @@ -109,10 +110,10 @@ static inline void intel_guc_notify(struct intel_guc *guc)
>    * @guc: intel guc.
>    * @vma: i915 graphics virtual memory area.
>    *
> - * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
> - * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
> - * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
> - * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
> + * GuC does not allow any gfx GGTT address that falls into range
> + * [0, GuC WOPCM top), which is reserved for Boot ROM, SRAM and WOPCM.
> + * All gfx objects used by GuC is pinned with PIN_OFFSET_BIAS along with
> + * top of WOPCM.
>    *
>    * Return: GGTT offset that meets the GuC gfx address requirement.
>    */
> @@ -121,7 +122,8 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>   {
>   	u32 offset = i915_ggtt_offset(vma);
>   
> -	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
> +	GEM_BUG_ON(!guc->wopcm.valid);
> +	GEM_BUG_ON(offset < guc->wopcm.top);
>   	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>   
>   	return offset;
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> index 73be9af..1555e79 100644
> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> @@ -25,22 +25,116 @@
>   #include "intel_guc_wopcm.h"
>   #include "i915_drv.h"
>   
> -/*
> - * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
> +static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +
> +	if (IS_GEN9_LP(i915))
> +		return BXT_GUC_WOPCM_RC6_RESERVED;
> +
> +	return 0;
> +}
> +
> +static inline int gen9_guc_wopcm_size_check(struct drm_i915_private *i915)
> +{
> +	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
use variable name as guc_wopcm?
> +	u32 guc_wopcm_start;
> +	u32 delta;
> +
> +	/*
> +	 * GuC WOPCM size is at least 4 bytes larger than the offset from WOPCM
> +	 * base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET) due
> +	 * to hardware limitation on Gen9.
> +	 */
> +	guc_wopcm_start = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
> +	if (unlikely(guc_wopcm_start > wopcm->size))
> +		return -E2BIG;
> +
> +	delta = wopcm->size - guc_wopcm_start;
> +	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
> +		return -E2BIG;
> +
> +	return 0;
> +}
> +
> +static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +
> +	if (IS_GEN9(i915))
> +		return gen9_guc_wopcm_size_check(i915);
> +
> +	return 0;
> +}
> +
> +/**
> + * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
remove extra "."
>    * @guc: intel guc.
> + * @guc_fw_size: size of GuC firmware.
> + * @huc_fw_size: size of HuC firmware.
>    *
> - * Get the platform specific GuC WOPCM size.
> + * Calculate the GuC WOPCM offset and size based on GuC and HuC firmware sizes.
> + * This function will to set the GuC WOPCM size to the size of maximum WOPCM
remove "to"
> + * available for GuC. This function will also enforce platform dependent
> + * hardware restrictions on GuC WOPCM offset and size. It will fail the GuC
> + * WOPCM init if any of these checks were failed, so that the following GuC
> + * firmware uploading would be aborted.
>    *
> - * Return: size of the GuC WOPCM.
> + * Return: 0 on success, non-zero error code on failure.
>    */
> -u32 intel_guc_wopcm_size(struct intel_guc *guc)
> +int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
> +			 u32 huc_fw_size)
>   {
> -	struct drm_i915_private *i915 = guc_to_i915(guc);
> -	u32 size = GUC_WOPCM_TOP;
> +	u32 reserved = guc_reserved_wopcm_size(guc);
> +	u32 offset, size, top;
> +	int err;
>   
> -	/* On BXT, the top of WOPCM is reserved for RC6 context */
> -	if (IS_GEN9_LP(i915))
> -		size -= BXT_GUC_WOPCM_RC6_RESERVED;
> +	if (guc->wopcm.valid)
> +		return 0;
> +
> +	if (!guc_fw_size)
> +		return -EINVAL;
> +
> +	if (reserved >= WOPCM_DEFAULT_SIZE)
> +		return -E2BIG;
> +
> +	offset = huc_fw_size + WOPCM_RESERVED_SIZE;
> +	if (offset >= WOPCM_DEFAULT_SIZE)
> +		return -E2BIG;
> +
> +	/* Hardware requires GuC WOPCM offset to be 16K aligned. */
> +	offset = ALIGN(offset, GUC_WOPCM_OFFSET_ALIGNMENT);
> +	if ((offset + reserved) >= WOPCM_DEFAULT_SIZE)
> +		return -E2BIG;
> +
> +	top = WOPCM_DEFAULT_SIZE - offset;
> +	size = top - reserved;
> +
> +	/* GuC WOPCM size must be multiple of 4K pages */
> +	size &= PAGE_MASK;
> +
> +	/*
> +	 * GuC firmware size needs to be less than or equal to the size of the
> +	 * available GuC WOPCM (total available GuC WOPCM size - reserved size).
> +	 * Need extra 8K stack for GuC firmware.
> +	 */
> +	reserved = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
> +	if ((guc_fw_size + reserved) > size)
> +		return -E2BIG;
> +
> +	guc->wopcm.offset = offset;
> +	guc->wopcm.size = size;
> +	guc->wopcm.top = top;
> +
> +	/* Check platform specific restrictions */
> +	err = guc_wopcm_check_hw_restrictions(guc);
> +	if (err)
> +		return err;
> +
> +	guc->wopcm.valid = 1;
> +
> +	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
> +			 offset >> 10, size >> 10, top >> 10);
>   
> -	return size;
> +	return 0;
>   }
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> index 53de931..28e4103 100644
> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> @@ -29,11 +29,67 @@
>   
>   struct intel_guc;
>   
> -#define GUC_WOPCM_OFFSET_VALUE		0x80000	/* 512KB */
> -/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
> -#define BXT_GUC_WOPCM_RC6_RESERVED	(0x10 << 12)	/* 64KB  */
> +/* Default WOPCM size 1MB. */
> +#define WOPCM_DEFAULT_SIZE		(0x1 << 20)
> +/* The initial 16KB WOPCM is reserved. */
> +#define WOPCM_RESERVED_SIZE		(0x4000)
>   
> -u32 intel_guc_wopcm_size(struct intel_guc *guc);
> +/* GUC WOPCM offset needs to be 16KB aligned. */
> +#define GUC_WOPCM_OFFSET_ALIGNMENT	(0x4000)
> +/* 16KB reserved at the beginning of GuC WOPCM. */
> +#define GUC_WOPCM_RESERVED		(0x4000)
> +/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
> +#define GUC_WOPCM_STACK_RESERVED	(0x2000)
> +/* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
> +#define BXT_GUC_WOPCM_RC6_RESERVED	(0x6000)
> +
> +#define GEN9_GUC_WOPCM_DELTA		4
> +/**
Only "/*"
> + * GuC WOPCM starts at 144KB (GUC_WOPCM_RESERVED + 128KB reserved for GuC
> + * firmware loading) from GuC WOPCM offset on BXT.
> + */
> +#define GEN9_GUC_WOPCM_OFFSET		(0x24000)
> +
> +/**
> + * intel_guc_wopcm - GuC WOPCM related settings.
> + * @offset: GuC WOPCM offset from the WOPCM base.
> + * @size: size of GuC WOPCM for GuC firmware.
> + * @top: start of the non-GuC WOPCM memory.
> + * @valid: whether this structure contains valid (1-valid, 0-invalid) info.
> + *
> + * We simply use this structure to track the GuC use of WOPCM. The layout of
> + * WOPCM would be defined by writing to GuC WOPCM offset and size registers as
> + * shown below.
> + *
> + * +-----------+<-- top
> + * |###########|
> + * +-----------+<-- size (GuC_WOPCM_SIZE register)
> + * | GuC WOPCM |
> + * +-----------+<-- offset (DMA_GUC_WOPCM_OFFSET register)
> + * |###########|
> + * +-----------+<-- WOPCM base
> + */
> +struct intel_guc_wopcm {
> +	u32 offset;
> +	u32 size;
> +	u32 top;
> +	u32 valid;
> +};
> +
> +/**
> + * intel_guc_wopcm_init_early() - Early initialization of the GuC WOPCM.
> + * @wopcm: GuC WOPCM.
Update this name too?
> + *
> + * Setup the GuC WOPCM top to the top of the overall WOPCM. This will guarantee
> + * that the allocation of the GuC accessible objects won't fall into WOPCM when
> + * GuC partition isn't present.
> + *
> + */
> +static inline void intel_guc_wopcm_init_early(struct intel_guc_wopcm *wopcm)
> +{
> +	wopcm->top = WOPCM_DEFAULT_SIZE;
> +}
> +
> +int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_size, u32 huc_size);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index aed9c1c..dc6a6c6 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -206,7 +206,7 @@ int intel_huc_auth(struct intel_huc *huc)
>   		return -ENOEXEC;
>   
>   	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
> -				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +				PIN_OFFSET_BIAS | guc->wopcm.top);
>   	if (IS_ERR(vma)) {
>   		ret = PTR_ERR(vma);
>   		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 1b2831b..2292f31 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -283,6 +283,9 @@ void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
>   int intel_uc_init(struct drm_i915_private *dev_priv)
>   {
>   	struct intel_guc *guc = &dev_priv->guc;
> +	struct intel_huc *huc = &dev_priv->huc;
> +	u32 guc_fw_size = intel_uc_fw_get_size(&guc->fw);
> +	u32 huc_fw_size = intel_uc_fw_get_size(&huc->fw);
>   	int ret;
>   
>   	if (!USES_GUC(dev_priv))
> @@ -291,6 +294,10 @@ int intel_uc_init(struct drm_i915_private *dev_priv)
>   	if (!HAS_GUC(dev_priv))
>   		return -ENODEV;
>   
> +	ret = intel_guc_wopcm_init(guc, guc_fw_size, huc_fw_size);
> +	if (ret)
> +		return ret;
> +
>   	ret = intel_guc_init(guc);
>   	if (ret)
>   		return ret;
> @@ -340,9 +347,9 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>   	gen9_reset_guc_interrupts(dev_priv);
>   
>   	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
> +	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> -		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
> +		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
>   
>   	/* WaEnableuKernelHeaderValidFix:skl */
>   	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
> index 24945cf..791263a 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -95,9 +95,13 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
>   	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>   
> -	/* Header and uCode will be loaded to WOPCM */
> +	/*
> +	 * Header and uCode will be loaded to WOPCM
> +	 * Only check the size against the overall available WOPCM here. Will
> +	 * continue to check the size during WOPCM partition calculation.
> +	 */
>   	size = uc_fw->header_size + uc_fw->ucode_size;
> -	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
> +	if (size > WOPCM_DEFAULT_SIZE) {
>   		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
>   			 intel_uc_fw_type_repr(uc_fw->type));
>   		err = -E2BIG;
> @@ -207,6 +211,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>   		       int (*xfer)(struct intel_uc_fw *uc_fw,
>   				   struct i915_vma *vma))
>   {
> +	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
>   	struct i915_vma *vma;
>   	int err;
>   
> @@ -230,7 +235,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>   	}
>   
>   	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
> -				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
> +				       PIN_OFFSET_BIAS | i915->guc.wopcm.top);
>   	if (IS_ERR(vma)) {
>   		err = PTR_ERR(vma);
>   		DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
> index d5fd460..298d475 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
> @@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
>   	return uc_fw->path != NULL;
>   }
>   
> +/**
> + * intel_uc_fw_get_size() - Get the size of the firmware.
> + * @uc_fw: intel_uc_fw structure.
> + *
> + * Get the size of the firmware that will be placed in WOPCM.
> + *
> + * Return: Zero on invalid firmware status. actual size on success.
> + */
> +static inline u32 intel_uc_fw_get_size(struct intel_uc_fw *uc_fw)
> +{
> +	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
> +		return 0;
> +
> +	return uc_fw->header_size + uc_fw->ucode_size;
> +}
> +
>   void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   		       struct intel_uc_fw *uc_fw);
>   int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,

-- 
Thanks,
Sagar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL
  2018-02-06  0:02 ` [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL Jackie Li
@ 2018-02-06  6:31   ` Sagar Arun Kamble
  2018-02-06 22:29     ` Michal Wajdeczko
  0 siblings, 1 reply; 26+ messages in thread
From: Sagar Arun Kamble @ 2018-02-06  6:31 UTC (permalink / raw)
  To: Jackie Li, intel-gfx



On 2/6/2018 5:32 AM, Jackie Li wrote:
> CNL has its own specific reserved GuC WOPCM size and hardware restrictions
> on GuC WOPCM size. On CNL A0 and Gen9, there's a hardware restriction that
> requires the available GuC WOPCM size to be larger than or equal to HuC
> firmware size.
>
> This patch updates GuC WOPCM init code to return the CNL specific reserved
> GuC WOPCM size and also adds new verfication code to ensure the available
> GuC WOPCM size to be larger than or equal to HuC firmware size on both Gen9
> and CNL A0.
>
> v6:
>   - Extended HuC FW size check against GuC WOPCM size to all
>     Gen9 and CNL A0 platforms
>
> v7:
>   - Fixed patch format issues
>
> v8:
>   - Renamed variables and functions to avoid ambiguity (Joonas)
>   - Updated commit message and comments to be more comprehensive (Sagar)
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
Need to update subject as "Update WOPCM restrictions for CNL and add HuC 
size related restriction for Gen9 and CNL A0"
Or else breaking into two patches would have been good idea.
But change looks good to me.
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 24 +++++++++++++++++++++++-
>   drivers/gpu/drm/i915/intel_guc_wopcm.h |  2 ++
>   2 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> index 1555e79..3cba9ac 100644
> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> @@ -32,6 +32,25 @@ static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
>   	if (IS_GEN9_LP(i915))
>   		return BXT_GUC_WOPCM_RC6_RESERVED;
>   
> +	if (IS_GEN10(i915))
> +		return CNL_GUC_WOPCM_RESERVED;
> +
> +	return 0;
> +}
> +
> +static inline int guc_wopcm_check_huc_fw_size(struct drm_i915_private *i915)
> +{
> +	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
> +	u32 huc_fw_size = intel_uc_fw_get_size(&i915->huc.fw);
> +
> +	/*
> +	 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
> +	 * size to be larger than or equal to HuC firmware size. Otherwise,
> +	 * firmware uploading would fail.
> +	 */
> +	if (unlikely(wopcm->size - GUC_WOPCM_RESERVED < huc_fw_size))
> +		return -E2BIG;
> +
>   	return 0;
>   }
>   
> @@ -54,7 +73,7 @@ static inline int gen9_guc_wopcm_size_check(struct drm_i915_private *i915)
>   	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
>   		return -E2BIG;
>   
> -	return 0;
> +	return guc_wopcm_check_huc_fw_size(i915);
>   }
>   
>   static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
> @@ -64,6 +83,9 @@ static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
>   	if (IS_GEN9(i915))
>   		return gen9_guc_wopcm_size_check(i915);
>   
> +	if (IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))
> +		return guc_wopcm_check_huc_fw_size(i915);
> +
>   	return 0;
>   }
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> index 28e4103..8c71d20a 100644
> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> @@ -42,6 +42,8 @@ struct intel_guc;
>   #define GUC_WOPCM_STACK_RESERVED	(0x2000)
>   /* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
>   #define BXT_GUC_WOPCM_RC6_RESERVED	(0x6000)
> +/* 36KB WOPCM reserved at the end of GuC WOPCM on CNL */
> +#define CNL_GUC_WOPCM_RESERVED		(0x9000)
>   
>   #define GEN9_GUC_WOPCM_DELTA		4
>   /**

-- 
Thanks,
Sagar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-06  0:02 ` [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
@ 2018-02-06  6:39   ` Sagar Arun Kamble
  2018-02-06 22:56     ` Michal Wajdeczko
  2018-02-07  3:12     ` Yaodong Li
  2018-02-06 10:29   ` Chris Wilson
  1 sibling, 2 replies; 26+ messages in thread
From: Sagar Arun Kamble @ 2018-02-06  6:39 UTC (permalink / raw)
  To: Jackie Li, intel-gfx



On 2/6/2018 5:32 AM, Jackie Li wrote:
> GuC WOPCM registers are write-once registers. Current driver code accesses
> these registers without checking the accessibility to these registers, this
> will lead unpredictable driver behaviors if these registers were touch by
> other components (such as faulty BIOS code).
>
> This patch moves the GuC WOPCM register updating operations into
> intel_guc_wopcm.c and adds checks before and after the write to GuC WOPCM
> registers to make sure the driver is in a known state before and after
> writing to these write-once registers.
>
> v6:
>   - Made sure module reloading won't bug the kernel while doing
>     locking status checking
>
> v7:
>   - Fixed patch format issues
>
> v8:
>   - Fixed coding style issue on register lock bit macro definition (Sagar)
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Jackie Li <yaodong.li@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc.h       |  2 +-
>   drivers/gpu/drm/i915/intel_guc_reg.h   |  2 +
>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 93 ++++++++++++++++++++++++++++++++--
>   drivers/gpu/drm/i915/intel_guc_wopcm.h |  9 +++-
>   drivers/gpu/drm/i915/intel_uc.c        |  5 +-
>   5 files changed, 101 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index 06f315e..cb1703b 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -122,7 +122,7 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>   {
>   	u32 offset = i915_ggtt_offset(vma);
>   
> -	GEM_BUG_ON(!guc->wopcm.valid);
> +	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
>   	GEM_BUG_ON(offset < guc->wopcm.top);
>   	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>   
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index de4f78b..18cb2ef 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -66,6 +66,7 @@
>   #define   UOS_MOVE			  (1<<4)
>   #define   START_DMA			  (1<<0)
>   #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
> +#define   DMA_GUC_WOPCM_OFFSET_MASK	  (0xffffc000)
>   #define   HUC_LOADING_AGENT_VCR		  (0<<1)
>   #define   HUC_LOADING_AGENT_GUC		  (1<<1)
>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
> @@ -75,6 +76,7 @@
>   
>   /* Defines WOPCM space available to GuC firmware */
>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> +#define   GUC_WOPCM_REG_LOCKED		  BIT(0)
>   
>   #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> index 3cba9ac..8317d9e 100644
> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
> @@ -89,6 +89,55 @@ static inline int guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
>   	return 0;
>   }
>   
> +static inline bool __reg_locked(struct drm_i915_private *dev_priv,
> +				i915_reg_t reg)
> +{
> +	/* Explicitly cast the return value to bool. */
> +	return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);
> +}
> +
> +static inline bool guc_wopcm_locked(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *i915 = guc_to_i915(guc);
> +	bool size_reg_locked = __reg_locked(i915, GUC_WOPCM_SIZE);
> +	bool offset_reg_locked = __reg_locked(i915, DMA_GUC_WOPCM_OFFSET);
> +
> +	return size_reg_locked && offset_reg_locked;
> +}
> +
> +static inline void guc_wopcm_hw_update(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> +	/* GuC WOPCM registers should be unlocked at this point. */
> +	GEM_BUG_ON(__reg_locked(dev_priv, GUC_WOPCM_SIZE));
> +	GEM_BUG_ON(__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
> +
> +	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
> +	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> +		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
> +
> +	GEM_BUG_ON(!__reg_locked(dev_priv, GUC_WOPCM_SIZE));
> +	GEM_BUG_ON(!__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
> +}
> +
> +static inline bool guc_wopcm_regs_valid(struct intel_guc *guc)
> +{
> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	u32 size, offset;
> +	bool guc_loads_huc;
> +
> +	/* GuC WOPCM size should be always multiple of 4K pages. */
> +	size = I915_READ(GUC_WOPCM_SIZE) & PAGE_MASK;
> +	offset = I915_READ(DMA_GUC_WOPCM_OFFSET);
> +
> +	guc_loads_huc = !!(offset & HUC_LOADING_AGENT_GUC);
> +	offset &= DMA_GUC_WOPCM_OFFSET_MASK;
> +
> +	return guc_loads_huc && (size == guc->wopcm.size) &&
> +		(offset == guc->wopcm.offset);
> +}
> +
>   /**
>    * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
>    * @guc: intel guc.
> @@ -111,8 +160,7 @@ int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
>   	u32 offset, size, top;
>   	int err;
>   
> -	if (guc->wopcm.valid)
> -		return 0;
> +	GEM_BUG_ON(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID);
>   
>   	if (!guc_fw_size)
>   		return -EINVAL;
> @@ -153,10 +201,49 @@ int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
>   	if (err)
>   		return err;
>   
> -	guc->wopcm.valid = 1;
> +	guc->wopcm.flags |= INTEL_GUC_WOPCM_VALID;
>   
>   	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
>   			 offset >> 10, size >> 10, top >> 10);
>   
>   	return 0;
>   }
> +
> +/**
> + * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers.
> + * @guc: intel guc.
> + *
> + * Setup the GuC WOPCM size and offset registers with the stored values. It will
> + * also check the registers locking status to determine whether these registers
> + * are unlocked and can be updated.
> + */
> +void intel_guc_wopcm_init_hw(struct intel_guc *guc)
> +{
> +	bool locked = guc_wopcm_locked(guc);
> +
> +	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
> +
> +	/*
> +	 * Bug if driver hasn't updated the HW Registers and GuC WOPCM has been
> +	 * locked. Return directly if WOPCM was locked and we have updated
> +	 * the registers.
> +	 */
> +	if (locked) {
> +		/*
> +		 * Mark as updated if registers contained correct values.
> +		 * This will happen while reloading the driver module without
> +		 * rebooting the system.
> +		 */
> +		if (guc_wopcm_regs_valid(guc))
> +			goto out;
> +
> +		GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_HW_UPDATED));
We should not go ahead with uc_init_hw in this case so returning error 
from here or
checking wopcm.flags to abort uc_init_hw is needed with debug message.
> +		return;
> +	}
> +
> +	/* Always update registers when GuC WOPCM is not locked. */
> +	guc_wopcm_hw_update(guc);
> +
> +out:
> +	guc->wopcm.flags |= INTEL_GUC_WOPCM_HW_UPDATED;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> index 8c71d20a..627f7fa 100644
> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
> @@ -52,12 +52,16 @@ struct intel_guc;
>    */
>   #define GEN9_GUC_WOPCM_OFFSET		(0x24000)
>   
> +/* GuC WOPCM flags */
> +#define INTEL_GUC_WOPCM_VALID		BIT(0)
> +#define INTEL_GUC_WOPCM_HW_UPDATED	BIT(1)
> +
>   /**
>    * intel_guc_wopcm - GuC WOPCM related settings.
>    * @offset: GuC WOPCM offset from the WOPCM base.
>    * @size: size of GuC WOPCM for GuC firmware.
>    * @top: start of the non-GuC WOPCM memory.
> - * @valid: whether this structure contains valid (1-valid, 0-invalid) info.
> + * @flags: bitmap of INTEL_GUC_WOPCM_<foo>.
>    *
>    * We simply use this structure to track the GuC use of WOPCM. The layout of
>    * WOPCM would be defined by writing to GuC WOPCM offset and size registers as
> @@ -75,7 +79,7 @@ struct intel_guc_wopcm {
>   	u32 offset;
>   	u32 size;
>   	u32 top;
> -	u32 valid;
> +	u32 flags;
>   };
>   
>   /**
> @@ -93,5 +97,6 @@ static inline void intel_guc_wopcm_init_early(struct intel_guc_wopcm *wopcm)
>   }
>   
>   int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_size, u32 huc_size);
> +void intel_guc_wopcm_init_hw(struct intel_guc *guc);
>   
>   #endif
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 2292f31..62e85b5 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -346,10 +346,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>   	guc_disable_communication(guc);
>   	gen9_reset_guc_interrupts(dev_priv);
>   
> -	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
> -	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
> -		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
> +	intel_guc_wopcm_init_hw(guc);
>   
>   	/* WaEnableuKernelHeaderValidFix:skl */
>   	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */

-- 
Thanks,
Sagar

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset
  2018-02-06  0:02 ` [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
  2018-02-06  5:21   ` Sagar Arun Kamble
@ 2018-02-06 10:25   ` Chris Wilson
  1 sibling, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2018-02-06 10:25 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2018-02-06 00:02:38)
> diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c
> index ac62753..7215594 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ads.c
> @@ -113,17 +113,6 @@ int intel_guc_ads_create(struct intel_guc *guc)
>                 blob->reg_state.white_list[engine->guc_id].count = 0;
>         }
>  
> -       /*
> -        * The GuC requires a "Golden Context" when it reinitialises
> -        * engines after a reset. Here we use the Render ring default
> -        * context, which must already exist and be pinned in the GGTT,
> -        * so its address won't change after we've told the GuC where
> -        * to find it. Note that we have to skip our header (1 page),
> -        * because our GuC shared data is there.
> -        */
> -       blob->ads.golden_context_lrca =
> -               guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) +
> -               skipped_offset;

> +       vma = dev_priv->kernel_context->engine[RCS].state;
> +       blob->ads.golden_context_lrca = intel_guc_ggtt_offset(guc, vma) +
> +               skipped_offset;
> +

Please consider the visual grouping in line breaks carefully. The
alignment in the first stanza couples the ggtt_offset with the addition
of the skipped_offset. The lack of alignment in the second, makes the
skipped_offset appear an unrelated after thought.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-06  0:02 ` [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
  2018-02-06  6:39   ` Sagar Arun Kamble
@ 2018-02-06 10:29   ` Chris Wilson
  1 sibling, 0 replies; 26+ messages in thread
From: Chris Wilson @ 2018-02-06 10:29 UTC (permalink / raw)
  To: Jackie Li, intel-gfx

Quoting Jackie Li (2018-02-06 00:02:41)
> +static inline bool __reg_locked(struct drm_i915_private *dev_priv,
> +                               i915_reg_t reg)
> +{
> +       /* Explicitly cast the return value to bool. */

You already did by using bool.

> +       return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);

i.e. this is equivalent as defined by the C spec to
	return I915_READ(reg) & GUC_WOPCM_REG_LOCKED;
-Chris
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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
  2018-02-06  5:15 ` [PATCH v8 1/6] " Sagar Arun Kamble
@ 2018-02-06 21:11   ` Michal Wajdeczko
  2018-02-07  3:23     ` Yaodong Li
  0 siblings, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2018-02-06 21:11 UTC (permalink / raw)
  To: Jackie Li, intel-gfx, Sagar Arun Kamble

On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

>
> On 2/6/2018 5:32 AM, Jackie Li wrote:
>> intel_guc_reg.h should only include definition for GuC registers and
>> related register bits. Non-register related GuC WOPCM macro definitions
>> should not be defined in intel_guc_reg.h
>>
>> This patch creates a better file structure by moving non-register  
>> related
>> GuC WOPCM macro definitions into a new header intel_guc_wopcm.h and  
>> moving
>> GuC WOPCM related functions to a new source file intel_guc_wopcm.c as
>> future patches will increase the complexity of determining the GuC WOPCM
>> offset and size.

Hmm, I'm not sure that we need such low-details explanation that repeats
filenames listed below. Maybe it can like this:

"New file structure is needed as future patches will increase the
complexity of determining the GuC WOPCM offset and size."

>>
>> v8:
>>   - Fixed naming, coding style issues and typo in commit message (Sagar)
>>   - Updated commit message to explain why we need create new file for  
>> GuC
>>     WOPCM related code (Chris)
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v7)
>> Signed-off-by: Jackie Li <yaodong.li@intel.com>
> Minor change in function comment needed below as per kernel-doc format.
> Otherwise, change is good.
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/Makefile          |  1 +
>>   drivers/gpu/drm/i915/intel_guc.c       | 11 --------
>>   drivers/gpu/drm/i915/intel_guc.h       |  2 +-
>>   drivers/gpu/drm/i915/intel_guc_reg.h   |  4 ---
>>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 46  
>> ++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_guc_wopcm.h | 39  
>> ++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_uc.c        |  2 +-
>>   drivers/gpu/drm/i915/intel_uc_fw.c     |  2 +-
>>   8 files changed, 89 insertions(+), 18 deletions(-)
>>   create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
>>   create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile  
>> b/drivers/gpu/drm/i915/Makefile
>> index 3bddd8a..1dc9988 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -88,6 +88,7 @@ i915-y += intel_uc.o \
>>   	  intel_guc_fw.o \
>>   	  intel_guc_log.o \
>>   	  intel_guc_submission.o \
>> +	  intel_guc_wopcm.o \
>>   	  intel_huc.o
>>     # autogenerated null render state
>> diff --git a/drivers/gpu/drm/i915/intel_guc.c  
>> b/drivers/gpu/drm/i915/intel_guc.c
>> index 21140cc..9f45e6d 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>> @@ -509,14 +509,3 @@ struct i915_vma *intel_guc_allocate_vma(struct  
>> intel_guc *guc, u32 size)
>>   	i915_gem_object_put(obj);
>>   	return vma;
>>   }
>> -
>> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
>> -{
>> -	u32 wopcm_size = GUC_WOPCM_TOP;
>> -
>> -	/* On BXT, the top of WOPCM is reserved for RC6 context */
>> -	if (IS_GEN9_LP(dev_priv))
>> -		wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
>> -
>> -	return wopcm_size;
>> -}
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
>> b/drivers/gpu/drm/i915/intel_guc.h
>> index 52856a9..9e0a97e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -31,6 +31,7 @@
>>   #include "intel_guc_ct.h"
>>   #include "intel_guc_log.h"
>>   #include "intel_guc_reg.h"
>> +#include "intel_guc_wopcm.h"
>>   #include "intel_uc_fw.h"
>>   #include "i915_vma.h"
>>   @@ -130,6 +131,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32  
>> rsa_offset);
>>   int intel_guc_suspend(struct drm_i915_private *dev_priv);
>>   int intel_guc_resume(struct drm_i915_private *dev_priv);
>>   struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
>> size);
>> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>>     #endif
>> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h  
>> b/drivers/gpu/drm/i915/intel_guc_reg.h
>> index 19a9247..1f52fb8 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
>> @@ -68,7 +68,6 @@
>>   #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>>   #define   HUC_LOADING_AGENT_VCR		  (0<<1)
>>   #define   HUC_LOADING_AGENT_GUC		  (1<<1)
>> -#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
>>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>>     #define HUC_STATUS2             _MMIO(0xD3B0)
>> @@ -76,9 +75,6 @@
>>     /* Defines WOPCM space available to GuC firmware */
>>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
>> -/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>> -#define   GUC_WOPCM_TOP			  (0x80 << 12)	/* 512KB */
>> -#define   BXT_GUC_WOPCM_RC6_RESERVED	  (0x10 << 12)	/* 64KB  */
>>     /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT  
>> */
>>   #define GUC_GGTT_TOP			0xFEE00000
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> new file mode 100644
>> index 0000000..73be9af
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> @@ -0,0 +1,46 @@
>> +/*
>> + * Copyright © 2017 Intel Corporation

2017-2018

>> + *
>> + * Permission is hereby granted, free of charge, to any person  
>> obtaining a
>> + * copy of this software and associated documentation files (the  
>> "Software"),
>> + * to deal in the Software without restriction, including without  
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,  
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom  
>> the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including  
>> the next
>> + * paragraph) shall be included in all copies or substantial portions  
>> of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,  
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF  
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT  
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES  
>> OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,  
>> ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER  
>> DEALINGS
>> + * IN THE SOFTWARE.

Hmm, recently there was a discussion about using SPDX identifiers, so  
maybe:

+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2017-2018 Intel Corporation
+ */

>> + *
>> + */
>> +
>> +#include "intel_guc_wopcm.h"
>> +#include "i915_drv.h"
>> +
>> +/*
> Should be "/**"
>> + * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
>> + * @guc: intel guc.
>> + *
>> + * Get the platform specific GuC WOPCM size.
>> + *
>> + * Return: size of the GuC WOPCM.
>> + */
>> +u32 intel_guc_wopcm_size(struct intel_guc *guc)
>> +{
>> +	struct drm_i915_private *i915 = guc_to_i915(guc);
>> +	u32 size = GUC_WOPCM_TOP;
>> +
>> +	/* On BXT, the top of WOPCM is reserved for RC6 context */
>> +	if (IS_GEN9_LP(i915))
>> +		size -= BXT_GUC_WOPCM_RC6_RESERVED;
>> +
>> +	return size;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> new file mode 100644
>> index 0000000..53de931
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> @@ -0,0 +1,39 @@
>> +/*
>> + * Copyright © 2017 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person  
>> obtaining a
>> + * copy of this software and associated documentation files (the  
>> "Software"),
>> + * to deal in the Software without restriction, including without  
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute,  
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom  
>> the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including  
>> the next
>> + * paragraph) shall be included in all copies or substantial portions  
>> of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,  
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF  
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT  
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES  
>> OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,  
>> ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER  
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */

Use SPDX here too

>> +
>> +#ifndef _INTEL_GUC_WOPCM_H_
>> +#define _INTEL_GUC_WOPCM_H_
>> +
>> +#include <linux/types.h>
>> +
>> +struct intel_guc;
>> +
>> +#define GUC_WOPCM_OFFSET_VALUE		0x80000	/* 512KB */

a) maybe we can write it as (512 * 1024) to avoid need for comment ?
b) is this value related somehow to GUC_WOPCM_TOP defined below ?
c) if not add description

>> +/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>> +#define GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>> +#define BXT_GUC_WOPCM_RC6_RESERVED	(0x10 << 12)	/* 64KB  */
>> +
>> +u32 intel_guc_wopcm_size(struct intel_guc *guc);
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 9f1bac6..1b2831b 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -340,7 +340,7 @@ int intel_uc_init_hw(struct drm_i915_private  
>> *dev_priv)
>>   	gen9_reset_guc_interrupts(dev_priv);
>>     	/* init WOPCM */
>> -	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>> +	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
>>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>>   		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
>>   diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c  
>> b/drivers/gpu/drm/i915/intel_uc_fw.c
>> index 784eff9..24945cf 100644
>> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
>> @@ -97,7 +97,7 @@ void intel_uc_fw_fetch(struct drm_i915_private  
>> *dev_priv,
>>     	/* Header and uCode will be loaded to WOPCM */
>>   	size = uc_fw->header_size + uc_fw->ucode_size;
>> -	if (size > intel_guc_wopcm_size(dev_priv)) {
>> +	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {

Hmm, I hope this will be moved to GuC specific loader or completely removed
in future patch as "uc" functions shall not use "guc" specific functions.

>>   		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
>>   			 intel_uc_fw_type_repr(uc_fw->type));
>>   		err = -E2BIG;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size
  2018-02-06  6:20   ` Sagar Arun Kamble
@ 2018-02-06 22:25     ` Michal Wajdeczko
  2018-02-07  4:51       ` Yaodong Li
  0 siblings, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2018-02-06 22:25 UTC (permalink / raw)
  To: Jackie Li, intel-gfx, Sagar Arun Kamble; +Cc: Sujaritha Sundaresan

On Tue, 06 Feb 2018 07:20:41 +0100, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

> change looks good to me. minor updates suggested with r-b.
>
>
> On 2/6/2018 5:32 AM, Jackie Li wrote:
>> Hardware may have specific restrictions on GuC WOPCM offset and size. On
>> Gen9, the value of the GuC WOPCM size register needs to be larger than  
>> the
>> value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for
>> reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size
>> will lead to GuC firmware execution failures.
> Add below line here?
>
> Second restriction is for Gen9 and Gen10 and it is w.r.t. HuC firmware  
> size as per which "GuC WOPCM size - 16K" should
> be greater than or equal to HuC firmware size.
>> So we need add code to verify
>> the GuC WOPCM offset and size to avoid any GuC failures. On the other  
>> hand,
>> with current static GuC WOPCM offset and size values (512KB for both  
>> offset
>> and size), the GuC WOPCM size verification will fail on Gen9 even if it  
>> can
>> be fixed by lowering the GuC WOPCM offset by calculating its value  
>> based on
>> HuC firmware size (which is likely less than 200KB on Gen9), so that we  
>> can
>> have a GuC WOPCM size value which is large enough to pass the GuC WOPCM
>> size check.
>>
>> This patch updates the reserved GuC WOPCM size for RC6 context on Gen9  
>> to
>> 24KB to strictly align with the Gen9 GuC WOPCM layout. It also adds  
>> support
>> to verify the GuC WOPCM size aganist the Gen9 hardware restrictions.
>> Meanwhile, it provides a common way to calculate GuC WOPCM offset and  
>> size
>> based on GuC and HuC firmware sizes for all GuC/HuC enabled platforms.
>> Currently, GuC WOPCM offset is calculated based on HuC firmware size +
>> reserved WOPCM size while GuC WOPCM size is set to total WOPCM size -  
>> GuC
>> WOPCM offset - reserved RC6CTX size. In this case, GuC WOPCM offset  
>> will be
>> updated based on the size of HuC firmware while GuC WOPCM size will be  
>> set
>> to use all the remaining WOPCM space.
>>
>> v2:
>>   - Removed intel_wopcm_init (Ville/Sagar/Joonas)
>>   - Renamed and Moved the intel_wopcm_partition into intel_guc (Sagar)
>>   - Removed unnecessary function calls (Joonas)
>>   - Init GuC WOPCM partition as soon as firmware fetching is completed
>>
>> v3:
>>   - Fixed indentation issues (Chris)
>>   - Removed layering violation code (Chris/Michal)
>>   - Created separat files for GuC wopcm code  (Michal)
>>   - Used inline function to avoid code duplication (Michal)
>>
>> v4:
>>   - Preset the GuC WOPCM top during early GuC init (Chris)
>>   - Fail intel_uc_init_hw() as soon as GuC WOPCM partitioning failed
>>
>> v5:
>>   - Moved GuC DMA WOPCM register updating code into intel_guc_wopcm.c
>>   - Took care of the locking status before writing to GuC DMA
>>     Write-Once registers. (Joonas)
>>
>> v6:
>>   - Made sure the GuC WOPCM size to be multiple of 4K (4K aligned)
>>
>> v8:
>>   - Updated comments and fixed naming issues (Sagar/Joonas)
>>   - Updated commit message to include more description about the  
>> hardware
>>     restriction on GuC WOPCM size (Sagar)
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: John Spotswood <john.a.spotswood@intel.com>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Signed-off-by: Jackie Li <yaodong.li@intel.com>
>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem_context.c |   5 +-
>>   drivers/gpu/drm/i915/intel_guc.c        |   5 +-
>>   drivers/gpu/drm/i915/intel_guc.h        |  12 ++--
>>   drivers/gpu/drm/i915/intel_guc_wopcm.c  | 116  
>> +++++++++++++++++++++++++++++---
>>   drivers/gpu/drm/i915/intel_guc_wopcm.h  |  66 ++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_huc.c        |   2 +-
>>   drivers/gpu/drm/i915/intel_uc.c         |  11 ++-
>>   drivers/gpu/drm/i915/intel_uc_fw.c      |  11 ++-
>>   drivers/gpu/drm/i915/intel_uc_fw.h      |  16 +++++
>>   9 files changed, 213 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c  
>> b/drivers/gpu/drm/i915/i915_gem_context.c
>> index 648e753..546404e 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> @@ -312,12 +312,13 @@ __create_hw_context(struct drm_i915_private  
>> *dev_priv,
>>   	ctx->desc_template =
>>   		default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>>   -	/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC  
>> is not
>> +	/*
>> +	 * GuC requires the ring to be placed above GuC WOPCM top. If GuC is  
>> not
>>   	 * present or not in use we still need a small bias as ring  
>> wraparound
>>   	 * at offset 0 sometimes hangs. No idea why.
>>   	 */
>>   	if (USES_GUC(dev_priv))
>> -		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
>> +		ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;

I know that Joonas was against using extra inline function to read
value of "guc.wopcm.top" but maybe we should discuss it again as
now we maybe using invalid/unset value since now we are not verifying
"guc->wopcm.valid" flag.

>>   	else
>>   		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
>>   diff --git a/drivers/gpu/drm/i915/intel_guc.c  
>> b/drivers/gpu/drm/i915/intel_guc.c
>> index d9bc2a9..ecd5da2 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>> @@ -65,6 +65,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>>   	intel_guc_fw_init_early(guc);
>>   	intel_guc_ct_init_early(&guc->ct);
>>   	intel_guc_log_init_early(guc);
>> +	intel_guc_wopcm_init_early(&guc->wopcm);
>>     	mutex_init(&guc->send_mutex);
>>   	guc->send = intel_guc_send_nop;
>> @@ -478,7 +479,7 @@ int intel_guc_resume(struct drm_i915_private  
>> *dev_priv)
>>    * This is a wrapper to create an object for use with the GuC. In  
>> order to
>>    * use it inside the GuC, an object needs to be pinned lifetime, so  
>> we allocate
>>    * both some backing storage and a range inside the Global GTT. We  
>> must pin
>> - * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because  
>> that
>> + * it in the GGTT somewhere other than than [0, GuC WOPCM top) because  
>> that
>>    * range is reserved inside GuC.
>>    *
>>    * Return:	A i915_vma if successful, otherwise an ERR_PTR.
>> @@ -499,7 +500,7 @@ struct i915_vma *intel_guc_allocate_vma(struct  
>> intel_guc *guc, u32 size)
>>   		goto err;
>>     	ret = i915_vma_pin(vma, 0, PAGE_SIZE,
>> -			   PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +			   PIN_GLOBAL | PIN_OFFSET_BIAS | guc->wopcm.top);
>>   	if (ret) {
>>   		vma = ERR_PTR(ret);
>>   		goto err;
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
>> b/drivers/gpu/drm/i915/intel_guc.h
>> index 50be6de..06f315e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -49,6 +49,7 @@ struct intel_guc {
>>   	struct intel_uc_fw fw;
>>   	struct intel_guc_log log;
>>   	struct intel_guc_ct ct;
>> +	struct intel_guc_wopcm wopcm;
>>     	/* Log snapshot if GuC errors during load */
>>   	struct drm_i915_gem_object *load_err_log;
>> @@ -109,10 +110,10 @@ static inline void intel_guc_notify(struct  
>> intel_guc *guc)
>>    * @guc: intel guc.
>>    * @vma: i915 graphics virtual memory area.
>>    *
>> - * GuC does not allow any gfx GGTT address that falls into range [0,  
>> WOPCM_TOP),
>> - * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top  
>> address is
>> - * 512K. In order to exclude 0-512K address space from GGTT, all gfx  
>> objects
>> - * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
>> + * GuC does not allow any gfx GGTT address that falls into range
>> + * [0, GuC WOPCM top), which is reserved for Boot ROM, SRAM and WOPCM.
>> + * All gfx objects used by GuC is pinned with PIN_OFFSET_BIAS along  
>> with
>> + * top of WOPCM.
>>    *
>>    * Return: GGTT offset that meets the GuC gfx address requirement.
>>    */
>> @@ -121,7 +122,8 @@ static inline u32 intel_guc_ggtt_offset(struct  
>> intel_guc *guc,
>>   {
>>   	u32 offset = i915_ggtt_offset(vma);
>>   -	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
>> +	GEM_BUG_ON(!guc->wopcm.valid);
>> +	GEM_BUG_ON(offset < guc->wopcm.top);
>>   	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>>     	return offset;
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> index 73be9af..1555e79 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> @@ -25,22 +25,116 @@
>>   #include "intel_guc_wopcm.h"
>>   #include "i915_drv.h"
>>   -/*
>> - * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
>> +static inline u32 guc_reserved_wopcm_size(struct intel_guc *guc)
>> +{
>> +	struct drm_i915_private *i915 = guc_to_i915(guc);
>> +
>> +	if (IS_GEN9_LP(i915))
>> +		return BXT_GUC_WOPCM_RC6_RESERVED;
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int gen9_guc_wopcm_size_check(struct drm_i915_private  
>> *i915)

maybe it would be better to pass "wopcm" instead of "i915" ?

>> +{
>> +	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
> use variable name as guc_wopcm?
>> +	u32 guc_wopcm_start;
>> +	u32 delta;
>> +
>> +	/*
>> +	 * GuC WOPCM size is at least 4 bytes larger than the offset from  
>> WOPCM

Either use 4B directly below (as you give explanation here) or move that
comment near the definition of GEN9_GUC_WOPCM_DELTA.

>> +	 * base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET) due
>> +	 * to hardware limitation on Gen9.
>> +	 */
>> +	guc_wopcm_start = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
>> +	if (unlikely(guc_wopcm_start > wopcm->size))
>> +		return -E2BIG;
>> +
>> +	delta = wopcm->size - guc_wopcm_start;
>> +	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
>> +		return -E2BIG;
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int guc_wopcm_check_hw_restrictions(struct intel_guc  
>> *guc)
>> +{
>> +	struct drm_i915_private *i915 = guc_to_i915(guc);
>> +
>> +	if (IS_GEN9(i915))
>> +		return gen9_guc_wopcm_size_check(i915);

please use function name that matches dispatcher function

guc_wopcm_check_hw_restrictions()
gen9_guc_wopcm_check_hw_restrictions()

or

guc_wopcm_size_check()
gen9_guc_wopcm_size_check()

>> +
>> +	return 0;
>> +}
>> +
>> +/**
>> + * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
> remove extra "."
>>    * @guc: intel guc.
>> + * @guc_fw_size: size of GuC firmware.
>> + * @huc_fw_size: size of HuC firmware.
>>    *
>> - * Get the platform specific GuC WOPCM size.
>> + * Calculate the GuC WOPCM offset and size based on GuC and HuC  
>> firmware sizes.
>> + * This function will to set the GuC WOPCM size to the size of maximum  
>> WOPCM
> remove "to"
>> + * available for GuC. This function will also enforce platform  
>> dependent
>> + * hardware restrictions on GuC WOPCM offset and size. It will fail  
>> the GuC
>> + * WOPCM init if any of these checks were failed, so that the  
>> following GuC
>> + * firmware uploading would be aborted.
>>    *
>> - * Return: size of the GuC WOPCM.
>> + * Return: 0 on success, non-zero error code on failure.
>>    */
>> -u32 intel_guc_wopcm_size(struct intel_guc *guc)

Hmm, it looks that all your changes for this function from patch 2/6
are now lost ...

>> +int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
>> +			 u32 huc_fw_size)
>>   {
>> -	struct drm_i915_private *i915 = guc_to_i915(guc);
>> -	u32 size = GUC_WOPCM_TOP;
>> +	u32 reserved = guc_reserved_wopcm_size(guc);
>> +	u32 offset, size, top;
>> +	int err;
>>   -	/* On BXT, the top of WOPCM is reserved for RC6 context */
>> -	if (IS_GEN9_LP(i915))
>> -		size -= BXT_GUC_WOPCM_RC6_RESERVED;
>> +	if (guc->wopcm.valid)
>> +		return 0;

Is there a scenario when this function will be called more than one?

>> +
>> +	if (!guc_fw_size)
>> +		return -EINVAL;

GEM_BUG_ON ?

>> +
>> +	if (reserved >= WOPCM_DEFAULT_SIZE)
>> +		return -E2BIG;

GEM_BUG_ON ?

>> +
>> +	offset = huc_fw_size + WOPCM_RESERVED_SIZE;

What's the difference between guc_reserved_wopcm_size and  
WOPCM_RESERVED_SIZE

>> +	if (offset >= WOPCM_DEFAULT_SIZE)
>> +		return -E2BIG;
>> +
>> +	/* Hardware requires GuC WOPCM offset to be 16K aligned. */
>> +	offset = ALIGN(offset, GUC_WOPCM_OFFSET_ALIGNMENT);
>> +	if ((offset + reserved) >= WOPCM_DEFAULT_SIZE)
>> +		return -E2BIG;
>> +
>> +	top = WOPCM_DEFAULT_SIZE - offset;
>> +	size = top - reserved;
>> +
>> +	/* GuC WOPCM size must be multiple of 4K pages */
>> +	size &= PAGE_MASK;
>> +
>> +	/*
>> +	 * GuC firmware size needs to be less than or equal to the size of the
>> +	 * available GuC WOPCM (total available GuC WOPCM size - reserved  
>> size).
>> +	 * Need extra 8K stack for GuC firmware.
>> +	 */
>> +	reserved = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
>> +	if ((guc_fw_size + reserved) > size)
>> +		return -E2BIG;
>> +
>> +	guc->wopcm.offset = offset;
>> +	guc->wopcm.size = size;
>> +	guc->wopcm.top = top;
>> +
>> +	/* Check platform specific restrictions */
>> +	err = guc_wopcm_check_hw_restrictions(guc);

maybe you should check HW restrictions *before* initializing the structure?

err = check_hw_restrictions(i915, offset, size, top);

>> +	if (err)
>> +		return err;
>> +
>> +	guc->wopcm.valid = 1;
>> +
>> +	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
>> +			 offset >> 10, size >> 10, top >> 10);
>>   -	return size;
>> +	return 0;
>>   }
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> index 53de931..28e4103 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> @@ -29,11 +29,67 @@
>>     struct intel_guc;
>>   -#define GUC_WOPCM_OFFSET_VALUE		0x80000	/* 512KB */
>> -/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>> -#define GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>> -#define BXT_GUC_WOPCM_RC6_RESERVED	(0x10 << 12)	/* 64KB  */
>> +/* Default WOPCM size 1MB. */
>> +#define WOPCM_DEFAULT_SIZE		(0x1 << 20)
>> +/* The initial 16KB WOPCM is reserved. */
>> +#define WOPCM_RESERVED_SIZE		(0x4000)
>>   -u32 intel_guc_wopcm_size(struct intel_guc *guc);
>> +/* GUC WOPCM offset needs to be 16KB aligned. */
>> +#define GUC_WOPCM_OFFSET_ALIGNMENT	(0x4000)
>> +/* 16KB reserved at the beginning of GuC WOPCM. */
>> +#define GUC_WOPCM_RESERVED		(0x4000)
>> +/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
>> +#define GUC_WOPCM_STACK_RESERVED	(0x2000)
>> +/* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
>> +#define BXT_GUC_WOPCM_RC6_RESERVED	(0x6000)

Please use human readable format like (24 * 1024)

>> +
>> +#define GEN9_GUC_WOPCM_DELTA		4
>> +/**
> Only "/*"
>> + * GuC WOPCM starts at 144KB (GUC_WOPCM_RESERVED + 128KB reserved for  
>> GuC
>> + * firmware loading) from GuC WOPCM offset on BXT.
>> + */
>> +#define GEN9_GUC_WOPCM_OFFSET		(0x24000)

maybe it is worth to add some drawings like below that describe all
these HW restrictions?
also as all these definitions are for private use only in guc_wopcm.c
file maybe it should be defined there?

>> +
>> +/**
>> + * intel_guc_wopcm - GuC WOPCM related settings.
>> + * @offset: GuC WOPCM offset from the WOPCM base.
>> + * @size: size of GuC WOPCM for GuC firmware.
>> + * @top: start of the non-GuC WOPCM memory.
>> + * @valid: whether this structure contains valid (1-valid, 0-invalid)  
>> info.
>> + *
>> + * We simply use this structure to track the GuC use of WOPCM. The  
>> layout of
>> + * WOPCM would be defined by writing to GuC WOPCM offset and size  
>> registers as
>> + * shown below.
>> + *
>> + * +-----------+<-- top
>> + * |###########|
>> + * +-----------+<-- size (GuC_WOPCM_SIZE register)

s/GuC_WOPCM_SIZE/GUC_WOPCM_SIZE

>> + * | GuC WOPCM |
>> + * +-----------+<-- offset (DMA_GUC_WOPCM_OFFSET register)
>> + * |###########|
>> + * +-----------+<-- WOPCM base
>> + */
>> +struct intel_guc_wopcm {
>> +	u32 offset;
>> +	u32 size;
>> +	u32 top;
>> +	u32 valid;
>> +};
>> +
>> +/**
>> + * intel_guc_wopcm_init_early() - Early initialization of the GuC  
>> WOPCM.
>> + * @wopcm: GuC WOPCM.
> Update this name too?
>> + *
>> + * Setup the GuC WOPCM top to the top of the overall WOPCM. This will  
>> guarantee
>> + * that the allocation of the GuC accessible objects won't fall into  
>> WOPCM when
>> + * GuC partition isn't present.
>> + *
>> + */
>> +static inline void intel_guc_wopcm_init_early(struct intel_guc_wopcm  
>> *wopcm)

in other functions you use "guc" as first parameter, please be consistent.

>> +{
>> +	wopcm->top = WOPCM_DEFAULT_SIZE;
>> +}
>> +
>> +int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_size, u32  
>> huc_size);
>>     #endif
>> diff --git a/drivers/gpu/drm/i915/intel_huc.c  
>> b/drivers/gpu/drm/i915/intel_huc.c
>> index aed9c1c..dc6a6c6 100644
>> --- a/drivers/gpu/drm/i915/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/intel_huc.c
>> @@ -206,7 +206,7 @@ int intel_huc_auth(struct intel_huc *huc)
>>   		return -ENOEXEC;
>>     	vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
>> -				PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +				PIN_OFFSET_BIAS | guc->wopcm.top);
>>   	if (IS_ERR(vma)) {
>>   		ret = PTR_ERR(vma);
>>   		DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 1b2831b..2292f31 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -283,6 +283,9 @@ void intel_uc_fini_misc(struct drm_i915_private  
>> *dev_priv)
>>   int intel_uc_init(struct drm_i915_private *dev_priv)
>>   {
>>   	struct intel_guc *guc = &dev_priv->guc;
>> +	struct intel_huc *huc = &dev_priv->huc;
>> +	u32 guc_fw_size = intel_uc_fw_get_size(&guc->fw);
>> +	u32 huc_fw_size = intel_uc_fw_get_size(&huc->fw);
>>   	int ret;
>>     	if (!USES_GUC(dev_priv))
>> @@ -291,6 +294,10 @@ int intel_uc_init(struct drm_i915_private  
>> *dev_priv)
>>   	if (!HAS_GUC(dev_priv))
>>   		return -ENODEV;
>>   +	ret = intel_guc_wopcm_init(guc, guc_fw_size, huc_fw_size);
>> +	if (ret)
>> +		return ret;
>> +
>>   	ret = intel_guc_init(guc);
>>   	if (ret)
>>   		return ret;
>> @@ -340,9 +347,9 @@ int intel_uc_init_hw(struct drm_i915_private  
>> *dev_priv)
>>   	gen9_reset_guc_interrupts(dev_priv);
>>     	/* init WOPCM */
>> -	I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
>> +	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
>>   	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>> -		   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
>> +		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
>>     	/* WaEnableuKernelHeaderValidFix:skl */
>>   	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
>> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c  
>> b/drivers/gpu/drm/i915/intel_uc_fw.c
>> index 24945cf..791263a 100644
>> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
>> @@ -95,9 +95,13 @@ void intel_uc_fw_fetch(struct drm_i915_private  
>> *dev_priv,
>>   	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
>>   	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) *  
>> sizeof(u32);
>>   -	/* Header and uCode will be loaded to WOPCM */
>> +	/*
>> +	 * Header and uCode will be loaded to WOPCM
>> +	 * Only check the size against the overall available WOPCM here. Will
>> +	 * continue to check the size during WOPCM partition calculation.
>> +	 */
>>   	size = uc_fw->header_size + uc_fw->ucode_size;
>> -	if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
>> +	if (size > WOPCM_DEFAULT_SIZE) {
>>   		DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
>>   			 intel_uc_fw_type_repr(uc_fw->type));
>>   		err = -E2BIG;
>> @@ -207,6 +211,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>>   		       int (*xfer)(struct intel_uc_fw *uc_fw,
>>   				   struct i915_vma *vma))
>>   {
>> +	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
>>   	struct i915_vma *vma;
>>   	int err;
>>   @@ -230,7 +235,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>>   	}
>>     	vma = i915_gem_object_ggtt_pin(uc_fw->obj, NULL, 0, 0,
>> -				       PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
>> +				       PIN_OFFSET_BIAS | i915->guc.wopcm.top);
>>   	if (IS_ERR(vma)) {
>>   		err = PTR_ERR(vma);
>>   		DRM_DEBUG_DRIVER("%s fw ggtt-pin err=%d\n",
>> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h  
>> b/drivers/gpu/drm/i915/intel_uc_fw.h
>> index d5fd460..298d475 100644
>> --- a/drivers/gpu/drm/i915/intel_uc_fw.h
>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
>> @@ -115,6 +115,22 @@ static inline bool intel_uc_fw_is_selected(struct  
>> intel_uc_fw *uc_fw)
>>   	return uc_fw->path != NULL;
>>   }
>>   +/**
>> + * intel_uc_fw_get_size() - Get the size of the firmware.
>> + * @uc_fw: intel_uc_fw structure.
>> + *
>> + * Get the size of the firmware that will be placed in WOPCM.
>> + *
>> + * Return: Zero on invalid firmware status. actual size on success.
>> + */
>> +static inline u32 intel_uc_fw_get_size(struct intel_uc_fw *uc_fw)
>> +{
>> +	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
>> +		return 0;
>> +
>> +	return uc_fw->header_size + uc_fw->ucode_size;
>> +}
>> +
>>   void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>>   		       struct intel_uc_fw *uc_fw);
>>   int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL
  2018-02-06  6:31   ` Sagar Arun Kamble
@ 2018-02-06 22:29     ` Michal Wajdeczko
  0 siblings, 0 replies; 26+ messages in thread
From: Michal Wajdeczko @ 2018-02-06 22:29 UTC (permalink / raw)
  To: Jackie Li, intel-gfx, Sagar Arun Kamble

On Tue, 06 Feb 2018 07:31:06 +0100, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

>
>
> On 2/6/2018 5:32 AM, Jackie Li wrote:
>> CNL has its own specific reserved GuC WOPCM size and hardware  
>> restrictions
>> on GuC WOPCM size. On CNL A0 and Gen9, there's a hardware restriction  
>> that
>> requires the available GuC WOPCM size to be larger than or equal to HuC
>> firmware size.
>>
>> This patch updates GuC WOPCM init code to return the CNL specific  
>> reserved
>> GuC WOPCM size and also adds new verfication code to ensure the  
>> available
>> GuC WOPCM size to be larger than or equal to HuC firmware size on both  
>> Gen9
>> and CNL A0.
>>
>> v6:
>>   - Extended HuC FW size check against GuC WOPCM size to all
>>     Gen9 and CNL A0 platforms
>>
>> v7:
>>   - Fixed patch format issues
>>
>> v8:
>>   - Renamed variables and functions to avoid ambiguity (Joonas)
>>   - Updated commit message and comments to be more comprehensive (Sagar)
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: John Spotswood <john.a.spotswood@intel.com>
>> Cc: Jeff McGee <jeff.mcgee@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Signed-off-by: Jackie Li <yaodong.li@intel.com>
> Need to update subject as "Update WOPCM restrictions for CNL and add HuC  
> size related restriction for Gen9 and CNL A0"
> Or else breaking into two patches would have been good idea.

+1 for split

> But change looks good to me.
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 24 +++++++++++++++++++++++-
>>   drivers/gpu/drm/i915/intel_guc_wopcm.h |  2 ++
>>   2 files changed, 25 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> index 1555e79..3cba9ac 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> @@ -32,6 +32,25 @@ static inline u32 guc_reserved_wopcm_size(struct  
>> intel_guc *guc)
>>   	if (IS_GEN9_LP(i915))
>>   		return BXT_GUC_WOPCM_RC6_RESERVED;
>>   +	if (IS_GEN10(i915))
>> +		return CNL_GUC_WOPCM_RESERVED;
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int guc_wopcm_check_huc_fw_size(struct drm_i915_private  
>> *i915)
>> +{
>> +	struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
>> +	u32 huc_fw_size = intel_uc_fw_get_size(&i915->huc.fw);

HuC fw size was passed as param to intel_guc_wopcm_init() but here
you decided to read it directly ?

>> +
>> +	/*
>> +	 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
>> +	 * size to be larger than or equal to HuC firmware size. Otherwise,
>> +	 * firmware uploading would fail.
>> +	 */
>> +	if (unlikely(wopcm->size - GUC_WOPCM_RESERVED < huc_fw_size))
>> +		return -E2BIG;
>> +
>>   	return 0;
>>   }
>>   @@ -54,7 +73,7 @@ static inline int gen9_guc_wopcm_size_check(struct  
>> drm_i915_private *i915)
>>   	if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
>>   		return -E2BIG;
>>   -	return 0;
>> +	return guc_wopcm_check_huc_fw_size(i915);
>>   }
>>     static inline int guc_wopcm_check_hw_restrictions(struct intel_guc  
>> *guc)
>> @@ -64,6 +83,9 @@ static inline int  
>> guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
>>   	if (IS_GEN9(i915))
>>   		return gen9_guc_wopcm_size_check(i915);
>>   +	if (IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))
>> +		return guc_wopcm_check_huc_fw_size(i915);
>> +
>>   	return 0;
>>   }
>>   diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> index 28e4103..8c71d20a 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> @@ -42,6 +42,8 @@ struct intel_guc;
>>   #define GUC_WOPCM_STACK_RESERVED	(0x2000)
>>   /* 24KB at the end of GuC WOPCM is reserved for RC6 CTX on BXT. */
>>   #define BXT_GUC_WOPCM_RC6_RESERVED	(0x6000)
>> +/* 36KB WOPCM reserved at the end of GuC WOPCM on CNL */
>> +#define CNL_GUC_WOPCM_RESERVED		(0x9000)
>>     #define GEN9_GUC_WOPCM_DELTA		4
>>   /**
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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-06  6:39   ` Sagar Arun Kamble
@ 2018-02-06 22:56     ` Michal Wajdeczko
  2018-02-07  4:02       ` Yaodong Li
  2018-02-07  3:12     ` Yaodong Li
  1 sibling, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2018-02-06 22:56 UTC (permalink / raw)
  To: Jackie Li, intel-gfx, Sagar Arun Kamble

On Tue, 06 Feb 2018 07:39:27 +0100, Sagar Arun Kamble  
<sagar.a.kamble@intel.com> wrote:

>
>
> On 2/6/2018 5:32 AM, Jackie Li wrote:
>> GuC WOPCM registers are write-once registers. Current driver code  
>> accesses
>> these registers without checking the accessibility to these registers,  
>> this
>> will lead unpredictable driver behaviors if these registers were touch  
>> by
>> other components (such as faulty BIOS code).
>>
>> This patch moves the GuC WOPCM register updating operations into
>> intel_guc_wopcm.c and adds checks before and after the write to GuC  
>> WOPCM
>> registers to make sure the driver is in a known state before and after
>> writing to these write-once registers.
>>
>> v6:
>>   - Made sure module reloading won't bug the kernel while doing
>>     locking status checking
>>
>> v7:
>>   - Fixed patch format issues
>>
>> v8:
>>   - Fixed coding style issue on register lock bit macro definition  
>> (Sagar)
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Signed-off-by: Jackie Li <yaodong.li@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_guc.h       |  2 +-
>>   drivers/gpu/drm/i915/intel_guc_reg.h   |  2 +
>>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 93  
>> ++++++++++++++++++++++++++++++++--
>>   drivers/gpu/drm/i915/intel_guc_wopcm.h |  9 +++-
>>   drivers/gpu/drm/i915/intel_uc.c        |  5 +-
>>   5 files changed, 101 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc.h  
>> b/drivers/gpu/drm/i915/intel_guc.h
>> index 06f315e..cb1703b 100644
>> --- a/drivers/gpu/drm/i915/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>> @@ -122,7 +122,7 @@ static inline u32 intel_guc_ggtt_offset(struct  
>> intel_guc *guc,
>>   {
>>   	u32 offset = i915_ggtt_offset(vma);
>>   -	GEM_BUG_ON(!guc->wopcm.valid);
>> +	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
>>   	GEM_BUG_ON(offset < guc->wopcm.top);
>>   	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>>   diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h  
>> b/drivers/gpu/drm/i915/intel_guc_reg.h
>> index de4f78b..18cb2ef 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
>> @@ -66,6 +66,7 @@
>>   #define   UOS_MOVE			  (1<<4)
>>   #define   START_DMA			  (1<<0)
>>   #define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>> +#define   DMA_GUC_WOPCM_OFFSET_MASK	  (0xffffc000)

please define _SHIFT and use it in _MASK definition

>>   #define   HUC_LOADING_AGENT_VCR		  (0<<1)
>>   #define   HUC_LOADING_AGENT_GUC		  (1<<1)
>>   #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>> @@ -75,6 +76,7 @@
>>     /* Defines WOPCM space available to GuC firmware */
>>   #define GUC_WOPCM_SIZE			_MMIO(0xc050)
>> +#define   GUC_WOPCM_REG_LOCKED		  BIT(0)

use (1 << 0) instead

>>     #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>>   #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> index 3cba9ac..8317d9e 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>> @@ -89,6 +89,55 @@ static inline int  
>> guc_wopcm_check_hw_restrictions(struct intel_guc *guc)
>>   	return 0;
>>   }
>>   +static inline bool __reg_locked(struct drm_i915_private *dev_priv,
>> +				i915_reg_t reg)
>> +{
>> +	/* Explicitly cast the return value to bool. */
>> +	return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);

you should avoid reusing bits defined for one register in others

>> +}
>> +
>> +static inline bool guc_wopcm_locked(struct intel_guc *guc)
>> +{
>> +	struct drm_i915_private *i915 = guc_to_i915(guc);
>> +	bool size_reg_locked = __reg_locked(i915, GUC_WOPCM_SIZE);
>> +	bool offset_reg_locked = __reg_locked(i915, DMA_GUC_WOPCM_OFFSET);
>> +
>> +	return size_reg_locked && offset_reg_locked;
>> +}
>> +
>> +static inline void guc_wopcm_hw_update(struct intel_guc *guc)
>> +{
>> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>> +
>> +	/* GuC WOPCM registers should be unlocked at this point. */
>> +	GEM_BUG_ON(__reg_locked(dev_priv, GUC_WOPCM_SIZE));
>> +	GEM_BUG_ON(__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
>> +
>> +	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
>> +	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>> +		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
>> +
>> +	GEM_BUG_ON(!__reg_locked(dev_priv, GUC_WOPCM_SIZE));
>> +	GEM_BUG_ON(!__reg_locked(dev_priv, DMA_GUC_WOPCM_OFFSET));
>> +}
>> +
>> +static inline bool guc_wopcm_regs_valid(struct intel_guc *guc)
>> +{
>> +	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>> +	u32 size, offset;
>> +	bool guc_loads_huc;
>> +
>> +	/* GuC WOPCM size should be always multiple of 4K pages. */
>> +	size = I915_READ(GUC_WOPCM_SIZE) & PAGE_MASK;
>> +	offset = I915_READ(DMA_GUC_WOPCM_OFFSET);
>> +
>> +	guc_loads_huc = !!(offset & HUC_LOADING_AGENT_GUC);

please follow Chris suggestions to avoid unnecessary explicit casts

>> +	offset &= DMA_GUC_WOPCM_OFFSET_MASK;

maybe like this for easier reading:

u32 reg;

reg = I915_READ(GUC_WOPCM_SIZE);
size = reg & PAGE_MASK;

reg = I915_READ(DMA_GUC_WOPCM_OFFSET);
offset = reg & DMA_GUC_WOPCM_OFFSET_MASK;
guc_loads_huc = reg & HUC_LOADING_AGENT_GUC;

>> +
>> +	return guc_loads_huc && (size == guc->wopcm.size) &&

what if we run in !USES_HUC() mode?

>> +		(offset == guc->wopcm.offset);
>> +}
>> +
>>   /**
>>    * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
>>    * @guc: intel guc.
>> @@ -111,8 +160,7 @@ int intel_guc_wopcm_init(struct intel_guc *guc, u32  
>> guc_fw_size,
>>   	u32 offset, size, top;
>>   	int err;
>>   -	if (guc->wopcm.valid)
>> -		return 0;
>> +	GEM_BUG_ON(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID);
>>     	if (!guc_fw_size)
>>   		return -EINVAL;
>> @@ -153,10 +201,49 @@ int intel_guc_wopcm_init(struct intel_guc *guc,  
>> u32 guc_fw_size,
>>   	if (err)
>>   		return err;
>>   -	guc->wopcm.valid = 1;
>> +	guc->wopcm.flags |= INTEL_GUC_WOPCM_VALID;
>>     	DRM_DEBUG_DRIVER("GuC WOPCM offset %dKB, size %dKB, top %dKB\n",
>>   			 offset >> 10, size >> 10, top >> 10);
>>     	return 0;
>>   }
>> +
>> +/**
>> + * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers.
>> + * @guc: intel guc.
>> + *
>> + * Setup the GuC WOPCM size and offset registers with the stored  
>> values. It will
>> + * also check the registers locking status to determine whether these  
>> registers
>> + * are unlocked and can be updated.
>> + */
>> +void intel_guc_wopcm_init_hw(struct intel_guc *guc)
>> +{
>> +	bool locked = guc_wopcm_locked(guc);
>> +
>> +	GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
>> +
>> +	/*
>> +	 * Bug if driver hasn't updated the HW Registers and GuC WOPCM has  
>> been
>> +	 * locked. Return directly if WOPCM was locked and we have updated
>> +	 * the registers.
>> +	 */
>> +	if (locked) {
>> +		/*
>> +		 * Mark as updated if registers contained correct values.
>> +		 * This will happen while reloading the driver module without
>> +		 * rebooting the system.
>> +		 */
>> +		if (guc_wopcm_regs_valid(guc))
>> +			goto out;
>> +
>> +		GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_HW_UPDATED));
> We should not go ahead with uc_init_hw in this case so returning error  
> from here or
> checking wopcm.flags to abort uc_init_hw is needed with debug message.
>> +		return;
>> +	}
>> +
>> +	/* Always update registers when GuC WOPCM is not locked. */
>> +	guc_wopcm_hw_update(guc);
>> +
>> +out:
>> +	guc->wopcm.flags |= INTEL_GUC_WOPCM_HW_UPDATED;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h  
>> b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> index 8c71d20a..627f7fa 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>> @@ -52,12 +52,16 @@ struct intel_guc;
>>    */
>>   #define GEN9_GUC_WOPCM_OFFSET		(0x24000)
>>   +/* GuC WOPCM flags */
>> +#define INTEL_GUC_WOPCM_VALID		BIT(0)
>> +#define INTEL_GUC_WOPCM_HW_UPDATED	BIT(1)

maybe just

bool valid:1;
bool hw_updated:1;

>> +
>>   /**
>>    * intel_guc_wopcm - GuC WOPCM related settings.
>>    * @offset: GuC WOPCM offset from the WOPCM base.
>>    * @size: size of GuC WOPCM for GuC firmware.
>>    * @top: start of the non-GuC WOPCM memory.
>> - * @valid: whether this structure contains valid (1-valid, 0-invalid)  
>> info.
>> + * @flags: bitmap of INTEL_GUC_WOPCM_<foo>.
>>    *
>>    * We simply use this structure to track the GuC use of WOPCM. The  
>> layout of
>>    * WOPCM would be defined by writing to GuC WOPCM offset and size  
>> registers as
>> @@ -75,7 +79,7 @@ struct intel_guc_wopcm {
>>   	u32 offset;
>>   	u32 size;
>>   	u32 top;
>> -	u32 valid;
>> +	u32 flags;
>>   };
>>     /**
>> @@ -93,5 +97,6 @@ static inline void intel_guc_wopcm_init_early(struct  
>> intel_guc_wopcm *wopcm)
>>   }
>>     int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_size, u32  
>> huc_size);
>> +void intel_guc_wopcm_init_hw(struct intel_guc *guc);
>>     #endif
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 2292f31..62e85b5 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -346,10 +346,7 @@ int intel_uc_init_hw(struct drm_i915_private  
>> *dev_priv)
>>   	guc_disable_communication(guc);
>>   	gen9_reset_guc_interrupts(dev_priv);
>>   -	/* init WOPCM */
>> -	I915_WRITE(GUC_WOPCM_SIZE, guc->wopcm.size);
>> -	I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>> -		   guc->wopcm.offset | HUC_LOADING_AGENT_GUC);
>> +	intel_guc_wopcm_init_hw(guc);
>>     	/* WaEnableuKernelHeaderValidFix:skl */
>>   	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-06  6:39   ` Sagar Arun Kamble
  2018-02-06 22:56     ` Michal Wajdeczko
@ 2018-02-07  3:12     ` Yaodong Li
  1 sibling, 0 replies; 26+ messages in thread
From: Yaodong Li @ 2018-02-07  3:12 UTC (permalink / raw)
  To: Sagar Arun Kamble, intel-gfx



On 02/05/2018 10:39 PM, Sagar Arun Kamble wrote:
>> +/**
>> + * intel_guc_wopcm_init_hw() - Setup GuC WOPCM registers.
>> + * @guc: intel guc.
>> + *
>> + * Setup the GuC WOPCM size and offset registers with the stored 
>> values. It will
>> + * also check the registers locking status to determine whether 
>> these registers
>> + * are unlocked and can be updated.
>> + */
>> +void intel_guc_wopcm_init_hw(struct intel_guc *guc)
>> +{
>> +    bool locked = guc_wopcm_locked(guc);
>> +
>> +    GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_VALID));
>> +
>> +    /*
>> +     * Bug if driver hasn't updated the HW Registers and GuC WOPCM 
>> has been
>> +     * locked. Return directly if WOPCM was locked and we have updated
>> +     * the registers.
>> +     */
>> +    if (locked) {
>> +        /*
>> +         * Mark as updated if registers contained correct values.
>> +         * This will happen while reloading the driver module without
>> +         * rebooting the system.
>> +         */
>> +        if (guc_wopcm_regs_valid(guc))
>> +            goto out;
>> +
>> +        GEM_BUG_ON(!(guc->wopcm.flags & INTEL_GUC_WOPCM_HW_UPDATED));
> We should not go ahead with uc_init_hw in this case so returning error 
> from here or
> checking wopcm.flags to abort uc_init_hw is needed with debug message.
In a second thought, I think we need do more work here to check whether the
locked values are sufficient for current fw sizes. if yes then return 
success else
fail the wopcm init.
I agree we only check the status and return the control to uc_init_hw.

Thanks & Regards,
-Jackie

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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files
  2018-02-06 21:11   ` Michal Wajdeczko
@ 2018-02-07  3:23     ` Yaodong Li
  0 siblings, 0 replies; 26+ messages in thread
From: Yaodong Li @ 2018-02-07  3:23 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-gfx, Sagar Arun Kamble



On 02/06/2018 01:11 PM, Michal Wajdeczko wrote:
> On Tue, 06 Feb 2018 06:15:54 +0100, Sagar Arun Kamble 
> <sagar.a.kamble@intel.com> wrote:
>
>>
>> On 2/6/2018 5:32 AM, Jackie Li wrote:
>>> intel_guc_reg.h should only include definition for GuC registers and
>>> related register bits. Non-register related GuC WOPCM macro definitions
>>> should not be defined in intel_guc_reg.h
>>>
>>> This patch creates a better file structure by moving non-register 
>>> related
>>> GuC WOPCM macro definitions into a new header intel_guc_wopcm.h and 
>>> moving
>>> GuC WOPCM related functions to a new source file intel_guc_wopcm.c as
>>> future patches will increase the complexity of determining the GuC 
>>> WOPCM
>>> offset and size.
>
> Hmm, I'm not sure that we need such low-details explanation that repeats
> filenames listed below. Maybe it can like this:
>
> "New file structure is needed as future patches will increase the
> complexity of determining the GuC WOPCM offset and size."
>
>>>
>>> v8:
>>>   - Fixed naming, coding style issues and typo in commit message 
>>> (Sagar)
>>>   - Updated commit message to explain why we need create new file 
>>> for GuC
>>>     WOPCM related code (Chris)
>>>
>>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> (v7)
>>> Signed-off-by: Jackie Li <yaodong.li@intel.com>
>> Minor change in function comment needed below as per kernel-doc format.
>> Otherwise, change is good.
>> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/Makefile          |  1 +
>>>   drivers/gpu/drm/i915/intel_guc.c       | 11 --------
>>>   drivers/gpu/drm/i915/intel_guc.h       |  2 +-
>>>   drivers/gpu/drm/i915/intel_guc_reg.h   |  4 ---
>>>   drivers/gpu/drm/i915/intel_guc_wopcm.c | 46 
>>> ++++++++++++++++++++++++++++++++++
>>>   drivers/gpu/drm/i915/intel_guc_wopcm.h | 39 
>>> ++++++++++++++++++++++++++++
>>>   drivers/gpu/drm/i915/intel_uc.c        |  2 +-
>>>   drivers/gpu/drm/i915/intel_uc_fw.c     |  2 +-
>>>   8 files changed, 89 insertions(+), 18 deletions(-)
>>>   create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.c
>>>   create mode 100644 drivers/gpu/drm/i915/intel_guc_wopcm.h
>>>
>>> diff --git a/drivers/gpu/drm/i915/Makefile 
>>> b/drivers/gpu/drm/i915/Makefile
>>> index 3bddd8a..1dc9988 100644
>>> --- a/drivers/gpu/drm/i915/Makefile
>>> +++ b/drivers/gpu/drm/i915/Makefile
>>> @@ -88,6 +88,7 @@ i915-y += intel_uc.o \
>>>         intel_guc_fw.o \
>>>         intel_guc_log.o \
>>>         intel_guc_submission.o \
>>> +      intel_guc_wopcm.o \
>>>         intel_huc.o
>>>     # autogenerated null render state
>>> diff --git a/drivers/gpu/drm/i915/intel_guc.c 
>>> b/drivers/gpu/drm/i915/intel_guc.c
>>> index 21140cc..9f45e6d 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc.c
>>> +++ b/drivers/gpu/drm/i915/intel_guc.c
>>> @@ -509,14 +509,3 @@ struct i915_vma *intel_guc_allocate_vma(struct 
>>> intel_guc *guc, u32 size)
>>>       i915_gem_object_put(obj);
>>>       return vma;
>>>   }
>>> -
>>> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
>>> -{
>>> -    u32 wopcm_size = GUC_WOPCM_TOP;
>>> -
>>> -    /* On BXT, the top of WOPCM is reserved for RC6 context */
>>> -    if (IS_GEN9_LP(dev_priv))
>>> -        wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
>>> -
>>> -    return wopcm_size;
>>> -}
>>> diff --git a/drivers/gpu/drm/i915/intel_guc.h 
>>> b/drivers/gpu/drm/i915/intel_guc.h
>>> index 52856a9..9e0a97e 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc.h
>>> +++ b/drivers/gpu/drm/i915/intel_guc.h
>>> @@ -31,6 +31,7 @@
>>>   #include "intel_guc_ct.h"
>>>   #include "intel_guc_log.h"
>>>   #include "intel_guc_reg.h"
>>> +#include "intel_guc_wopcm.h"
>>>   #include "intel_uc_fw.h"
>>>   #include "i915_vma.h"
>>>   @@ -130,6 +131,5 @@ int intel_guc_auth_huc(struct intel_guc *guc, 
>>> u32 rsa_offset);
>>>   int intel_guc_suspend(struct drm_i915_private *dev_priv);
>>>   int intel_guc_resume(struct drm_i915_private *dev_priv);
>>>   struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
>>> size);
>>> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
>>>     #endif
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h 
>>> b/drivers/gpu/drm/i915/intel_guc_reg.h
>>> index 19a9247..1f52fb8 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
>>> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
>>> @@ -68,7 +68,6 @@
>>>   #define DMA_GUC_WOPCM_OFFSET        _MMIO(0xc340)
>>>   #define   HUC_LOADING_AGENT_VCR          (0<<1)
>>>   #define   HUC_LOADING_AGENT_GUC          (1<<1)
>>> -#define   GUC_WOPCM_OFFSET_VALUE      0x80000    /* 512KB */
>>>   #define GUC_MAX_IDLE_COUNT        _MMIO(0xC3E4)
>>>     #define HUC_STATUS2             _MMIO(0xD3B0)
>>> @@ -76,9 +75,6 @@
>>>     /* Defines WOPCM space available to GuC firmware */
>>>   #define GUC_WOPCM_SIZE            _MMIO(0xc050)
>>> -/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>>> -#define   GUC_WOPCM_TOP              (0x80 << 12)    /* 512KB */
>>> -#define   BXT_GUC_WOPCM_RC6_RESERVED      (0x10 << 12)    /* 64KB  */
>>>     /* GuC addresses above GUC_GGTT_TOP also don't map through the 
>>> GTT */
>>>   #define GUC_GGTT_TOP            0xFEE00000
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.c 
>>> b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>>> new file mode 100644
>>> index 0000000..73be9af
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
>>> @@ -0,0 +1,46 @@
>>> +/*
>>> + * Copyright © 2017 Intel Corporation
>
> 2017-2018
>
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person 
>>> obtaining a
>>> + * copy of this software and associated documentation files (the 
>>> "Software"),
>>> + * to deal in the Software without restriction, including without 
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, 
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to 
>>> whom the
>>> + * Software is furnished to do so, subject to the following 
>>> conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including 
>>> the next
>>> + * paragraph) shall be included in all copies or substantial 
>>> portions of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
>>> EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, 
>>> DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
>>> ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 
>>> OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>
> Hmm, recently there was a discussion about using SPDX identifiers, so 
> maybe:
>
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2017-2018 Intel Corporation
> + */
>
Thanks for the heads up, will update it.
>>> + *
>>> + */
>>> +
>>> +#include "intel_guc_wopcm.h"
>>> +#include "i915_drv.h"
>>> +
>>> +/*
>> Should be "/**"
>>> + * intel_guc_wopcm_size() - Get the size of GuC WOPCM.
>>> + * @guc: intel guc.
>>> + *
>>> + * Get the platform specific GuC WOPCM size.
>>> + *
>>> + * Return: size of the GuC WOPCM.
>>> + */
>>> +u32 intel_guc_wopcm_size(struct intel_guc *guc)
>>> +{
>>> +    struct drm_i915_private *i915 = guc_to_i915(guc);
>>> +    u32 size = GUC_WOPCM_TOP;
>>> +
>>> +    /* On BXT, the top of WOPCM is reserved for RC6 context */
>>> +    if (IS_GEN9_LP(i915))
>>> +        size -= BXT_GUC_WOPCM_RC6_RESERVED;
>>> +
>>> +    return size;
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_wopcm.h 
>>> b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>>> new file mode 100644
>>> index 0000000..53de931
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_guc_wopcm.h
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * Copyright © 2017 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person 
>>> obtaining a
>>> + * copy of this software and associated documentation files (the 
>>> "Software"),
>>> + * to deal in the Software without restriction, including without 
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, 
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to 
>>> whom the
>>> + * Software is furnished to do so, subject to the following 
>>> conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including 
>>> the next
>>> + * paragraph) shall be included in all copies or substantial 
>>> portions of the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
>>> EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, 
>>> DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
>>> ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 
>>> OTHER DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + */
>
> Use SPDX here too
>
>>> +
>>> +#ifndef _INTEL_GUC_WOPCM_H_
>>> +#define _INTEL_GUC_WOPCM_H_
>>> +
>>> +#include <linux/types.h>
>>> +
>>> +struct intel_guc;
>>> +
>>> +#define GUC_WOPCM_OFFSET_VALUE        0x80000    /* 512KB */
>
> a) maybe we can write it as (512 * 1024) to avoid need for comment ?
I prefer to keep it as 0x80000 to avoid some extra calculation.
> b) is this value related somehow to GUC_WOPCM_TOP defined below ?
> c) if not add description
>
it's a static value we currently use in code.
>>> +/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
>>> +#define GUC_WOPCM_TOP            (0x80 << 12)    /* 512KB */
>>> +#define BXT_GUC_WOPCM_RC6_RESERVED    (0x10 << 12) /* 64KB  */
>>> +
>>> +u32 intel_guc_wopcm_size(struct intel_guc *guc);
>>> +
>>> +#endif
>>> diff --git a/drivers/gpu/drm/i915/intel_uc.c 
>>> b/drivers/gpu/drm/i915/intel_uc.c
>>> index 9f1bac6..1b2831b 100644
>>> --- a/drivers/gpu/drm/i915/intel_uc.c
>>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>>> @@ -340,7 +340,7 @@ int intel_uc_init_hw(struct drm_i915_private 
>>> *dev_priv)
>>>       gen9_reset_guc_interrupts(dev_priv);
>>>         /* init WOPCM */
>>> -    I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
>>> +    I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
>>>       I915_WRITE(DMA_GUC_WOPCM_OFFSET,
>>>              GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
>>>   diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c 
>>> b/drivers/gpu/drm/i915/intel_uc_fw.c
>>> index 784eff9..24945cf 100644
>>> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
>>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
>>> @@ -97,7 +97,7 @@ void intel_uc_fw_fetch(struct drm_i915_private 
>>> *dev_priv,
>>>         /* Header and uCode will be loaded to WOPCM */
>>>       size = uc_fw->header_size + uc_fw->ucode_size;
>>> -    if (size > intel_guc_wopcm_size(dev_priv)) {
>>> +    if (size > intel_guc_wopcm_size(&dev_priv->guc)) {
>
> Hmm, I hope this will be moved to GuC specific loader or completely 
> removed
> in future patch as "uc" functions shall not use "guc" specific functions.
>
Actually, I've already had some new thoughts about this. Will submit new 
patches later:-)
>>>           DRM_WARN("%s: Firmware is too large to fit in WOPCM\n",
>>>                intel_uc_fw_type_repr(uc_fw->type));
>>>           err = -E2BIG;

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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-06 22:56     ` Michal Wajdeczko
@ 2018-02-07  4:02       ` Yaodong Li
  2018-02-07 17:24         ` Michal Wajdeczko
  0 siblings, 1 reply; 26+ messages in thread
From: Yaodong Li @ 2018-02-07  4:02 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-gfx, Sagar Arun Kamble



On 02/06/2018 02:56 PM, Michal Wajdeczko wrote:

>>> +    /* Explicitly cast the return value to bool. */
>>> +    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);
>
> you should avoid reusing bits defined for one register in others
>
it's a common bit. use BIT(0) instead?
>
>
>>> +    offset &= DMA_GUC_WOPCM_OFFSET_MASK;
>
> maybe like this for easier reading:
>
> u32 reg;
>
> reg = I915_READ(GUC_WOPCM_SIZE);
> size = reg & PAGE_MASK;
>
> reg = I915_READ(DMA_GUC_WOPCM_OFFSET);
> offset = reg & DMA_GUC_WOPCM_OFFSET_MASK;
hmm, this will clear the HUC_LOADING_AGENT_GUC.
> guc_loads_huc = reg & HUC_LOADING_AGENT_GUC;
>
>>> +
>>> +    return guc_loads_huc && (size == guc->wopcm.size) &&
>
> what if we run in !USES_HUC() mode?
>
Do you mean the HUC_LOADING_AGENT bit?

this patch series is trying to align with the current driver logic. this bit
is current set regardless USES_HUC()

Are you suggest we should not set this bit for !USE_HUC() mode?
>>> +        (offset == guc->wopcm.offset);
>>>   #define GEN9_GUC_WOPCM_OFFSET        (0x24000)
>>>   +/* GuC WOPCM flags */
>>> +#define INTEL_GUC_WOPCM_VALID        BIT(0)
>>> +#define INTEL_GUC_WOPCM_HW_UPDATED    BIT(1)
>
> maybe just
>
> bool valid:1;
> bool hw_updated:1;
>
I was trying to avoid bool in struct (really struggling with it actual 
size), maybe
u32 valid:1;
u32 hw_updated:1

Regards,
-Jackie


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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size
  2018-02-06 22:25     ` Michal Wajdeczko
@ 2018-02-07  4:51       ` Yaodong Li
  2018-02-07 17:24         ` Michal Wajdeczko
  0 siblings, 1 reply; 26+ messages in thread
From: Yaodong Li @ 2018-02-07  4:51 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-gfx, Sagar Arun Kamble; +Cc: Sujaritha Sundaresan



On 02/06/2018 02:25 PM, Michal Wajdeczko wrote:
>
>>> default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>>>   -    /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If 
>>> GuC is not
>>> +    /*
>>> +     * GuC requires the ring to be placed above GuC WOPCM top. If 
>>> GuC is not
>>>        * present or not in use we still need a small bias as ring 
>>> wraparound
>>>        * at offset 0 sometimes hangs. No idea why.
>>>        */
>>>       if (USES_GUC(dev_priv))
>>> -        ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
>>> +        ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;
>
> I know that Joonas was against using extra inline function to read
> value of "guc.wopcm.top" but maybe we should discuss it again as
> now we maybe using invalid/unset value since now we are not verifying
> "guc->wopcm.valid" flag.
>
It should be fine in this case since we have early inited the value to 
the worst
case (using the size of all WOPCM). we could not use valid here since 
uc_init
has been called at this point.
>>>
>>> +static inline int gen9_guc_wopcm_size_check(struct drm_i915_private 
>>> *i915)
>
> maybe it would be better to pass "wopcm" instead of "i915" ?
>
hmm, I think it's better to have an unified parameter list for all the 
check functions.
and it the same since we will have to get wopcm from i915 anyways.
>>> +{
>>> +    struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
>> use variable name as guc_wopcm?
>>> +    u32 guc_wopcm_start;
>>> +    u32 delta;
>>> +
>>> +    /*
>>> +     * GuC WOPCM size is at least 4 bytes larger than the offset 
>>> from WOPCM
>
> Either use 4B directly below (as you give explanation here) or move that
> comment near the definition of GEN9_GUC_WOPCM_DELTA.
>
>>> +     * base (GuC WOPCM offset from WOPCM base + 
>>> GEN9_GUC_WOPCM_OFFSET) due
>>> +     * to hardware limitation on Gen9.
>>> +     */
>>> +    guc_wopcm_start = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
>>> +    if (unlikely(guc_wopcm_start > wopcm->size))
>>> +        return -E2BIG;
>>> +
>>> +    delta = wopcm->size - guc_wopcm_start;
>>> +    if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
>>> +        return -E2BIG;
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static inline int guc_wopcm_check_hw_restrictions(struct intel_guc 
>>> *guc)
>>> +{
>>> +    struct drm_i915_private *i915 = guc_to_i915(guc);
>>> +
>>> +    if (IS_GEN9(i915))
>>> +        return gen9_guc_wopcm_size_check(i915);
>
> please use function name that matches dispatcher function
>
> guc_wopcm_check_hw_restrictions()
> gen9_guc_wopcm_check_hw_restrictions()
>
> or
>
> guc_wopcm_size_check()
> gen9_guc_wopcm_size_check()
>
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +/**
>>> + * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
>> remove extra "."
>>>    * @guc: intel guc.
>>> + * @guc_fw_size: size of GuC firmware.
>>> + * @huc_fw_size: size of HuC firmware.
>>>    *
>>> - * Get the platform specific GuC WOPCM size.
>>> + * Calculate the GuC WOPCM offset and size based on GuC and HuC 
>>> firmware sizes.
>>> + * This function will to set the GuC WOPCM size to the size of 
>>> maximum WOPCM
>> remove "to"
>>> + * available for GuC. This function will also enforce platform 
>>> dependent
>>> + * hardware restrictions on GuC WOPCM offset and size. It will fail 
>>> the GuC
>>> + * WOPCM init if any of these checks were failed, so that the 
>>> following GuC
>>> + * firmware uploading would be aborted.
>>>    *
>>> - * Return: size of the GuC WOPCM.
>>> + * Return: 0 on success, non-zero error code on failure.
>>>    */
>>> -u32 intel_guc_wopcm_size(struct intel_guc *guc)
>
> Hmm, it looks that all your changes for this function from patch 2/6
> are now lost ...
>
patch 1/6 & 2/6 are only for some code movings. but have to make it clean.
but I do not need this func anymore:o)
>>> +int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
>>> +             u32 huc_fw_size)
>>>   {
>>> -    struct drm_i915_private *i915 = guc_to_i915(guc);
>>> -    u32 size = GUC_WOPCM_TOP;
>>> +    u32 reserved = guc_reserved_wopcm_size(guc);
>>> +    u32 offset, size, top;
>>> +    int err;
>>>   -    /* On BXT, the top of WOPCM is reserved for RC6 context */
>>> -    if (IS_GEN9_LP(i915))
>>> -        size -= BXT_GUC_WOPCM_RC6_RESERVED;
>>> +    if (guc->wopcm.valid)
>>> +        return 0;
>
> Is there a scenario when this function will be called more than one?
You're right. we need not need such a check anymore.
>
>>> +
>>> +    if (!guc_fw_size)
>>> +        return -EINVAL;
>
> GEM_BUG_ON ?
>
>>> +
>>> +    if (reserved >= WOPCM_DEFAULT_SIZE)
>>> +        return -E2BIG;
>
> GEM_BUG_ON ?
Will give the control back to uc_init.?
>
>>> +
>>> +    offset = huc_fw_size + WOPCM_RESERVED_SIZE;
>
> What's the difference between guc_reserved_wopcm_size and 
> WOPCM_RESERVED_SIZE
>
WOPCM_RESERVED_SIZE is the reserved size in Non-GuC WOPCM.
>>> +    guc->wopcm.offset = offset;
>>> +    guc->wopcm.size = size;
>>> +    guc->wopcm.top = top;
>>> +
>>> +    /* Check platform specific restrictions */
>>> +    err = guc_wopcm_check_hw_restrictions(guc);
>
> maybe you should check HW restrictions *before* initializing the 
> structure?
>
> err = check_hw_restrictions(i915, offset, size, top);
Actually, I was struggling on this a bit, but it's clearer to have to 
valid bit in this
struct instead of only checking offset/size/top. And now that we have 
valid bit
it would be better to init the other fields and using less parameters 
for this function?

Regards,
-Jackie


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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-07  4:02       ` Yaodong Li
@ 2018-02-07 17:24         ` Michal Wajdeczko
  2018-02-07 19:15           ` Yaodong Li
  0 siblings, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2018-02-07 17:24 UTC (permalink / raw)
  To: intel-gfx, Sagar Arun Kamble, Yaodong Li

On Wed, 07 Feb 2018 05:02:00 +0100, Yaodong Li <yaodong.li@intel.com>  
wrote:

>
>
> On 02/06/2018 02:56 PM, Michal Wajdeczko wrote:
>
>>>> +    /* Explicitly cast the return value to bool. */
>>>> +    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);
>>
>> you should avoid reusing bits defined for one register in others
>>
> it's a common bit. use BIT(0) instead?

How common?
Note that your function accepts all registers.
Btw, even for these two registers used below bit0 has different
name definitions (Locked vs Offset Valid) which we should use.

>>
>>
>>>> +    offset &= DMA_GUC_WOPCM_OFFSET_MASK;
>>
>> maybe like this for easier reading:
>>
>> u32 reg;
>>
>> reg = I915_READ(GUC_WOPCM_SIZE);
>> size = reg & PAGE_MASK;
>>
>> reg = I915_READ(DMA_GUC_WOPCM_OFFSET);
>> offset = reg & DMA_GUC_WOPCM_OFFSET_MASK;
> hmm, this will clear the HUC_LOADING_AGENT_GUC.

that's expected

>> guc_loads_huc = reg & HUC_LOADING_AGENT_GUC;
>>
>>>> +
>>>> +    return guc_loads_huc && (size == guc->wopcm.size) &&
>>
>> what if we run in !USES_HUC() mode?
>>
> Do you mean the HUC_LOADING_AGENT bit?
>
> this patch series is trying to align with the current driver logic. this  
> bit
> is current set regardless USES_HUC()
>
> Are you suggest we should not set this bit for !USE_HUC() mode?

We can set it as before, but when we compare already initialized
registers we can ignore this bit if we're running without HuC.
It must match only if we use HuC.

>>>> +        (offset == guc->wopcm.offset);
>>>>   #define GEN9_GUC_WOPCM_OFFSET        (0x24000)
>>>>   +/* GuC WOPCM flags */
>>>> +#define INTEL_GUC_WOPCM_VALID        BIT(0)
>>>> +#define INTEL_GUC_WOPCM_HW_UPDATED    BIT(1)
>>
>> maybe just
>>
>> bool valid:1;
>> bool hw_updated:1;
>>
> I was trying to avoid bool in struct (really struggling with it actual  
> size), maybe
> u32 valid:1;
> u32 hw_updated:1

bool:1 will work the same, try it !

>
> Regards,
> -Jackie
>
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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size
  2018-02-07  4:51       ` Yaodong Li
@ 2018-02-07 17:24         ` Michal Wajdeczko
  2018-02-07 19:52           ` Yaodong Li
  0 siblings, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2018-02-07 17:24 UTC (permalink / raw)
  To: intel-gfx, Sagar Arun Kamble, Yaodong Li; +Cc: Sujaritha Sundaresan

On Wed, 07 Feb 2018 05:51:56 +0100, Yaodong Li <yaodong.li@intel.com>  
wrote:

>
>
> On 02/06/2018 02:25 PM, Michal Wajdeczko wrote:
>>
>>>> default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
>>>>   -    /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If  
>>>> GuC is not
>>>> +    /*
>>>> +     * GuC requires the ring to be placed above GuC WOPCM top. If  
>>>> GuC is not
>>>>        * present or not in use we still need a small bias as ring  
>>>> wraparound
>>>>        * at offset 0 sometimes hangs. No idea why.
>>>>        */
>>>>       if (USES_GUC(dev_priv))
>>>> -        ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
>>>> +        ctx->ggtt_offset_bias = dev_priv->guc.wopcm.top;
>>
>> I know that Joonas was against using extra inline function to read
>> value of "guc.wopcm.top" but maybe we should discuss it again as
>> now we maybe using invalid/unset value since now we are not verifying
>> "guc->wopcm.valid" flag.
>>
> It should be fine in this case since we have early inited the value to  
> the worst
> case (using the size of all WOPCM). we could not use valid here since  
> uc_init
> has been called at this point.
>>>>
>>>> +static inline int gen9_guc_wopcm_size_check(struct drm_i915_private  
>>>> *i915)
>>
>> maybe it would be better to pass "wopcm" instead of "i915" ?
>>
> hmm, I think it's better to have an unified parameter list for all the  
> check functions.
> and it the same since we will have to get wopcm from i915 anyways.

but you can still access i915 from wopcm using container_of trick.

>>>> +{
>>>> +    struct intel_guc_wopcm *wopcm = &i915->guc.wopcm;
>>> use variable name as guc_wopcm?
>>>> +    u32 guc_wopcm_start;
>>>> +    u32 delta;
>>>> +
>>>> +    /*
>>>> +     * GuC WOPCM size is at least 4 bytes larger than the offset  
>>>> from WOPCM
>>
>> Either use 4B directly below (as you give explanation here) or move that
>> comment near the definition of GEN9_GUC_WOPCM_DELTA.
>>
>>>> +     * base (GuC WOPCM offset from WOPCM base +  
>>>> GEN9_GUC_WOPCM_OFFSET) due
>>>> +     * to hardware limitation on Gen9.
>>>> +     */
>>>> +    guc_wopcm_start = wopcm->offset + GEN9_GUC_WOPCM_OFFSET;
>>>> +    if (unlikely(guc_wopcm_start > wopcm->size))
>>>> +        return -E2BIG;
>>>> +
>>>> +    delta = wopcm->size - guc_wopcm_start;
>>>> +    if (unlikely(delta < GEN9_GUC_WOPCM_DELTA))
>>>> +        return -E2BIG;
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static inline int guc_wopcm_check_hw_restrictions(struct intel_guc  
>>>> *guc)
>>>> +{
>>>> +    struct drm_i915_private *i915 = guc_to_i915(guc);
>>>> +
>>>> +    if (IS_GEN9(i915))
>>>> +        return gen9_guc_wopcm_size_check(i915);
>>
>> please use function name that matches dispatcher function
>>
>> guc_wopcm_check_hw_restrictions()
>> gen9_guc_wopcm_check_hw_restrictions()
>>
>> or
>>
>> guc_wopcm_size_check()
>> gen9_guc_wopcm_size_check()
>>
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +/**
>>>> + * intel_guc_wopcm_init() - Initialize the GuC WOPCM..
>>> remove extra "."
>>>>    * @guc: intel guc.
>>>> + * @guc_fw_size: size of GuC firmware.
>>>> + * @huc_fw_size: size of HuC firmware.
>>>>    *
>>>> - * Get the platform specific GuC WOPCM size.
>>>> + * Calculate the GuC WOPCM offset and size based on GuC and HuC  
>>>> firmware sizes.
>>>> + * This function will to set the GuC WOPCM size to the size of  
>>>> maximum WOPCM
>>> remove "to"
>>>> + * available for GuC. This function will also enforce platform  
>>>> dependent
>>>> + * hardware restrictions on GuC WOPCM offset and size. It will fail  
>>>> the GuC
>>>> + * WOPCM init if any of these checks were failed, so that the  
>>>> following GuC
>>>> + * firmware uploading would be aborted.
>>>>    *
>>>> - * Return: size of the GuC WOPCM.
>>>> + * Return: 0 on success, non-zero error code on failure.
>>>>    */
>>>> -u32 intel_guc_wopcm_size(struct intel_guc *guc)
>>
>> Hmm, it looks that all your changes for this function from patch 2/6
>> are now lost ...
>>
> patch 1/6 & 2/6 are only for some code movings. but have to make it  
> clean.
> but I do not need this func anymore:o)

so maybe part of these code movement was unnecessary, and affected
code can be replaced directly in this patch ?

>>>> +int intel_guc_wopcm_init(struct intel_guc *guc, u32 guc_fw_size,
>>>> +             u32 huc_fw_size)
>>>>   {
>>>> -    struct drm_i915_private *i915 = guc_to_i915(guc);
>>>> -    u32 size = GUC_WOPCM_TOP;
>>>> +    u32 reserved = guc_reserved_wopcm_size(guc);
>>>> +    u32 offset, size, top;
>>>> +    int err;
>>>>   -    /* On BXT, the top of WOPCM is reserved for RC6 context */
>>>> -    if (IS_GEN9_LP(i915))
>>>> -        size -= BXT_GUC_WOPCM_RC6_RESERVED;
>>>> +    if (guc->wopcm.valid)
>>>> +        return 0;
>>
>> Is there a scenario when this function will be called more than one?
> You're right. we need not need such a check anymore.
>>
>>>> +
>>>> +    if (!guc_fw_size)
>>>> +        return -EINVAL;
>>
>> GEM_BUG_ON ?
>>
>>>> +
>>>> +    if (reserved >= WOPCM_DEFAULT_SIZE)
>>>> +        return -E2BIG;
>>
>> GEM_BUG_ON ?
> Will give the control back to uc_init.?

Why?
Note that we control what guc_reserved_wopcm_size() will return
so this check is just for us, we should never fail here.

>>
>>>> +
>>>> +    offset = huc_fw_size + WOPCM_RESERVED_SIZE;
>>
>> What's the difference between guc_reserved_wopcm_size and  
>> WOPCM_RESERVED_SIZE
>>
> WOPCM_RESERVED_SIZE is the reserved size in Non-GuC WOPCM.
>>>> +    guc->wopcm.offset = offset;
>>>> +    guc->wopcm.size = size;
>>>> +    guc->wopcm.top = top;
>>>> +
>>>> +    /* Check platform specific restrictions */
>>>> +    err = guc_wopcm_check_hw_restrictions(guc);
>>
>> maybe you should check HW restrictions *before* initializing the  
>> structure?
>>
>> err = check_hw_restrictions(i915, offset, size, top);
> Actually, I was struggling on this a bit, but it's clearer to have to  
> valid bit in this
> struct instead of only checking offset/size/top. And now that we have  
> valid bit

But if check_hw_restrictions() fails we will return error and we should
never use this struct, so this 'valid' bit now seems more redundant.

> it would be better to init the other fields and using less parameters  
> for this function?

If I recall correctly x86-64 can pass 6 function parameters in registers.

Michal

>
> Regards,
> -Jackie
>
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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers
  2018-02-07 17:24         ` Michal Wajdeczko
@ 2018-02-07 19:15           ` Yaodong Li
  0 siblings, 0 replies; 26+ messages in thread
From: Yaodong Li @ 2018-02-07 19:15 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-gfx, Sagar Arun Kamble

On 02/07/2018 09:24 AM, Michal Wajdeczko wrote:
> On Wed, 07 Feb 2018 05:02:00 +0100, Yaodong Li <yaodong.li@intel.com> 
> wrote:
>
>>
>>
>> On 02/06/2018 02:56 PM, Michal Wajdeczko wrote:
>>
>>>>> +    /* Explicitly cast the return value to bool. */
>>>>> +    return !!(I915_READ(reg) & GUC_WOPCM_REG_LOCKED);
>>>
>>> you should avoid reusing bits defined for one register in others
>>>
>> it's a common bit. use BIT(0) instead?
>
> How common?
> Note that your function accepts all registers.
> Btw, even for these two registers used below bit0 has different
> name definitions (Locked vs Offset Valid) which we should use.
>
this bit suggests the w-o registers were locked, right? (I mean
no matter how we call this bit).
>>>
>>>
>>>>> +    offset &= DMA_GUC_WOPCM_OFFSET_MASK;
>>>
>>> maybe like this for easier reading:
>>>
>>> u32 reg;
>>>
>>> reg = I915_READ(GUC_WOPCM_SIZE);
>>> size = reg & PAGE_MASK;
>>>
>>> reg = I915_READ(DMA_GUC_WOPCM_OFFSET);
>>> offset = reg & DMA_GUC_WOPCM_OFFSET_MASK;
>> hmm, this will clear the HUC_LOADING_AGENT_GUC.
>
> that's expected
the values here are expected to be the same as the values
set to registers. otherwise, we need update the registers.
in the case of !USES_HUC() if we would add the change
to set HUC_LOADING_AGENT bit accordingly. we still
need such a check, right?
>
>>> guc_loads_huc = reg & HUC_LOADING_AGENT_GUC;
>>>
>>>>> +
>>>>> +    return guc_loads_huc && (size == guc->wopcm.size) &&
>>>
>>> what if we run in !USES_HUC() mode?
>>>
>> Do you mean the HUC_LOADING_AGENT bit?
>>
>> this patch series is trying to align with the current driver logic. 
>> this bit
>> is current set regardless USES_HUC()
>>
>> Are you suggest we should not set this bit for !USE_HUC() mode?
>
> We can set it as before, but when we compare already initialized
> registers we can ignore this bit if we're running without HuC.
> It must match only if we use HuC.
>
I can add these changes.
>>>>> +        (offset == guc->wopcm.offset);
>>>>>   #define GEN9_GUC_WOPCM_OFFSET        (0x24000)
>>>>>   +/* GuC WOPCM flags */
>>>>> +#define INTEL_GUC_WOPCM_VALID        BIT(0)
>>>>> +#define INTEL_GUC_WOPCM_HW_UPDATED    BIT(1)
>>>
>>> maybe just
>>>
>>> bool valid:1;
>>> bool hw_updated:1;
>>>
>> I was trying to avoid bool in struct (really struggling with it 
>> actual size), maybe
>> u32 valid:1;
>> u32 hw_updated:1
>
> bool:1 will work the same, try it !
>
I sure it's going to work:-) Just obsessed with the ideas that:
0) bool (_Bool) could be any length, but it's fine for us since we know 
the compiler and hw.
1) I cannot see any benefits for using bits definition for each flag for 
two reasons:
      a) it's won't provide any performance/code readability improvement.
      b) the struct definition would grow bigger visually and we need 
explain these are flags and
          come back to modify the struct every time we need to add more 
flags.
      One more reason:-) which may not apply here, but the beauty of use 
of flags is
      we can do flags |= (flag 1 | flag 2) once instead of flags.flag1 = 
1; flags.flag2 = 1;

So let keep it;-)? (please do let me know if I've made any nonsense 
assumptions again just like we
need explicitly cast int to bool with !! even the compiler already did so)
>>
>> Regards,
>> -Jackie
>>

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^ permalink raw reply	[flat|nested] 26+ messages in thread
* Re: [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size
  2018-02-07 17:24         ` Michal Wajdeczko
@ 2018-02-07 19:52           ` Yaodong Li
  0 siblings, 0 replies; 26+ messages in thread
From: Yaodong Li @ 2018-02-07 19:52 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-gfx, Sagar Arun Kamble; +Cc: Sujaritha Sundaresan

On 02/07/2018 09:24 AM, Michal Wajdeczko wrote:
  int guc_wopcm_check_huc_fw_size(struct guc_wopcm *wopcm, u32 huc_size)
>>>
>> patch 1/6 & 2/6 are only for some code movings. but have to make it 
>> clean.
>> but I do not need this func anymore:o)
>
> so maybe part of these code movement was unnecessary, and affected
> code can be replaced directly in this patch ?
>
That's how I did it before!:-) but I learned my lesson that I've to keep 
every change/patch
clear enough or readers will get confused;-) Actually, I was struggling 
on this a bit, but it's clearer to have to valid bit in this
>> struct instead of only checking offset/size/top. And now that we have 
>> valid bit
>
> But if check_hw_restrictions() fails we will return error and we should
> never use this struct, so this 'valid' bit now seems more redundant.
>
In current code, we do verify the ggtt offset against wopcm top in our 
current code which means
current code won't trust the fact that ggtt offset would never be used 
after uc/guc init failed.
This is the reason for this valid bit - I won't assume the ggtt_offset 
would never be called even
if the uc/guc_init returned failure either, since it would be weird if 
we don't check the valid bit
in guc_ggtt_offset() but still verify the offset against the wopcm top.

Regards,
-Jackie

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^ permalink raw reply	[flat|nested] 26+ messages in thread
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-- links below jump to the message on this page --
2018-02-06  0:02 [PATCH v8 1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Jackie Li
2018-02-06  0:02 ` [PATCH v8 2/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset Jackie Li
2018-02-06  5:21   ` Sagar Arun Kamble
2018-02-06 10:25   ` Chris Wilson
2018-02-06  0:02 ` [PATCH v8 3/6] drm/i915/guc: Implement dynamic GuC WOPCM offset and size Jackie Li
2018-02-06  6:20   ` Sagar Arun Kamble
2018-02-06 22:25     ` Michal Wajdeczko
2018-02-07  4:51       ` Yaodong Li
2018-02-07 17:24         ` Michal Wajdeczko
2018-02-07 19:52           ` Yaodong Li
2018-02-06  0:02 ` [PATCH v8 4/6] drm/i915/guc: Add dynamic GuC WOPCM offset and size support for CNL Jackie Li
2018-02-06  6:31   ` Sagar Arun Kamble
2018-02-06 22:29     ` Michal Wajdeczko
2018-02-06  0:02 ` [PATCH v8 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers Jackie Li
2018-02-06  6:39   ` Sagar Arun Kamble
2018-02-06 22:56     ` Michal Wajdeczko
2018-02-07  4:02       ` Yaodong Li
2018-02-07 17:24         ` Michal Wajdeczko
2018-02-07 19:15           ` Yaodong Li
2018-02-07  3:12     ` Yaodong Li
2018-02-06 10:29   ` Chris Wilson
2018-02-06  0:02 ` [PATCH v8 6/6] HAX Enable GuC Submission for CI Jackie Li
2018-02-06  0:25 ` ✗ Fi.CI.BAT: failure for series starting with [v8,1/6] drm/i915/guc: Move GuC WOPCM related code into separate files Patchwork
2018-02-06  5:15 ` [PATCH v8 1/6] " Sagar Arun Kamble
2018-02-06 21:11   ` Michal Wajdeczko
2018-02-07  3:23     ` Yaodong Li

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