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From: Juergen Gross <jgross@suse.com>
To: Tim Deegan <tim@xen.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
	Jan Beulich <JBeulich@suse.com>,
	xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v8 1/9] x86/xpti: avoid copying L4 page table contents when possible
Date: Tue, 24 Apr 2018 13:45:14 +0200	[thread overview]
Message-ID: <d9eaa254-3970-047b-d0b4-b3e1cfc144a3@suse.com> (raw)
In-Reply-To: <20180424103101.GA25276@deinos.phlegethon.org>

On 24/04/18 12:31, Tim Deegan wrote:
> At 07:45 +0200 on 23 Apr (1524469545), Juergen Gross wrote:
>> On 22/04/18 18:39, Tim Deegan wrote:
>>> At 19:11 +0200 on 21 Apr (1524337893), Juergen Gross wrote:
>>>> On 21/04/18 15:32, Tim Deegan wrote:
>>>>> At 09:44 +0200 on 19 Apr (1524131080), Juergen Gross wrote:
>>>>>> Another alternative would be to pass another flag to the callers to
>>>>>> signal the need for a flush. This would require quite some modifications
>>>>>> to shadow code I'd like to avoid, though. OTOH this way we could combine
>>>>>> flushing the tlb and the root page tables. Tim, any preferences?
>>>>>
>>>>> This sounds a promising direction but it should be doabl without major
>>>>> surgery to the shadow code.  The shadow code already leaves old sl4es
>>>>> visible (in TLBs) when it's safe to do so, so I think the right place
>>>>> to hook this is on the receiving side of the TLB flush IPI.  IOW as
>>>>> long as:
>>>>>  - you copy the L4 on context switch; and
>>>>>  - you copy it on the TLB flush IPI is received
>>>>> then you can rely on the existing TLB flush mechanisms to do what you need.
>>>>> And shadow doesn't have to behave differently from 'normal' PV MM.
>>>>
>>>> It is not so easy. The problem is that e.g. a page fault will flush the
>>>> TLB entry for the page in question, but it won't lead to the L4 to be
>>>> copied.
>>>
>>> Oh yes, I see; thanks for the explanation.  It might be worth copying
>>> what the hardware does here, and checking/propagating the relevant l4e
>>> in the PV pagefault handler.
>>
>> While in the long run being an interesting option I'm not sure I want
>> to go this route for 4.11. There might be nasty corner cases and I think
>> such a lazy approach is much more error prone than doing explicit
>> updates of the L4 table on the affected cpus in case of a modified
>> entry. I think we should either do the explicit call of flush_mask() in
>> shadow_set_l4e() or propagate the need for the flush up to the caller.
> 
> FWIW, I disagree -- I think that having the fault handler DTRT and
> relying on the existing, tested, TLB-flush logic is more likely to
> work than introducing a new mechanism that _also_ has to catch every
> possible l4e update.  It should touch less code and be less likely to
> break with later changes.  And I think it would be better to do it
> 'properly' now than to hope there's time to revisit it later.  That
> said, if Jan agrees that this way is OK, I'll quit grumbling and
> review the shadow parts. :)

Okay, thanks.

> I think that setting the bits in shadow_set_l4e() is better than
> having this leak out into all the callers.  I'm happy to see that the
> hunk in l4e_propagate_from_guest() has gone away too.
> 
> Please move the shadow_set_l4e() hunk up so it's just after the write,
> and before the general TLB flush logic.

Okay.

> Please move the logic into your code: the new function should take a
> domain pointer and do all the filtering itself rather than have shadow
> code be aware of what xpti is or why the domain's dirty-cpumask is
> relevant.

Okay.

> It doesn't look like there's any check limiting this to PV guests, and
> I think there should be, right?

In my newest version it already is testing that.


Juergen

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  reply	other threads:[~2018-04-24 11:45 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-18  8:30 [PATCH v8 0/9] xen/x86: various XPTI speedups Juergen Gross
2018-04-18  8:30 ` [PATCH v8 1/9] x86/xpti: avoid copying L4 page table contents when possible Juergen Gross
2018-04-18 16:12   ` Jan Beulich
     [not found]   ` <5AD76E5A02000078001BC770@suse.com>
2018-04-19  6:19     ` Juergen Gross
2018-04-19  7:39       ` Jan Beulich
     [not found]       ` <5AD847BD02000078001BC8D9@suse.com>
2018-04-19  7:44         ` Juergen Gross
2018-04-21 13:32           ` Tim Deegan
2018-04-21 17:11             ` Juergen Gross
2018-04-22 16:39               ` Tim Deegan
2018-04-23  5:45                 ` Juergen Gross
2018-04-24 10:31                   ` Tim Deegan
2018-04-24 11:45                     ` Juergen Gross [this message]
2018-04-18  8:30 ` [PATCH v8 2/9] xen/x86: add a function for modifying cr3 Juergen Gross
2018-04-18  8:30 ` [PATCH v8 3/9] xen/x86: support per-domain flag for xpti Juergen Gross
2018-04-18  9:42   ` Sergey Dyasli
2018-04-18  9:49     ` Jan Beulich
2018-04-18  9:52       ` Juergen Gross
2018-04-18  9:54     ` Juergen Gross
2018-04-18 15:29   ` Jan Beulich
     [not found]   ` <5AD7647502000078001BC6C8@suse.com>
2018-04-18 15:33     ` Juergen Gross
2018-04-18 15:45       ` Jan Beulich
     [not found]       ` <5AD7680102000078001BC725@suse.com>
2018-04-18 15:54         ` Juergen Gross
2018-04-18 16:06           ` Jan Beulich
2018-04-18  8:30 ` [PATCH v8 4/9] xen/x86: use invpcid for flushing the TLB Juergen Gross
2018-04-18  8:30 ` [PATCH v8 5/9] xen/x86: disable global pages for domains with XPTI active Juergen Gross
2018-04-18  8:30 ` [PATCH v8 6/9] xen/x86: use flag byte for decision whether xen_cr3 is valid Juergen Gross
2018-04-18  8:30 ` [PATCH v8 7/9] xen/x86: convert pv_guest_cr4_to_real_cr4() to a function Juergen Gross
2018-04-18  8:30 ` [PATCH v8 8/9] xen/x86: add some cr3 helpers Juergen Gross
2018-04-18  8:30 ` [PATCH v8 9/9] xen/x86: use PCID feature Juergen Gross
2018-04-18  9:13   ` Jan Beulich
2018-04-18  9:37     ` Juergen Gross
2018-04-18 15:32       ` Jan Beulich
     [not found]       ` <5AD7652902000078001BC6F4@suse.com>
2018-04-18 15:36         ` Juergen Gross

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