* [PATCH 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
@ 2019-09-09 3:43 ` Manasi Navare
2019-09-17 14:51 ` Maarten Lankhorst
2019-09-09 3:43 ` [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports Manasi Navare
` (9 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical tile that needs to be genlocked with
all other slave tiles.
This patch identifies saves the master transcoder in all the slave
CRTC states. This is needed to select the master CRTC/transcoder
while configuring transcoder port sync for the corresponding slaves.
v3:
* Use master_tramscoder instead of master_crtc for valid
HW state readouts (Ville)
v2:
* Move this to intel_mode_set_pipe_config(Jani N, Ville)
* Use slave_bitmask to save associated slaves in master crtc state (Ville)
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 105 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +
3 files changed, 112 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4c30672bd108..8942c905ae66 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11745,6 +11745,91 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int icl_add_sync_mode_crtcs(struct drm_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
+ struct drm_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_connector *master_connector, *connector;
+ struct drm_connector_state *connector_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc *master_crtc = NULL;
+ struct drm_crtc_state *master_crtc_state;
+ struct intel_crtc_state *master_pipe_config;
+ int i, tile_group_id;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ return 0;
+
+ /*
+ * In case of tiled displays there could be one or more slaves but there is
+ * only one master. Lets make the CRTC used by the connector corresponding
+ * to the last horizonal and last vertical tile a master/genlock CRTC.
+ * All the other CRTCs corresponding to other tiles of the same Tile group
+ * are the slave CRTCs and hold a pointer to their genlock CRTC.
+ */
+ for_each_new_connector_in_state(state, connector, connector_state, i) {
+ if (connector_state->crtc != crtc)
+ continue;
+ if (!connector->has_tile)
+ continue;
+ if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
+ crtc_state->base.mode.vdisplay != connector->tile_v_size)
+ return 0;
+ if (connector->tile_h_loc == connector->num_h_tile - 1 &&
+ connector->tile_v_loc == connector->num_v_tile - 1)
+ continue;
+ crtc_state->sync_mode_slaves_mask = 0;
+ tile_group_id = connector->tile_group->id;
+ drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ drm_for_each_connector_iter(master_connector, &conn_iter) {
+ struct drm_connector_state *master_conn_state = NULL;
+
+ if (!master_connector->has_tile)
+ continue;
+ if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
+ master_connector->tile_v_loc != master_connector->num_v_tile - 1)
+ continue;
+ if (master_connector->tile_group->id != tile_group_id)
+ continue;
+
+ master_conn_state = drm_atomic_get_connector_state(state,
+ master_connector);
+ if (IS_ERR(master_conn_state)) {
+ drm_connector_list_iter_end(&conn_iter);
+ return PTR_ERR(master_conn_state);
+ }
+ if (master_conn_state->crtc) {
+ master_crtc = master_conn_state->crtc;
+ break;
+ }
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (!master_crtc) {
+ DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
+ connector_state->crtc->base.id);
+ return -EINVAL;
+ }
+
+ master_crtc_state = drm_atomic_get_crtc_state(state,
+ master_crtc);
+ if (IS_ERR(master_crtc_state))
+ return PTR_ERR(master_crtc_state);
+
+ master_pipe_config = to_intel_crtc_state(master_crtc_state);
+ crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
+ master_pipe_config->sync_mode_slaves_mask |=
+ BIT(crtc_state->cpu_transcoder);
+ DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
+ transcoder_name(crtc_state->master_transcoder),
+ crtc_state->base.crtc->base.id,
+ master_pipe_config->sync_mode_slaves_mask);
+ }
+
+ return 0;
+}
+
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@@ -12250,6 +12335,12 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
if (IS_G4X(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
saved_state->wm = crtc_state->wm;
+ /* Save the slave bitmask which gets filled for master crtc state during
+ * slave atomic check call.
+ */
+ if (is_trans_port_sync_master(dev_priv, crtc_state))
+ saved_state->sync_mode_slaves_mask =
+ crtc_state->sync_mode_slaves_mask;
/* Keep base drm_crtc_state intact, only clear our extended struct */
BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
@@ -12343,6 +12434,15 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
CRTC_STEREO_DOUBLE);
+ /* Set the crtc_state defaults for trans_port_sync */
+ pipe_config->master_transcoder = INVALID_TRANSCODER;
+ ret = icl_add_sync_mode_crtcs(crtc, pipe_config, state);
+ if (ret) {
+ DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
+ ret);
+ return ret;
+ }
+
/* Pass our mode to the connectors and the CRTC to give them a chance to
* adjust it according to limitations or connector properties, and also
* a chance to reject the mode entirely.
@@ -12856,6 +12956,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ if (INTEL_GEN(dev_priv) >= 11) {
+ PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
+ PIPE_CONF_CHECK_I(master_transcoder);
+ }
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_BOOL
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 33fd523c4622..c1011204b407 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -91,6 +91,7 @@ enum pipe {
#define pipe_name(p) ((p) + 'A')
enum transcoder {
+ INVALID_TRANSCODER = -1,
/*
* The following transcoders have a 1:1 transcoder -> pipe mapping,
* keep their values fixed: the code assumes that TRANSCODER_A=0, the
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..17ff34ca298b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -991,6 +991,12 @@ struct intel_crtc_state {
/* Forward Error correction State */
bool fec_enable;
+
+ /* Pointer to master transcoder in case of tiled displays */
+ enum transcoder master_transcoder;
+
+ /* Bitmask to indicate slaves attached */
+ u8 sync_mode_slaves_mask;
};
struct intel_crtc {
--
2.19.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
2019-09-09 3:43 ` [PATCH 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync Manasi Navare
@ 2019-09-17 14:51 ` Maarten Lankhorst
0 siblings, 0 replies; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 14:51 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Daniel Vetter
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> In case of tiled displays when the two tiles are sent across two CRTCs
> over two separate DP SST connectors, we need a mechanism to synchronize
> the two CRTCs and their corresponding transcoders.
> So use the master-slave mode where there is one master corresponding
> to last horizontal and vertical tile that needs to be genlocked with
> all other slave tiles.
> This patch identifies saves the master transcoder in all the slave
> CRTC states. This is needed to select the master CRTC/transcoder
> while configuring transcoder port sync for the corresponding slaves.
>
> v3:
> * Use master_tramscoder instead of master_crtc for valid
> HW state readouts (Ville)
> v2:
> * Move this to intel_mode_set_pipe_config(Jani N, Ville)
> * Use slave_bitmask to save associated slaves in master crtc state (Ville)
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 105 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.h | 1 +
> .../drm/i915/display/intel_display_types.h | 6 +
> 3 files changed, 112 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4c30672bd108..8942c905ae66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11745,6 +11745,91 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> }
>
> +static int icl_add_sync_mode_crtcs(struct drm_crtc *crtc,
> + struct intel_crtc_state *crtc_state,
> + struct drm_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> + struct drm_connector *master_connector, *connector;
> + struct drm_connector_state *connector_state;
> + struct drm_connector_list_iter conn_iter;
> + struct drm_crtc *master_crtc = NULL;
> + struct drm_crtc_state *master_crtc_state;
> + struct intel_crtc_state *master_pipe_config;
> + int i, tile_group_id;
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + /*
> + * In case of tiled displays there could be one or more slaves but there is
> + * only one master. Lets make the CRTC used by the connector corresponding
> + * to the last horizonal and last vertical tile a master/genlock CRTC.
> + * All the other CRTCs corresponding to other tiles of the same Tile group
> + * are the slave CRTCs and hold a pointer to their genlock CRTC.
> + */
> + for_each_new_connector_in_state(state, connector, connector_state, i) {
> + if (connector_state->crtc != crtc)
> + continue;
> + if (!connector->has_tile)
> + continue;
> + if (crtc_state->base.mode.hdisplay != connector->tile_h_size ||
> + crtc_state->base.mode.vdisplay != connector->tile_v_size)
> + return 0;
> + if (connector->tile_h_loc == connector->num_h_tile - 1 &&
> + connector->tile_v_loc == connector->num_v_tile - 1)
> + continue;
> + crtc_state->sync_mode_slaves_mask = 0;
> + tile_group_id = connector->tile_group->id;
> + drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> + drm_for_each_connector_iter(master_connector, &conn_iter) {
> + struct drm_connector_state *master_conn_state = NULL;
> +
> + if (!master_connector->has_tile)
> + continue;
> + if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 ||
> + master_connector->tile_v_loc != master_connector->num_v_tile - 1)
> + continue;
> + if (master_connector->tile_group->id != tile_group_id)
> + continue;
> +
> + master_conn_state = drm_atomic_get_connector_state(state,
> + master_connector);
> + if (IS_ERR(master_conn_state)) {
> + drm_connector_list_iter_end(&conn_iter);
> + return PTR_ERR(master_conn_state);
> + }
> + if (master_conn_state->crtc) {
> + master_crtc = master_conn_state->crtc;
> + break;
> + }
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + if (!master_crtc) {
> + DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n",
> + connector_state->crtc->base.id);
> + return -EINVAL;
> + }
> +
> + master_crtc_state = drm_atomic_get_crtc_state(state,
> + master_crtc);
> + if (IS_ERR(master_crtc_state))
> + return PTR_ERR(master_crtc_state);
> +
> + master_pipe_config = to_intel_crtc_state(master_crtc_state);
> + crtc_state->master_transcoder = master_pipe_config->cpu_transcoder;
> + master_pipe_config->sync_mode_slaves_mask |=
> + BIT(crtc_state->cpu_transcoder);
> + DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n",
> + transcoder_name(crtc_state->master_transcoder),
> + crtc_state->base.crtc->base.id,
> + master_pipe_config->sync_mode_slaves_mask);
> + }
Ugh, no better way than a double loop? :( Probably not. Looks good.
> +
> + return 0;
> +}
> +
> static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> struct drm_crtc_state *crtc_state)
> {
> @@ -12250,6 +12335,12 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
> if (IS_G4X(dev_priv) ||
> IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> saved_state->wm = crtc_state->wm;
> + /* Save the slave bitmask which gets filled for master crtc state during
> + * slave atomic check call.
> + */
> + if (is_trans_port_sync_master(dev_priv, crtc_state))
> + saved_state->sync_mode_slaves_mask =
> + crtc_state->sync_mode_slaves_mask;
>
> /* Keep base drm_crtc_state intact, only clear our extended struct */
> BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
> @@ -12343,6 +12434,15 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
> drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
> CRTC_STEREO_DOUBLE);
>
> + /* Set the crtc_state defaults for trans_port_sync */
> + pipe_config->master_transcoder = INVALID_TRANSCODER;
> + ret = icl_add_sync_mode_crtcs(crtc, pipe_config, state);
> + if (ret) {
> + DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n",
> + ret);
> + return ret;
> + }
> +
> /* Pass our mode to the connectors and the CRTC to give them a chance to
> * adjust it according to limitations or connector properties, and also
> * a chance to reject the mode entirely.
> @@ -12856,6 +12956,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_INFOFRAME(hdmi);
> PIPE_CONF_CHECK_INFOFRAME(drm);
>
> + if (INTEL_GEN(dev_priv) >= 11) {
> + PIPE_CONF_CHECK_I(sync_mode_slaves_mask);
> + PIPE_CONF_CHECK_I(master_transcoder);
> + }
> +
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_BOOL
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 33fd523c4622..c1011204b407 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -91,6 +91,7 @@ enum pipe {
> #define pipe_name(p) ((p) + 'A')
>
> enum transcoder {
> + INVALID_TRANSCODER = -1,
> /*
> * The following transcoders have a 1:1 transcoder -> pipe mapping,
> * keep their values fixed: the code assumes that TRANSCODER_A=0, the
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d5cc4b810d9e..17ff34ca298b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -991,6 +991,12 @@ struct intel_crtc_state {
>
> /* Forward Error correction State */
> bool fec_enable;
> +
> + /* Pointer to master transcoder in case of tiled displays */
> + enum transcoder master_transcoder;
> +
> + /* Bitmask to indicate slaves attached */
> + u8 sync_mode_slaves_mask;
> };
>
> struct intel_crtc {
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
2019-09-09 3:43 ` [PATCH 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync Manasi Navare
@ 2019-09-09 3:43 ` Manasi Navare
2019-09-17 14:52 ` Maarten Lankhorst
2019-09-17 14:52 ` Maarten Lankhorst
2019-09-09 3:43 ` [PATCH 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config Manasi Navare
` (8 subsequent siblings)
10 siblings, 2 replies; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Daniel Vetter
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave transcoder
and the master transcoder is unaware that it is operating
in this mode.
This has been tested with tiled display connected to ICL.
v4:
Rebase
v3:
* Check of DP_MST moved to atomic_check (Maarten)
v2:
* Do not use RMW, just write to the register in commit (Jani N)
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8942c905ae66..b8f7a919b6d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4380,6 +4380,46 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
+static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 trans_ddi_func_ctl2_val;
+ u8 master_select;
+
+ /*
+ * Configure the master select and enable Transcoder Port Sync for
+ * Slave CRTCs transcoder.
+ */
+ if (crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ switch (crtc_state->master_transcoder) {
+ case TRANSCODER_A:
+ master_select = 1;
+ break;
+ case TRANSCODER_B:
+ master_select = 2;
+ break;
+ case TRANSCODER_C:
+ master_select = 3;
+ break;
+ case TRANSCODER_EDP:
+ default:
+ master_select = 0;
+ break;
+ }
+ /* Set the master select bits for Tranascoder Port Sync */
+ trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
+ PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
+ /* Enable Transcoder Port Sync */
+ trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
+
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
+ trans_ddi_func_ctl2_val);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -6448,6 +6488,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_set_pipe_timings(pipe_config);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_enable_trans_port_sync(pipe_config);
+
intel_set_pipe_src_size(pipe_config);
if (cpu_transcoder != TRANSCODER_EDP &&
--
2.19.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
2019-09-09 3:43 ` [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports Manasi Navare
@ 2019-09-17 14:52 ` Maarten Lankhorst
2019-09-17 14:52 ` Maarten Lankhorst
1 sibling, 0 replies; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 14:52 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Jani Nikula, Daniel Vetter
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> In case of tiled displays where different tiles are displayed across
> different ports, we need to synchronize the transcoders involved.
> This patch implements the transcoder port sync feature for
> synchronizing one master transcoder with one or more slave
> transcoders. This is only enbaled in slave transcoder
> and the master transcoder is unaware that it is operating
> in this mode.
> This has been tested with tiled display connected to ICL.
>
> v4:
> Rebase
> v3:
> * Check of DP_MST moved to atomic_check (Maarten)
> v2:
> * Do not use RMW, just write to the register in commit (Jani N)
>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8942c905ae66..b8f7a919b6d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4380,6 +4380,46 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
>
> +static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 trans_ddi_func_ctl2_val;
> + u8 master_select;
> +
> + /*
> + * Configure the master select and enable Transcoder Port Sync for
> + * Slave CRTCs transcoder.
> + */
> + if (crtc_state->master_transcoder == INVALID_TRANSCODER)
> + return;
> +
> + switch (crtc_state->master_transcoder) {
> + case TRANSCODER_A:
> + master_select = 1;
> + break;
> + case TRANSCODER_B:
> + master_select = 2;
> + break;
> + case TRANSCODER_C:
> + master_select = 3;
> + break;
> + case TRANSCODER_EDP:
> + default:
> + master_select = 0;
> + break;
> + }
default should use MISSING_CASE() Otherwise looks good.
> + /* Set the master select bits for Tranascoder Port Sync */
> + trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
> + PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
> + PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
> + /* Enable Transcoder Port Sync */
> + trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
> +
> + I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
> + trans_ddi_func_ctl2_val);
> +}
> +
> static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> @@ -6448,6 +6488,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_set_pipe_timings(pipe_config);
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_enable_trans_port_sync(pipe_config);
> +
> intel_set_pipe_src_size(pipe_config);
>
> if (cpu_transcoder != TRANSCODER_EDP &&
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
2019-09-09 3:43 ` [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports Manasi Navare
2019-09-17 14:52 ` Maarten Lankhorst
@ 2019-09-17 14:52 ` Maarten Lankhorst
2019-09-17 16:55 ` Manasi Navare
1 sibling, 1 reply; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 14:52 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Jani Nikula, Daniel Vetter
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> In case of tiled displays where different tiles are displayed across
> different ports, we need to synchronize the transcoders involved.
> This patch implements the transcoder port sync feature for
> synchronizing one master transcoder with one or more slave
> transcoders. This is only enbaled in slave transcoder
> and the master transcoder is unaware that it is operating
> in this mode.
> This has been tested with tiled display connected to ICL.
>
> v4:
> Rebase
> v3:
> * Check of DP_MST moved to atomic_check (Maarten)
> v2:
> * Do not use RMW, just write to the register in commit (Jani N)
>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8942c905ae66..b8f7a919b6d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4380,6 +4380,46 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
>
> +static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 trans_ddi_func_ctl2_val;
> + u8 master_select;
> +
> + /*
> + * Configure the master select and enable Transcoder Port Sync for
> + * Slave CRTCs transcoder.
> + */
> + if (crtc_state->master_transcoder == INVALID_TRANSCODER)
> + return;
> +
> + switch (crtc_state->master_transcoder) {
> + case TRANSCODER_A:
> + master_select = 1;
> + break;
> + case TRANSCODER_B:
> + master_select = 2;
> + break;
> + case TRANSCODER_C:
> + master_select = 3;
> + break;
TRANSCODER_D btw?
> + case TRANSCODER_EDP:
> + default:
> + master_select = 0;
> + break;
> + }
> + /* Set the master select bits for Tranascoder Port Sync */
> + trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
> + PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
> + PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
> + /* Enable Transcoder Port Sync */
> + trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
> +
> + I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
> + trans_ddi_func_ctl2_val);
> +}
> +
> static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> @@ -6448,6 +6488,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_set_pipe_timings(pipe_config);
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_enable_trans_port_sync(pipe_config);
> +
> intel_set_pipe_src_size(pipe_config);
>
> if (cpu_transcoder != TRANSCODER_EDP &&
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
2019-09-17 14:52 ` Maarten Lankhorst
@ 2019-09-17 16:55 ` Manasi Navare
0 siblings, 0 replies; 31+ messages in thread
From: Manasi Navare @ 2019-09-17 16:55 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Jani Nikula, Daniel Vetter, intel-gfx
On Tue, Sep 17, 2019 at 04:52:54PM +0200, Maarten Lankhorst wrote:
> Op 09-09-2019 om 05:43 schreef Manasi Navare:
> > In case of tiled displays where different tiles are displayed across
> > different ports, we need to synchronize the transcoders involved.
> > This patch implements the transcoder port sync feature for
> > synchronizing one master transcoder with one or more slave
> > transcoders. This is only enbaled in slave transcoder
> > and the master transcoder is unaware that it is operating
> > in this mode.
> > This has been tested with tiled display connected to ICL.
> >
> > v4:
> > Rebase
> > v3:
> > * Check of DP_MST moved to atomic_check (Maarten)
> > v2:
> > * Do not use RMW, just write to the register in commit (Jani N)
> >
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++++
> > 1 file changed, 43 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8942c905ae66..b8f7a919b6d3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4380,6 +4380,46 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> > I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> > }
> >
> > +static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + u32 trans_ddi_func_ctl2_val;
> > + u8 master_select;
> > +
> > + /*
> > + * Configure the master select and enable Transcoder Port Sync for
> > + * Slave CRTCs transcoder.
> > + */
> > + if (crtc_state->master_transcoder == INVALID_TRANSCODER)
> > + return;
> > +
> > + switch (crtc_state->master_transcoder) {
> > + case TRANSCODER_A:
> > + master_select = 1;
> > + break;
> > + case TRANSCODER_B:
> > + master_select = 2;
> > + break;
> > + case TRANSCODER_C:
> > + master_select = 3;
> > + break;
> TRANSCODER_D btw?
Yes will add that
Manasi
> > + case TRANSCODER_EDP:
> > + default:
> > + master_select = 0;
> > + break;
> > + }
> > + /* Set the master select bits for Tranascoder Port Sync */
> > + trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
> > + PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
> > + PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
> > + /* Enable Transcoder Port Sync */
> > + trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
> > +
> > + I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
> > + trans_ddi_func_ctl2_val);
> > +}
> > +
> > static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> > const struct intel_crtc_state *new_crtc_state)
> > {
> > @@ -6448,6 +6488,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_set_pipe_timings(pipe_config);
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + icl_enable_trans_port_sync(pipe_config);
> > +
> > intel_set_pipe_src_size(pipe_config);
> >
> > if (cpu_transcoder != TRANSCODER_EDP &&
>
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
2019-09-09 3:43 ` [PATCH 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync Manasi Navare
2019-09-09 3:43 ` [PATCH 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports Manasi Navare
@ 2019-09-09 3:43 ` Manasi Navare
2019-09-17 14:53 ` Maarten Lankhorst
2019-09-09 3:43 ` [PATCH 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync Manasi Navare
` (7 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state mismatch.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 47 ++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b8f7a919b6d3..76ca1ca864c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10421,6 +10421,50 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
}
}
+static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 trans_port_sync, transcoders, master_select;
+ enum transcoder cpu_transcoder;
+
+ trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(pipe_config->cpu_transcoder));
+ if (trans_port_sync & PORT_SYNC_MODE_ENABLE) {
+ master_select = trans_port_sync &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK;
+ switch (master_select) {
+ case 1:
+ pipe_config->master_transcoder = TRANSCODER_A;
+ break;
+ case 2:
+ pipe_config->master_transcoder = TRANSCODER_B;
+ break;
+ case 3:
+ pipe_config->master_transcoder = TRANSCODER_C;
+ break;
+ default:
+ pipe_config->master_transcoder = TRANSCODER_EDP;
+ break;
+ }
+
+ pipe_config->sync_mode_slaves_mask = 0;
+ } else {
+ pipe_config->master_transcoder = INVALID_TRANSCODER;
+
+ transcoders = BIT(TRANSCODER_EDP) |
+ BIT(TRANSCODER_A) |
+ BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C);
+ for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+
+ if (trans_port_sync & PORT_SYNC_MODE_ENABLE)
+ pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder);
+ }
+ }
+}
+
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10517,6 +10561,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
+ if (INTEL_GEN(dev_priv) >= 11)
+ icelake_get_trans_port_sync_config(crtc, pipe_config);
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv,
--
2.19.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
2019-09-09 3:43 ` [PATCH 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config Manasi Navare
@ 2019-09-17 14:53 ` Maarten Lankhorst
0 siblings, 0 replies; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 14:53 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Jani Nikula
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> After the state is committed, we readout the HW registers and compare
> the HW state with the SW state that we just committed.
> For Transcdoer port sync, we add master_transcoder and the
> salves bitmask to the crtc_state, hence we need to read those during
> the HW state readout to avoid pipe state mismatch.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 47 ++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b8f7a919b6d3..76ca1ca864c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10421,6 +10421,50 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> }
> }
>
> +static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + u32 trans_port_sync, transcoders, master_select;
> + enum transcoder cpu_transcoder;
> +
> + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(pipe_config->cpu_transcoder));
> + if (trans_port_sync & PORT_SYNC_MODE_ENABLE) {
> + master_select = trans_port_sync &
> + PORT_SYNC_MODE_MASTER_SELECT_MASK;
> + switch (master_select) {
> + case 1:
> + pipe_config->master_transcoder = TRANSCODER_A;
> + break;
> + case 2:
> + pipe_config->master_transcoder = TRANSCODER_B;
> + break;
> + case 3:
> + pipe_config->master_transcoder = TRANSCODER_C;
> + break;
Same, TRANSCODER_D + MISSING_CASE()
> + default:
> + pipe_config->master_transcoder = TRANSCODER_EDP;
> + break;
> + }
> +
> + pipe_config->sync_mode_slaves_mask = 0;
> + } else {
> + pipe_config->master_transcoder = INVALID_TRANSCODER;
> +
> + transcoders = BIT(TRANSCODER_EDP) |
> + BIT(TRANSCODER_A) |
> + BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C);
> + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
> +
> + if (trans_port_sync & PORT_SYNC_MODE_ENABLE)
> + pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder);
> + }
> + }
> +}
> +
> static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -10517,6 +10561,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icelake_get_trans_port_sync_config(crtc, pipe_config);
> +
> out:
> for_each_power_domain(power_domain, power_domain_mask)
> intel_display_power_put(dev_priv,
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (2 preceding siblings ...)
2019-09-09 3:43 ` [PATCH 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config Manasi Navare
@ 2019-09-09 3:43 ` Manasi Navare
2019-09-09 15:52 ` [PATCH v2 " Manasi Navare
2019-09-09 3:43 ` [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence Manasi Navare
` (6 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcoder port sync mode is configured and enabled
and the Vblanks of both ports are synchronized so then set DP_TP_CTL
for the slave and master to Normal and do post crtc enable updates.
v4:
* Reuse skl_commit_modeset_enables() hook (Maarten)
* Obtain slave crtc and states from master (Maarten)
v3:
* Rebase on drm-tip (Manasi)
v2:
* Create a icl_update_crtcs hook (Maarten, Danvet)
* This sequence only for CRTCs in trans port sync mode (Maarten)
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 158 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.h | 4 +
3 files changed, 162 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..62e9f5602b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3347,7 +3347,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
- if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+ if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+ !is_trans_port_sync_mode(dev_priv, crtc_state))
intel_dp_stop_link_train(intel_dp);
intel_ddi_enable_fec(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 76ca1ca864c0..351c90ad7059 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,6 +521,24 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(&state->base);
}
+bool
+is_trans_port_sync_mode(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *state)
+{
+ return (INTEL_GEN(dev_priv) >= 11 &&
+ (state->master_transcoder != INVALID_TRANSCODER ||
+ state->sync_mode_slaves_mask));
+}
+
+static bool
+is_trans_port_sync_master(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *state)
+{
+ return (INTEL_GEN(dev_priv) >= 11 &&
+ (state->master_transcoder == INVALID_TRANSCODER &&
+ state->sync_mode_slaves_mask));
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -13974,6 +13992,30 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_finish_crtc_commit(state, crtc);
}
+static struct intel_crtc * intel_get_slave_crtc(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *new_crtc_state)
+{
+ if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_A))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_A);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_B))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_B);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_C))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_C);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_D))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_D);
+ /* should never happen */
+ WARN_ON(1);
+ return NULL;
+}
+
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state,
@@ -14052,6 +14094,104 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
}
}
+static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ update_scanline_offset(new_crtc_state);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+ intel_crtc_enable_pipe_crc(crtc);
+}
+
+static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
+{
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_dp *intel_dp;
+ int i;
+
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+ if (conn_state->crtc == &crtc->base)
+ break;
+ }
+ intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
+ intel_dp_stop_link_train(intel_dp);
+}
+
+static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_plane_state *new_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ to_intel_plane(crtc->base.primary));
+
+ if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
+ intel_fbc_disable(crtc);
+ else if (new_plane_state)
+ intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
+
+ intel_begin_crtc_commit(state, crtc);
+ skl_update_planes_on_crtc(state, crtc);
+ intel_finish_crtc_commit(state, crtc);
+}
+
+static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+ new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
+ crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
+ slave_crtc->base.name);
+
+ /* Enable seq for slave with with DP_TP_CTL left Idle until the
+ * master is ready
+ */
+ intel_crtc_enable_trans_port_sync(slave_crtc,
+ state,
+ new_slave_crtc_state);
+
+ /* Enable seq for master with with DP_TP_CTL left Idle */
+ intel_crtc_enable_trans_port_sync(crtc,
+ state,
+ new_crtc_state);
+
+ /* Set Slave's DP_TP_CTL to Normal */
+ intel_set_dp_tp_ctl_normal(slave_crtc,
+ state);
+
+ /* Set Master's DP_TP_CTL To Normal */
+ usleep_range(200, 400);
+ intel_set_dp_tp_ctl_normal(crtc,
+ state);
+
+ /* Now do the post crtc enable for all master and slaves */
+ intel_post_crtc_enable_updates(slave_crtc,
+ state,
+ new_slave_crtc_state,
+ old_slave_crtc_state);
+ intel_post_crtc_enable_updates(crtc,
+ state,
+ new_crtc_state,
+ old_crtc_state);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14086,6 +14226,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
bool vbl_wait = false;
unsigned int cmask = drm_crtc_mask(&crtc->base);
+ bool modeset = needs_modeset(new_crtc_state);
pipe = crtc->pipe;
@@ -14108,12 +14249,25 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
*/
if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
&old_crtc_state->wm.skl.ddb) &&
+ !modeset &&
!new_crtc_state->base.active_changed &&
state->wm_results.dirty_pipes != updated)
vbl_wait = true;
- intel_update_crtc(crtc, state, old_crtc_state,
- new_crtc_state);
+ if (modeset && is_trans_port_sync_mode(dev_priv,
+ new_crtc_state)) {
+ if (is_trans_port_sync_master(dev_priv,
+ new_crtc_state))
+ intel_update_trans_port_sync_crtcs(crtc,
+ state,
+ old_crtc_state,
+ new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_update_crtc(crtc, state, old_crtc_state,
+ new_crtc_state);
+ }
if (vbl_wait)
intel_wait_for_vblank(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index c1011204b407..3e0a36ec580d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,6 +27,7 @@
#include <drm/drm_util.h>
#include <drm/i915_drm.h>
+#include "intel_dp_link_training.h"
enum link_m_n_set;
struct dpll;
@@ -52,6 +53,7 @@ struct intel_plane;
struct intel_plane_state;
struct intel_remapped_info;
struct intel_rotation_info;
+struct intel_crtc_state;
enum i915_gpio {
GPIOA,
@@ -449,6 +451,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
+bool is_trans_port_sync_mode(struct drm_i915_private *i915,
+ const struct intel_crtc_state *state);
void intel_plane_destroy(struct drm_plane *plane);
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync
2019-09-09 3:43 ` [PATCH 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync Manasi Navare
@ 2019-09-09 15:52 ` Manasi Navare
2019-09-17 15:01 ` Maarten Lankhorst
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 15:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
As per the display enable sequence, we need to follow the enable sequence
for slaves first with DP_TP_CTL set to Idle and configure the transcoder
port sync register to select the corersponding master, then follow the
enable sequence for master leaving DP_TP_CTL to idle.
At this point the transcoder port sync mode is configured and enabled
and the Vblanks of both ports are synchronized so then set DP_TP_CTL
for the slave and master to Normal and do post crtc enable updates.
v5:
* Fix checkpatch warning (Manasi)
v4:
* Reuse skl_commit_modeset_enables() hook (Maarten)
* Obtain slave crtc and states from master (Maarten)
v3:
* Rebase on drm-tip (Manasi)
v2:
* Create a icl_update_crtcs hook (Maarten, Danvet)
* This sequence only for CRTCs in trans port sync mode (Maarten)
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 158 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.h | 4 +
3 files changed, 162 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..62e9f5602b6b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3347,7 +3347,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
intel_dp_start_link_train(intel_dp);
- if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+ if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
+ !is_trans_port_sync_mode(dev_priv, crtc_state))
intel_dp_stop_link_train(intel_dp);
intel_ddi_enable_fec(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 76ca1ca864c0..5e583e9157f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -521,6 +521,24 @@ needs_modeset(const struct intel_crtc_state *state)
return drm_atomic_crtc_needs_modeset(&state->base);
}
+bool
+is_trans_port_sync_mode(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *state)
+{
+ return (INTEL_GEN(dev_priv) >= 11 &&
+ (state->master_transcoder != INVALID_TRANSCODER ||
+ state->sync_mode_slaves_mask));
+}
+
+static bool
+is_trans_port_sync_master(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *state)
+{
+ return (INTEL_GEN(dev_priv) >= 11 &&
+ (state->master_transcoder == INVALID_TRANSCODER &&
+ state->sync_mode_slaves_mask));
+}
+
/*
* Platform specific helpers to calculate the port PLL loopback- (clock.m),
* and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
@@ -13974,6 +13992,30 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_finish_crtc_commit(state, crtc);
}
+static struct intel_crtc *intel_get_slave_crtc(struct drm_i915_private *dev_priv,
+ struct intel_crtc_state *new_crtc_state)
+{
+ if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_A))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_A);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_B))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_B);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_C))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_C);
+ else if (new_crtc_state->sync_mode_slaves_mask &
+ BIT(TRANSCODER_D))
+ return intel_get_crtc_for_pipe(dev_priv,
+ PIPE_D);
+ /* should never happen */
+ WARN_ON(1);
+ return NULL;
+}
+
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state,
@@ -14052,6 +14094,104 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
}
}
+static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ update_scanline_offset(new_crtc_state);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+ intel_crtc_enable_pipe_crc(crtc);
+}
+
+static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
+ struct intel_atomic_state *state)
+{
+ struct drm_connector_state *conn_state;
+ struct drm_connector *conn;
+ struct intel_dp *intel_dp;
+ int i;
+
+ for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
+ if (conn_state->crtc == &crtc->base)
+ break;
+ }
+ intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
+ intel_dp_stop_link_train(intel_dp);
+}
+
+static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_plane_state *new_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ to_intel_plane(crtc->base.primary));
+
+ if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
+ intel_fbc_disable(crtc);
+ else if (new_plane_state)
+ intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
+
+ intel_begin_crtc_commit(state, crtc);
+ skl_update_planes_on_crtc(state, crtc);
+ intel_finish_crtc_commit(state, crtc);
+}
+
+static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+ new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
+ crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
+ slave_crtc->base.name);
+
+ /* Enable seq for slave with with DP_TP_CTL left Idle until the
+ * master is ready
+ */
+ intel_crtc_enable_trans_port_sync(slave_crtc,
+ state,
+ new_slave_crtc_state);
+
+ /* Enable seq for master with with DP_TP_CTL left Idle */
+ intel_crtc_enable_trans_port_sync(crtc,
+ state,
+ new_crtc_state);
+
+ /* Set Slave's DP_TP_CTL to Normal */
+ intel_set_dp_tp_ctl_normal(slave_crtc,
+ state);
+
+ /* Set Master's DP_TP_CTL To Normal */
+ usleep_range(200, 400);
+ intel_set_dp_tp_ctl_normal(crtc,
+ state);
+
+ /* Now do the post crtc enable for all master and slaves */
+ intel_post_crtc_enable_updates(slave_crtc,
+ state,
+ new_slave_crtc_state,
+ old_slave_crtc_state);
+ intel_post_crtc_enable_updates(crtc,
+ state,
+ new_crtc_state,
+ old_crtc_state);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14086,6 +14226,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
bool vbl_wait = false;
unsigned int cmask = drm_crtc_mask(&crtc->base);
+ bool modeset = needs_modeset(new_crtc_state);
pipe = crtc->pipe;
@@ -14108,12 +14249,25 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
*/
if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
&old_crtc_state->wm.skl.ddb) &&
+ !modeset &&
!new_crtc_state->base.active_changed &&
state->wm_results.dirty_pipes != updated)
vbl_wait = true;
- intel_update_crtc(crtc, state, old_crtc_state,
- new_crtc_state);
+ if (modeset && is_trans_port_sync_mode(dev_priv,
+ new_crtc_state)) {
+ if (is_trans_port_sync_master(dev_priv,
+ new_crtc_state))
+ intel_update_trans_port_sync_crtcs(crtc,
+ state,
+ old_crtc_state,
+ new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_update_crtc(crtc, state, old_crtc_state,
+ new_crtc_state);
+ }
if (vbl_wait)
intel_wait_for_vblank(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index c1011204b407..3e0a36ec580d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,6 +27,7 @@
#include <drm/drm_util.h>
#include <drm/i915_drm.h>
+#include "intel_dp_link_training.h"
enum link_m_n_set;
struct dpll;
@@ -52,6 +53,7 @@ struct intel_plane;
struct intel_plane_state;
struct intel_remapped_info;
struct intel_rotation_info;
+struct intel_crtc_state;
enum i915_gpio {
GPIOA,
@@ -449,6 +451,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
+bool is_trans_port_sync_mode(struct drm_i915_private *i915,
+ const struct intel_crtc_state *state);
void intel_plane_destroy(struct drm_plane *plane);
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v2 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync
2019-09-09 15:52 ` [PATCH v2 " Manasi Navare
@ 2019-09-17 15:01 ` Maarten Lankhorst
0 siblings, 0 replies; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 15:01 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Daniel Vetter
Op 09-09-2019 om 17:52 schreef Manasi Navare:
> As per the display enable sequence, we need to follow the enable sequence
> for slaves first with DP_TP_CTL set to Idle and configure the transcoder
> port sync register to select the corersponding master, then follow the
> enable sequence for master leaving DP_TP_CTL to idle.
> At this point the transcoder port sync mode is configured and enabled
> and the Vblanks of both ports are synchronized so then set DP_TP_CTL
> for the slave and master to Normal and do post crtc enable updates.
>
> v5:
> * Fix checkpatch warning (Manasi)
> v4:
> * Reuse skl_commit_modeset_enables() hook (Maarten)
> * Obtain slave crtc and states from master (Maarten)
> v3:
> * Rebase on drm-tip (Manasi)
> v2:
> * Create a icl_update_crtcs hook (Maarten, Danvet)
> * This sequence only for CRTCs in trans port sync mode (Maarten)
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 158 ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> 3 files changed, 162 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3e6394139964..62e9f5602b6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3347,7 +3347,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
> true);
> intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> intel_dp_start_link_train(intel_dp);
> - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> + if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
> + !is_trans_port_sync_mode(dev_priv, crtc_state))
> intel_dp_stop_link_train(intel_dp);
>
> intel_ddi_enable_fec(encoder, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 76ca1ca864c0..5e583e9157f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -521,6 +521,24 @@ needs_modeset(const struct intel_crtc_state *state)
> return drm_atomic_crtc_needs_modeset(&state->base);
> }
>
> +bool
> +is_trans_port_sync_mode(struct drm_i915_private *dev_priv,
> + const struct intel_crtc_state *state)
> +{
> + return (INTEL_GEN(dev_priv) >= 11 &&
> + (state->master_transcoder != INVALID_TRANSCODER ||
> + state->sync_mode_slaves_mask));
> +}
> +
> +static bool
> +is_trans_port_sync_master(struct drm_i915_private *dev_priv,
> + const struct intel_crtc_state *state)
> +{
> + return (INTEL_GEN(dev_priv) >= 11 &&
> + (state->master_transcoder == INVALID_TRANSCODER &&
> + state->sync_mode_slaves_mask));
> +}
> +
> /*
> * Platform specific helpers to calculate the port PLL loopback- (clock.m),
> * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
> @@ -13974,6 +13992,30 @@ static void intel_update_crtc(struct intel_crtc *crtc,
> intel_finish_crtc_commit(state, crtc);
> }
>
> +static struct intel_crtc *intel_get_slave_crtc(struct drm_i915_private *dev_priv,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + if (new_crtc_state->sync_mode_slaves_mask &
> + BIT(TRANSCODER_A))
> + return intel_get_crtc_for_pipe(dev_priv,
> + PIPE_A);
> + else if (new_crtc_state->sync_mode_slaves_mask &
> + BIT(TRANSCODER_B))
> + return intel_get_crtc_for_pipe(dev_priv,
> + PIPE_B);
> + else if (new_crtc_state->sync_mode_slaves_mask &
> + BIT(TRANSCODER_C))
> + return intel_get_crtc_for_pipe(dev_priv,
> + PIPE_C);
> + else if (new_crtc_state->sync_mode_slaves_mask &
> + BIT(TRANSCODER_D))
> + return intel_get_crtc_for_pipe(dev_priv,
> + PIPE_D);
> + /* should never happen */
> + WARN_ON(1);
> + return NULL;
> +}
> +
> static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state *new_crtc_state,
> @@ -14052,6 +14094,104 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
> }
> }
>
> +static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
> + struct intel_atomic_state *state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> + update_scanline_offset(new_crtc_state);
> + dev_priv->display.crtc_enable(new_crtc_state, state);
> + intel_crtc_enable_pipe_crc(crtc);
> +}
> +
> +static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
> + struct intel_atomic_state *state)
> +{
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + struct intel_dp *intel_dp;
> + int i;
> +
> + for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> + if (conn_state->crtc == &crtc->base)
> + break;
> + }
> + intel_dp = enc_to_intel_dp(&intel_attached_encoder(conn)->base);
> + intel_dp_stop_link_train(intel_dp);
> +}
> +
> +static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
> + struct intel_atomic_state *state,
> + struct intel_crtc_state *old_crtc_state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct intel_plane_state *new_plane_state =
> + intel_atomic_get_new_plane_state(state,
> + to_intel_plane(crtc->base.primary));
> +
> + if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
> + intel_fbc_disable(crtc);
> + else if (new_plane_state)
> + intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
> +
> + intel_begin_crtc_commit(state, crtc);
> + skl_update_planes_on_crtc(state, crtc);
> + intel_finish_crtc_commit(state, crtc);
> +}
> +
> +static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
> + struct intel_atomic_state *state,
> + struct intel_crtc_state *old_crtc_state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
> + new_crtc_state);
> + struct intel_crtc_state *new_slave_crtc_state =
> + intel_atomic_get_new_crtc_state(state, slave_crtc);
> + struct intel_crtc_state *old_slave_crtc_state =
> + intel_atomic_get_old_crtc_state(state, slave_crtc);
> +
> + WARN_ON(!slave_crtc || !new_slave_crtc_state ||
> + !old_slave_crtc_state);
> +
> + DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
> + crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id,
> + slave_crtc->base.name);
> +
> + /* Enable seq for slave with with DP_TP_CTL left Idle until the
> + * master is ready
> + */
> + intel_crtc_enable_trans_port_sync(slave_crtc,
> + state,
> + new_slave_crtc_state);
> +
> + /* Enable seq for master with with DP_TP_CTL left Idle */
> + intel_crtc_enable_trans_port_sync(crtc,
> + state,
> + new_crtc_state);
> +
> + /* Set Slave's DP_TP_CTL to Normal */
> + intel_set_dp_tp_ctl_normal(slave_crtc,
> + state);
> +
> + /* Set Master's DP_TP_CTL To Normal */
> + usleep_range(200, 400);
> + intel_set_dp_tp_ctl_normal(crtc,
> + state);
> +
> + /* Now do the post crtc enable for all master and slaves */
> + intel_post_crtc_enable_updates(slave_crtc,
> + state,
> + new_slave_crtc_state,
> + old_slave_crtc_state);
> + intel_post_crtc_enable_updates(crtc,
> + state,
> + new_crtc_state,
> + old_crtc_state);
> +}
Looks sort of like what I had in mind. :)
As a patch 7/6, you should really have a function like intel_update_bigjoiner in
https://patchwork.freedesktop.org/patch/331201/?series=66802&rev=1
This will ensure tear-free updates when using atomic to update both. But it would be something that can be done more easily after bigjoiner work has landed.
> static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> @@ -14086,6 +14226,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> bool vbl_wait = false;
> unsigned int cmask = drm_crtc_mask(&crtc->base);
> + bool modeset = needs_modeset(new_crtc_state);
>
> pipe = crtc->pipe;
>
> @@ -14108,12 +14249,25 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> */
> if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
> &old_crtc_state->wm.skl.ddb) &&
> + !modeset &&
> !new_crtc_state->base.active_changed &&
!modeset implies !active_changed, but with this fixed looks good.
> state->wm_results.dirty_pipes != updated)
> vbl_wait = true;
>
> - intel_update_crtc(crtc, state, old_crtc_state,
> - new_crtc_state);
> + if (modeset && is_trans_port_sync_mode(dev_priv,
> + new_crtc_state)) {
> + if (is_trans_port_sync_master(dev_priv,
> + new_crtc_state))
> + intel_update_trans_port_sync_crtcs(crtc,
> + state,
> + old_crtc_state,
> + new_crtc_state);
> + else
> + continue;
Yeah, this looks as I expect it to. :)
> + } else {
> + intel_update_crtc(crtc, state, old_crtc_state,
> + new_crtc_state);
> + }
>
> if (vbl_wait)
> intel_wait_for_vblank(dev_priv, pipe);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index c1011204b407..3e0a36ec580d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -27,6 +27,7 @@
>
> #include <drm/drm_util.h>
> #include <drm/i915_drm.h>
> +#include "intel_dp_link_training.h"
>
> enum link_m_n_set;
> struct dpll;
> @@ -52,6 +53,7 @@ struct intel_plane;
> struct intel_plane_state;
> struct intel_remapped_info;
> struct intel_rotation_info;
> +struct intel_crtc_state;
>
> enum i915_gpio {
> GPIOA,
> @@ -449,6 +451,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> +bool is_trans_port_sync_mode(struct drm_i915_private *i915,
> + const struct intel_crtc_state *state);
>
> void intel_plane_destroy(struct drm_plane *plane);
> void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (3 preceding siblings ...)
2019-09-09 3:43 ` [PATCH 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync Manasi Navare
@ 2019-09-09 3:43 ` Manasi Navare
2019-09-17 15:04 ` Maarten Lankhorst
2019-09-09 3:43 ` [PATCH 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master Manasi Navare
` (5 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
register during crtc_disable().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 351c90ad7059..07deb0b93f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4438,6 +4438,26 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state
trans_ddi_func_ctl2_val);
}
+static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg;
+ u32 trans_ddi_func_ctl2_val;
+
+ if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
+ transcoder_name(old_crtc_state->cpu_transcoder));
+
+ reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
+ trans_ddi_func_ctl2_val = I915_READ(reg);
+ trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
+ PORT_SYNC_MODE_MASTER_SELECT_MASK);
+ I915_WRITE(reg, trans_ddi_func_ctl2_val);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -6687,6 +6707,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_disable_transcoder_port_sync(old_crtc_state);
+
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_disable_transcoder_func(old_crtc_state);
--
2.19.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
2019-09-09 3:43 ` [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence Manasi Navare
@ 2019-09-17 15:04 ` Maarten Lankhorst
2019-09-17 16:37 ` Manasi Navare
0 siblings, 1 reply; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 15:04 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Jani Nikula
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
> register during crtc_disable().
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 351c90ad7059..07deb0b93f5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4438,6 +4438,26 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state
> trans_ddi_func_ctl2_val);
> }
>
> +static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + i915_reg_t reg;
> + u32 trans_ddi_func_ctl2_val;
> +
> + if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
> + return;
> +
> + DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
> + transcoder_name(old_crtc_state->cpu_transcoder));
> +
> + reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
> + trans_ddi_func_ctl2_val = I915_READ(reg);
> + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
> + PORT_SYNC_MODE_MASTER_SELECT_MASK);
> + I915_WRITE(reg, trans_ddi_func_ctl2_val);
> +}
> +
Would anything break if we just wrote 0 here?
> static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> @@ -6687,6 +6707,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_disable_transcoder_port_sync(old_crtc_state);
> +
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
2019-09-17 15:04 ` Maarten Lankhorst
@ 2019-09-17 16:37 ` Manasi Navare
2019-09-18 8:51 ` Maarten Lankhorst
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-17 16:37 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Jani Nikula, intel-gfx
On Tue, Sep 17, 2019 at 05:04:28PM +0200, Maarten Lankhorst wrote:
> Op 09-09-2019 om 05:43 schreef Manasi Navare:
> > This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
> > register during crtc_disable().
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 351c90ad7059..07deb0b93f5c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4438,6 +4438,26 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state
> > trans_ddi_func_ctl2_val);
> > }
> >
> > +static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + i915_reg_t reg;
> > + u32 trans_ddi_func_ctl2_val;
> > +
> > + if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
> > + return;
> > +
> > + DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
> > + transcoder_name(old_crtc_state->cpu_transcoder));
> > +
> > + reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
> > + trans_ddi_func_ctl2_val = I915_READ(reg);
> > + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
> > + PORT_SYNC_MODE_MASTER_SELECT_MASK);
> > + I915_WRITE(reg, trans_ddi_func_ctl2_val);
> > +}
> > +
> Would anything break if we just wrote 0 here?
We dont want to accidently reset other bits in the register which are for DSI and not used currently but
to make this function more future proof, I have avoided writing a 0
But if you strongly feel against this, I can switch this to writing 0 directly.
Manasi
> > static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> > const struct intel_crtc_state *new_crtc_state)
> > {
> > @@ -6687,6 +6707,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> > if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
> > intel_ddi_set_vc_payload_alloc(old_crtc_state, false);
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + icl_disable_transcoder_port_sync(old_crtc_state);
> > +
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_ddi_disable_transcoder_func(old_crtc_state);
> >
>
>
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
2019-09-17 16:37 ` Manasi Navare
@ 2019-09-18 8:51 ` Maarten Lankhorst
2019-09-18 15:16 ` Manasi Navare
0 siblings, 1 reply; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-18 8:51 UTC (permalink / raw)
To: Manasi Navare; +Cc: Jani Nikula, intel-gfx
Op 17-09-2019 om 18:37 schreef Manasi Navare:
> On Tue, Sep 17, 2019 at 05:04:28PM +0200, Maarten Lankhorst wrote:
>> Op 09-09-2019 om 05:43 schreef Manasi Navare:
>>> This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
>>> register during crtc_disable().
>>>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++++
>>> 1 file changed, 23 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index 351c90ad7059..07deb0b93f5c 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -4438,6 +4438,26 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state
>>> trans_ddi_func_ctl2_val);
>>> }
>>>
>>> +static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
>>> +{
>>> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>> + i915_reg_t reg;
>>> + u32 trans_ddi_func_ctl2_val;
>>> +
>>> + if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
>>> + return;
>>> +
>>> + DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
>>> + transcoder_name(old_crtc_state->cpu_transcoder));
>>> +
>>> + reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
>>> + trans_ddi_func_ctl2_val = I915_READ(reg);
>>> + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
>>> + PORT_SYNC_MODE_MASTER_SELECT_MASK);
>>> + I915_WRITE(reg, trans_ddi_func_ctl2_val);
>>> +}
>>> +
>> Would anything break if we just wrote 0 here?
> We dont want to accidently reset other bits in the register which are for DSI and not used currently but
> to make this function more future proof, I have avoided writing a 0
>
> But if you strongly feel against this, I can switch this to writing 0 directly.
We overwrite func_ctl2 in enable_port_sync so it makes sense to do the same in disable. :)
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^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
2019-09-18 8:51 ` Maarten Lankhorst
@ 2019-09-18 15:16 ` Manasi Navare
0 siblings, 0 replies; 31+ messages in thread
From: Manasi Navare @ 2019-09-18 15:16 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Jani Nikula, intel-gfx
On Wed, Sep 18, 2019 at 10:51:54AM +0200, Maarten Lankhorst wrote:
> Op 17-09-2019 om 18:37 schreef Manasi Navare:
> > On Tue, Sep 17, 2019 at 05:04:28PM +0200, Maarten Lankhorst wrote:
> >> Op 09-09-2019 om 05:43 schreef Manasi Navare:
> >>> This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
> >>> register during crtc_disable().
> >>>
> >>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> >>> Cc: Matt Roper <matthew.d.roper@intel.com>
> >>> Cc: Jani Nikula <jani.nikula@intel.com>
> >>> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++++
> >>> 1 file changed, 23 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >>> index 351c90ad7059..07deb0b93f5c 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>> @@ -4438,6 +4438,26 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state
> >>> trans_ddi_func_ctl2_val);
> >>> }
> >>>
> >>> +static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
> >>> +{
> >>> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> >>> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >>> + i915_reg_t reg;
> >>> + u32 trans_ddi_func_ctl2_val;
> >>> +
> >>> + if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
> >>> + return;
> >>> +
> >>> + DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
> >>> + transcoder_name(old_crtc_state->cpu_transcoder));
> >>> +
> >>> + reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
> >>> + trans_ddi_func_ctl2_val = I915_READ(reg);
> >>> + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
> >>> + PORT_SYNC_MODE_MASTER_SELECT_MASK);
> >>> + I915_WRITE(reg, trans_ddi_func_ctl2_val);
> >>> +}
> >>> +
> >> Would anything break if we just wrote 0 here?
> > We dont want to accidently reset other bits in the register which are for DSI and not used currently but
> > to make this function more future proof, I have avoided writing a 0
> >
> > But if you strongly feel against this, I can switch this to writing 0 directly.
>
> We overwrite func_ctl2 in enable_port_sync so it makes sense to do the same in disable. :)
Yes as per the reviews on the enable patch, the RMW was not recommended, so even here I will just overwrite with ~(PORT_SYNC_MODE_ENABLE | PORT_SYNC_MODE_MASTER_SELECT_MASK);
This sounds good?
Manasi
>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (4 preceding siblings ...)
2019-09-09 3:43 ` [PATCH 5/6] drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence Manasi Navare
@ 2019-09-09 3:43 ` Manasi Navare
2019-09-09 15:52 ` [PATCH v2 " Manasi Navare
2019-09-09 4:10 ` ✗ Fi.CI.CHECKPATCH: warning for Remaining patches to enable Transcoder Port Sync for tiled displays Patchwork
` (4 subsequent siblings)
10 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 3:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() helper
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++++++++++--
1 file changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 07deb0b93f5c..bc0d523e1cd1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14074,8 +14074,42 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
new_crtc_state);
}
+static void intel_trans_port_sync_modeset_disables (struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+ new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ /* Disable Slave first */
+ intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+ if (old_slave_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_slave_crtc_state,
+ new_slave_crtc_state,
+ slave_crtc);
+
+ /* Disable Master */
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+}
+
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
int i;
@@ -14092,13 +14126,29 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
- intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ /* In case of Transcoder port Sync master slave CRTCs can be
+ * assigned in any order and we need to make sure that
+ * slave CRTCs are disabled first and then master CRTC since
+ * Slave vblanks are masked till Master Vblanks.
+ */
+ if (is_trans_port_sync_mode(dev_priv, new_crtc_state)) {
+ if (is_trans_port_sync_master(dev_priv,
+ new_crtc_state))
+ intel_trans_port_sync_modeset_disables(state,
+ crtc,
+ old_crtc_state,
+ new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->base.active)
- intel_old_crtc_state_disables(state,
- old_crtc_state,
- new_crtc_state,
- crtc);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+ }
}
}
--
2.19.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master
2019-09-09 3:43 ` [PATCH 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master Manasi Navare
@ 2019-09-09 15:52 ` Manasi Navare
2019-09-17 15:05 ` Maarten Lankhorst
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-09 15:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
In the transcoder port sync mode, the slave transcoders mask their vblanks
until master transcoder's vblank so while disabling them, make
sure slaves are disabled first and then the masters.
v4:
* Obtain slave state from master (Maarten)
v3:
* Rebase
v2:
* Use the intel_old_crtc_state_disables() helper
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++++++++++--
1 file changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ac6e880570ea..8c333280d8f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14074,8 +14074,42 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
new_crtc_state);
}
+static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
+ new_crtc_state);
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave_crtc);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave_crtc);
+
+ WARN_ON(!slave_crtc || !new_slave_crtc_state ||
+ !old_slave_crtc_state);
+
+ /* Disable Slave first */
+ intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
+ if (old_slave_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_slave_crtc_state,
+ new_slave_crtc_state,
+ slave_crtc);
+
+ /* Disable Master */
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+}
+
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
int i;
@@ -14092,13 +14126,29 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
if (!needs_modeset(new_crtc_state))
continue;
- intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ /* In case of Transcoder port Sync master slave CRTCs can be
+ * assigned in any order and we need to make sure that
+ * slave CRTCs are disabled first and then master CRTC since
+ * Slave vblanks are masked till Master Vblanks.
+ */
+ if (is_trans_port_sync_mode(dev_priv, new_crtc_state)) {
+ if (is_trans_port_sync_master(dev_priv,
+ new_crtc_state))
+ intel_trans_port_sync_modeset_disables(state,
+ crtc,
+ old_crtc_state,
+ new_crtc_state);
+ else
+ continue;
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
- if (old_crtc_state->base.active)
- intel_old_crtc_state_disables(state,
- old_crtc_state,
- new_crtc_state,
- crtc);
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
+ old_crtc_state,
+ new_crtc_state,
+ crtc);
+ }
}
}
--
2.19.1
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^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v2 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master
2019-09-09 15:52 ` [PATCH v2 " Manasi Navare
@ 2019-09-17 15:05 ` Maarten Lankhorst
0 siblings, 0 replies; 31+ messages in thread
From: Maarten Lankhorst @ 2019-09-17 15:05 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Jani Nikula
Op 09-09-2019 om 17:52 schreef Manasi Navare:
> In the transcoder port sync mode, the slave transcoders mask their vblanks
> until master transcoder's vblank so while disabling them, make
> sure slaves are disabled first and then the masters.
>
> v4:
> * Obtain slave state from master (Maarten)
> v3:
> * Rebase
> v2:
> * Use the intel_old_crtc_state_disables() helper
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++++++++++--
> 1 file changed, 56 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ac6e880570ea..8c333280d8f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14074,8 +14074,42 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> new_crtc_state);
> }
>
> +static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_crtc_state *old_crtc_state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *slave_crtc = intel_get_slave_crtc(dev_priv,
> + new_crtc_state);
> + struct intel_crtc_state *new_slave_crtc_state =
> + intel_atomic_get_new_crtc_state(state, slave_crtc);
> + struct intel_crtc_state *old_slave_crtc_state =
> + intel_atomic_get_old_crtc_state(state, slave_crtc);
> +
> + WARN_ON(!slave_crtc || !new_slave_crtc_state ||
> + !old_slave_crtc_state);
> +
> + /* Disable Slave first */
> + intel_pre_plane_update(old_slave_crtc_state, new_slave_crtc_state);
> + if (old_slave_crtc_state->base.active)
> + intel_old_crtc_state_disables(state,
> + old_slave_crtc_state,
> + new_slave_crtc_state,
> + slave_crtc);
> +
> + /* Disable Master */
> + intel_pre_plane_update(old_crtc_state, new_crtc_state);
> + if (old_crtc_state->base.active)
> + intel_old_crtc_state_disables(state,
> + old_crtc_state,
> + new_crtc_state,
> + crtc);
> +}
> +
> static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> {
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> struct intel_crtc *crtc;
> int i;
> @@ -14092,13 +14126,29 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> if (!needs_modeset(new_crtc_state))
> continue;
>
> - intel_pre_plane_update(old_crtc_state, new_crtc_state);
> + /* In case of Transcoder port Sync master slave CRTCs can be
> + * assigned in any order and we need to make sure that
> + * slave CRTCs are disabled first and then master CRTC since
> + * Slave vblanks are masked till Master Vblanks.
> + */
> + if (is_trans_port_sync_mode(dev_priv, new_crtc_state)) {
> + if (is_trans_port_sync_master(dev_priv,
> + new_crtc_state))
> + intel_trans_port_sync_modeset_disables(state,
> + crtc,
> + old_crtc_state,
> + new_crtc_state);
> + else
> + continue;
> + } else {
> + intel_pre_plane_update(old_crtc_state, new_crtc_state);
>
> - if (old_crtc_state->base.active)
> - intel_old_crtc_state_disables(state,
> - old_crtc_state,
> - new_crtc_state,
> - crtc);
> + if (old_crtc_state->base.active)
> + intel_old_crtc_state_disables(state,
> + old_crtc_state,
> + new_crtc_state,
> + crtc);
> + }
> }
> }
>
Series looks good with those fixes:
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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^ permalink raw reply [flat|nested] 31+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (5 preceding siblings ...)
2019-09-09 3:43 ` [PATCH 6/6] drm/i915/display/icl: In port sync mode disable slaves first then master Manasi Navare
@ 2019-09-09 4:10 ` Patchwork
2019-09-09 4:11 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-09-09 4:10 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays
URL : https://patchwork.freedesktop.org/series/66403/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b5030e9f1630 drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
28255a0f88ab drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
9f1c5ffded6c drm/i915/display/icl: HW state readout for transcoder port sync config
1d8c2a6820a9 drm/i915/display/icl: Enable master-slaves in trans port sync
-:32: WARNING:BAD_SIGN_OFF: Duplicate signature
#32:
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
-:81: ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:13995:
+static struct intel_crtc * intel_get_slave_crtc(struct drm_i915_private *dev_priv,
total: 1 errors, 1 warnings, 0 checks, 223 lines checked
2301db48a9ee drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
b2814fee7fcb drm/i915/display/icl: In port sync mode disable slaves first then master
-:35: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#35: FILE: drivers/gpu/drm/i915/display/intel_display.c:14077:
+static void intel_trans_port_sync_modeset_disables (struct intel_atomic_state *state,
-:53: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 32)
#53: FILE: drivers/gpu/drm/i915/display/intel_display.c:14095:
+ if (old_slave_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
-:61: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 32)
#61: FILE: drivers/gpu/drm/i915/display/intel_display.c:14103:
+ if (old_crtc_state->base.active)
+ intel_old_crtc_state_disables(state,
total: 0 errors, 3 warnings, 0 checks, 77 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.SPARSE: warning for Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (6 preceding siblings ...)
2019-09-09 4:10 ` ✗ Fi.CI.CHECKPATCH: warning for Remaining patches to enable Transcoder Port Sync for tiled displays Patchwork
@ 2019-09-09 4:11 ` Patchwork
2019-09-09 19:44 ` ✗ Fi.CI.SPARSE: warning for Remaining patches to enable Transcoder Port Sync for tiled displays (rev3) Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-09-09 4:11 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays
URL : https://patchwork.freedesktop.org/series/66403/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.SPARSE: warning for Remaining patches to enable Transcoder Port Sync for tiled displays (rev3)
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (7 preceding siblings ...)
2019-09-09 4:11 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-09-09 19:44 ` Patchwork
2019-09-09 20:06 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-09-10 9:29 ` [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Jani Nikula
10 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-09-09 19:44 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays (rev3)
URL : https://patchwork.freedesktop.org/series/66403/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ Fi.CI.BAT: failure for Remaining patches to enable Transcoder Port Sync for tiled displays (rev3)
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (8 preceding siblings ...)
2019-09-09 19:44 ` ✗ Fi.CI.SPARSE: warning for Remaining patches to enable Transcoder Port Sync for tiled displays (rev3) Patchwork
@ 2019-09-09 20:06 ` Patchwork
2019-09-10 9:29 ` [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Jani Nikula
10 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2019-09-09 20:06 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: Remaining patches to enable Transcoder Port Sync for tiled displays (rev3)
URL : https://patchwork.freedesktop.org/series/66403/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6854 -> Patchwork_14331
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14331 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14331, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14331/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14331:
### IGT changes ###
#### Possible regressions ####
* igt@kms_busy@basic-flip-a:
- fi-icl-u3: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14331/fi-icl-u3/igt@kms_busy@basic-flip-a.html
- fi-icl-u2: NOTRUN -> [DMESG-WARN][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14331/fi-icl-u2/igt@kms_busy@basic-flip-a.html
Known issues
------------
Here are the changes found in Patchwork_14331 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14331/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
#### Possible fixes ####
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [INCOMPLETE][5] ([fdo#107713] / [fdo#111381]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6854/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14331/fi-icl-u2/igt@gem_ctx_switch@legacy-render.html
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (51 -> 46)
------------------------------
Additional (3): fi-icl-dsi fi-cfl-guc fi-icl-u3
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6854 -> Patchwork_14331
CI-20190529: 20190529
CI_DRM_6854: 5a70800ed2837e2d35a331e2cfd43a55df58c4fc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5176: 0102dcf4e2e8b357b59173fe1ff78069148080c6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14331: c6089022b185ffc336e501d5dcedf3a417be1aa0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c6089022b185 drm/i915/display/icl: In port sync mode disable slaves first then master
3c58f43453f3 drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence
2576578487b6 drm/i915/display/icl: Enable master-slaves in trans port sync
ba73d181a88e drm/i915/display/icl: HW state readout for transcoder port sync config
aa76e13afd97 drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports
93aa5d97589f drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14331/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-09 3:43 [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Manasi Navare
` (9 preceding siblings ...)
2019-09-09 20:06 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-09-10 9:29 ` Jani Nikula
2019-09-10 18:07 ` Manasi Navare
10 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2019-09-10 9:29 UTC (permalink / raw)
To: Manasi Navare, intel-gfx
On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> This patch series addresses all review comments and now the enable and
> disable paths follow the method of obtaining slave states from master
> and updating master-slaves in correct order during master modeset.
Main high level question: what does it take to enable this on gen9+?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-10 9:29 ` [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays Jani Nikula
@ 2019-09-10 18:07 ` Manasi Navare
2019-09-10 21:19 ` Manasi Navare
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-10 18:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > This patch series addresses all review comments and now the enable and
> > disable paths follow the method of obtaining slave states from master
> > and updating master-slaves in correct order during master modeset.
>
> Main high level question: what does it take to enable this on gen9+?
As per the Bspec project platforms, the first platform that supports this is
ICL
Regards
Manasi
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-10 18:07 ` Manasi Navare
@ 2019-09-10 21:19 ` Manasi Navare
2019-09-11 9:08 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-10 21:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > > This patch series addresses all review comments and now the enable and
> > > disable paths follow the method of obtaining slave states from master
> > > and updating master-slaves in correct order during master modeset.
> >
> > Main high level question: what does it take to enable this on gen9+?
>
> As per the Bspec project platforms, the first platform that supports this is
> ICL
Hi Jani,
Apparently the Bspec caused some confusion, after double checking with the
HW teams here, this feature is enabled starting BDW for the SST connectors
and only the MST support is new to Gen 11+.
So i guess I can change the patches to add support starting BDW and this should
also fix the 5K tiled display issue that Ankit has been working on
Manasi
>
> Regards
> Manasi
>
> >
> > BR,
> > Jani.
> >
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-10 21:19 ` Manasi Navare
@ 2019-09-11 9:08 ` Jani Nikula
2019-09-11 16:27 ` Manasi Navare
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2019-09-11 9:08 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
>> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
>> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
>> > > This patch series addresses all review comments and now the enable and
>> > > disable paths follow the method of obtaining slave states from master
>> > > and updating master-slaves in correct order during master modeset.
>> >
>> > Main high level question: what does it take to enable this on gen9+?
>>
>> As per the Bspec project platforms, the first platform that supports this is
>> ICL
>
> Hi Jani,
>
> Apparently the Bspec caused some confusion, after double checking with the
> HW teams here, this feature is enabled starting BDW for the SST connectors
> and only the MST support is new to Gen 11+.
>
> So i guess I can change the patches to add support starting BDW and
> this should also fix the 5K tiled display issue that Ankit has been
> working on
Thanks! I don't mind getting the patches merged for ICL+ at first, and
updating to cover older gens in follow-up.
BR,
Jani.
>
> Manasi
>
>>
>> Regards
>> Manasi
>>
>> >
>> > BR,
>> > Jani.
>> >
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-11 9:08 ` Jani Nikula
@ 2019-09-11 16:27 ` Manasi Navare
2019-09-12 6:42 ` Jani Nikula
0 siblings, 1 reply; 31+ messages in thread
From: Manasi Navare @ 2019-09-11 16:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote:
> On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> >> > > This patch series addresses all review comments and now the enable and
> >> > > disable paths follow the method of obtaining slave states from master
> >> > > and updating master-slaves in correct order during master modeset.
> >> >
> >> > Main high level question: what does it take to enable this on gen9+?
> >>
> >> As per the Bspec project platforms, the first platform that supports this is
> >> ICL
> >
> > Hi Jani,
> >
> > Apparently the Bspec caused some confusion, after double checking with the
> > HW teams here, this feature is enabled starting BDW for the SST connectors
> > and only the MST support is new to Gen 11+.
> >
> > So i guess I can change the patches to add support starting BDW and
> > this should also fix the 5K tiled display issue that Ankit has been
> > working on
>
> Thanks! I don't mind getting the patches merged for ICL+ at first, and
> updating to cover older gens in follow-up.
So you are suggesting that i keep the patches as is and have them get merged first
and then i could change the GEN checks to add support for BDW+?
Regards
Manasi
>
> BR,
> Jani.
>
>
> >
> > Manasi
> >
> >>
> >> Regards
> >> Manasi
> >>
> >> >
> >> > BR,
> >> > Jani.
> >> >
> >> >
> >> > --
> >> > Jani Nikula, Intel Open Source Graphics Center
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-11 16:27 ` Manasi Navare
@ 2019-09-12 6:42 ` Jani Nikula
2019-09-12 18:35 ` Manasi Navare
0 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2019-09-12 6:42 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, 11 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote:
>> On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
>> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
>> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
>> >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
>> >> > > This patch series addresses all review comments and now the enable and
>> >> > > disable paths follow the method of obtaining slave states from master
>> >> > > and updating master-slaves in correct order during master modeset.
>> >> >
>> >> > Main high level question: what does it take to enable this on gen9+?
>> >>
>> >> As per the Bspec project platforms, the first platform that supports this is
>> >> ICL
>> >
>> > Hi Jani,
>> >
>> > Apparently the Bspec caused some confusion, after double checking with the
>> > HW teams here, this feature is enabled starting BDW for the SST connectors
>> > and only the MST support is new to Gen 11+.
>> >
>> > So i guess I can change the patches to add support starting BDW and
>> > this should also fix the 5K tiled display issue that Ankit has been
>> > working on
>>
>> Thanks! I don't mind getting the patches merged for ICL+ at first, and
>> updating to cover older gens in follow-up.
>
> So you are suggesting that i keep the patches as is and have them get
> merged first and then i could change the GEN checks to add support for
> BDW+?
I'm saying it's up to you. Whatever makes most sense to you. If you're
at the brink of getting the ICL patches merged, there's not much point
in rehashing and delaying that, is there?
BR,
Jani.
>
> Regards
> Manasi
>
>>
>> BR,
>> Jani.
>>
>>
>> >
>> > Manasi
>> >
>> >>
>> >> Regards
>> >> Manasi
>> >>
>> >> >
>> >> > BR,
>> >> > Jani.
>> >> >
>> >> >
>> >> > --
>> >> > Jani Nikula, Intel Open Source Graphics Center
>> >> _______________________________________________
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH 0/6] Remaining patches to enable Transcoder Port Sync for tiled displays
2019-09-12 6:42 ` Jani Nikula
@ 2019-09-12 18:35 ` Manasi Navare
0 siblings, 0 replies; 31+ messages in thread
From: Manasi Navare @ 2019-09-12 18:35 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Sep 12, 2019 at 09:42:11AM +0300, Jani Nikula wrote:
> On Wed, 11 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> > On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote:
> >> On Tue, 10 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> >> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
> >> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> >> >> > On Sun, 08 Sep 2019, Manasi Navare <manasi.d.navare@intel.com> wrote:
> >> >> > > This patch series addresses all review comments and now the enable and
> >> >> > > disable paths follow the method of obtaining slave states from master
> >> >> > > and updating master-slaves in correct order during master modeset.
> >> >> >
> >> >> > Main high level question: what does it take to enable this on gen9+?
> >> >>
> >> >> As per the Bspec project platforms, the first platform that supports this is
> >> >> ICL
> >> >
> >> > Hi Jani,
> >> >
> >> > Apparently the Bspec caused some confusion, after double checking with the
> >> > HW teams here, this feature is enabled starting BDW for the SST connectors
> >> > and only the MST support is new to Gen 11+.
> >> >
> >> > So i guess I can change the patches to add support starting BDW and
> >> > this should also fix the 5K tiled display issue that Ankit has been
> >> > working on
> >>
> >> Thanks! I don't mind getting the patches merged for ICL+ at first, and
> >> updating to cover older gens in follow-up.
> >
> > So you are suggesting that i keep the patches as is and have them get
> > merged first and then i could change the GEN checks to add support for
> > BDW+?
>
> I'm saying it's up to you. Whatever makes most sense to you. If you're
> at the brink of getting the ICL patches merged, there's not much point
> in rehashing and delaying that, is there?
Yes I agree, thanks a lot Jani for your inputs/suggestions. I will push for the
reviews on these for ICL+ and get these merged first.
Manasi
>
> BR,
> Jani.
>
>
> >
> > Regards
> > Manasi
> >
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> >
> >> > Manasi
> >> >
> >> >>
> >> >> Regards
> >> >> Manasi
> >> >>
> >> >> >
> >> >> > BR,
> >> >> > Jani.
> >> >> >
> >> >> >
> >> >> > --
> >> >> > Jani Nikula, Intel Open Source Graphics Center
> >> >> _______________________________________________
> >> >> Intel-gfx mailing list
> >> >> Intel-gfx@lists.freedesktop.org
> >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 31+ messages in thread