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From: Jan Siegmund <jan.siegmund0@hm.edu>
To: "u-boot@lists.denx.de" <u-boot@lists.denx.de>
Cc: Anatolij Gustschin <agust@denx.de>,
	"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
	marex@denx.de
Subject: Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA
Date: Mon, 18 Dec 2017 21:44:24 +0100	[thread overview]
Message-ID: <db4aae59-d3fa-4904-c4ac-e96668667f3f@hm.edu> (raw)

Hi all,
Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC.
Is is possible to configure the the interface in U-Boot or SPL,
without reprogramming the FPGA? Maybe through the usage of the generated
header files from the Quartus synthesis?
The SDRAM controller's registers only differ in eight entries in Linux when the
FPGA is programmed or not.

+----------+-------------+------------+----------------+
| address  |    name     | programmed | not programmed |
+----------+-------------+------------+----------------+
| FFC25064 |             | 00044003   | 00044FFF       |
| FFC25068 |             | 2C000000   | 2C03FFFF       |
| FFC2506c |             | 00B00000   | 00B3FFFF       |
| FFC25070 |             | 00760000   | 0076FFFF       |
| FFC25074 |             | 00980000   | 0098FFFF       |
| FFC25078 |             | 0005A003   | 0005AFFF       |
| FFC2507c | portcfg     | 00000000   | 0000003F       |
| FFC25080 | fpgaportrst | 000001FF   | 00000000       |
+----------+-------------+------------+----------------+

The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map
[1], so are they even intended to be configured?

Thanks



[1]
https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sfo1411577380716

WARNING: multiple messages have this Message-ID (diff)
From: Jan Siegmund <jan.siegmund0@hm.edu>
To: u-boot@lists.denx.de
Subject: [U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA
Date: Mon, 18 Dec 2017 21:44:24 +0100	[thread overview]
Message-ID: <db4aae59-d3fa-4904-c4ac-e96668667f3f@hm.edu> (raw)

Hi all,
Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC.
Is is possible to configure the the interface in U-Boot or SPL,
without reprogramming the FPGA? Maybe through the usage of the generated
header files from the Quartus synthesis?
The SDRAM controller's registers only differ in eight entries in Linux when the
FPGA is programmed or not.

+----------+-------------+------------+----------------+
| address  |    name     | programmed | not programmed |
+----------+-------------+------------+----------------+
| FFC25064 |             | 00044003   | 00044FFF       |
| FFC25068 |             | 2C000000   | 2C03FFFF       |
| FFC2506c |             | 00B00000   | 00B3FFFF       |
| FFC25070 |             | 00760000   | 0076FFFF       |
| FFC25074 |             | 00980000   | 0098FFFF       |
| FFC25078 |             | 0005A003   | 0005AFFF       |
| FFC2507c | portcfg     | 00000000   | 0000003F       |
| FFC25080 | fpgaportrst | 000001FF   | 00000000       |
+----------+-------------+------------+----------------+

The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map
[1], so are they even intended to be configured?

Thanks



[1]
https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sfo1411577380716

             reply	other threads:[~2017-12-18 20:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-18 20:44 Jan Siegmund [this message]
2017-12-18 20:44 ` [U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA Jan Siegmund
2017-12-18 21:05 ` Marek Vasut
2017-12-18 21:05   ` [U-Boot] " Marek Vasut
2017-12-19 23:29   ` Jan Siegmund
2017-12-19 23:29     ` [U-Boot] " Jan Siegmund
2017-12-20  9:35     ` Marek Vasut
2017-12-20  9:35       ` [U-Boot] " Marek Vasut
2017-12-20 11:51       ` Jan Siegmund
2017-12-20 11:51         ` [U-Boot] " Jan Siegmund
2017-12-20 15:06         ` Marek Vasut
2017-12-20 15:06           ` [U-Boot] " Marek Vasut

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