* [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers
@ 2017-12-18 8:49 Kever Yang
2017-12-18 8:49 ` [U-Boot] [PATCH v4 2/2] rockchip: clk: bind reset driver Kever Yang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Kever Yang @ 2017-12-18 8:49 UTC (permalink / raw)
To: u-boot
From: Elaine Zhang <zhangqing@rock-chips.com>
Create driver to support all Rockchip SoCs soft reset.
Example of usage:
i2c driver:
ret = reset_get_by_name(dev, "i2c", &reset_ctl);
if (ret) {
error("reset_get_by_name() failed: %d\n", ret);
}
reset_assert(&reset_ctl);
udelay(50);
reset_deassert(&reset_ctl);
i2c dts node:
resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
reset-names = "p_i2c", "i2c";
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- fix Kconfig more than 80 length
- use MACRO for reset bits in one reg
- use rkclr/set_reg for reg access
- add rockchip_reset_bind()
- use dev_read_addr_size() instead of fdtdec_
drivers/reset/Kconfig | 9 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 drivers/reset/reset-rockchip.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ce46e27..97a78d7 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -74,4 +74,13 @@ config AST2500_RESET
resets that are supported by watchdog. The main limitation though
is that some reset signals, like I2C or MISC reset multiple devices.
+config RESET_ROCKCHIP
+ bool "Reset controller driver for Rockchip SoCs"
+ depends on DM_RESET && CLK
+ default y
+ help
+ Support for reset controller on rockchip SoC. The main limitation
+ though is that some reset signals, like I2C or MISC reset multiple
+ devices.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 252cefe..7d7e080 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
new file mode 100644
index 0000000..01047a2
--- /dev/null
+++ b/drivers/reset/reset-rockchip.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <linux/io.h>
+#include <asm/arch/hardware.h>
+#include <dm/lists.h>
+/*
+ * Each reg has 16 bits reset signal for devices
+ * Note: Not including rk2818 and older SoCs
+ */
+#define ROCKCHIP_RESET_NUM_IN_REG 16
+
+struct rockchip_reset_priv {
+ void __iomem *base;
+ /* Rockchip reset reg locate at cru controller */
+ u32 reset_reg_offset;
+ /* Rockchip reset reg number */
+ u32 reset_reg_num;
+};
+
+static int rockchip_reset_request(struct reset_ctl *reset_ctl)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
+
+ if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rockchip_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+ int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id,
+ priv->base + (bank * 4));
+
+ rk_setreg(priv->base + (bank * 4), BIT(offset));
+
+ return 0;
+}
+
+static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+ int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+ reset_ctl, reset_ctl->dev, reset_ctl->id,
+ priv->base + (bank * 4));
+
+ rk_clrreg(priv->base + (bank * 4), BIT(offset));
+
+ return 0;
+}
+
+struct reset_ops rockchip_reset_ops = {
+ .request = rockchip_reset_request,
+ .free = rockchip_reset_free,
+ .rst_assert = rockchip_reset_assert,
+ .rst_deassert = rockchip_reset_deassert,
+};
+
+static int rockchip_reset_probe(struct udevice *dev)
+{
+ struct rockchip_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = dev_read_addr_size(dev, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
+ return -EINVAL;
+
+ addr += priv->reset_reg_offset;
+ priv->base = ioremap(addr, size);
+
+ debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
+ priv->base, priv->reset_reg_offset, priv->reset_reg_num);
+
+ return 0;
+}
+
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+ struct udevice *rst_dev;
+ struct rockchip_reset_priv *priv;
+ int ret;
+
+ ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
+ dev_ofnode(pdev), &rst_dev);
+ if (ret) {
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+ return ret;
+ }
+ priv = malloc(sizeof(struct rockchip_reset_priv));
+ priv->reset_reg_offset = reg_offset;
+ priv->reset_reg_num = reg_number;
+ rst_dev->priv = priv;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_reset) = {
+ .name = "rockchip_reset",
+ .id = UCLASS_RESET,
+ .probe = rockchip_reset_probe,
+ .ops = &rockchip_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v4 2/2] rockchip: clk: bind reset driver
2017-12-18 8:49 [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers Kever Yang
@ 2017-12-18 8:49 ` Kever Yang
2017-12-18 9:55 ` [U-Boot] [U-Boot,v4,2/2] " Philipp Tomsich
2017-12-18 9:55 ` [U-Boot] [U-Boot, v4, 1/2] drivers/reset: support rockchip reset drivers Philipp Tomsich
2017-12-19 9:29 ` [U-Boot] [PATCH v4 " Dr. Philipp Tomsich
2 siblings, 1 reply; 6+ messages in thread
From: Kever Yang @ 2017-12-18 8:49 UTC (permalink / raw)
To: u-boot
From: Elaine Zhang <zhangqing@rock-chips.com>
Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v4:
- fix compile error if CONFIG_RESET_ROCKCHIP not defined
Changes in v3:
- add missing offset for rk3399 pmuclk bind
Changes in v2:
- use rockchip_reset_bind() to bind reset driver.
arch/arm/include/asm/arch-rockchip/clock.h | 10 ++++++++++
drivers/clk/rockchip/clk_rk3036.c | 7 +++++++
drivers/clk/rockchip/clk_rk3188.c | 7 +++++++
drivers/clk/rockchip/clk_rk322x.c | 7 +++++++
drivers/clk/rockchip/clk_rk3288.c | 7 +++++++
drivers/clk/rockchip/clk_rk3328.c | 7 +++++++
drivers/clk/rockchip/clk_rk3368.c | 7 +++++++
drivers/clk/rockchip/clk_rk3399.c | 21 +++++++++++++++++++++
drivers/clk/rockchip/clk_rv1108.c | 7 +++++++
9 files changed, 80 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 736b260..5264111 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -85,4 +85,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
int rockchip_get_clk(struct udevice **devp);
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
#endif
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 280ebb9..510a00a 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -347,6 +347,13 @@ static int rk3036_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 9);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index fca6899..6451c95 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -590,6 +590,13 @@ static int rk3188_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 9);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index ff52b55..c8a2413 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -402,6 +402,13 @@ static int rk322x_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 9);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index ac53239..b64c107 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -876,6 +876,13 @@ static int rk3288_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 12);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 4d522a7..fa0c777 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -614,6 +614,13 @@ static int rk3328_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3328_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 12);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return ret;
}
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index bfeef39..a831991 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -543,6 +543,13 @@ static int rk3368_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3368_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 15);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return ret;
}
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 2e85ac7..2f4c4e3 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1046,6 +1046,13 @@ static int rk3399_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3399_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 21);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
@@ -1221,6 +1228,19 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
return 0;
}
+static int rk3399_pmuclk_bind(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ int ret;
+
+ ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 2);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+ return 0;
+}
+
static const struct udevice_id rk3399_pmuclk_ids[] = {
{ .compatible = "rockchip,rk3399-pmucru" },
{ }
@@ -1234,6 +1254,7 @@ U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
.ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
.ops = &rk3399_pmuclk_ops,
.probe = rk3399_pmuclk_probe,
+ .bind = rk3399_pmuclk_bind,
#if CONFIG_IS_ENABLED(OF_PLATDATA)
.platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
#endif
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index a119548..224c813 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -240,6 +240,13 @@ static int rv1108_clk_bind(struct udevice *dev)
sys_child->priv = priv;
}
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+ ret = offsetof(struct rk3368_cru, softrst_con[0]);
+ ret = rockchip_reset_bind(dev, ret, 13);
+ if (ret)
+ debug("Warning: software reset driver bind faile\n");
+#endif
+
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [U-Boot, v4, 1/2] drivers/reset: support rockchip reset drivers
2017-12-18 8:49 [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers Kever Yang
2017-12-18 8:49 ` [U-Boot] [PATCH v4 2/2] rockchip: clk: bind reset driver Kever Yang
@ 2017-12-18 9:55 ` Philipp Tomsich
2017-12-19 9:29 ` [U-Boot] [PATCH v4 " Dr. Philipp Tomsich
2 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2017-12-18 9:55 UTC (permalink / raw)
To: u-boot
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> Create driver to support all Rockchip SoCs soft reset.
> Example of usage:
> i2c driver:
> ret = reset_get_by_name(dev, "i2c", &reset_ctl);
> if (ret) {
> error("reset_get_by_name() failed: %d\n", ret);
> }
>
> reset_assert(&reset_ctl);
> udelay(50);
> reset_deassert(&reset_ctl);
>
> i2c dts node:
> resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
> reset-names = "p_i2c", "i2c";
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - fix Kconfig more than 80 length
> - use MACRO for reset bits in one reg
> - use rkclr/set_reg for reg access
> - add rockchip_reset_bind()
> - use dev_read_addr_size() instead of fdtdec_
>
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 drivers/reset/reset-rockchip.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [U-Boot,v4,2/2] rockchip: clk: bind reset driver
2017-12-18 8:49 ` [U-Boot] [PATCH v4 2/2] rockchip: clk: bind reset driver Kever Yang
@ 2017-12-18 9:55 ` Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2017-12-18 9:55 UTC (permalink / raw)
To: u-boot
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> Bind rockchip reset to clock-controller with rockchip_reset_bind().
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v4:
> - fix compile error if CONFIG_RESET_ROCKCHIP not defined
>
> Changes in v3:
> - add missing offset for rk3399 pmuclk bind
>
> Changes in v2:
> - use rockchip_reset_bind() to bind reset driver.
>
> arch/arm/include/asm/arch-rockchip/clock.h | 10 ++++++++++
> drivers/clk/rockchip/clk_rk3036.c | 7 +++++++
> drivers/clk/rockchip/clk_rk3188.c | 7 +++++++
> drivers/clk/rockchip/clk_rk322x.c | 7 +++++++
> drivers/clk/rockchip/clk_rk3288.c | 7 +++++++
> drivers/clk/rockchip/clk_rk3328.c | 7 +++++++
> drivers/clk/rockchip/clk_rk3368.c | 7 +++++++
> drivers/clk/rockchip/clk_rk3399.c | 21 +++++++++++++++++++++
> drivers/clk/rockchip/clk_rv1108.c | 7 +++++++
> 9 files changed, 80 insertions(+)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers
2017-12-18 8:49 [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers Kever Yang
2017-12-18 8:49 ` [U-Boot] [PATCH v4 2/2] rockchip: clk: bind reset driver Kever Yang
2017-12-18 9:55 ` [U-Boot] [U-Boot, v4, 1/2] drivers/reset: support rockchip reset drivers Philipp Tomsich
@ 2017-12-19 9:29 ` Dr. Philipp Tomsich
2017-12-19 10:25 ` Kever Yang
2 siblings, 1 reply; 6+ messages in thread
From: Dr. Philipp Tomsich @ 2017-12-19 9:29 UTC (permalink / raw)
To: u-boot
Kever,
while this version has finally fixed the build errors for the rockchip-targets, it still
causes major build failures for other target families:
see https://travis-ci.org/ptomsich/u-boot-rockchip/builds/318128281
The new driver still appears to be built for the failing boards.
Regards,
Philipp.
> On 18 Dec 2017, at 09:49, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> Create driver to support all Rockchip SoCs soft reset.
> Example of usage:
> i2c driver:
> ret = reset_get_by_name(dev, "i2c", &reset_ctl);
> if (ret) {
> error("reset_get_by_name() failed: %d\n", ret);
> }
>
> reset_assert(&reset_ctl);
> udelay(50);
> reset_deassert(&reset_ctl);
>
> i2c dts node:
> resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
> reset-names = "p_i2c", "i2c";
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - fix Kconfig more than 80 length
> - use MACRO for reset bits in one reg
> - use rkclr/set_reg for reg access
> - add rockchip_reset_bind()
> - use dev_read_addr_size() instead of fdtdec_
>
> drivers/reset/Kconfig | 9 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 drivers/reset/reset-rockchip.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index ce46e27..97a78d7 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -74,4 +74,13 @@ config AST2500_RESET
> resets that are supported by watchdog. The main limitation though
> is that some reset signals, like I2C or MISC reset multiple devices.
>
> +config RESET_ROCKCHIP
> + bool "Reset controller driver for Rockchip SoCs"
> + depends on DM_RESET && CLK
> + default y
> + help
> + Support for reset controller on rockchip SoC. The main limitation
> + though is that some reset signals, like I2C or MISC reset multiple
> + devices.
> +
> endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 252cefe..7d7e080 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
> obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
> +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
> diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
> new file mode 100644
> index 0000000..01047a2
> --- /dev/null
> +++ b/drivers/reset/reset-rockchip.c
> @@ -0,0 +1,133 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <reset-uclass.h>
> +#include <linux/io.h>
> +#include <asm/arch/hardware.h>
> +#include <dm/lists.h>
> +/*
> + * Each reg has 16 bits reset signal for devices
> + * Note: Not including rk2818 and older SoCs
> + */
> +#define ROCKCHIP_RESET_NUM_IN_REG 16
> +
> +struct rockchip_reset_priv {
> + void __iomem *base;
> + /* Rockchip reset reg locate at cru controller */
> + u32 reset_reg_offset;
> + /* Rockchip reset reg number */
> + u32 reset_reg_num;
> +};
> +
> +static int rockchip_reset_request(struct reset_ctl *reset_ctl)
> +{
> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> +
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
> + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
> +
> + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int rockchip_reset_free(struct reset_ctl *reset_ctl)
> +{
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
> + reset_ctl->dev, reset_ctl->id);
> +
> + return 0;
> +}
> +
> +static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
> +{
> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
> + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
> +
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
> + reset_ctl, reset_ctl->dev, reset_ctl->id,
> + priv->base + (bank * 4));
> +
> + rk_setreg(priv->base + (bank * 4), BIT(offset));
> +
> + return 0;
> +}
> +
> +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
> +{
> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
> + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
> + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
> +
> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
> + reset_ctl, reset_ctl->dev, reset_ctl->id,
> + priv->base + (bank * 4));
> +
> + rk_clrreg(priv->base + (bank * 4), BIT(offset));
> +
> + return 0;
> +}
> +
> +struct reset_ops rockchip_reset_ops = {
> + .request = rockchip_reset_request,
> + .free = rockchip_reset_free,
> + .rst_assert = rockchip_reset_assert,
> + .rst_deassert = rockchip_reset_deassert,
> +};
> +
> +static int rockchip_reset_probe(struct udevice *dev)
> +{
> + struct rockchip_reset_priv *priv = dev_get_priv(dev);
> + fdt_addr_t addr;
> + fdt_size_t size;
> +
> + addr = dev_read_addr_size(dev, "reg", &size);
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
> + return -EINVAL;
> +
> + addr += priv->reset_reg_offset;
> + priv->base = ioremap(addr, size);
> +
> + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
> + priv->base, priv->reset_reg_offset, priv->reset_reg_num);
> +
> + return 0;
> +}
> +
> +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
> +{
> + struct udevice *rst_dev;
> + struct rockchip_reset_priv *priv;
> + int ret;
> +
> + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
> + dev_ofnode(pdev), &rst_dev);
> + if (ret) {
> + debug("Warning: No rockchip reset driver: ret=%d\n", ret);
> + return ret;
> + }
> + priv = malloc(sizeof(struct rockchip_reset_priv));
> + priv->reset_reg_offset = reg_offset;
> + priv->reset_reg_num = reg_number;
> + rst_dev->priv = priv;
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(rockchip_reset) = {
> + .name = "rockchip_reset",
> + .id = UCLASS_RESET,
> + .probe = rockchip_reset_probe,
> + .ops = &rockchip_reset_ops,
> + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
> +};
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers
2017-12-19 9:29 ` [U-Boot] [PATCH v4 " Dr. Philipp Tomsich
@ 2017-12-19 10:25 ` Kever Yang
0 siblings, 0 replies; 6+ messages in thread
From: Kever Yang @ 2017-12-19 10:25 UTC (permalink / raw)
To: u-boot
Philipp,
On 12/19/2017 05:29 PM, Dr. Philipp Tomsich wrote:
> Kever,
>
> while this version has finally fixed the build errors for the rockchip-targets, it still
> causes major build failures for other target families:
> see https://travis-ci.org/ptomsich/u-boot-rockchip/builds/318128281
>
> The new driver still appears to be built for the failing boards.
I will make it depends on ARCH_ROCKCHIP.
Thanks,
- Kever
>
> Regards,
> Philipp.
>
>> On 18 Dec 2017, at 09:49, Kever Yang <kever.yang@rock-chips.com> wrote:
>>
>> From: Elaine Zhang <zhangqing@rock-chips.com>
>>
>> Create driver to support all Rockchip SoCs soft reset.
>> Example of usage:
>> i2c driver:
>> ret = reset_get_by_name(dev, "i2c", &reset_ctl);
>> if (ret) {
>> error("reset_get_by_name() failed: %d\n", ret);
>> }
>>
>> reset_assert(&reset_ctl);
>> udelay(50);
>> reset_deassert(&reset_ctl);
>>
>> i2c dts node:
>> resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
>> reset-names = "p_i2c", "i2c";
>>
>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2:
>> - fix Kconfig more than 80 length
>> - use MACRO for reset bits in one reg
>> - use rkclr/set_reg for reg access
>> - add rockchip_reset_bind()
>> - use dev_read_addr_size() instead of fdtdec_
>>
>> drivers/reset/Kconfig | 9 +++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 143 insertions(+)
>> create mode 100644 drivers/reset/reset-rockchip.c
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index ce46e27..97a78d7 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -74,4 +74,13 @@ config AST2500_RESET
>> resets that are supported by watchdog. The main limitation though
>> is that some reset signals, like I2C or MISC reset multiple devices.
>>
>> +config RESET_ROCKCHIP
>> + bool "Reset controller driver for Rockchip SoCs"
>> + depends on DM_RESET && CLK
>> + default y
>> + help
>> + Support for reset controller on rockchip SoC. The main limitation
>> + though is that some reset signals, like I2C or MISC reset multiple
>> + devices.
>> +
>> endmenu
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 252cefe..7d7e080 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
>> obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
>> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
>> +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
>> diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
>> new file mode 100644
>> index 0000000..01047a2
>> --- /dev/null
>> +++ b/drivers/reset/reset-rockchip.c
>> @@ -0,0 +1,133 @@
>> +/*
>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <reset-uclass.h>
>> +#include <linux/io.h>
>> +#include <asm/arch/hardware.h>
>> +#include <dm/lists.h>
>> +/*
>> + * Each reg has 16 bits reset signal for devices
>> + * Note: Not including rk2818 and older SoCs
>> + */
>> +#define ROCKCHIP_RESET_NUM_IN_REG 16
>> +
>> +struct rockchip_reset_priv {
>> + void __iomem *base;
>> + /* Rockchip reset reg locate at cru controller */
>> + u32 reset_reg_offset;
>> + /* Rockchip reset reg number */
>> + u32 reset_reg_num;
>> +};
>> +
>> +static int rockchip_reset_request(struct reset_ctl *reset_ctl)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
>> +
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
>> + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
>> +
>> + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
>> + return -EINVAL;
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_reset_free(struct reset_ctl *reset_ctl)
>> +{
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
>> + reset_ctl->dev, reset_ctl->id);
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
>> + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
>> + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
>> +
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
>> + reset_ctl, reset_ctl->dev, reset_ctl->id,
>> + priv->base + (bank * 4));
>> +
>> + rk_setreg(priv->base + (bank * 4), BIT(offset));
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
>> + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
>> + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
>> +
>> + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
>> + reset_ctl, reset_ctl->dev, reset_ctl->id,
>> + priv->base + (bank * 4));
>> +
>> + rk_clrreg(priv->base + (bank * 4), BIT(offset));
>> +
>> + return 0;
>> +}
>> +
>> +struct reset_ops rockchip_reset_ops = {
>> + .request = rockchip_reset_request,
>> + .free = rockchip_reset_free,
>> + .rst_assert = rockchip_reset_assert,
>> + .rst_deassert = rockchip_reset_deassert,
>> +};
>> +
>> +static int rockchip_reset_probe(struct udevice *dev)
>> +{
>> + struct rockchip_reset_priv *priv = dev_get_priv(dev);
>> + fdt_addr_t addr;
>> + fdt_size_t size;
>> +
>> + addr = dev_read_addr_size(dev, "reg", &size);
>> + if (addr == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
>> + return -EINVAL;
>> +
>> + addr += priv->reset_reg_offset;
>> + priv->base = ioremap(addr, size);
>> +
>> + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
>> + priv->base, priv->reset_reg_offset, priv->reset_reg_num);
>> +
>> + return 0;
>> +}
>> +
>> +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
>> +{
>> + struct udevice *rst_dev;
>> + struct rockchip_reset_priv *priv;
>> + int ret;
>> +
>> + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
>> + dev_ofnode(pdev), &rst_dev);
>> + if (ret) {
>> + debug("Warning: No rockchip reset driver: ret=%d\n", ret);
>> + return ret;
>> + }
>> + priv = malloc(sizeof(struct rockchip_reset_priv));
>> + priv->reset_reg_offset = reg_offset;
>> + priv->reset_reg_num = reg_number;
>> + rst_dev->priv = priv;
>> +
>> + return 0;
>> +}
>> +
>> +U_BOOT_DRIVER(rockchip_reset) = {
>> + .name = "rockchip_reset",
>> + .id = UCLASS_RESET,
>> + .probe = rockchip_reset_probe,
>> + .ops = &rockchip_reset_ops,
>> + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
>> +};
>> --
>> 1.9.1
>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-12-19 10:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-18 8:49 [U-Boot] [PATCH v4 1/2] drivers/reset: support rockchip reset drivers Kever Yang
2017-12-18 8:49 ` [U-Boot] [PATCH v4 2/2] rockchip: clk: bind reset driver Kever Yang
2017-12-18 9:55 ` [U-Boot] [U-Boot,v4,2/2] " Philipp Tomsich
2017-12-18 9:55 ` [U-Boot] [U-Boot, v4, 1/2] drivers/reset: support rockchip reset drivers Philipp Tomsich
2017-12-19 9:29 ` [U-Boot] [PATCH v4 " Dr. Philipp Tomsich
2017-12-19 10:25 ` Kever Yang
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