* [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x
@ 2022-06-30 10:20 Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 01/13] dt-bindings: net: make internal-delay-ps based on phy-mode Arun Ramadoss
` (12 more replies)
0 siblings, 13 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
LAN937x is a Multi-Port 100BASE-T1 Ethernet Physical Layer switch
compliant with the IEEE 802.3bw-2015 specification. The device provides
100 Mbit/s transmit and receive capability over a single Unshielded
Twisted Pair (UTP) cable. LAN937x is successive revision of KSZ series
switch.
This series of patches provide the DSA driver support for
Microchip LAN937X switch through MII/RMII interface. The RGMII interface
support will be added in the follow up series. LAN937x uses the most of
functionality of KSZ9477.
The LAN937x switch series family consists of following SKUs:
LAN9370:
- 4 T1 Phys
- 1 RGMII port
LAN9371:
- 3 T1 Phys & 1 TX Phy
- 2 RGMII ports
LAN9372:
- 5 T1 Phys & 1 TX Phy
- 2 RGMII ports
LAN9373:
- 5 T1 Phys
- 2 RGMII & 1 SGMII port
LAN9374:
- 6 T1 Phys
- 2 RGMII ports
Changes in v14:
- Updated the patch series to latest ksz code refactoring.
- RGMII register configuration is removed from the series. It will be added in
the follow up patch series.
Changes in v13:
- Fixed the compilation issue in patch 5 and 6
Changes in v12:
- Removed the reduntant spi indirect enable in lan937x_init
- Used the ksz_port_stp_state_set function
- Apply rgmii internal delay only if it is rgmii port
- Set the bit for 100baseTx in phylink_get_caps
- Moved the ethtool related API from patch 5 to 7
- Moved lan_alu_entry struct in lan937x_dev.h from patch 5 to 9
- Moved lan_vlan_entry in lan937x_dev.h from patch 5 to 10
- Used the ksz_get_stats64 function for get_stats64 hook
- Splitted the patch 5. one for port configuration, spi driver, phy read &
write and mtu configuration.
- Updated the indentation in ethernet-controller.yaml
- lan937x.yaml: Removed the blank lines, updated the ethernet handle to macb0.
Added the rgmii internal delay only for the ports.
Changes in v11:
- Tagged as RFC to get the feedback for the subpatches 1/10, 5/10 and 6/10
Changes in v10:
- dsa.yaml: dropped moving mdio properties to dsa.yaml as per the feedback
https://patchwork.kernel.org/project/netdevbpf/patch/20220318085540.281721-3-prasanna.vengateshan@microchip.com/#24787466
- microchip,lan937x.yaml: Naming convention changes in the example
- lan937x_main.c: Moving configurations from lan937x_reset_switch() to setup()
- lan937x_main.c: helper function has been introduced for
lan937x_internal_phy_read & write
- lan937x_dev.h: lan_alu_struct struct data type changes
- lan937x_main.c: lan937x_get_stats64 make non blocking
- lan937x_main.c: modified lan937x_port_mirror_add to include extack
Changes in v9:
- lan937x_main.c: of_node_put() correction in lan937x_parse_dt_rgmii_delay
- lan937x_dev.c: removed the interface checks from lan937x_apply_rgmii_delay.
- changes in ethernet-controller.yaml and dsa.yaml
Changes in v8:
- lan937x_dev.c: fixed lan937x_r_mib_pkt warning in the sub patches
- lan937x_main.c: phylink_autoneg_inband() check removed in
lan937x_phylink_mac_link_up()
- lan937x_main.c: made legacy_pre_march2020 = false as this is non-legacy driver
and indentation correction in lan937x_phylink_mac_link_up()
- removed unnecessary parenthesis in lan937x_get_strings()
Changes in v7:
- microchip,lan937x.yaml: *-internal-delay-ps enum values & commit messages
corrections
- lan937x_main.c: removed phylink_validate() and added phylink_get_caps()
- lan937x_main.c: added support for ethtool standard stats (get_eth_*_stats
and get_stats64)
- lan937x_main.c: removed unnecessary PVID read from lan937x_port_vlan_del()
- integrated the changes of ksz9477 multi bridging support to lan937x dev and
tested both multi bridging and STP
- lan937x_port_vlan_del - dummy pvid read removed
Changes in v6:
- microchip_t1.c: There was new merge done in the net-next tree for
microchip_1.c after the v5 submission. Hence rebased it for v6.
Changes in v5:
- microchip,lan937x.yaml: Added mdio properties detail
- microchip,lan937x.yaml: *-internal-delay-ps added under port node
- lan937x_dev.c: changed devm_mdiobus_alloc from of_mdiobus_register as suggested
by Vladimir
- lan937x_dev.c: added dev_info for rgmii internal delay & error message to user
in case of out of range values
- lan937x_dev.c: return -EOPNOTSUPP for C45 regnum values for
lan937x_sw_mdio_read & write operations
- return from function with out storing in a variable
- lan937x_main.c: Added vlan_enable info in vlan_filtering API
- lan937x_main.c: lan937x_port_vlan_del: removed unintended PVID write
Changes in v4:
- tag_ksz.c: cpu_to_be16 to put_unaligned_be16
- correct spacing in comments
- tag_ksz.c: NETIF_F_HW_CSUM fix is integrated
- lan937x_dev.c: mdio_np is removed from global and handled locally
- lan937x_dev.c: unused functions removed lan937x_cfg32 & lan937x_port_cfg32
- lan937x_dev.c: lan937x_is_internal_100BTX_phy_port function name changes
- lan937x_dev.c: RGMII internal delay handling for MAC. Delay values are
retrieved from DTS and updated
- lan937x_dev.c: corrected mutex operations for few dev variables
- microchip,lan937x.yaml: introduced rx-internal-delay-ps &
tx-internal-delay-ps for RGMII internal delay
- lan937x_dev.c: Unnecessary mutex_lock has been removed
- lan937x_main.c: PHY_INTERFACE_MODE_NA handling for lan937x_phylink_validate
- lan937x_main.c: PORT_MIRROR_SNIFFER check in right place
- lan937x_main.c: memset is used instead of writing 0's individually in
lan937x_port_fdb_add function
- lan937x_main.c: Removed \n from NL_SET_ERR_MSG_MOD calls
Changes in v3:
- Removed settings of cnt_ptr to zero and the memset()
added a cleanup patch which moves this into ksz_init_mib_timer().
- Used ret everywhere instead of rc
- microchip,lan937x.yaml: Remove mdio compatible
- microchip_t1.c: Renaming standard phy registers
- tag_ksz.c: LAN937X_TAIL_TAG_OVERRIDE renaming
LAN937X_TAIL_TAG_BLOCKING_OVERRIDE
- tag_ksz.c: Changed Ingress and Egress naming convention based on
Host
- tag_ksz.c: converted to skb_mac_header(skb) from
(is_link_local_ether_addr(hdr->h_dest))
- lan937x_dev.c: Removed BCAST Storm protection settings since we
have Tc commands for them
- lan937x_dev.c: Flow control setting in lan937x_port_setup function
- lan937x_dev.c: RGMII internal delay added only for cpu port,
- lan937x_dev.c: of_get_compatible_child(node,
"microchip,lan937x-mdio") to of_get_child_by_name(node, "mdio");
- lan937x_dev.c:lan937x_get_interface API: returned
PHY_INTERFACE_MODE_INTERNAL instead of PHY_INTERFACE_MODE_NA
- lan937x_main.c: Removed compat interface implementation in
lan937x_config_cpu_port() API & dev_info corrected as well
- lan937x_main.c: deleted ds->configure_vlan_while_not_filtering
= true
- lan937x_main.c: Added explanation for lan937x_setup lines
- lan937x_main.c: FR_MAX_SIZE correction in lan937x_get_max_mtu API
- lan937x_main.c: removed lan937x_port_bridge_flags dummy functions
- lan937x_spi.c - mdiobus_unregister to be added to spi_remove
function
- lan937x_main.c: phy link layer changes
- lan937x_main.c: port mirroring: sniff port selection limiting to
one port
- lan937x_main.c: Changed to global vlan filtering
- lan937x_main.c: vlan_table array to structure
- lan937x_main.c -Use extack instead of reporting errors to Console
- lan937x_main.c - Remove cpu_port addition in vlan_add api
- lan937x_main.c - removed pvid resetting
Changes in v2:
- return check for register read/writes
- dt compatible compatible check is added against chip id value
- lan937x_internal_t1_tx_phy_write() is renamed to
lan937x_internal_phy_write()
- lan937x_is_internal_tx_phy_port is renamed to
lan937x_is_internal_100BTX_phy_port as it is 100Base-Tx phy
- Return value for lan937x_internal_phy_write() is -EOPNOTSUPP
in case of failures
- Return value for lan937x_internal_phy_read() is 0xffff
for non existent phy
- cpu_port checking is removed from lan937x_port_stp_state_set()
- lan937x_phy_link_validate: 100baseT_Full to 100baseT1_Full
- T1 Phy driver is moved to drivers/net/phy/microchip_t1.c
- Tx phy driver support will be added later
- Legacy switch checkings in dts file are removed.
- tag_ksz.c: Re-used ksz9477_rcv for lan937x_rcv
- tag_ksz.c: Xmit() & rcv() Comments are corrected w.r.to host
- net/dsa/Kconfig: Family skew numbers altered in ascending order
- microchip,lan937x.yaml: eth is replaced with ethernet
- microchip,lan937x.yaml: spi1 is replaced with spi
- microchip,lan937x.yaml: cpu labelling is removed
- microchip,lan937x.yaml: port@x value will match the reg value now
Arun Ramadoss (10):
net: dsa: microchip: generic access to ksz9477 static and reserved
table
net: dsa: microchip: add DSA support for microchip LAN937x
net: dsa: microchip: lan937x: add dsa_tag_protocol
net: dsa: microchip: lan937x: add phy read and write support
net: dsa: microchip: lan937x: register mdio-bus
net: dsa: microchip: lan937x: add MTU and fast_age support
net: dsa: microchip: lan937x: add phylink_get_caps support
net: dsa: microchip: lan937x: add phylink_mac_link_up support
net: dsa: microchip: lan937x: add phylink_mac_config support
net: dsa: microchip: add LAN937x in the ksz spi probe
Prasanna Vengateshan (3):
dt-bindings: net: make internal-delay-ps based on phy-mode
dt-bindings: net: dsa: dt bindings for microchip lan937x
net: dsa: tag_ksz: add tag handling for Microchip LAN937x
.../bindings/net/dsa/microchip,lan937x.yaml | 192 +++++++
.../bindings/net/ethernet-controller.yaml | 35 +-
MAINTAINERS | 1 +
drivers/net/dsa/microchip/Kconfig | 2 +-
drivers/net/dsa/microchip/Makefile | 1 +
drivers/net/dsa/microchip/ksz9477.c | 27 +-
drivers/net/dsa/microchip/ksz9477_reg.h | 3 -
drivers/net/dsa/microchip/ksz_common.c | 105 ++++
drivers/net/dsa/microchip/ksz_common.h | 20 +
drivers/net/dsa/microchip/ksz_spi.c | 26 +
drivers/net/dsa/microchip/lan937x.h | 27 +
drivers/net/dsa/microchip/lan937x_main.c | 497 ++++++++++++++++++
drivers/net/dsa/microchip/lan937x_reg.h | 180 +++++++
include/net/dsa.h | 2 +
net/dsa/Kconfig | 4 +-
net/dsa/tag_ksz.c | 59 +++
16 files changed, 1156 insertions(+), 25 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
create mode 100644 drivers/net/dsa/microchip/lan937x.h
create mode 100644 drivers/net/dsa/microchip/lan937x_main.c
create mode 100644 drivers/net/dsa/microchip/lan937x_reg.h
base-commit: dbc6fc7e3f76ac8a584cd39f9978d6b41a96e75a
--
2.36.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Patch net-next v14 01/13] dt-bindings: net: make internal-delay-ps based on phy-mode
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 02/13] dt-bindings: net: dsa: dt bindings for microchip lan937x Arun Ramadoss
` (11 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
From: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
*-internal-delay-ps properties would be applicable only for RGMII interface
modes.
It is changed as per the request.
Ran dt_binding_check to confirm nothing is broken.
link: https://lore.kernel.org/netdev/d8e5f6a8-a7e1-dabd-f4b4-ea8ea21d0a1d@gmail.com/
Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../bindings/net/ethernet-controller.yaml | 35 ++++++++++++-------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 4f15463611f8..56d9aca8c954 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -133,12 +133,6 @@ properties:
and is useful for determining certain configuration settings
such as flow control thresholds.
- rx-internal-delay-ps:
- description: |
- RGMII Receive Clock Delay defined in pico seconds.
- This is used for controllers that have configurable RX internal delays.
- If this property is present then the MAC applies the RX delay.
-
sfp:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -150,12 +144,6 @@ properties:
The size of the controller\'s transmit fifo in bytes. This
is used for components that can have configurable fifo sizes.
- tx-internal-delay-ps:
- description: |
- RGMII Transmit Clock Delay defined in pico seconds.
- This is used for controllers that have configurable TX internal delays.
- If this property is present then the MAC applies the TX delay.
-
managed:
description:
Specifies the PHY management type. If auto is set and fixed-link
@@ -232,6 +220,29 @@ properties:
required:
- speed
+allOf:
+ - if:
+ properties:
+ phy-mode:
+ contains:
+ enum:
+ - rgmii
+ - rgmii-rxid
+ - rgmii-txid
+ - rgmii-id
+ then:
+ properties:
+ rx-internal-delay-ps:
+ description:
+ RGMII Receive Clock Delay defined in pico seconds.This is used for
+ controllers that have configurable RX internal delays. If this
+ property is present then the MAC applies the RX delay.
+ tx-internal-delay-ps:
+ description:
+ RGMII Transmit Clock Delay defined in pico seconds.This is used for
+ controllers that have configurable TX internal delays. If this
+ property is present then the MAC applies the TX delay.
+
additionalProperties: true
...
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 02/13] dt-bindings: net: dsa: dt bindings for microchip lan937x
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 01/13] dt-bindings: net: make internal-delay-ps based on phy-mode Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 03/13] net: dsa: tag_ksz: add tag handling for Microchip LAN937x Arun Ramadoss
` (10 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
From: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Documentation in .yaml format and updates to the MAINTAINERS
Also 'make dt_binding_check' is passed.
RGMII internal delay values for the mac is retrieved from
rx-internal-delay-ps & tx-internal-delay-ps as per the feedback from
v3 patch series.
https://lore.kernel.org/netdev/20210802121550.gqgbipqdvp5x76ii@skbuf/
It supports only the delay value of 0ns and 2ns.
Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../bindings/net/dsa/microchip,lan937x.yaml | 192 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 193 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
new file mode 100644
index 000000000000..630bf0f8294b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LAN937x Ethernet Switch Series Tree Bindings
+
+maintainers:
+ - UNGLinuxDriver@microchip.com
+
+allOf:
+ - $ref: dsa.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,lan9370
+ - microchip,lan9371
+ - microchip,lan9372
+ - microchip,lan9373
+ - microchip,lan9374
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 50000000
+
+ reset-gpios:
+ description: Optional gpio specifier for a reset line
+ maxItems: 1
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+
+patternProperties:
+ "^(ethernet-)?ports$":
+ patternProperties:
+ "^(ethernet-)?port@[0-9]+$":
+ allOf:
+ - if:
+ properties:
+ phy-mode:
+ contains:
+ enum:
+ - rgmii
+ - rgmii-id
+ - rgmii-txid
+ - rgmii-rxid
+ then:
+ properties:
+ rx-internal-delay-ps:
+ enum: [0, 2000]
+ default: 0
+ tx-internal-delay-ps:
+ enum: [0, 2000]
+ default: 0
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ macb0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan9374: switch@0 {
+ compatible = "microchip,lan9374";
+ reg = <0>;
+ spi-max-frequency = <44000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&t1phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&t1phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&t1phy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan6";
+ phy-mode = "internal";
+ phy-handle = <&t1phy3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ phy-mode = "rgmii";
+ tx-internal-delay-ps = <2000>;
+ rx-internal-delay-ps = <2000>;
+ ethernet = <&macb0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan7";
+ phy-mode = "rgmii";
+ tx-internal-delay-ps = <2000>;
+ rx-internal-delay-ps = <2000>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "lan5";
+ phy-mode = "internal";
+ phy-handle = <&t1phy6>;
+ };
+
+ port@7 {
+ reg = <7>;
+ label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&t1phy7>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ t1phy0: ethernet-phy@0{
+ reg = <0x0>;
+ };
+
+ t1phy1: ethernet-phy@1{
+ reg = <0x1>;
+ };
+
+ t1phy2: ethernet-phy@2{
+ reg = <0x2>;
+ };
+
+ t1phy3: ethernet-phy@3{
+ reg = <0x3>;
+ };
+
+ t1phy6: ethernet-phy@6{
+ reg = <0x6>;
+ };
+
+ t1phy7: ethernet-phy@7{
+ reg = <0x7>;
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 7c029ab73265..683ecc0973b8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13057,6 +13057,7 @@ M: UNGLinuxDriver@microchip.com
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
+F: Documentation/devicetree/bindings/net/dsa/microchip,lan937x.yaml
F: drivers/net/dsa/microchip/*
F: include/linux/platform_data/microchip-ksz.h
F: net/dsa/tag_ksz.c
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 03/13] net: dsa: tag_ksz: add tag handling for Microchip LAN937x
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 01/13] dt-bindings: net: make internal-delay-ps based on phy-mode Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 02/13] dt-bindings: net: dsa: dt bindings for microchip lan937x Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 04/13] net: dsa: microchip: generic access to ksz9477 static and reserved table Arun Ramadoss
` (9 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
From: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
The Microchip LAN937X switches have a tagging protocol which is
very similar to KSZ tagging. So that the implementation is added to
tag_ksz.c and reused common APIs
Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com>
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
include/net/dsa.h | 2 ++
net/dsa/Kconfig | 4 ++--
net/dsa/tag_ksz.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index ea7bf007f34f..b902b31bebce 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -54,6 +54,7 @@ struct phylink_link_state;
#define DSA_TAG_PROTO_RTL8_4_VALUE 24
#define DSA_TAG_PROTO_RTL8_4T_VALUE 25
#define DSA_TAG_PROTO_RZN1_A5PSW_VALUE 26
+#define DSA_TAG_PROTO_LAN937X_VALUE 27
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -83,6 +84,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_RTL8_4 = DSA_TAG_PROTO_RTL8_4_VALUE,
DSA_TAG_PROTO_RTL8_4T = DSA_TAG_PROTO_RTL8_4T_VALUE,
DSA_TAG_PROTO_RZN1_A5PSW = DSA_TAG_PROTO_RZN1_A5PSW_VALUE,
+ DSA_TAG_PROTO_LAN937X = DSA_TAG_PROTO_LAN937X_VALUE,
};
struct dsa_switch;
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 63853fff4e2f..3eef72ce99a4 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -87,10 +87,10 @@ config NET_DSA_TAG_MTK
Mediatek switches.
config NET_DSA_TAG_KSZ
- tristate "Tag driver for Microchip 8795/9477/9893 families of switches"
+ tristate "Tag driver for Microchip 8795/937x/9477/9893 families of switches"
help
Say Y if you want to enable support for tagging frames for the
- Microchip 8795/9477/9893 families of switches.
+ Microchip 8795/937x/9477/9893 families of switches.
config NET_DSA_TAG_OCELOT
tristate "Tag driver for Ocelot family of switches, using NPI port"
diff --git a/net/dsa/tag_ksz.c b/net/dsa/tag_ksz.c
index 3509fc967ca9..38fa19c1e2d5 100644
--- a/net/dsa/tag_ksz.c
+++ b/net/dsa/tag_ksz.c
@@ -193,10 +193,69 @@ static const struct dsa_device_ops ksz9893_netdev_ops = {
DSA_TAG_DRIVER(ksz9893_netdev_ops);
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_KSZ9893);
+/* For xmit, 2 bytes are added before FCS.
+ * ---------------------------------------------------------------------------
+ * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|tag1(1byte)|FCS(4bytes)
+ * ---------------------------------------------------------------------------
+ * tag0 : represents tag override, lookup and valid
+ * tag1 : each bit represents port (eg, 0x01=port1, 0x02=port2, 0x80=port8)
+ *
+ * For rcv, 1 byte is added before FCS.
+ * ---------------------------------------------------------------------------
+ * DA(6bytes)|SA(6bytes)|....|Data(nbytes)|tag0(1byte)|FCS(4bytes)
+ * ---------------------------------------------------------------------------
+ * tag0 : zero-based value represents port
+ * (eg, 0x00=port1, 0x02=port3, 0x07=port8)
+ */
+#define LAN937X_EGRESS_TAG_LEN 2
+
+#define LAN937X_TAIL_TAG_BLOCKING_OVERRIDE BIT(11)
+#define LAN937X_TAIL_TAG_LOOKUP BIT(12)
+#define LAN937X_TAIL_TAG_VALID BIT(13)
+#define LAN937X_TAIL_TAG_PORT_MASK 7
+
+static struct sk_buff *lan937x_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dsa_port *dp = dsa_slave_to_port(dev);
+ const struct ethhdr *hdr = eth_hdr(skb);
+ __be16 *tag;
+ u16 val;
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL && skb_checksum_help(skb))
+ return NULL;
+
+ tag = skb_put(skb, LAN937X_EGRESS_TAG_LEN);
+
+ val = BIT(dp->index);
+
+ if (is_link_local_ether_addr(hdr->h_dest))
+ val |= LAN937X_TAIL_TAG_BLOCKING_OVERRIDE;
+
+ /* Tail tag valid bit - This bit should always be set by the CPU */
+ val |= LAN937X_TAIL_TAG_VALID;
+
+ put_unaligned_be16(val, tag);
+
+ return skb;
+}
+
+static const struct dsa_device_ops lan937x_netdev_ops = {
+ .name = "lan937x",
+ .proto = DSA_TAG_PROTO_LAN937X,
+ .xmit = lan937x_xmit,
+ .rcv = ksz9477_rcv,
+ .needed_tailroom = LAN937X_EGRESS_TAG_LEN,
+};
+
+DSA_TAG_DRIVER(lan937x_netdev_ops);
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_LAN937X);
+
static struct dsa_tag_driver *dsa_tag_driver_array[] = {
&DSA_TAG_DRIVER_NAME(ksz8795_netdev_ops),
&DSA_TAG_DRIVER_NAME(ksz9477_netdev_ops),
&DSA_TAG_DRIVER_NAME(ksz9893_netdev_ops),
+ &DSA_TAG_DRIVER_NAME(lan937x_netdev_ops),
};
module_dsa_tag_drivers(dsa_tag_driver_array);
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 04/13] net: dsa: microchip: generic access to ksz9477 static and reserved table
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (2 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 03/13] net: dsa: tag_ksz: add tag handling for Microchip LAN937x Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 05/13] net: dsa: microchip: add DSA support for microchip LAN937x Arun Ramadoss
` (8 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
The ksz9477 and lan937x has few difference in the static and reserved
table register 0x041C. For the ksz9477 if the bit 0 is 1 - read
operation and 0 - write operation. But for lan937x bit 1:0 used for
selecting the read/write operation, 01 - write and 10 - read.
To use ksz9477 mdb add/del and enable_stp_addr for the lan937x, masks &
shifts are introduced for ksz9477 & lan937x in ksz_common.c. Then
updated the function with masks & shifts based on the switch instead of
hard coding it.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz9477.c | 27 ++++++++++++++-----
drivers/net/dsa/microchip/ksz9477_reg.h | 3 ---
drivers/net/dsa/microchip/ksz_common.c | 35 +++++++++++++++++++++++++
drivers/net/dsa/microchip/ksz_common.h | 3 +++
4 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index 0e808d27124c..6453642fa14c 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -644,11 +644,16 @@ int ksz9477_mdb_add(struct ksz_device *dev, int port,
const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
{
u32 static_table[4];
+ const u8 *shifts;
+ const u32 *masks;
u32 data;
int index;
u32 mac_hi, mac_lo;
int err = 0;
+ shifts = dev->info->shifts;
+ masks = dev->info->masks;
+
mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
@@ -657,8 +662,8 @@ int ksz9477_mdb_add(struct ksz_device *dev, int port,
for (index = 0; index < dev->info->num_statics; index++) {
/* find empty slot first */
- data = (index << ALU_STAT_INDEX_S) |
- ALU_STAT_READ | ALU_STAT_START;
+ data = (index << shifts[ALU_STAT_INDEX]) |
+ masks[ALU_STAT_READ] | ALU_STAT_START;
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
/* wait to be finished */
@@ -702,7 +707,7 @@ int ksz9477_mdb_add(struct ksz_device *dev, int port,
ksz9477_write_table(dev, static_table);
- data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
+ data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START;
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
/* wait to be finished */
@@ -718,11 +723,16 @@ int ksz9477_mdb_del(struct ksz_device *dev, int port,
const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
{
u32 static_table[4];
+ const u8 *shifts;
+ const u32 *masks;
u32 data;
int index;
int ret = 0;
u32 mac_hi, mac_lo;
+ shifts = dev->info->shifts;
+ masks = dev->info->masks;
+
mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
@@ -731,8 +741,8 @@ int ksz9477_mdb_del(struct ksz_device *dev, int port,
for (index = 0; index < dev->info->num_statics; index++) {
/* find empty slot first */
- data = (index << ALU_STAT_INDEX_S) |
- ALU_STAT_READ | ALU_STAT_START;
+ data = (index << shifts[ALU_STAT_INDEX]) |
+ masks[ALU_STAT_READ] | ALU_STAT_START;
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
/* wait to be finished */
@@ -774,7 +784,7 @@ int ksz9477_mdb_del(struct ksz_device *dev, int port,
ksz9477_write_table(dev, static_table);
- data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
+ data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START;
ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
/* wait to be finished */
@@ -1230,9 +1240,12 @@ void ksz9477_config_cpu_port(struct dsa_switch *ds)
int ksz9477_enable_stp_addr(struct ksz_device *dev)
{
+ const u32 *masks;
u32 data;
int ret;
+ masks = dev->info->masks;
+
/* Enable Reserved multicast table */
ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true);
@@ -1242,7 +1255,7 @@ int ksz9477_enable_stp_addr(struct ksz_device *dev)
if (ret < 0)
return ret;
- data = ALU_STAT_START | ALU_RESV_MCAST_ADDR;
+ data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE];
ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
if (ret < 0)
diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
index 2ba0f4449130..d0cce4ca3cf9 100644
--- a/drivers/net/dsa/microchip/ksz9477_reg.h
+++ b/drivers/net/dsa/microchip/ksz9477_reg.h
@@ -419,12 +419,9 @@
#define REG_SW_ALU_STAT_CTRL__4 0x041C
-#define ALU_STAT_INDEX_M (BIT(4) - 1)
-#define ALU_STAT_INDEX_S 16
#define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
#define ALU_STAT_START BIT(7)
#define ALU_RESV_MCAST_ADDR BIT(1)
-#define ALU_STAT_READ BIT(0)
#define REG_SW_ALU_VAL_A 0x0420
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 29b42b3b39c9..d631a4bf35ed 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -314,7 +314,24 @@ static const u16 ksz9477_regs[] = {
[S_START_CTRL] = 0x0300,
[S_BROADCAST_CTRL] = 0x0332,
[S_MULTICAST_CTRL] = 0x0331,
+};
+
+static const u32 ksz9477_masks[] = {
+ [ALU_STAT_WRITE] = 0,
+ [ALU_STAT_READ] = 1,
+};
+
+static const u8 ksz9477_shifts[] = {
+ [ALU_STAT_INDEX] = 16,
+};
+
+static const u32 lan937x_masks[] = {
+ [ALU_STAT_WRITE] = 1,
+ [ALU_STAT_READ] = 2,
+};
+static const u8 lan937x_shifts[] = {
+ [ALU_STAT_INDEX] = 8,
};
const struct ksz_chip_data ksz_switch_chips[] = {
@@ -432,6 +449,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = ksz9477_masks,
+ .shifts = ksz9477_shifts,
.supports_mii = {false, false, false, false,
false, true, false},
.supports_rmii = {false, false, false, false,
@@ -456,6 +475,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = ksz9477_masks,
+ .shifts = ksz9477_shifts,
.supports_mii = {false, false, false, false,
false, true, true},
.supports_rmii = {false, false, false, false,
@@ -479,6 +500,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = ksz9477_masks,
+ .shifts = ksz9477_shifts,
.supports_mii = {false, false, true},
.supports_rmii = {false, false, true},
.supports_rgmii = {false, false, true},
@@ -499,6 +522,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = ksz9477_masks,
+ .shifts = ksz9477_shifts,
.supports_mii = {false, false, false, false,
false, true, true},
.supports_rmii = {false, false, false, false,
@@ -521,6 +546,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = lan937x_masks,
+ .shifts = lan937x_shifts,
.supports_mii = {false, false, false, false, true},
.supports_rmii = {false, false, false, false, true},
.supports_rgmii = {false, false, false, false, true},
@@ -539,6 +566,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = lan937x_masks,
+ .shifts = lan937x_shifts,
.supports_mii = {false, false, false, false, true, true},
.supports_rmii = {false, false, false, false, true, true},
.supports_rgmii = {false, false, false, false, true, true},
@@ -557,6 +586,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = lan937x_masks,
+ .shifts = lan937x_shifts,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
@@ -579,6 +610,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = lan937x_masks,
+ .shifts = lan937x_shifts,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
@@ -601,6 +634,8 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
.regs = ksz9477_regs,
+ .masks = lan937x_masks,
+ .shifts = lan937x_shifts,
.supports_mii = {false, false, false, false,
true, true, false, false},
.supports_rmii = {false, false, false, false,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index b61e569a9949..5f69dc872752 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -191,6 +191,8 @@ enum ksz_masks {
DYNAMIC_MAC_TABLE_FID,
DYNAMIC_MAC_TABLE_SRC_PORT,
DYNAMIC_MAC_TABLE_TIMESTAMP,
+ ALU_STAT_WRITE,
+ ALU_STAT_READ,
};
enum ksz_shifts {
@@ -203,6 +205,7 @@ enum ksz_shifts {
DYNAMIC_MAC_FID,
DYNAMIC_MAC_TIMESTAMP,
DYNAMIC_MAC_SRC_PORT,
+ ALU_STAT_INDEX,
};
struct alu_struct {
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 05/13] net: dsa: microchip: add DSA support for microchip LAN937x
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (3 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 04/13] net: dsa: microchip: generic access to ksz9477 static and reserved table Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 06/13] net: dsa: microchip: lan937x: add dsa_tag_protocol Arun Ramadoss
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
Basic DSA driver support for lan937x and the device will be
configured through SPI interface.
It adds the lan937x_dev_ops in ksz_common.c file and tries to reuse the
functionality of ksz9477 series switch.
drivers/net/dsa/microchip/ path is already part of MAINTAINERS &
the new files come under this path. Hence no update needed to the
MAINTAINERS
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/Kconfig | 2 +-
drivers/net/dsa/microchip/Makefile | 1 +
drivers/net/dsa/microchip/ksz_common.c | 34 +++++
drivers/net/dsa/microchip/lan937x.h | 15 +++
drivers/net/dsa/microchip/lan937x_main.c | 154 +++++++++++++++++++++++
drivers/net/dsa/microchip/lan937x_reg.h | 128 +++++++++++++++++++
6 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/dsa/microchip/lan937x.h
create mode 100644 drivers/net/dsa/microchip/lan937x_main.c
create mode 100644 drivers/net/dsa/microchip/lan937x_reg.h
diff --git a/drivers/net/dsa/microchip/Kconfig b/drivers/net/dsa/microchip/Kconfig
index 2edb88080790..06b1efdb5e7d 100644
--- a/drivers/net/dsa/microchip/Kconfig
+++ b/drivers/net/dsa/microchip/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig NET_DSA_MICROCHIP_KSZ_COMMON
- tristate "Microchip KSZ8795/KSZ9477 series switch support"
+ tristate "Microchip KSZ8795/KSZ9477/LAN937x series switch support"
depends on NET_DSA
select NET_DSA_TAG_KSZ
help
diff --git a/drivers/net/dsa/microchip/Makefile b/drivers/net/dsa/microchip/Makefile
index b2ba7c1bcb93..28873559efc2 100644
--- a/drivers/net/dsa/microchip/Makefile
+++ b/drivers/net/dsa/microchip/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON) += ksz_switch.o
ksz_switch-objs := ksz_common.o
ksz_switch-objs += ksz9477.o
ksz_switch-objs += ksz8795.o
+ksz_switch-objs += lan937x_main.o
obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C) += ksz9477_i2c.o
obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_SPI) += ksz_spi.o
obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI) += ksz8863_smi.o
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index d631a4bf35ed..83e44598d00c 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -23,6 +23,7 @@
#include "ksz_common.h"
#include "ksz8.h"
#include "ksz9477.h"
+#include "lan937x.h"
#define MIB_COUNTER_NUM 0x20
@@ -201,6 +202,34 @@ static const struct ksz_dev_ops ksz9477_dev_ops = {
.exit = ksz9477_switch_exit,
};
+static const struct ksz_dev_ops lan937x_dev_ops = {
+ .setup = lan937x_setup,
+ .get_port_addr = ksz9477_get_port_addr,
+ .cfg_port_member = ksz9477_cfg_port_member,
+ .port_setup = lan937x_port_setup,
+ .r_mib_cnt = ksz9477_r_mib_cnt,
+ .r_mib_pkt = ksz9477_r_mib_pkt,
+ .r_mib_stat64 = ksz_r_mib_stats64,
+ .freeze_mib = ksz9477_freeze_mib,
+ .port_init_cnt = ksz9477_port_init_cnt,
+ .vlan_filtering = ksz9477_port_vlan_filtering,
+ .vlan_add = ksz9477_port_vlan_add,
+ .vlan_del = ksz9477_port_vlan_del,
+ .mirror_add = ksz9477_port_mirror_add,
+ .mirror_del = ksz9477_port_mirror_del,
+ .fdb_dump = ksz9477_fdb_dump,
+ .fdb_add = ksz9477_fdb_add,
+ .fdb_del = ksz9477_fdb_del,
+ .mdb_add = ksz9477_mdb_add,
+ .mdb_del = ksz9477_mdb_del,
+ .max_mtu = ksz9477_max_mtu,
+ .config_cpu_port = lan937x_config_cpu_port,
+ .enable_stp_addr = ksz9477_enable_stp_addr,
+ .reset = lan937x_reset_switch,
+ .init = lan937x_switch_init,
+ .exit = lan937x_switch_exit,
+};
+
static const u16 ksz8795_regs[] = {
[REG_IND_CTRL_0] = 0x6E,
[REG_IND_DATA_8] = 0x70,
@@ -542,6 +571,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.num_statics = 256,
.cpu_ports = 0x10, /* can be configured as cpu port */
.port_cnt = 5, /* total physical port count */
+ .ops = &lan937x_dev_ops,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
@@ -562,6 +592,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.num_statics = 256,
.cpu_ports = 0x30, /* can be configured as cpu port */
.port_cnt = 6, /* total physical port count */
+ .ops = &lan937x_dev_ops,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
@@ -582,6 +613,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.num_statics = 256,
.cpu_ports = 0x30, /* can be configured as cpu port */
.port_cnt = 8, /* total physical port count */
+ .ops = &lan937x_dev_ops,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
@@ -606,6 +638,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.num_statics = 256,
.cpu_ports = 0x38, /* can be configured as cpu port */
.port_cnt = 5, /* total physical port count */
+ .ops = &lan937x_dev_ops,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
@@ -630,6 +663,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
.num_statics = 256,
.cpu_ports = 0x30, /* can be configured as cpu port */
.port_cnt = 8, /* total physical port count */
+ .ops = &lan937x_dev_ops,
.mib_names = ksz9477_mib_names,
.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
.reg_mib_cnt = MIB_COUNTER_NUM,
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
new file mode 100644
index 000000000000..534f5a7a1129
--- /dev/null
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Microchip lan937x dev ops headers
+ * Copyright (C) 2019-2022 Microchip Technology Inc.
+ */
+
+#ifndef __LAN937X_CFG_H
+#define __LAN937X_CFG_H
+
+int lan937x_reset_switch(struct ksz_device *dev);
+int lan937x_setup(struct dsa_switch *ds);
+void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port);
+void lan937x_config_cpu_port(struct dsa_switch *ds);
+int lan937x_switch_init(struct ksz_device *dev);
+void lan937x_switch_exit(struct ksz_device *dev);
+#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
new file mode 100644
index 000000000000..e167a0c1ff85
--- /dev/null
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Microchip LAN937X switch driver main logic
+ * Copyright (C) 2019-2022 Microchip Technology Inc.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/iopoll.h>
+#include <linux/phy.h>
+#include <linux/of_net.h>
+#include <linux/if_bridge.h>
+#include <linux/math.h>
+#include <net/dsa.h>
+#include <net/switchdev.h>
+
+#include "lan937x_reg.h"
+#include "ksz_common.h"
+#include "lan937x.h"
+
+static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
+{
+ return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
+}
+
+static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
+ u8 bits, bool set)
+{
+ return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
+ bits, set ? bits : 0);
+}
+
+int lan937x_reset_switch(struct ksz_device *dev)
+{
+ u32 data32;
+ int ret;
+
+ /* reset switch */
+ ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
+ if (ret < 0)
+ return ret;
+
+ /* Enable Auto Aging */
+ ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true);
+ if (ret < 0)
+ return ret;
+
+ /* disable interrupts */
+ ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF);
+ if (ret < 0)
+ return ret;
+
+ return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
+}
+
+void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
+{
+ struct dsa_switch *ds = dev->ds;
+ u8 member;
+
+ /* enable tag tail for host port */
+ if (cpu_port)
+ lan937x_port_cfg(dev, port, REG_PORT_CTRL_0,
+ PORT_TAIL_TAG_ENABLE, true);
+
+ /* disable frame check length field */
+ lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, PORT_CHECK_LENGTH,
+ false);
+
+ /* set back pressure for half duplex */
+ lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE,
+ true);
+
+ /* enable 802.1p priority */
+ lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
+
+ if (!dev->info->internal_phy[port])
+ lan937x_port_cfg(dev, port, REG_PORT_XMII_CTRL_0,
+ PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL,
+ true);
+
+ if (cpu_port)
+ member = dsa_user_ports(ds);
+ else
+ member = BIT(dsa_upstream_port(ds, port));
+
+ dev->dev_ops->cfg_port_member(dev, port, member);
+}
+
+void lan937x_config_cpu_port(struct dsa_switch *ds)
+{
+ struct ksz_device *dev = ds->priv;
+ struct dsa_port *dp;
+
+ dsa_switch_for_each_cpu_port(dp, ds) {
+ if (dev->info->cpu_ports & (1 << dp->index)) {
+ dev->cpu_port = dp->index;
+
+ /* enable cpu port */
+ lan937x_port_setup(dev, dp->index, true);
+ }
+ }
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
+ }
+}
+
+int lan937x_setup(struct dsa_switch *ds)
+{
+ struct ksz_device *dev = ds->priv;
+
+ /* The VLAN aware is a global setting. Mixed vlan
+ * filterings are not supported.
+ */
+ ds->vlan_filtering_is_global = true;
+
+ /* Enable aggressive back off for half duplex & UNH mode */
+ lan937x_cfg(dev, REG_SW_MAC_CTRL_0,
+ (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF),
+ true);
+
+ /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop
+ * packets when 16 or more collisions occur
+ */
+ lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true);
+
+ /* enable global MIB counter freeze function */
+ lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
+
+ /* disable CLK125 & CLK25, 1: disable, 0: enable */
+ lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
+ (SW_CLK125_ENB | SW_CLK25_ENB), true);
+
+ return 0;
+}
+
+int lan937x_switch_init(struct ksz_device *dev)
+{
+ dev->port_mask = (1 << dev->info->port_cnt) - 1;
+
+ return 0;
+}
+
+void lan937x_switch_exit(struct ksz_device *dev)
+{
+ lan937x_reset_switch(dev);
+}
+
+MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>");
+MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
new file mode 100644
index 000000000000..5e27b2bd2d86
--- /dev/null
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Microchip LAN937X switch register definitions
+ * Copyright (C) 2019-2021 Microchip Technology Inc.
+ */
+#ifndef __LAN937X_REG_H
+#define __LAN937X_REG_H
+
+#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
+
+/* 0 - Operation */
+#define REG_SW_INT_STATUS__4 0x0010
+#define REG_SW_INT_MASK__4 0x0014
+
+#define LUE_INT BIT(31)
+#define TRIG_TS_INT BIT(30)
+#define APB_TIMEOUT_INT BIT(29)
+#define OVER_TEMP_INT BIT(28)
+#define HSR_INT BIT(27)
+#define PIO_INT BIT(26)
+#define POR_READY_INT BIT(25)
+
+#define SWITCH_INT_MASK \
+ (LUE_INT | TRIG_TS_INT | APB_TIMEOUT_INT | OVER_TEMP_INT | HSR_INT | \
+ PIO_INT | POR_READY_INT)
+
+#define REG_SW_PORT_INT_STATUS__4 0x0018
+#define REG_SW_PORT_INT_MASK__4 0x001C
+
+/* 1 - Global */
+#define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
+#define SW_CLK125_ENB BIT(1)
+#define SW_CLK25_ENB BIT(0)
+
+/* 3 - Operation Control */
+#define REG_SW_OPERATION 0x0300
+
+#define SW_DOUBLE_TAG BIT(7)
+#define SW_OVER_TEMP_ENABLE BIT(2)
+#define SW_RESET BIT(1)
+
+#define REG_SW_LUE_CTRL_0 0x0310
+
+#define SW_VLAN_ENABLE BIT(7)
+#define SW_DROP_INVALID_VID BIT(6)
+#define SW_AGE_CNT_M 0x7
+#define SW_AGE_CNT_S 3
+#define SW_RESV_MCAST_ENABLE BIT(2)
+
+#define REG_SW_LUE_CTRL_1 0x0311
+
+#define UNICAST_LEARN_DISABLE BIT(7)
+#define SW_FLUSH_STP_TABLE BIT(5)
+#define SW_FLUSH_MSTP_TABLE BIT(4)
+#define SW_SRC_ADDR_FILTER BIT(3)
+#define SW_AGING_ENABLE BIT(2)
+#define SW_FAST_AGING BIT(1)
+#define SW_LINK_AUTO_AGING BIT(0)
+
+#define REG_SW_MAC_CTRL_0 0x0330
+#define SW_NEW_BACKOFF BIT(7)
+#define SW_PAUSE_UNH_MODE BIT(1)
+#define SW_AGGR_BACKOFF BIT(0)
+
+#define REG_SW_MAC_CTRL_1 0x0331
+#define SW_SHORT_IFG BIT(7)
+#define MULTICAST_STORM_DISABLE BIT(6)
+#define SW_BACK_PRESSURE BIT(5)
+#define FAIR_FLOW_CTRL BIT(4)
+#define NO_EXC_COLLISION_DROP BIT(3)
+#define SW_LEGAL_PACKET_DISABLE BIT(1)
+#define SW_PASS_SHORT_FRAME BIT(0)
+
+#define REG_SW_MAC_CTRL_6 0x0336
+#define SW_MIB_COUNTER_FLUSH BIT(7)
+#define SW_MIB_COUNTER_FREEZE BIT(6)
+
+/* 4 - LUE */
+#define REG_SW_ALU_STAT_CTRL__4 0x041C
+
+#define REG_SW_ALU_VAL_B 0x0424
+#define ALU_V_OVERRIDE BIT(31)
+#define ALU_V_USE_FID BIT(30)
+#define ALU_V_PORT_MAP 0xFF
+
+/* Port Registers */
+
+/* 0 - Operation */
+#define REG_PORT_CTRL_0 0x0020
+
+#define PORT_MAC_LOOPBACK BIT(7)
+#define PORT_MAC_REMOTE_LOOPBACK BIT(6)
+#define PORT_K2L_INSERT_ENABLE BIT(5)
+#define PORT_K2L_DEBUG_ENABLE BIT(4)
+#define PORT_TAIL_TAG_ENABLE BIT(2)
+#define PORT_QUEUE_SPLIT_ENABLE 0x3
+
+/* 3 - xMII */
+#define REG_PORT_XMII_CTRL_0 0x0300
+#define PORT_SGMII_SEL BIT(7)
+#define PORT_MII_FULL_DUPLEX BIT(6)
+#define PORT_MII_TX_FLOW_CTRL BIT(5)
+#define PORT_MII_100MBIT BIT(4)
+#define PORT_MII_RX_FLOW_CTRL BIT(3)
+#define PORT_GRXC_ENABLE BIT(0)
+
+/* 4 - MAC */
+#define REG_PORT_MAC_CTRL_0 0x0400
+#define PORT_CHECK_LENGTH BIT(2)
+#define PORT_BROADCAST_STORM BIT(1)
+#define PORT_JUMBO_PACKET BIT(0)
+
+#define REG_PORT_MAC_CTRL_1 0x0401
+#define PORT_BACK_PRESSURE BIT(3)
+#define PORT_PASS_ALL BIT(0)
+
+/* 8 - Classification and Policing */
+#define REG_PORT_MRI_PRIO_CTRL 0x0801
+#define PORT_HIGHEST_PRIO BIT(7)
+#define PORT_OR_PRIO BIT(6)
+#define PORT_MAC_PRIO_ENABLE BIT(4)
+#define PORT_VLAN_PRIO_ENABLE BIT(3)
+#define PORT_802_1P_PRIO_ENABLE BIT(2)
+#define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
+#define PORT_ACL_PRIO_ENABLE BIT(0)
+
+#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL
+
+#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 06/13] net: dsa: microchip: lan937x: add dsa_tag_protocol
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (4 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 05/13] net: dsa: microchip: add DSA support for microchip LAN937x Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 07/13] net: dsa: microchip: lan937x: add phy read and write support Arun Ramadoss
` (6 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch update the ksz_get_tag_protocol to return LAN937x specific
tag if the chip id matches one of LAN937x series switch
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_common.c | 3 +++
drivers/net/dsa/microchip/ksz_common.h | 9 +++++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 83e44598d00c..07b6f34a437e 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -1254,6 +1254,9 @@ static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
dev->chip_id == KSZ9567_CHIP_ID)
proto = DSA_TAG_PROTO_KSZ9477;
+ if (is_lan937x(dev))
+ proto = DSA_TAG_PROTO_LAN937X_VALUE;
+
return proto;
}
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 5f69dc872752..bf4f3f3922a5 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -403,6 +403,15 @@ static inline void ksz_regmap_unlock(void *__mtx)
mutex_unlock(mtx);
}
+static inline int is_lan937x(struct ksz_device *dev)
+{
+ return dev->chip_id == LAN9370_CHIP_ID ||
+ dev->chip_id == LAN9371_CHIP_ID ||
+ dev->chip_id == LAN9372_CHIP_ID ||
+ dev->chip_id == LAN9373_CHIP_ID ||
+ dev->chip_id == LAN9374_CHIP_ID;
+}
+
/* STP State Defines */
#define PORT_TX_ENABLE BIT(2)
#define PORT_RX_ENABLE BIT(1)
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 07/13] net: dsa: microchip: lan937x: add phy read and write support
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (5 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 06/13] net: dsa: microchip: lan937x: add dsa_tag_protocol Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 08/13] net: dsa: microchip: lan937x: register mdio-bus Arun Ramadoss
` (5 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch add support for the writing and reading of the phy registers.
LAN937x uses the Vphy indirect addressing method for accessing the phys.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_common.c | 2 +
drivers/net/dsa/microchip/lan937x.h | 2 +
drivers/net/dsa/microchip/lan937x_main.c | 116 +++++++++++++++++++++++
drivers/net/dsa/microchip/lan937x_reg.h | 36 +++++++
4 files changed, 156 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 07b6f34a437e..67bb4bff4d9b 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -207,6 +207,8 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.get_port_addr = ksz9477_get_port_addr,
.cfg_port_member = ksz9477_cfg_port_member,
.port_setup = lan937x_port_setup,
+ .r_phy = lan937x_r_phy,
+ .w_phy = lan937x_w_phy,
.r_mib_cnt = ksz9477_r_mib_cnt,
.r_mib_pkt = ksz9477_r_mib_pkt,
.r_mib_stat64 = ksz_r_mib_stats64,
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 534f5a7a1129..370203406a05 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -12,4 +12,6 @@ void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port);
void lan937x_config_cpu_port(struct dsa_switch *ds);
int lan937x_switch_init(struct ksz_device *dev);
void lan937x_switch_exit(struct ksz_device *dev);
+void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data);
+void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index e167a0c1ff85..5a2e14fe3cf3 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -28,6 +28,114 @@ static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset,
bits, set ? bits : 0);
}
+static int lan937x_enable_spi_indirect_access(struct ksz_device *dev)
+{
+ u16 data16;
+ int ret;
+
+ /* Enable Phy access through SPI */
+ ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16);
+ if (ret < 0)
+ return ret;
+
+ /* Allow SPI access */
+ data16 |= VPHY_SPI_INDIRECT_ENABLE;
+
+ return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16);
+}
+
+static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
+{
+ u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
+ u16 temp;
+
+ /* get register address based on the logical port */
+ temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));
+
+ return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp);
+}
+
+static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg,
+ u16 val)
+{
+ unsigned int value;
+ int ret;
+
+ /* Check for internal phy port */
+ if (!dev->info->internal_phy[addr])
+ return -EOPNOTSUPP;
+
+ ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
+ if (ret < 0)
+ return ret;
+
+ /* Write the data to be written to the VPHY reg */
+ ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val);
+ if (ret < 0)
+ return ret;
+
+ /* Write the Write En and Busy bit */
+ ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2,
+ (VPHY_IND_WRITE | VPHY_IND_BUSY));
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
+ value, !(value & VPHY_IND_BUSY), 10,
+ 1000);
+ if (ret < 0) {
+ dev_err(dev->dev, "Failed to write phy register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg,
+ u16 *val)
+{
+ unsigned int value;
+ int ret;
+
+ /* Check for internal phy port, return 0xffff for non-existent phy */
+ if (!dev->info->internal_phy[addr])
+ return 0xffff;
+
+ ret = lan937x_vphy_ind_addr_wr(dev, addr, reg);
+ if (ret < 0)
+ return ret;
+
+ /* Write Read and Busy bit to start the transaction */
+ ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY);
+ if (ret < 0)
+ return ret;
+
+ ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2,
+ value, !(value & VPHY_IND_BUSY), 10,
+ 1000);
+ if (ret < 0) {
+ dev_err(dev->dev, "Failed to read phy register\n");
+ return ret;
+ }
+
+ /* Read the VPHY register which has the PHY data */
+ return ksz_read16(dev, REG_VPHY_IND_DATA__2, val);
+}
+
+void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
+{
+ lan937x_internal_phy_read(dev, addr, reg, data);
+}
+
+void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
+{
+ lan937x_internal_phy_write(dev, addr, reg, val);
+}
+
int lan937x_reset_switch(struct ksz_device *dev)
{
u32 data32;
@@ -111,6 +219,14 @@ void lan937x_config_cpu_port(struct dsa_switch *ds)
int lan937x_setup(struct dsa_switch *ds)
{
struct ksz_device *dev = ds->priv;
+ int ret;
+
+ /* enable Indirect Access from SPI to the VPHY registers */
+ ret = lan937x_enable_spi_indirect_access(dev);
+ if (ret < 0) {
+ dev_err(dev->dev, "failed to enable spi indirect access");
+ return ret;
+ }
/* The VLAN aware is a global setting. Mixed vlan
* filterings are not supported.
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 5e27b2bd2d86..7a0fa2595950 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -8,6 +8,12 @@
#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
/* 0 - Operation */
+#define REG_GLOBAL_CTRL_0 0x0007
+
+#define SW_PHY_REG_BLOCK BIT(7)
+#define SW_FAST_MODE BIT(3)
+#define SW_FAST_MODE_OVERRIDE BIT(2)
+
#define REG_SW_INT_STATUS__4 0x0010
#define REG_SW_INT_MASK__4 0x0014
@@ -82,6 +88,33 @@
#define ALU_V_USE_FID BIT(30)
#define ALU_V_PORT_MAP 0xFF
+/* 7 - VPhy */
+#define REG_VPHY_IND_ADDR__2 0x075C
+#define REG_VPHY_IND_DATA__2 0x0760
+
+#define REG_VPHY_IND_CTRL__2 0x0768
+
+#define VPHY_IND_WRITE BIT(1)
+#define VPHY_IND_BUSY BIT(0)
+
+#define REG_VPHY_SPECIAL_CTRL__2 0x077C
+#define VPHY_SMI_INDIRECT_ENABLE BIT(15)
+#define VPHY_SW_LOOPBACK BIT(14)
+#define VPHY_MDIO_INTERNAL_ENABLE BIT(13)
+#define VPHY_SPI_INDIRECT_ENABLE BIT(12)
+#define VPHY_PORT_MODE_M 0x3
+#define VPHY_PORT_MODE_S 8
+#define VPHY_MODE_RGMII 0
+#define VPHY_MODE_MII_PHY 1
+#define VPHY_MODE_SGMII 2
+#define VPHY_MODE_RMII_PHY 3
+#define VPHY_SW_COLLISION_TEST BIT(7)
+#define VPHY_SPEED_DUPLEX_STAT_M 0x7
+#define VPHY_SPEED_DUPLEX_STAT_S 2
+#define VPHY_SPEED_1000 BIT(4)
+#define VPHY_SPEED_100 BIT(3)
+#define VPHY_FULL_DUPLEX BIT(2)
+
/* Port Registers */
/* 0 - Operation */
@@ -94,6 +127,9 @@
#define PORT_TAIL_TAG_ENABLE BIT(2)
#define PORT_QUEUE_SPLIT_ENABLE 0x3
+/* 1 - Phy */
+#define REG_PORT_T1_PHY_CTRL_BASE 0x0100
+
/* 3 - xMII */
#define REG_PORT_XMII_CTRL_0 0x0300
#define PORT_SGMII_SEL BIT(7)
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 08/13] net: dsa: microchip: lan937x: register mdio-bus
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (6 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 07/13] net: dsa: microchip: lan937x: add phy read and write support Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 09/13] net: dsa: microchip: lan937x: add MTU and fast_age support Arun Ramadoss
` (4 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch register mdio-bus for the lan937x series switch. mdio read
and write uses the vphy for accessing the phy register.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/lan937x_main.c | 74 ++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 5a2e14fe3cf3..7090947cf52c 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -7,6 +7,7 @@
#include <linux/iopoll.h>
#include <linux/phy.h>
#include <linux/of_net.h>
+#include <linux/of_mdio.h>
#include <linux/if_bridge.h>
#include <linux/math.h>
#include <net/dsa.h>
@@ -136,6 +137,73 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
lan937x_internal_phy_write(dev, addr, reg, val);
}
+static int lan937x_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
+{
+ struct ksz_device *dev = bus->priv;
+ u16 val;
+ int ret;
+
+ if (regnum & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
+ ret = lan937x_internal_phy_read(dev, addr, regnum, &val);
+ if (ret < 0)
+ return ret;
+
+ return val;
+}
+
+static int lan937x_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
+ u16 val)
+{
+ struct ksz_device *dev = bus->priv;
+
+ if (regnum & MII_ADDR_C45)
+ return -EOPNOTSUPP;
+
+ return lan937x_internal_phy_write(dev, addr, regnum, val);
+}
+
+static int lan937x_mdio_register(struct ksz_device *dev)
+{
+ struct dsa_switch *ds = dev->ds;
+ struct device_node *mdio_np;
+ struct mii_bus *bus;
+ int ret;
+
+ mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
+ if (!mdio_np) {
+ dev_err(ds->dev, "no MDIO bus node\n");
+ return -ENODEV;
+ }
+
+ bus = devm_mdiobus_alloc(ds->dev);
+ if (!bus) {
+ of_node_put(mdio_np);
+ return -ENOMEM;
+ }
+
+ bus->priv = dev;
+ bus->read = lan937x_sw_mdio_read;
+ bus->write = lan937x_sw_mdio_write;
+ bus->name = "lan937x slave smi";
+ snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
+ bus->parent = ds->dev;
+ bus->phy_mask = ~ds->phys_mii_mask;
+
+ ds->slave_mii_bus = bus;
+
+ ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
+ if (ret) {
+ dev_err(ds->dev, "unable to register MDIO bus %s\n",
+ bus->id);
+ }
+
+ of_node_put(mdio_np);
+
+ return ret;
+}
+
int lan937x_reset_switch(struct ksz_device *dev)
{
u32 data32;
@@ -228,6 +296,12 @@ int lan937x_setup(struct dsa_switch *ds)
return ret;
}
+ ret = lan937x_mdio_register(dev);
+ if (ret < 0) {
+ dev_err(dev->dev, "failed to register the mdio");
+ return ret;
+ }
+
/* The VLAN aware is a global setting. Mixed vlan
* filterings are not supported.
*/
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 09/13] net: dsa: microchip: lan937x: add MTU and fast_age support
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (7 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 08/13] net: dsa: microchip: lan937x: register mdio-bus Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support Arun Ramadoss
` (3 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch add the support for port_max_mtu, port_change_mtu and
port_fast_age dsa functionality.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_common.c | 2 ++
drivers/net/dsa/microchip/lan937x.h | 1 +
drivers/net/dsa/microchip/lan937x_main.c | 28 ++++++++++++++++++++++++
drivers/net/dsa/microchip/lan937x_reg.h | 5 +++++
4 files changed, 36 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 67bb4bff4d9b..fb0de48a3f5e 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -206,6 +206,7 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.setup = lan937x_setup,
.get_port_addr = ksz9477_get_port_addr,
.cfg_port_member = ksz9477_cfg_port_member,
+ .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
.port_setup = lan937x_port_setup,
.r_phy = lan937x_r_phy,
.w_phy = lan937x_w_phy,
@@ -224,6 +225,7 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.fdb_del = ksz9477_fdb_del,
.mdb_add = ksz9477_mdb_add,
.mdb_del = ksz9477_mdb_del,
+ .change_mtu = lan937x_change_mtu,
.max_mtu = ksz9477_max_mtu,
.config_cpu_port = lan937x_config_cpu_port,
.enable_stp_addr = ksz9477_enable_stp_addr,
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 370203406a05..50563874600d 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -14,4 +14,5 @@ int lan937x_switch_init(struct ksz_device *dev);
void lan937x_switch_exit(struct ksz_device *dev);
void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data);
void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
+int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu);
#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 7090947cf52c..5917cc11ba59 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -9,6 +9,7 @@
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/if_bridge.h>
+#include <linux/if_vlan.h>
#include <linux/math.h>
#include <net/dsa.h>
#include <net/switchdev.h>
@@ -284,6 +285,33 @@ void lan937x_config_cpu_port(struct dsa_switch *ds)
}
}
+int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
+{
+ struct dsa_switch *ds = dev->ds;
+ int ret;
+
+ new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
+
+ if (dsa_is_cpu_port(ds, port))
+ new_mtu += LAN937X_TAG_LEN;
+
+ if (new_mtu >= FR_MIN_SIZE)
+ ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
+ PORT_JUMBO_PACKET, true);
+ else
+ ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0,
+ PORT_JUMBO_PACKET, false);
+ if (ret < 0) {
+ dev_err(ds->dev, "failed to enable jumbo\n");
+ return ret;
+ }
+
+ /* Write the frame size in PORT_MAX_FR_SIZE register */
+ ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu);
+
+ return 0;
+}
+
int lan937x_setup(struct dsa_switch *ds)
{
struct ksz_device *dev = ds->priv;
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 7a0fa2595950..19f3aa344228 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -149,6 +149,9 @@
#define PORT_BACK_PRESSURE BIT(3)
#define PORT_PASS_ALL BIT(0)
+#define PORT_MAX_FR_SIZE 0x404
+#define FR_MIN_SIZE 1522
+
/* 8 - Classification and Policing */
#define REG_PORT_MRI_PRIO_CTRL 0x0801
#define PORT_HIGHEST_PRIO BIT(7)
@@ -161,4 +164,6 @@
#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL
+#define LAN937X_TAG_LEN 2
+
#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (8 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 09/13] net: dsa: microchip: lan937x: add MTU and fast_age support Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 11:36 ` Russell King (Oracle)
2022-06-30 10:20 ` [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support Arun Ramadoss
` (2 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
The internal phy of the LAN937x are capable of 100Mbps speed. And the
xMII port of switch is capable of 10/100/1000Mbps.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_common.c | 1 +
drivers/net/dsa/microchip/lan937x.h | 2 ++
drivers/net/dsa/microchip/lan937x_main.c | 12 ++++++++++++
3 files changed, 15 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index fb0de48a3f5e..ca7ca327285d 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -220,6 +220,7 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.vlan_del = ksz9477_port_vlan_del,
.mirror_add = ksz9477_port_mirror_add,
.mirror_del = ksz9477_port_mirror_del,
+ .get_caps = lan937x_phylink_get_caps,
.fdb_dump = ksz9477_fdb_dump,
.fdb_add = ksz9477_fdb_add,
.fdb_del = ksz9477_fdb_del,
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 50563874600d..d4207e97a130 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -15,4 +15,6 @@ void lan937x_switch_exit(struct ksz_device *dev);
void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data);
void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu);
+void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
+ struct phylink_config *config);
#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 5917cc11ba59..8cb46caf5340 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -312,6 +312,18 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
return 0;
}
+void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
+ struct phylink_config *config)
+{
+ config->mac_capabilities = MAC_100FD;
+
+ if (dev->info->supports_rgmii[port]) {
+ /* MII/RMII/RGMII ports */
+ config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_100HD | MAC_10 | MAC_1000FD;
+ }
+}
+
int lan937x_setup(struct dsa_switch *ds)
{
struct ksz_device *dev = ds->priv;
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (9 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 11:42 ` Russell King (Oracle)
2022-06-30 10:20 ` [Patch net-next v14 12/13] net: dsa: microchip: lan937x: add phylink_mac_config support Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 13/13] net: dsa: microchip: add LAN937x in the ksz spi probe Arun Ramadoss
12 siblings, 1 reply; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch add support for phylink_mac_link_up. It configures the mac
for the speed, flow control and duplex mode.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_common.c | 16 ++++++
drivers/net/dsa/microchip/ksz_common.h | 5 ++
drivers/net/dsa/microchip/lan937x.h | 4 ++
drivers/net/dsa/microchip/lan937x_main.c | 67 ++++++++++++++++++++++++
drivers/net/dsa/microchip/lan937x_reg.h | 11 ++++
5 files changed, 103 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index ca7ca327285d..9972b2fabf27 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -221,6 +221,7 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.mirror_add = ksz9477_port_mirror_add,
.mirror_del = ksz9477_port_mirror_del,
.get_caps = lan937x_phylink_get_caps,
+ .phylink_mac_link_up = lan937x_phylink_mac_link_up,
.fdb_dump = ksz9477_fdb_dump,
.fdb_add = ksz9477_fdb_add,
.fdb_del = ksz9477_fdb_del,
@@ -1340,6 +1341,20 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
return dev->dev_ops->max_mtu(dev, port);
}
+static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface,
+ struct phy_device *phydev, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ struct ksz_device *dev = ds->priv;
+
+ if (dev->dev_ops->phylink_mac_link_up)
+ dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
+ phydev, speed, duplex,
+ tx_pause, rx_pause);
+}
+
static int ksz_switch_detect(struct ksz_device *dev)
{
u8 id1, id2;
@@ -1413,6 +1428,7 @@ static const struct dsa_switch_ops ksz_switch_ops = {
.phy_read = ksz_phy_read16,
.phy_write = ksz_phy_write16,
.phylink_get_caps = ksz_phylink_get_caps,
+ .phylink_mac_link_up = ksz_phylink_mac_link_up,
.phylink_mac_link_down = ksz_mac_link_down,
.port_enable = ksz_enable_port,
.get_strings = ksz_get_strings,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index bf4f3f3922a5..f449feab5499 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -271,6 +271,11 @@ struct ksz_dev_ops {
int (*max_mtu)(struct ksz_device *dev, int port);
void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
void (*port_init_cnt)(struct ksz_device *dev, int port);
+ void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
+ unsigned int mode,
+ phy_interface_t interface,
+ struct phy_device *phydev, int speed,
+ int duplex, bool tx_pause, bool rx_pause);
void (*config_cpu_port)(struct dsa_switch *ds);
int (*enable_stp_addr)(struct ksz_device *dev);
int (*reset)(struct ksz_device *dev);
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index d4207e97a130..145770aec963 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -17,4 +17,8 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu);
void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config);
+void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
+ unsigned int mode, phy_interface_t interface,
+ struct phy_device *phydev, int speed,
+ int duplex, bool tx_pause, bool rx_pause);
#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 8cb46caf5340..95700e0233de 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -312,6 +312,60 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
return 0;
}
+static void lan937x_config_gbit(struct ksz_device *dev, bool gbit, u8 *data)
+{
+ if (gbit)
+ *data &= ~PORT_MII_NOT_1GBIT;
+ else
+ *data |= PORT_MII_NOT_1GBIT;
+}
+
+static void lan937x_config_interface(struct ksz_device *dev, int port,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+{
+ u8 xmii_ctrl0, xmii_ctrl1;
+
+ ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
+ ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1);
+
+ switch (speed) {
+ case SPEED_1000:
+ lan937x_config_gbit(dev, true, &xmii_ctrl1);
+ break;
+ case SPEED_100:
+ lan937x_config_gbit(dev, false, &xmii_ctrl1);
+ xmii_ctrl0 |= PORT_MII_100MBIT;
+ break;
+ case SPEED_10:
+ lan937x_config_gbit(dev, false, &xmii_ctrl1);
+ xmii_ctrl0 &= ~PORT_MII_100MBIT;
+ break;
+ default:
+ dev_err(dev->dev, "Unsupported speed on port %d: %d\n",
+ port, speed);
+ return;
+ }
+
+ if (duplex)
+ xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
+ else
+ xmii_ctrl0 &= ~PORT_MII_FULL_DUPLEX;
+
+ if (tx_pause)
+ xmii_ctrl0 |= PORT_MII_TX_FLOW_CTRL;
+ else
+ xmii_ctrl1 &= ~PORT_MII_TX_FLOW_CTRL;
+
+ if (rx_pause)
+ xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
+ else
+ xmii_ctrl0 &= ~PORT_MII_RX_FLOW_CTRL;
+
+ ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
+ ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1);
+}
+
void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
struct phylink_config *config)
{
@@ -324,6 +378,19 @@ void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
}
}
+void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
+ unsigned int mode, phy_interface_t interface,
+ struct phy_device *phydev, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ /* Internal PHYs */
+ if (dev->info->internal_phy[port])
+ return;
+
+ lan937x_config_interface(dev, port, speed, duplex,
+ tx_pause, rx_pause);
+}
+
int lan937x_setup(struct dsa_switch *ds)
{
struct ksz_device *dev = ds->priv;
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 19f3aa344228..c187d0a3e7fa 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -139,6 +139,17 @@
#define PORT_MII_RX_FLOW_CTRL BIT(3)
#define PORT_GRXC_ENABLE BIT(0)
+#define REG_PORT_XMII_CTRL_1 0x0301
+#define PORT_MII_NOT_1GBIT BIT(6)
+#define PORT_MII_SEL_EDGE BIT(5)
+#define PORT_RGMII_ID_IG_ENABLE BIT(4)
+#define PORT_RGMII_ID_EG_ENABLE BIT(3)
+#define PORT_MII_MAC_MODE BIT(2)
+#define PORT_MII_SEL_M 0x3
+#define PORT_RGMII_SEL 0x0
+#define PORT_RMII_SEL 0x1
+#define PORT_MII_SEL 0x2
+
/* 4 - MAC */
#define REG_PORT_MAC_CTRL_0 0x0400
#define PORT_CHECK_LENGTH BIT(2)
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 12/13] net: dsa: microchip: lan937x: add phylink_mac_config support
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (10 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 13/13] net: dsa: microchip: add LAN937x in the ksz spi probe Arun Ramadoss
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch add support for phylink_mac_config dsa hook. It configures
the mac for MII/RMII modes. The RGMII mode will be added in the future
patches.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_common.c | 12 +++++++
drivers/net/dsa/microchip/ksz_common.h | 3 ++
drivers/net/dsa/microchip/lan937x.h | 3 ++
drivers/net/dsa/microchip/lan937x_main.c | 46 ++++++++++++++++++++++++
4 files changed, 64 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 9972b2fabf27..28d7cb2ce98f 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -221,6 +221,7 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
.mirror_add = ksz9477_port_mirror_add,
.mirror_del = ksz9477_port_mirror_del,
.get_caps = lan937x_phylink_get_caps,
+ .phylink_mac_config = lan937x_phylink_mac_config,
.phylink_mac_link_up = lan937x_phylink_mac_link_up,
.fdb_dump = ksz9477_fdb_dump,
.fdb_add = ksz9477_fdb_add,
@@ -1341,6 +1342,16 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
return dev->dev_ops->max_mtu(dev, port);
}
+static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct ksz_device *dev = ds->priv;
+
+ if (dev->dev_ops->phylink_mac_config)
+ dev->dev_ops->phylink_mac_config(dev, port, mode, state);
+}
+
static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
@@ -1428,6 +1439,7 @@ static const struct dsa_switch_ops ksz_switch_ops = {
.phy_read = ksz_phy_read16,
.phy_write = ksz_phy_write16,
.phylink_get_caps = ksz_phylink_get_caps,
+ .phylink_mac_config = ksz_phylink_mac_config,
.phylink_mac_link_up = ksz_phylink_mac_link_up,
.phylink_mac_link_down = ksz_mac_link_down,
.port_enable = ksz_enable_port,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index f449feab5499..d5dddb7ec045 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -271,6 +271,9 @@ struct ksz_dev_ops {
int (*max_mtu)(struct ksz_device *dev, int port);
void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
void (*port_init_cnt)(struct ksz_device *dev, int port);
+ void (*phylink_mac_config)(struct ksz_device *dev, int port,
+ unsigned int mode,
+ const struct phylink_link_state *state);
void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
unsigned int mode,
phy_interface_t interface,
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 145770aec963..72ba9cb2fbc6 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -21,4 +21,7 @@ void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
unsigned int mode, phy_interface_t interface,
struct phy_device *phydev, int speed,
int duplex, bool tx_pause, bool rx_pause);
+void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
+ unsigned int mode,
+ const struct phylink_link_state *state);
#endif
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 95700e0233de..1608cd6b41cd 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -320,6 +320,36 @@ static void lan937x_config_gbit(struct ksz_device *dev, bool gbit, u8 *data)
*data |= PORT_MII_NOT_1GBIT;
}
+void lan937x_mac_config(struct ksz_device *dev, int port,
+ phy_interface_t interface)
+{
+ u8 data8;
+
+ ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
+
+ /* clear MII selection & set it based on interface later */
+ data8 &= ~PORT_MII_SEL_M;
+
+ /* configure MAC based on interface */
+ switch (interface) {
+ case PHY_INTERFACE_MODE_MII:
+ lan937x_config_gbit(dev, false, &data8);
+ data8 |= PORT_MII_SEL;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ lan937x_config_gbit(dev, false, &data8);
+ data8 |= PORT_RMII_SEL;
+ break;
+ default:
+ dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
+ phy_modes(interface), port);
+ return;
+ }
+
+ /* Write the updated value */
+ ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
+}
+
static void lan937x_config_interface(struct ksz_device *dev, int port,
int speed, int duplex,
bool tx_pause, bool rx_pause)
@@ -391,6 +421,22 @@ void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
tx_pause, rx_pause);
}
+void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ /* Internal PHYs */
+ if (dev->info->internal_phy[port])
+ return;
+
+ if (phylink_autoneg_inband(mode)) {
+ dev_err(dev->dev, "In-band AN not supported!\n");
+ return;
+ }
+
+ lan937x_mac_config(dev, port, state->interface);
+}
+
int lan937x_setup(struct dsa_switch *ds)
{
struct ksz_device *dev = ds->priv;
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Patch net-next v14 13/13] net: dsa: microchip: add LAN937x in the ksz spi probe
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
` (11 preceding siblings ...)
2022-06-30 10:20 ` [Patch net-next v14 12/13] net: dsa: microchip: lan937x: add phylink_mac_config support Arun Ramadoss
@ 2022-06-30 10:20 ` Arun Ramadoss
12 siblings, 0 replies; 20+ messages in thread
From: Arun Ramadoss @ 2022-06-30 10:20 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, bpf
Cc: Woojung Huh, UNGLinuxDriver, Andrew Lunn, Vivien Didelot,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Russell King, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Song Liu, Yonghong Song,
John Fastabend, KP Singh
This patch add the LAN937x part support in the existing ksz_spi_probe.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
drivers/net/dsa/microchip/ksz_spi.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/net/dsa/microchip/ksz_spi.c b/drivers/net/dsa/microchip/ksz_spi.c
index 69fabb190f26..4844830dca72 100644
--- a/drivers/net/dsa/microchip/ksz_spi.c
+++ b/drivers/net/dsa/microchip/ksz_spi.c
@@ -166,6 +166,26 @@ static const struct of_device_id ksz_dt_ids[] = {
.compatible = "microchip,ksz9567",
.data = &ksz_switch_chips[KSZ9567]
},
+ {
+ .compatible = "microchip,lan9370",
+ .data = &ksz_switch_chips[LAN9370]
+ },
+ {
+ .compatible = "microchip,lan9371",
+ .data = &ksz_switch_chips[LAN9371]
+ },
+ {
+ .compatible = "microchip,lan9372",
+ .data = &ksz_switch_chips[LAN9372]
+ },
+ {
+ .compatible = "microchip,lan9373",
+ .data = &ksz_switch_chips[LAN9373]
+ },
+ {
+ .compatible = "microchip,lan9374",
+ .data = &ksz_switch_chips[LAN9374]
+ },
{},
};
MODULE_DEVICE_TABLE(of, ksz_dt_ids);
@@ -182,6 +202,11 @@ static const struct spi_device_id ksz_spi_ids[] = {
{ "ksz9563" },
{ "ksz8563" },
{ "ksz9567" },
+ { "lan9370" },
+ { "lan9371" },
+ { "lan9372" },
+ { "lan9373" },
+ { "lan9374" },
{ },
};
MODULE_DEVICE_TABLE(spi, ksz_spi_ids);
@@ -206,6 +231,7 @@ MODULE_ALIAS("spi:ksz9893");
MODULE_ALIAS("spi:ksz9563");
MODULE_ALIAS("spi:ksz8563");
MODULE_ALIAS("spi:ksz9567");
+MODULE_ALIAS("spi:lan937x");
MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
MODULE_DESCRIPTION("Microchip ksz Series Switch SPI Driver");
MODULE_LICENSE("GPL");
--
2.36.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support
2022-06-30 10:20 ` [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support Arun Ramadoss
@ 2022-06-30 11:36 ` Russell King (Oracle)
2022-07-01 5:51 ` Arun.Ramadoss
0 siblings, 1 reply; 20+ messages in thread
From: Russell King (Oracle) @ 2022-06-30 11:36 UTC (permalink / raw)
To: Arun Ramadoss
Cc: netdev, devicetree, linux-kernel, bpf, Woojung Huh,
UNGLinuxDriver, Andrew Lunn, Vivien Didelot, Florian Fainelli,
Vladimir Oltean, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Alexei Starovoitov, Daniel Borkmann, Andrii Nakryiko,
Martin KaFai Lau, Song Liu, Yonghong Song, John Fastabend,
KP Singh
On Thu, Jun 30, 2022 at 03:50:38PM +0530, Arun Ramadoss wrote:
> The internal phy of the LAN937x are capable of 100Mbps speed. And the
Good English grammar suggests never to start a sentence with "And".
> xMII port of switch is capable of 10/100/1000Mbps.
... and supports flow control?
> +void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
> + struct phylink_config *config)
> +{
> + config->mac_capabilities = MAC_100FD;
> +
> + if (dev->info->supports_rgmii[port]) {
> + /* MII/RMII/RGMII ports */
> + config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
> + MAC_100HD | MAC_10 | MAC_1000FD;
And SGMII too? (Which seems to be a given because from your list in the
series cover message, SGMII ports also support RGMII).
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support
2022-06-30 10:20 ` [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support Arun Ramadoss
@ 2022-06-30 11:42 ` Russell King (Oracle)
2022-07-01 5:44 ` Arun.Ramadoss
0 siblings, 1 reply; 20+ messages in thread
From: Russell King (Oracle) @ 2022-06-30 11:42 UTC (permalink / raw)
To: Arun Ramadoss
Cc: netdev, devicetree, linux-kernel, bpf, Woojung Huh,
UNGLinuxDriver, Andrew Lunn, Vivien Didelot, Florian Fainelli,
Vladimir Oltean, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Alexei Starovoitov, Daniel Borkmann, Andrii Nakryiko,
Martin KaFai Lau, Song Liu, Yonghong Song, John Fastabend,
KP Singh
On Thu, Jun 30, 2022 at 03:50:39PM +0530, Arun Ramadoss wrote:
> +static void lan937x_config_gbit(struct ksz_device *dev, bool gbit, u8 *data)
> +{
> + if (gbit)
> + *data &= ~PORT_MII_NOT_1GBIT;
> + else
> + *data |= PORT_MII_NOT_1GBIT;
> +}
> +
> +static void lan937x_config_interface(struct ksz_device *dev, int port,
> + int speed, int duplex,
> + bool tx_pause, bool rx_pause)
> +{
> + u8 xmii_ctrl0, xmii_ctrl1;
> +
> + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
> + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1);
> +
> + switch (speed) {
> + case SPEED_1000:
> + lan937x_config_gbit(dev, true, &xmii_ctrl1);
> + break;
> + case SPEED_100:
> + lan937x_config_gbit(dev, false, &xmii_ctrl1);
> + xmii_ctrl0 |= PORT_MII_100MBIT;
> + break;
> + case SPEED_10:
> + lan937x_config_gbit(dev, false, &xmii_ctrl1);
> + xmii_ctrl0 &= ~PORT_MII_100MBIT;
> + break;
> + default:
> + dev_err(dev->dev, "Unsupported speed on port %d: %d\n",
> + port, speed);
> + return;
> + }
Isn't this:
if (speed == SPEED_1000)
xmii_ctrl1 &= ~PORT_MII_NOT_1GBIT;
else
xmii_ctrl1 |= PORT_MII_NOT_1GBIT;
if (speed == SPEED_100)
xmii_ctrl0 |= PORT_MII_100MBIT;
else
xmii_ctrl0 &= ~PORT_MII_100MBIT;
There isn't much need to validate that "speed" is correct, you've
already told phylink that you only support 1G, 100M and 10M so you're
not going to get called with anything except one of those.
> +
> + if (duplex)
> + xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
> + else
> + xmii_ctrl0 &= ~PORT_MII_FULL_DUPLEX;
> +
> + if (tx_pause)
> + xmii_ctrl0 |= PORT_MII_TX_FLOW_CTRL;
> + else
> + xmii_ctrl1 &= ~PORT_MII_TX_FLOW_CTRL;
It seems weird to set a bit in one register and clear it in a different
register. I suspect you mean xmii_ctrl0 here.
> +
> + if (rx_pause)
> + xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
> + else
> + xmii_ctrl0 &= ~PORT_MII_RX_FLOW_CTRL;
> +
> + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
> + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1);
> +}
> +
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support
2022-06-30 11:42 ` Russell King (Oracle)
@ 2022-07-01 5:44 ` Arun.Ramadoss
0 siblings, 0 replies; 20+ messages in thread
From: Arun.Ramadoss @ 2022-07-01 5:44 UTC (permalink / raw)
To: linux
Cc: andrew, linux-kernel, UNGLinuxDriver, vivien.didelot, ast, bpf,
olteanv, devicetree, robh+dt, andrii, songliubraving, f.fainelli,
daniel, john.fastabend, kuba, edumazet, pabeni, kpsingh, netdev,
Woojung.Huh, krzysztof.kozlowski+dt, yhs, davem, kafai
Hi Russell,
Thanks for the review comment.
On Thu, 2022-06-30 at 12:42 +0100, Russell King (Oracle) wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Thu, Jun 30, 2022 at 03:50:39PM +0530, Arun Ramadoss wrote:
> > +static void lan937x_config_gbit(struct ksz_device *dev, bool gbit,
> > u8 *data)
> > +{
> > + if (gbit)
> > + *data &= ~PORT_MII_NOT_1GBIT;
> > + else
> > + *data |= PORT_MII_NOT_1GBIT;
> > +}
> > +
> > +static void lan937x_config_interface(struct ksz_device *dev, int
> > port,
> > + int speed, int duplex,
> > + bool tx_pause, bool rx_pause)
> > +{
> > + u8 xmii_ctrl0, xmii_ctrl1;
> > +
> > + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
> > + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1);
> > +
> > + switch (speed) {
> > + case SPEED_1000:
> > + lan937x_config_gbit(dev, true, &xmii_ctrl1);
> > + break;
> > + case SPEED_100:
> > + lan937x_config_gbit(dev, false, &xmii_ctrl1);
> > + xmii_ctrl0 |= PORT_MII_100MBIT;
> > + break;
> > + case SPEED_10:
> > + lan937x_config_gbit(dev, false, &xmii_ctrl1);
> > + xmii_ctrl0 &= ~PORT_MII_100MBIT;
> > + break;
> > + default:
> > + dev_err(dev->dev, "Unsupported speed on port %d:
> > %d\n",
> > + port, speed);
> > + return;
> > + }
>
> Isn't this:
>
> if (speed == SPEED_1000)
> xmii_ctrl1 &= ~PORT_MII_NOT_1GBIT;
> else
> xmii_ctrl1 |= PORT_MII_NOT_1GBIT;
>
> if (speed == SPEED_100)
> xmii_ctrl0 |= PORT_MII_100MBIT;
> else
> xmii_ctrl0 &= ~PORT_MII_100MBIT;
>
> There isn't much need to validate that "speed" is correct, you've
> already told phylink that you only support 1G, 100M and 10M so you're
> not going to get called with anything except one of those.
Ok, I will update the code.
>
> > +
> > + if (duplex)
> > + xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
> > + else
> > + xmii_ctrl0 &= ~PORT_MII_FULL_DUPLEX;
> > +
> > + if (tx_pause)
> > + xmii_ctrl0 |= PORT_MII_TX_FLOW_CTRL;
> > + else
> > + xmii_ctrl1 &= ~PORT_MII_TX_FLOW_CTRL;
>
> It seems weird to set a bit in one register and clear it in a
> different
> register. I suspect you mean xmii_ctrl0 here.
Sorry, its a typo mistake. I will update the register.
>
> > +
> > + if (rx_pause)
> > + xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
> > + else
> > + xmii_ctrl0 &= ~PORT_MII_RX_FLOW_CTRL;
> > +
> > + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
> > + ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1);
> > +}
> > +
>
> Thanks!
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support
2022-06-30 11:36 ` Russell King (Oracle)
@ 2022-07-01 5:51 ` Arun.Ramadoss
2022-07-01 8:07 ` Russell King (Oracle)
0 siblings, 1 reply; 20+ messages in thread
From: Arun.Ramadoss @ 2022-07-01 5:51 UTC (permalink / raw)
To: linux
Cc: andrew, linux-kernel, UNGLinuxDriver, vivien.didelot, ast, bpf,
olteanv, devicetree, robh+dt, andrii, songliubraving, f.fainelli,
daniel, john.fastabend, kuba, edumazet, pabeni, kpsingh, netdev,
Woojung.Huh, krzysztof.kozlowski+dt, yhs, davem, kafai
Hi Russell,
Thanks for the review comment.
On Thu, 2022-06-30 at 12:36 +0100, Russell King (Oracle) wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Thu, Jun 30, 2022 at 03:50:38PM +0530, Arun Ramadoss wrote:
> > The internal phy of the LAN937x are capable of 100Mbps speed. And
> > the
>
> Good English grammar suggests never to start a sentence with "And".
Ok. I will update the description.
>
> > xMII port of switch is capable of 10/100/1000Mbps.
>
> ... and supports flow control?
>
> > +void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
> > + struct phylink_config *config)
> > +{
> > + config->mac_capabilities = MAC_100FD;
> > +
> > + if (dev->info->supports_rgmii[port]) {
> > + /* MII/RMII/RGMII ports */
> > + config->mac_capabilities |= MAC_ASYM_PAUSE |
> > MAC_SYM_PAUSE |
> > + MAC_100HD | MAC_10 |
> > MAC_1000FD;
>
> And SGMII too? (Which seems to be a given because from your list in
> the
> series cover message, SGMII ports also support RGMII).
No, SGMII port does not support the RGMII. I have mentioned in the
cover message that LAN9373 has 2 RGMII and 1 SGMII port. No other part
number has SGMII port.
>
> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support
2022-07-01 5:51 ` Arun.Ramadoss
@ 2022-07-01 8:07 ` Russell King (Oracle)
2022-07-01 8:37 ` Arun.Ramadoss
0 siblings, 1 reply; 20+ messages in thread
From: Russell King (Oracle) @ 2022-07-01 8:07 UTC (permalink / raw)
To: Arun.Ramadoss
Cc: andrew, linux-kernel, UNGLinuxDriver, vivien.didelot, ast, bpf,
olteanv, devicetree, robh+dt, andrii, songliubraving, f.fainelli,
daniel, john.fastabend, kuba, edumazet, pabeni, kpsingh, netdev,
Woojung.Huh, krzysztof.kozlowski+dt, yhs, davem, kafai
On Fri, Jul 01, 2022 at 05:51:33AM +0000, Arun.Ramadoss@microchip.com wrote:
> > > +void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
> > > + struct phylink_config *config)
> > > +{
> > > + config->mac_capabilities = MAC_100FD;
> > > +
> > > + if (dev->info->supports_rgmii[port]) {
> > > + /* MII/RMII/RGMII ports */
> > > + config->mac_capabilities |= MAC_ASYM_PAUSE |
> > > MAC_SYM_PAUSE |
> > > + MAC_100HD | MAC_10 |
> > > MAC_1000FD;
> >
> > And SGMII too? (Which seems to be a given because from your list in
> > the
> > series cover message, SGMII ports also support RGMII).
>
> No, SGMII port does not support the RGMII. I have mentioned in the
> cover message that LAN9373 has 2 RGMII and 1 SGMII port. No other part
> number has SGMII port.
So when using SGMII, there's no way for pause frames to be supported?
It seems a bit weird that the pause frame capability is dependent on
the interface type, as pause frames are just the same as normal
ethernet frames, except they're ggenerally enerated and/or interpreted
by the MAC.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support
2022-07-01 8:07 ` Russell King (Oracle)
@ 2022-07-01 8:37 ` Arun.Ramadoss
0 siblings, 0 replies; 20+ messages in thread
From: Arun.Ramadoss @ 2022-07-01 8:37 UTC (permalink / raw)
To: linux
Cc: olteanv, linux-kernel, UNGLinuxDriver, vivien.didelot, ast, bpf,
andrew, devicetree, robh+dt, andrii, songliubraving, f.fainelli,
daniel, john.fastabend, kuba, edumazet, pabeni, kpsingh, netdev,
Woojung.Huh, krzysztof.kozlowski+dt, yhs, davem, kafai
On Fri, 2022-07-01 at 09:07 +0100, Russell King (Oracle) wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Fri, Jul 01, 2022 at 05:51:33AM +0000, Arun.Ramadoss@microchip.com
> wrote:
> > > > +void lan937x_phylink_get_caps(struct ksz_device *dev, int
> > > > port,
> > > > + struct phylink_config *config)
> > > > +{
> > > > + config->mac_capabilities = MAC_100FD;
> > > > +
> > > > + if (dev->info->supports_rgmii[port]) {
> > > > + /* MII/RMII/RGMII ports */
> > > > + config->mac_capabilities |= MAC_ASYM_PAUSE |
> > > > MAC_SYM_PAUSE |
> > > > + MAC_100HD | MAC_10 |
> > > > MAC_1000FD;
> > >
> > > And SGMII too? (Which seems to be a given because from your list
> > > in
> > > the
> > > series cover message, SGMII ports also support RGMII).
> >
> > No, SGMII port does not support the RGMII. I have mentioned in the
> > cover message that LAN9373 has 2 RGMII and 1 SGMII port. No other
> > part
> > number has SGMII port.
>
> So when using SGMII, there's no way for pause frames to be supported?
> It seems a bit weird that the pause frame capability is dependent on
> the interface type, as pause frames are just the same as normal
> ethernet frames, except they're ggenerally enerated and/or
> interpreted
> by the MAC.
As per the comment, I infer that you want to include the capability of
SGMII port as well. As of now, we implemented the dsa for RMII/RGMII.
Yet to implement and test the SGMII port. Since we have not tested the
port, we haven't included it. As per datasheet, SGMII port supports the
flow control.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-07-01 8:38 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-30 10:20 [Patch net-next v14 00/13] net: dsa: microchip: DSA Driver support for LAN937x Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 01/13] dt-bindings: net: make internal-delay-ps based on phy-mode Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 02/13] dt-bindings: net: dsa: dt bindings for microchip lan937x Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 03/13] net: dsa: tag_ksz: add tag handling for Microchip LAN937x Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 04/13] net: dsa: microchip: generic access to ksz9477 static and reserved table Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 05/13] net: dsa: microchip: add DSA support for microchip LAN937x Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 06/13] net: dsa: microchip: lan937x: add dsa_tag_protocol Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 07/13] net: dsa: microchip: lan937x: add phy read and write support Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 08/13] net: dsa: microchip: lan937x: register mdio-bus Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 09/13] net: dsa: microchip: lan937x: add MTU and fast_age support Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 10/13] net: dsa: microchip: lan937x: add phylink_get_caps support Arun Ramadoss
2022-06-30 11:36 ` Russell King (Oracle)
2022-07-01 5:51 ` Arun.Ramadoss
2022-07-01 8:07 ` Russell King (Oracle)
2022-07-01 8:37 ` Arun.Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 11/13] net: dsa: microchip: lan937x: add phylink_mac_link_up support Arun Ramadoss
2022-06-30 11:42 ` Russell King (Oracle)
2022-07-01 5:44 ` Arun.Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 12/13] net: dsa: microchip: lan937x: add phylink_mac_config support Arun Ramadoss
2022-06-30 10:20 ` [Patch net-next v14 13/13] net: dsa: microchip: add LAN937x in the ksz spi probe Arun Ramadoss
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