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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, wenmeng_zhang@c-sky.com,
	Alistair.Francis@wdc.com, wxy194768@alibaba-inc.com
Subject: Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits
Date: Tue, 30 Jun 2020 08:00:59 -0700	[thread overview]
Message-ID: <dcac30bb-4d01-48fa-ee48-0feed464b180@linaro.org> (raw)
In-Reply-To: <20200629130731.1080-3-zhiwei_liu@c-sky.com>

On 6/29/20 6:07 AM, LIU Zhiwei wrote:
> +static bool
> +gen_amo_w(DisasContext *ctx, arg_atomic *a,
> +          void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
> +          MemOp mop, bool sign)
>  {
>      TCGv src1 = tcg_temp_new();
>      TCGv src2 = tcg_temp_new();
>  
>      gen_get_gpr(src1, a->rs1);
>      gen_get_gpr(src2, a->rs2);
> +    if (sign) {
> +        tcg_gen_ext32s_tl(src2, src2);
> +    } else {
> +        tcg_gen_ext32u_tl(src2, src2);
> +    }
>  
>      (*func)(src2, src1, src2, ctx->mem_idx, mop);
> -
> +    tcg_gen_ext32s_tl(src2, src2);
>      gen_set_gpr(a->rd, src2);
> +
>      tcg_temp_free(src1);
>      tcg_temp_free(src2);
>      return true;

With the fix to tcg, there should be no change required here, since you're
already passing MO_TESL for signed input.

Note that unsigned comparisions work as expected with sign-extended inputs.
That's what the risc-v isa does, after all.


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com
Subject: Re: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits
Date: Tue, 30 Jun 2020 08:00:59 -0700	[thread overview]
Message-ID: <dcac30bb-4d01-48fa-ee48-0feed464b180@linaro.org> (raw)
In-Reply-To: <20200629130731.1080-3-zhiwei_liu@c-sky.com>

On 6/29/20 6:07 AM, LIU Zhiwei wrote:
> +static bool
> +gen_amo_w(DisasContext *ctx, arg_atomic *a,
> +          void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
> +          MemOp mop, bool sign)
>  {
>      TCGv src1 = tcg_temp_new();
>      TCGv src2 = tcg_temp_new();
>  
>      gen_get_gpr(src1, a->rs1);
>      gen_get_gpr(src2, a->rs2);
> +    if (sign) {
> +        tcg_gen_ext32s_tl(src2, src2);
> +    } else {
> +        tcg_gen_ext32u_tl(src2, src2);
> +    }
>  
>      (*func)(src2, src1, src2, ctx->mem_idx, mop);
> -
> +    tcg_gen_ext32s_tl(src2, src2);
>      gen_set_gpr(a->rd, src2);
> +
>      tcg_temp_free(src1);
>      tcg_temp_free(src2);
>      return true;

With the fix to tcg, there should be no change required here, since you're
already passing MO_TESL for signed input.

Note that unsigned comparisions work as expected with sign-extended inputs.
That's what the risc-v isa does, after all.


r~


  reply	other threads:[~2020-06-30 15:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29 13:07 [PATCH 0/2] target/riscv: fixup atomic implementation LIU Zhiwei
2020-06-29 13:07 ` LIU Zhiwei
2020-06-29 13:07 ` [PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN LIU Zhiwei
2020-06-29 13:07   ` LIU Zhiwei
2020-06-30 14:56   ` Richard Henderson
2020-06-30 14:56     ` Richard Henderson
2020-06-30 15:22     ` LIU Zhiwei
2020-06-30 15:22       ` LIU Zhiwei
2020-06-29 13:07 ` [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits LIU Zhiwei
2020-06-29 13:07   ` LIU Zhiwei
2020-06-30 15:00   ` Richard Henderson [this message]
2020-06-30 15:00     ` Richard Henderson
2020-06-30 15:38     ` LIU Zhiwei
2020-06-30 15:38       ` LIU Zhiwei

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