* [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields
@ 2018-09-14 9:07 Suzuki K Poulose
2018-09-14 17:12 ` Catalin Marinas
0 siblings, 1 reply; 5+ messages in thread
From: Suzuki K Poulose @ 2018-09-14 9:07 UTC (permalink / raw)
To: linux-arm-kernel
Instructions for modifying the PSTATE fields which were not supported
in the older toolchains (e.g, PAN, UAO) are generated using macros.
We have so far used the normal sys_reg() helper for defining the PSTATE
fields. While this works fine, it is really difficult to correlate the
code with the Arm ARM definition.
As per Arm ARM, the PSTATE fields are defined only using Op1, Op2 fields,
with fixed values for Op0, CRn. Also the CRm field has been reserved
for the Immediate value for the instruction. So using the sys_reg()
looks quite confusing.
This patch cleans up the instruction helpers by bringing them
in line with the Arm ARM definitions to make it easier to correlate
code with the document. No functional changes.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/sysreg.h | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c1470931b897..68c22360551e 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -84,13 +84,23 @@
#endif /* CONFIG_BROKEN_GAS_INST */
-#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
-#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
+/*
+ * Instructions for modifying PSTATE fields.
+ * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
+ * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
+ * for accessing PSTATE fields have the following encoding:
+ * Op0 = 0, CRn = 4
+ * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
+ * CRm = Imm4 for the instruction.
+ * Rt = 0x1f
+ */
+#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
+#define PSTATE_Imm_shift CRm_shift
+#define PSTATE_PAN pstate_field(0, 4)
+#define PSTATE_UAO pstate_field(0, 3)
-#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
- (!!x)<<8 | 0x1f)
-#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
- (!!x)<<8 | 0x1f)
+#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
--
2.19.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields
2018-09-14 9:07 [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields Suzuki K Poulose
@ 2018-09-14 17:12 ` Catalin Marinas
2018-09-14 17:23 ` Suzuki K Poulose
0 siblings, 1 reply; 5+ messages in thread
From: Catalin Marinas @ 2018-09-14 17:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Suzuki,
On Fri, Sep 14, 2018 at 10:07:49AM +0100, Suzuki K. Poulose wrote:
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index c1470931b897..68c22360551e 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -84,13 +84,23 @@
>
> #endif /* CONFIG_BROKEN_GAS_INST */
>
> -#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
> -#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
> +/*
> + * Instructions for modifying PSTATE fields.
> + * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
> + * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
> + * for accessing PSTATE fields have the following encoding:
> + * Op0 = 0, CRn = 4
> + * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
> + * CRm = Imm4 for the instruction.
> + * Rt = 0x1f
> + */
> +#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
> +#define PSTATE_Imm_shift CRm_shift
> +#define PSTATE_PAN pstate_field(0, 4)
> +#define PSTATE_UAO pstate_field(0, 3)
>
> -#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
> - (!!x)<<8 | 0x1f)
> -#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
> - (!!x)<<8 | 0x1f)
> +#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
> +#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
Could you please rebase this on top of arm64 for-next/core and also fix
Will's SSBS macros which conflict with the above?
Thanks.
--
Catalin
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields
2018-09-14 17:12 ` Catalin Marinas
@ 2018-09-14 17:23 ` Suzuki K Poulose
0 siblings, 0 replies; 5+ messages in thread
From: Suzuki K Poulose @ 2018-09-14 17:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi Catalin,
On 14/09/18 18:12, Catalin Marinas wrote:
> Hi Suzuki,
>
> On Fri, Sep 14, 2018 at 10:07:49AM +0100, Suzuki K. Poulose wrote:
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index c1470931b897..68c22360551e 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
..
>> +#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
>> +#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
>
> Could you please rebase this on top of arm64 for-next/core and also fix
> Will's SSBS macros which conflict with the above?
>
Sure, will do.
Suzuki
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields
2018-09-16 22:17 Suzuki K Poulose
@ 2018-09-17 14:17 ` Catalin Marinas
0 siblings, 0 replies; 5+ messages in thread
From: Catalin Marinas @ 2018-09-17 14:17 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Sep 16, 2018 at 11:17:23PM +0100, Suzuki K. Poulose wrote:
> Instructions for modifying the PSTATE fields which were not supported
> in the older toolchains (e.g, PAN, UAO) are generated using macros.
> We have so far used the normal sys_reg() helper for defining the PSTATE
> fields. While this works fine, it is really difficult to correlate the
> code with the Arm ARM definition.
>
> As per Arm ARM, the PSTATE fields are defined only using Op1, Op2 fields,
> with fixed values for Op0, CRn. Also the CRm field has been reserved
> for the Immediate value for the instruction. So using the sys_reg()
> looks quite confusing.
>
> This patch cleans up the instruction helpers by bringing them
> in line with the Arm ARM definitions to make it easier to correlate
> code with the document. No functional changes.
>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> Changes since v1
> - Rebased to arm64 for-next/core.
> - Cleanup SSBS defintions and replace CRm_shift => PSTATE_Imm_shift
Applied for 4.20. Thanks.
--
Catalin
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields
@ 2018-09-16 22:17 Suzuki K Poulose
2018-09-17 14:17 ` Catalin Marinas
0 siblings, 1 reply; 5+ messages in thread
From: Suzuki K Poulose @ 2018-09-16 22:17 UTC (permalink / raw)
To: linux-arm-kernel
Instructions for modifying the PSTATE fields which were not supported
in the older toolchains (e.g, PAN, UAO) are generated using macros.
We have so far used the normal sys_reg() helper for defining the PSTATE
fields. While this works fine, it is really difficult to correlate the
code with the Arm ARM definition.
As per Arm ARM, the PSTATE fields are defined only using Op1, Op2 fields,
with fixed values for Op0, CRn. Also the CRm field has been reserved
for the Immediate value for the instruction. So using the sys_reg()
looks quite confusing.
This patch cleans up the instruction helpers by bringing them
in line with the Arm ARM definitions to make it easier to correlate
code with the document. No functional changes.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v1
- Rebased to arm64 for-next/core.
- Cleanup SSBS defintions and replace CRm_shift => PSTATE_Imm_shift
---
arch/arm64/include/asm/sysreg.h | 28 +++++++++++++++++++---------
arch/arm64/kernel/cpufeature.c | 6 +++---
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3091ae5975a3..7e9ab1fa090c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -84,16 +84,26 @@
#endif /* CONFIG_BROKEN_GAS_INST */
-#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
-#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
-#define REG_PSTATE_SSBS_IMM sys_reg(0, 3, 4, 0, 1)
+/*
+ * Instructions for modifying PSTATE fields.
+ * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
+ * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
+ * for accessing PSTATE fields have the following encoding:
+ * Op0 = 0, CRn = 4
+ * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
+ * CRm = Imm4 for the instruction.
+ * Rt = 0x1f
+ */
+#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
+#define PSTATE_Imm_shift CRm_shift
-#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
- (!!x)<<8 | 0x1f)
-#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
- (!!x)<<8 | 0x1f)
-#define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \
- (!!x)<<8 | 0x1f)
+#define PSTATE_PAN pstate_field(0, 4)
+#define PSTATE_UAO pstate_field(0, 3)
+#define PSTATE_SSBS pstate_field(3, 1)
+
+#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 35796ca1db50..f15e2fb97011 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1045,7 +1045,7 @@ static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
if (user_mode(regs))
return 1;
- if (instr & BIT(CRm_shift))
+ if (instr & BIT(PSTATE_Imm_shift))
regs->pstate |= PSR_SSBS_BIT;
else
regs->pstate &= ~PSR_SSBS_BIT;
@@ -1055,8 +1055,8 @@ static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
}
static struct undef_hook ssbs_emulation_hook = {
- .instr_mask = ~(1U << CRm_shift),
- .instr_val = 0xd500001f | REG_PSTATE_SSBS_IMM,
+ .instr_mask = ~(1U << PSTATE_Imm_shift),
+ .instr_val = 0xd500401f | PSTATE_SSBS,
.fn = ssbs_emulation_handler,
};
--
2.19.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2018-09-14 9:07 [PATCH] arm64: sysreg: Clean up instructions for modifying PSTATE fields Suzuki K Poulose
2018-09-14 17:12 ` Catalin Marinas
2018-09-14 17:23 ` Suzuki K Poulose
2018-09-16 22:17 Suzuki K Poulose
2018-09-17 14:17 ` Catalin Marinas
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