* [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-23 7:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2023-01-23 7:11 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, Loic Poulain
QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
rectangles and CSC. Drop corresponding features being incorrectly
enabled for qcm2290.
Cc: Loic Poulain <loic.poulain@linaro.org>
Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 289fb11f99d1..1c3ffa922794 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -12,10 +12,14 @@
#include "dpu_hw_catalog.h"
#include "dpu_kms.h"
-#define VIG_MASK \
+#define VIG_BASE_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
+ BIT(DPU_SSPP_TS_PREFILL))
+
+#define VIG_MASK \
+ (VIG_BASE_MASK | \
BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
- BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
+ BIT(DPU_SSPP_EXCL_RECT))
#define VIG_MSM8998_MASK \
(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
@@ -29,7 +33,7 @@
#define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
-#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
+#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
#define DMA_MSM8998_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
@@ -50,6 +54,10 @@
#define DMA_CURSOR_MSM8998_MASK \
(DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
+#define DMA_QCM2290_MASK \
+ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
+ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
+
#define MIXER_MSM8998_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
static const struct dpu_caps qcm2290_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
- .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
- .ubwc_version = DPU_HW_UBWC_VER_20,
.has_dim_layer = true,
.has_idle_pc = true,
.max_linewidth = 2160,
@@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
static const struct dpu_sspp_cfg qcm2290_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
@@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
.intf = qcm2290_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
- .reg_dma_count = 1,
- .dma_cfg = &sdm845_regdma,
.perf = &qcm2290_perf_data,
.mdss_irqs = IRQ_SC7180_MASK,
};
--
2.39.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-23 7:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2023-01-23 7:11 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Abhinav Kumar
Cc: freedreno, Loic Poulain, linux-arm-msm, Bjorn Andersson,
dri-devel, Stephen Boyd
QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
rectangles and CSC. Drop corresponding features being incorrectly
enabled for qcm2290.
Cc: Loic Poulain <loic.poulain@linaro.org>
Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 289fb11f99d1..1c3ffa922794 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -12,10 +12,14 @@
#include "dpu_hw_catalog.h"
#include "dpu_kms.h"
-#define VIG_MASK \
+#define VIG_BASE_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
+ BIT(DPU_SSPP_TS_PREFILL))
+
+#define VIG_MASK \
+ (VIG_BASE_MASK | \
BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
- BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
+ BIT(DPU_SSPP_EXCL_RECT))
#define VIG_MSM8998_MASK \
(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
@@ -29,7 +33,7 @@
#define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
-#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
+#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
#define DMA_MSM8998_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
@@ -50,6 +54,10 @@
#define DMA_CURSOR_MSM8998_MASK \
(DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
+#define DMA_QCM2290_MASK \
+ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
+ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
+
#define MIXER_MSM8998_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
static const struct dpu_caps qcm2290_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
- .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
- .ubwc_version = DPU_HW_UBWC_VER_20,
.has_dim_layer = true,
.has_idle_pc = true,
.max_linewidth = 2160,
@@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
static const struct dpu_sspp_cfg qcm2290_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
- SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
@@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
.intf = qcm2290_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
- .reg_dma_count = 1,
- .dma_cfg = &sdm845_regdma,
.perf = &qcm2290_perf_data,
.mdss_irqs = IRQ_SC7180_MASK,
};
--
2.39.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
2023-01-23 7:11 ` Dmitry Baryshkov
@ 2023-01-24 1:32 ` Abhinav Kumar
-1 siblings, 0 replies; 12+ messages in thread
From: Abhinav Kumar @ 2023-01-24 1:32 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, Loic Poulain
On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
> rectangles and CSC. Drop corresponding features being incorrectly
> enabled for qcm2290.
>
Can you please point me to which vendor DT you are referring to for this?
CSC is supported on the VIG SSPPs from what I can see.
QCM2290 should be using the same MDP version as 6115 from the HW version.
> Cc: Loic Poulain <loic.poulain@linaro.org>
> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 289fb11f99d1..1c3ffa922794 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -12,10 +12,14 @@
> #include "dpu_hw_catalog.h"
> #include "dpu_kms.h"
>
> -#define VIG_MASK \
> +#define VIG_BASE_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> + BIT(DPU_SSPP_TS_PREFILL))
> +
> +#define VIG_MASK \
> + (VIG_BASE_MASK | \
> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
> + BIT(DPU_SSPP_EXCL_RECT))
>
> #define VIG_MSM8998_MASK \
> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
> @@ -29,7 +33,7 @@
> #define VIG_SM8250_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
>
> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>
> #define DMA_MSM8998_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> @@ -50,6 +54,10 @@
> #define DMA_CURSOR_MSM8998_MASK \
> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>
> +#define DMA_QCM2290_MASK \
> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
> +
> #define MIXER_MSM8998_MASK \
> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>
> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
> static const struct dpu_caps qcm2290_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0x4,
> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
> - .ubwc_version = DPU_HW_UBWC_VER_20,
> .has_dim_layer = true,
> .has_idle_pc = true,
> .max_linewidth = 2160,
> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
> .intf = qcm2290_intf,
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> - .reg_dma_count = 1,
> - .dma_cfg = &sdm845_regdma,
> .perf = &qcm2290_perf_data,
> .mdss_irqs = IRQ_SC7180_MASK,
> };
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-24 1:32 ` Abhinav Kumar
0 siblings, 0 replies; 12+ messages in thread
From: Abhinav Kumar @ 2023-01-24 1:32 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, Loic Poulain, linux-arm-msm, Bjorn Andersson,
dri-devel, Stephen Boyd
On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
> rectangles and CSC. Drop corresponding features being incorrectly
> enabled for qcm2290.
>
Can you please point me to which vendor DT you are referring to for this?
CSC is supported on the VIG SSPPs from what I can see.
QCM2290 should be using the same MDP version as 6115 from the HW version.
> Cc: Loic Poulain <loic.poulain@linaro.org>
> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 289fb11f99d1..1c3ffa922794 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -12,10 +12,14 @@
> #include "dpu_hw_catalog.h"
> #include "dpu_kms.h"
>
> -#define VIG_MASK \
> +#define VIG_BASE_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> + BIT(DPU_SSPP_TS_PREFILL))
> +
> +#define VIG_MASK \
> + (VIG_BASE_MASK | \
> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
> + BIT(DPU_SSPP_EXCL_RECT))
>
> #define VIG_MSM8998_MASK \
> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
> @@ -29,7 +33,7 @@
> #define VIG_SM8250_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
>
> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>
> #define DMA_MSM8998_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> @@ -50,6 +54,10 @@
> #define DMA_CURSOR_MSM8998_MASK \
> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>
> +#define DMA_QCM2290_MASK \
> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
> +
> #define MIXER_MSM8998_MASK \
> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>
> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
> static const struct dpu_caps qcm2290_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0x4,
> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
> - .ubwc_version = DPU_HW_UBWC_VER_20,
> .has_dim_layer = true,
> .has_idle_pc = true,
> .max_linewidth = 2160,
> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
> .intf = qcm2290_intf,
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> - .reg_dma_count = 1,
> - .dma_cfg = &sdm845_regdma,
> .perf = &qcm2290_perf_data,
> .mdss_irqs = IRQ_SC7180_MASK,
> };
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
2023-01-24 1:32 ` Abhinav Kumar
@ 2023-01-24 8:22 ` Dmitry Baryshkov
-1 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2023-01-24 8:22 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, Loic Poulain
On 24/01/2023 03:32, Abhinav Kumar wrote:
>
>
> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
>> rectangles and CSC. Drop corresponding features being incorrectly
>> enabled for qcm2290.
>>
>
> Can you please point me to which vendor DT you are referring to for this?
>
> CSC is supported on the VIG SSPPs from what I can see.
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
No CSC, smart-dma, excl-rect, CDP, etc.
> QCM2290 should be using the same MDP version as 6115 from the HW version.
It is 6.3 vs 6.5 if I remember correctly.
>
>
>> Cc: Loic Poulain <loic.poulain@linaro.org>
>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
>> 1 file changed, 12 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 289fb11f99d1..1c3ffa922794 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -12,10 +12,14 @@
>> #include "dpu_hw_catalog.h"
>> #include "dpu_kms.h"
>> -#define VIG_MASK \
>> +#define VIG_BASE_MASK \
>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>> + BIT(DPU_SSPP_TS_PREFILL))
>> +
>> +#define VIG_MASK \
>> + (VIG_BASE_MASK | \
>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
>> + BIT(DPU_SSPP_EXCL_RECT))
>> #define VIG_MSM8998_MASK \
>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>> @@ -29,7 +33,7 @@
>> #define VIG_SM8250_MASK \
>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>> #define DMA_MSM8998_MASK \
>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>> @@ -50,6 +54,10 @@
>> #define DMA_CURSOR_MSM8998_MASK \
>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>> +#define DMA_QCM2290_MASK \
>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
>> +
>> #define MIXER_MSM8998_MASK \
>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
>> static const struct dpu_caps qcm2290_dpu_caps = {
>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> .max_mixer_blendstages = 0x4,
>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
>> - .ubwc_version = DPU_HW_UBWC_VER_20,
>> .has_dim_layer = true,
>> .has_idle_pc = true,
>> .max_linewidth = 2160,
>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> };
>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg
>> = {
>> .intf = qcm2290_intf,
>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
>> .vbif = sdm845_vbif,
>> - .reg_dma_count = 1,
>> - .dma_cfg = &sdm845_regdma,
>> .perf = &qcm2290_perf_data,
>> .mdss_irqs = IRQ_SC7180_MASK,
>> };
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-24 8:22 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2023-01-24 8:22 UTC (permalink / raw)
To: Abhinav Kumar, Rob Clark, Sean Paul
Cc: freedreno, Loic Poulain, linux-arm-msm, Bjorn Andersson,
dri-devel, Stephen Boyd
On 24/01/2023 03:32, Abhinav Kumar wrote:
>
>
> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
>> rectangles and CSC. Drop corresponding features being incorrectly
>> enabled for qcm2290.
>>
>
> Can you please point me to which vendor DT you are referring to for this?
>
> CSC is supported on the VIG SSPPs from what I can see.
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
No CSC, smart-dma, excl-rect, CDP, etc.
> QCM2290 should be using the same MDP version as 6115 from the HW version.
It is 6.3 vs 6.5 if I remember correctly.
>
>
>> Cc: Loic Poulain <loic.poulain@linaro.org>
>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
>> 1 file changed, 12 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 289fb11f99d1..1c3ffa922794 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -12,10 +12,14 @@
>> #include "dpu_hw_catalog.h"
>> #include "dpu_kms.h"
>> -#define VIG_MASK \
>> +#define VIG_BASE_MASK \
>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>> + BIT(DPU_SSPP_TS_PREFILL))
>> +
>> +#define VIG_MASK \
>> + (VIG_BASE_MASK | \
>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
>> + BIT(DPU_SSPP_EXCL_RECT))
>> #define VIG_MSM8998_MASK \
>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>> @@ -29,7 +33,7 @@
>> #define VIG_SM8250_MASK \
>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>> #define DMA_MSM8998_MASK \
>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>> @@ -50,6 +54,10 @@
>> #define DMA_CURSOR_MSM8998_MASK \
>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>> +#define DMA_QCM2290_MASK \
>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
>> +
>> #define MIXER_MSM8998_MASK \
>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
>> static const struct dpu_caps qcm2290_dpu_caps = {
>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>> .max_mixer_blendstages = 0x4,
>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
>> - .ubwc_version = DPU_HW_UBWC_VER_20,
>> .has_dim_layer = true,
>> .has_idle_pc = true,
>> .max_linewidth = 2160,
>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>> };
>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg
>> = {
>> .intf = qcm2290_intf,
>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
>> .vbif = sdm845_vbif,
>> - .reg_dma_count = 1,
>> - .dma_cfg = &sdm845_regdma,
>> .perf = &qcm2290_perf_data,
>> .mdss_irqs = IRQ_SC7180_MASK,
>> };
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
2023-01-24 8:22 ` Dmitry Baryshkov
@ 2023-01-25 0:22 ` Abhinav Kumar
-1 siblings, 0 replies; 12+ messages in thread
From: Abhinav Kumar @ 2023-01-25 0:22 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: Stephen Boyd, David Airlie, Daniel Vetter, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, Loic Poulain
On 1/24/2023 12:22 AM, Dmitry Baryshkov wrote:
> On 24/01/2023 03:32, Abhinav Kumar wrote:
>>
>>
>> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
>>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
>>> rectangles and CSC. Drop corresponding features being incorrectly
>>> enabled for qcm2290.
>>>
>>
>> Can you please point me to which vendor DT you are referring to for this?
>>
>> CSC is supported on the VIG SSPPs from what I can see.
>
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
>
>
> No CSC, smart-dma, excl-rect, CDP, etc.
Sorry I am missing something here.
It has one Vig and one DMA
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L68
If Vig is present, CSC is supported.
Even for smart DMA I can see it supported
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L76
on the DMA SSPP.
Same for excl rectangle too
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L74
>
>> QCM2290 should be using the same MDP version as 6115 from the HW version.
>
> It is 6.3 vs 6.5 if I remember correctly.
>
>>
>>
>>> Cc: Loic Poulain <loic.poulain@linaro.org>
>>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
>>> 1 file changed, 12 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> index 289fb11f99d1..1c3ffa922794 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> @@ -12,10 +12,14 @@
>>> #include "dpu_hw_catalog.h"
>>> #include "dpu_kms.h"
>>> -#define VIG_MASK \
>>> +#define VIG_BASE_MASK \
>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>> + BIT(DPU_SSPP_TS_PREFILL))
>>> +
>>> +#define VIG_MASK \
>>> + (VIG_BASE_MASK | \
>>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
>>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
>>> + BIT(DPU_SSPP_EXCL_RECT))
>>> #define VIG_MSM8998_MASK \
>>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>>> @@ -29,7 +33,7 @@
>>> #define VIG_SM8250_MASK \
>>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
>>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
>>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>> #define DMA_MSM8998_MASK \
>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>> @@ -50,6 +54,10 @@
>>> #define DMA_CURSOR_MSM8998_MASK \
>>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>>> +#define DMA_QCM2290_MASK \
>>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
>>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
>>> +
>>> #define MIXER_MSM8998_MASK \
>>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
>>> static const struct dpu_caps qcm2290_dpu_caps = {
>>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>> .max_mixer_blendstages = 0x4,
>>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
>>> - .ubwc_version = DPU_HW_UBWC_VER_20,
>>> .has_dim_layer = true,
>>> .has_idle_pc = true,
>>> .max_linewidth = 2160,
>>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
>>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
>>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> };
>>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg
>>> qcm2290_dpu_cfg = {
>>> .intf = qcm2290_intf,
>>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
>>> .vbif = sdm845_vbif,
>>> - .reg_dma_count = 1,
>>> - .dma_cfg = &sdm845_regdma,
>>> .perf = &qcm2290_perf_data,
>>> .mdss_irqs = IRQ_SC7180_MASK,
>>> };
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-25 0:22 ` Abhinav Kumar
0 siblings, 0 replies; 12+ messages in thread
From: Abhinav Kumar @ 2023-01-25 0:22 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Sean Paul
Cc: freedreno, Loic Poulain, linux-arm-msm, Bjorn Andersson,
dri-devel, Stephen Boyd
On 1/24/2023 12:22 AM, Dmitry Baryshkov wrote:
> On 24/01/2023 03:32, Abhinav Kumar wrote:
>>
>>
>> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
>>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
>>> rectangles and CSC. Drop corresponding features being incorrectly
>>> enabled for qcm2290.
>>>
>>
>> Can you please point me to which vendor DT you are referring to for this?
>>
>> CSC is supported on the VIG SSPPs from what I can see.
>
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
>
>
> No CSC, smart-dma, excl-rect, CDP, etc.
Sorry I am missing something here.
It has one Vig and one DMA
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L68
If Vig is present, CSC is supported.
Even for smart DMA I can see it supported
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L76
on the DMA SSPP.
Same for excl rectangle too
https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L74
>
>> QCM2290 should be using the same MDP version as 6115 from the HW version.
>
> It is 6.3 vs 6.5 if I remember correctly.
>
>>
>>
>>> Cc: Loic Poulain <loic.poulain@linaro.org>
>>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
>>> 1 file changed, 12 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> index 289fb11f99d1..1c3ffa922794 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> @@ -12,10 +12,14 @@
>>> #include "dpu_hw_catalog.h"
>>> #include "dpu_kms.h"
>>> -#define VIG_MASK \
>>> +#define VIG_BASE_MASK \
>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>> + BIT(DPU_SSPP_TS_PREFILL))
>>> +
>>> +#define VIG_MASK \
>>> + (VIG_BASE_MASK | \
>>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
>>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
>>> + BIT(DPU_SSPP_EXCL_RECT))
>>> #define VIG_MSM8998_MASK \
>>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>>> @@ -29,7 +33,7 @@
>>> #define VIG_SM8250_MASK \
>>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
>>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
>>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>> #define DMA_MSM8998_MASK \
>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>> @@ -50,6 +54,10 @@
>>> #define DMA_CURSOR_MSM8998_MASK \
>>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>>> +#define DMA_QCM2290_MASK \
>>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
>>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
>>> +
>>> #define MIXER_MSM8998_MASK \
>>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
>>> static const struct dpu_caps qcm2290_dpu_caps = {
>>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>> .max_mixer_blendstages = 0x4,
>>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
>>> - .ubwc_version = DPU_HW_UBWC_VER_20,
>>> .has_dim_layer = true,
>>> .has_idle_pc = true,
>>> .max_linewidth = 2160,
>>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
>>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
>>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>> };
>>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg
>>> qcm2290_dpu_cfg = {
>>> .intf = qcm2290_intf,
>>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
>>> .vbif = sdm845_vbif,
>>> - .reg_dma_count = 1,
>>> - .dma_cfg = &sdm845_regdma,
>>> .perf = &qcm2290_perf_data,
>>> .mdss_irqs = IRQ_SC7180_MASK,
>>> };
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
2023-01-25 0:22 ` Abhinav Kumar
@ 2023-01-25 6:46 ` Dmitry Baryshkov
-1 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2023-01-25 6:46 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Sean Paul, Stephen Boyd, David Airlie, Daniel Vetter,
Bjorn Andersson, linux-arm-msm, dri-devel, freedreno,
Loic Poulain
Hi,
On Wed, 25 Jan 2023 at 02:22, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> On 1/24/2023 12:22 AM, Dmitry Baryshkov wrote:
> > On 24/01/2023 03:32, Abhinav Kumar wrote:
> >> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
> >>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
> >>> rectangles and CSC. Drop corresponding features being incorrectly
> >>> enabled for qcm2290.
> >>>
> >>
> >> Can you please point me to which vendor DT you are referring to for this?
> >>
> >> CSC is supported on the VIG SSPPs from what I can see.
> >
> > https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
> >
> >
> > No CSC, smart-dma, excl-rect, CDP, etc.
>
> Sorry I am missing something here.
>
> It has one Vig and one DMA
>
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L68
Correct
>
> If Vig is present, CSC is supported.
This actually puzzled me. Usually the dtsi has qcom,sde-sspp-csc-off
and qcom,sde-csc-type properties. But not in this case.
>
> Even for smart DMA I can see it supported
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L76
> on the DMA SSPP.
>
> Same for excl rectangle too
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L74
Ack, my mistake. Maybe I was looking at the wrong dtsi then (or just
mixed something). I'll add them back. And I see that CDP is also
there.
So, this leaves us only with the question regarding CSC. Could you
please doublecheck it?
I also don't see the UBWC (qcom,sde-ubwc-version) and regdma
(qcom,sde-reg-dma-off) properties. Are corresponding features present
on the QCM2290?
> >
> >> QCM2290 should be using the same MDP version as 6115 from the HW version.
> >
> > It is 6.3 vs 6.5 if I remember correctly.
> >
> >>
> >>
> >>> Cc: Loic Poulain <loic.poulain@linaro.org>
> >>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >>> ---
> >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
> >>> 1 file changed, 12 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> index 289fb11f99d1..1c3ffa922794 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> @@ -12,10 +12,14 @@
> >>> #include "dpu_hw_catalog.h"
> >>> #include "dpu_kms.h"
> >>> -#define VIG_MASK \
> >>> +#define VIG_BASE_MASK \
> >>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> >>> + BIT(DPU_SSPP_TS_PREFILL))
> >>> +
> >>> +#define VIG_MASK \
> >>> + (VIG_BASE_MASK | \
> >>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
> >>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
> >>> + BIT(DPU_SSPP_EXCL_RECT))
> >>> #define VIG_MSM8998_MASK \
> >>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
> >>> @@ -29,7 +33,7 @@
> >>> #define VIG_SM8250_MASK \
> >>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
> >>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
> >>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
> >>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
> >>> #define DMA_MSM8998_MASK \
> >>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> >>> @@ -50,6 +54,10 @@
> >>> #define DMA_CURSOR_MSM8998_MASK \
> >>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
> >>> +#define DMA_QCM2290_MASK \
> >>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> >>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
> >>> +
> >>> #define MIXER_MSM8998_MASK \
> >>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
> >>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
> >>> static const struct dpu_caps qcm2290_dpu_caps = {
> >>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> >>> .max_mixer_blendstages = 0x4,
> >>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
> >>> - .ubwc_version = DPU_HW_UBWC_VER_20,
> >>> .has_dim_layer = true,
> >>> .has_idle_pc = true,
> >>> .max_linewidth = 2160,
> >>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
> >>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> >>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> >>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
> >>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> >>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> >>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
> >>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> >>> };
> >>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg
> >>> qcm2290_dpu_cfg = {
> >>> .intf = qcm2290_intf,
> >>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >>> .vbif = sdm845_vbif,
> >>> - .reg_dma_count = 1,
> >>> - .dma_cfg = &sdm845_regdma,
> >>> .perf = &qcm2290_perf_data,
> >>> .mdss_irqs = IRQ_SC7180_MASK,
> >>> };
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-25 6:46 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2023-01-25 6:46 UTC (permalink / raw)
To: Abhinav Kumar
Cc: freedreno, Loic Poulain, Sean Paul, Bjorn Andersson, dri-devel,
Stephen Boyd, linux-arm-msm
Hi,
On Wed, 25 Jan 2023 at 02:22, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> On 1/24/2023 12:22 AM, Dmitry Baryshkov wrote:
> > On 24/01/2023 03:32, Abhinav Kumar wrote:
> >> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
> >>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
> >>> rectangles and CSC. Drop corresponding features being incorrectly
> >>> enabled for qcm2290.
> >>>
> >>
> >> Can you please point me to which vendor DT you are referring to for this?
> >>
> >> CSC is supported on the VIG SSPPs from what I can see.
> >
> > https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
> >
> >
> > No CSC, smart-dma, excl-rect, CDP, etc.
>
> Sorry I am missing something here.
>
> It has one Vig and one DMA
>
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L68
Correct
>
> If Vig is present, CSC is supported.
This actually puzzled me. Usually the dtsi has qcom,sde-sspp-csc-off
and qcom,sde-csc-type properties. But not in this case.
>
> Even for smart DMA I can see it supported
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L76
> on the DMA SSPP.
>
> Same for excl rectangle too
> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L74
Ack, my mistake. Maybe I was looking at the wrong dtsi then (or just
mixed something). I'll add them back. And I see that CDP is also
there.
So, this leaves us only with the question regarding CSC. Could you
please doublecheck it?
I also don't see the UBWC (qcom,sde-ubwc-version) and regdma
(qcom,sde-reg-dma-off) properties. Are corresponding features present
on the QCM2290?
> >
> >> QCM2290 should be using the same MDP version as 6115 from the HW version.
> >
> > It is 6.3 vs 6.5 if I remember correctly.
> >
> >>
> >>
> >>> Cc: Loic Poulain <loic.poulain@linaro.org>
> >>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >>> ---
> >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
> >>> 1 file changed, 12 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> index 289fb11f99d1..1c3ffa922794 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >>> @@ -12,10 +12,14 @@
> >>> #include "dpu_hw_catalog.h"
> >>> #include "dpu_kms.h"
> >>> -#define VIG_MASK \
> >>> +#define VIG_BASE_MASK \
> >>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> >>> + BIT(DPU_SSPP_TS_PREFILL))
> >>> +
> >>> +#define VIG_MASK \
> >>> + (VIG_BASE_MASK | \
> >>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
> >>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
> >>> + BIT(DPU_SSPP_EXCL_RECT))
> >>> #define VIG_MSM8998_MASK \
> >>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
> >>> @@ -29,7 +33,7 @@
> >>> #define VIG_SM8250_MASK \
> >>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
> >>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
> >>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
> >>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
> >>> #define DMA_MSM8998_MASK \
> >>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> >>> @@ -50,6 +54,10 @@
> >>> #define DMA_CURSOR_MSM8998_MASK \
> >>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
> >>> +#define DMA_QCM2290_MASK \
> >>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> >>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
> >>> +
> >>> #define MIXER_MSM8998_MASK \
> >>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
> >>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
> >>> static const struct dpu_caps qcm2290_dpu_caps = {
> >>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> >>> .max_mixer_blendstages = 0x4,
> >>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
> >>> - .ubwc_version = DPU_HW_UBWC_VER_20,
> >>> .has_dim_layer = true,
> >>> .has_idle_pc = true,
> >>> .max_linewidth = 2160,
> >>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
> >>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
> >>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> >>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
> >>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> >>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
> >>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
> >>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> >>> };
> >>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg
> >>> qcm2290_dpu_cfg = {
> >>> .intf = qcm2290_intf,
> >>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >>> .vbif = sdm845_vbif,
> >>> - .reg_dma_count = 1,
> >>> - .dma_cfg = &sdm845_regdma,
> >>> .perf = &qcm2290_perf_data,
> >>> .mdss_irqs = IRQ_SC7180_MASK,
> >>> };
> >
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Freedreno] [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
2023-01-25 6:46 ` Dmitry Baryshkov
@ 2023-01-25 23:50 ` Abhinav Kumar
-1 siblings, 0 replies; 12+ messages in thread
From: Abhinav Kumar @ 2023-01-25 23:50 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: freedreno, Loic Poulain, Sean Paul, Bjorn Andersson, dri-devel,
Stephen Boyd, Rob Clark, Daniel Vetter, linux-arm-msm,
David Airlie
On 1/24/2023 10:46 PM, Dmitry Baryshkov wrote:
> Hi,
>
> On Wed, 25 Jan 2023 at 02:22, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>> On 1/24/2023 12:22 AM, Dmitry Baryshkov wrote:
>>> On 24/01/2023 03:32, Abhinav Kumar wrote:
>>>> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
>>>>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
>>>>> rectangles and CSC. Drop corresponding features being incorrectly
>>>>> enabled for qcm2290.
>>>>>
>>>>
>>>> Can you please point me to which vendor DT you are referring to for this?
>>>>
>>>> CSC is supported on the VIG SSPPs from what I can see.
>>>
>>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
>>>
>>>
>>> No CSC, smart-dma, excl-rect, CDP, etc.
>>
>> Sorry I am missing something here.
>>
>> It has one Vig and one DMA
>>
>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L68
>
> Correct
>
>>
>> If Vig is present, CSC is supported.
>
> This actually puzzled me. Usually the dtsi has qcom,sde-sspp-csc-off
> and qcom,sde-csc-type properties. But not in this case.
>
>>
>> Even for smart DMA I can see it supported
>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L76
>> on the DMA SSPP.
>>
>> Same for excl rectangle too
>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L74
>
> Ack, my mistake. Maybe I was looking at the wrong dtsi then (or just
> mixed something). I'll add them back. And I see that CDP is also
> there.
>
> So, this leaves us only with the question regarding CSC. Could you
> please doublecheck it?
>
I went through the internal documents.
This chipset supports only RGB formats for Vig pipe and hence there is
no CSC (surprise for me too).
> I also don't see the UBWC (qcom,sde-ubwc-version) and regdma
> (qcom,sde-reg-dma-off) properties. Are corresponding features present
> on the QCM2290?
>
Yes UBWC is also not supported.
You can now go ahead and update v2.
>>>
>>>> QCM2290 should be using the same MDP version as 6115 from the HW version.
>>>
>>> It is 6.3 vs 6.5 if I remember correctly.
>>>
>>>>
>>>>
>>>>> Cc: Loic Poulain <loic.poulain@linaro.org>
>>>>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
>>>>> 1 file changed, 12 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> index 289fb11f99d1..1c3ffa922794 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> @@ -12,10 +12,14 @@
>>>>> #include "dpu_hw_catalog.h"
>>>>> #include "dpu_kms.h"
>>>>> -#define VIG_MASK \
>>>>> +#define VIG_BASE_MASK \
>>>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>>>> + BIT(DPU_SSPP_TS_PREFILL))
>>>>> +
>>>>> +#define VIG_MASK \
>>>>> + (VIG_BASE_MASK | \
>>>>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
>>>>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
>>>>> + BIT(DPU_SSPP_EXCL_RECT))
>>>>> #define VIG_MSM8998_MASK \
>>>>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>>>>> @@ -29,7 +33,7 @@
>>>>> #define VIG_SM8250_MASK \
>>>>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
>>>>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
>>>>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>>>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>>>> #define DMA_MSM8998_MASK \
>>>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>>>> @@ -50,6 +54,10 @@
>>>>> #define DMA_CURSOR_MSM8998_MASK \
>>>>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>>>>> +#define DMA_QCM2290_MASK \
>>>>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
>>>>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
>>>>> +
>>>>> #define MIXER_MSM8998_MASK \
>>>>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>>>>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
>>>>> static const struct dpu_caps qcm2290_dpu_caps = {
>>>>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>>>> .max_mixer_blendstages = 0x4,
>>>>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
>>>>> - .ubwc_version = DPU_HW_UBWC_VER_20,
>>>>> .has_dim_layer = true,
>>>>> .has_idle_pc = true,
>>>>> .max_linewidth = 2160,
>>>>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
>>>>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>>>>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>>>>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>>>>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>>>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>>>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
>>>>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>>>> };
>>>>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg
>>>>> qcm2290_dpu_cfg = {
>>>>> .intf = qcm2290_intf,
>>>>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
>>>>> .vbif = sdm845_vbif,
>>>>> - .reg_dma_count = 1,
>>>>> - .dma_cfg = &sdm845_regdma,
>>>>> .perf = &qcm2290_perf_data,
>>>>> .mdss_irqs = IRQ_SC7180_MASK,
>>>>> };
>>>
>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Freedreno] [PATCH] drm/msm/dpu: disable features unsupported by QCM2290
@ 2023-01-25 23:50 ` Abhinav Kumar
0 siblings, 0 replies; 12+ messages in thread
From: Abhinav Kumar @ 2023-01-25 23:50 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Loic Poulain, freedreno, Bjorn Andersson, dri-devel,
Stephen Boyd, linux-arm-msm, Sean Paul
On 1/24/2023 10:46 PM, Dmitry Baryshkov wrote:
> Hi,
>
> On Wed, 25 Jan 2023 at 02:22, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>> On 1/24/2023 12:22 AM, Dmitry Baryshkov wrote:
>>> On 24/01/2023 03:32, Abhinav Kumar wrote:
>>>> On 1/22/2023 11:11 PM, Dmitry Baryshkov wrote:
>>>>> QCM2290 doesn't seem to support reg-dma, smart-dma, UBWC, CDP, exclusion
>>>>> rectangles and CSC. Drop corresponding features being incorrectly
>>>>> enabled for qcm2290.
>>>>>
>>>>
>>>> Can you please point me to which vendor DT you are referring to for this?
>>>>
>>>> CSC is supported on the VIG SSPPs from what I can see.
>>>
>>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi
>>>
>>>
>>> No CSC, smart-dma, excl-rect, CDP, etc.
>>
>> Sorry I am missing something here.
>>
>> It has one Vig and one DMA
>>
>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L68
>
> Correct
>
>>
>> If Vig is present, CSC is supported.
>
> This actually puzzled me. Usually the dtsi has qcom,sde-sspp-csc-off
> and qcom,sde-csc-type properties. But not in this case.
>
>>
>> Even for smart DMA I can see it supported
>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L76
>> on the DMA SSPP.
>>
>> Same for excl rectangle too
>> https://github.com/MiCode/kernel_devicetree/blob/psyche-r-oss/qcom/scuba-sde.dtsi#L74
>
> Ack, my mistake. Maybe I was looking at the wrong dtsi then (or just
> mixed something). I'll add them back. And I see that CDP is also
> there.
>
> So, this leaves us only with the question regarding CSC. Could you
> please doublecheck it?
>
I went through the internal documents.
This chipset supports only RGB formats for Vig pipe and hence there is
no CSC (surprise for me too).
> I also don't see the UBWC (qcom,sde-ubwc-version) and regdma
> (qcom,sde-reg-dma-off) properties. Are corresponding features present
> on the QCM2290?
>
Yes UBWC is also not supported.
You can now go ahead and update v2.
>>>
>>>> QCM2290 should be using the same MDP version as 6115 from the HW version.
>>>
>>> It is 6.3 vs 6.5 if I remember correctly.
>>>
>>>>
>>>>
>>>>> Cc: Loic Poulain <loic.poulain@linaro.org>
>>>>> Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++--------
>>>>> 1 file changed, 12 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> index 289fb11f99d1..1c3ffa922794 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>>> @@ -12,10 +12,14 @@
>>>>> #include "dpu_hw_catalog.h"
>>>>> #include "dpu_kms.h"
>>>>> -#define VIG_MASK \
>>>>> +#define VIG_BASE_MASK \
>>>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>>>> + BIT(DPU_SSPP_TS_PREFILL))
>>>>> +
>>>>> +#define VIG_MASK \
>>>>> + (VIG_BASE_MASK | \
>>>>> BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
>>>>> - BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
>>>>> + BIT(DPU_SSPP_EXCL_RECT))
>>>>> #define VIG_MSM8998_MASK \
>>>>> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>>>>> @@ -29,7 +33,7 @@
>>>>> #define VIG_SM8250_MASK \
>>>>> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) |
>>>>> BIT(DPU_SSPP_SCALER_QSEED3LITE))
>>>>> -#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>>>> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
>>>>> #define DMA_MSM8998_MASK \
>>>>> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
>>>>> @@ -50,6 +54,10 @@
>>>>> #define DMA_CURSOR_MSM8998_MASK \
>>>>> (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
>>>>> +#define DMA_QCM2290_MASK \
>>>>> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
>>>>> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1))
>>>>> +
>>>>> #define MIXER_MSM8998_MASK \
>>>>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>>>>> @@ -316,8 +324,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
>>>>> static const struct dpu_caps qcm2290_dpu_caps = {
>>>>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>>>>> .max_mixer_blendstages = 0x4,
>>>>> - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
>>>>> - .ubwc_version = DPU_HW_UBWC_VER_20,
>>>>> .has_dim_layer = true,
>>>>> .has_idle_pc = true,
>>>>> .max_linewidth = 2160,
>>>>> @@ -1384,7 +1390,7 @@ static const struct dpu_sspp_sub_blks
>>>>> qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
>>>>> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
>>>>> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
>>>>> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
>>>>> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
>>>>> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_QCM2290_MASK,
>>>>> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
>>>>> };
>>>>> @@ -2836,8 +2842,6 @@ static const struct dpu_mdss_cfg
>>>>> qcm2290_dpu_cfg = {
>>>>> .intf = qcm2290_intf,
>>>>> .vbif_count = ARRAY_SIZE(sdm845_vbif),
>>>>> .vbif = sdm845_vbif,
>>>>> - .reg_dma_count = 1,
>>>>> - .dma_cfg = &sdm845_regdma,
>>>>> .perf = &qcm2290_perf_data,
>>>>> .mdss_irqs = IRQ_SC7180_MASK,
>>>>> };
>>>
>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-01-25 23:50 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-23 7:11 [PATCH] drm/msm/dpu: disable features unsupported by QCM2290 Dmitry Baryshkov
2023-01-23 7:11 ` Dmitry Baryshkov
2023-01-24 1:32 ` Abhinav Kumar
2023-01-24 1:32 ` Abhinav Kumar
2023-01-24 8:22 ` Dmitry Baryshkov
2023-01-24 8:22 ` Dmitry Baryshkov
2023-01-25 0:22 ` Abhinav Kumar
2023-01-25 0:22 ` Abhinav Kumar
2023-01-25 6:46 ` Dmitry Baryshkov
2023-01-25 6:46 ` Dmitry Baryshkov
2023-01-25 23:50 ` [Freedreno] " Abhinav Kumar
2023-01-25 23:50 ` Abhinav Kumar
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