[PATCH v4 00/22] Add driver nodes for MT8192 SoC

[PATCH v4 00/22] Add driver nodes for MT8192 SoC

[Allen-KH Cheng]

Add driver nodes for MT8192 SoC and this series are based on tag: next-20220318, linux-next/master.

The current mmsys dt-binding,
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't define mboxes or mediatek,gce-client-reg.
Need to reference the below link
https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$ 

changes since v3:
- add patch: add the mmsys reset bit to reset the dsi0
- dsi0: use mmsys for reset controller support
- mmc: reorder clocks as specified in the dt-bindings
- vcodec: use ranges for regs of subnodes

changes since v2:
- rebase on next-20220304
- remove power domains controller patch from series (already in linux-next)
- scp: fix indentation
- t-phy: change node name from usb-phy to t-phy and set ranges address
- usb: change node name from xhci to usb and add disabled status
- audsys: syscon: add increasing the address range's length info in commit message
- infracfg_rst: add simple-mfd info in commit message
- nor_flash: add Fixes tag d0a197a0d064a in  commit message
- efuse: use lower case characters
- mmc: use single line for reg
- mipi_tx: change node name from mipi-dphy to dsi-phy, drop clock-names and add disabled status
- m4u and smi: fixing the formatting of the mediatek,larbs properties and remove smi-id property
- H264 venc: fix indentation, remove '0x' prefix for node address
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
  set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
- dpi: add disabled status
- display: appended "mediatek,mt8183-disp-aal" for ccorr
- dsi: fix indentation and add disabled status
- gce info: add drivers' CMDQ support inn commit message
- pwm: add disabled status
- i2c aliases: move the aliases at the board level.

changes since v1:
- add usb-phy node for xhci node
- move infracfg_rst patch in front of PCIe patch
- add display nodes, i2c aliases and pwm node.

Allen-KH Cheng (22):
  arm64: dts: mt8192: Add pwrap node
  arm64: dts: mt8192: Add spmi node
  arm64: dts: mt8192: Add gce node
  arm64: dts: mt8192: Add SCP node
  arm64: dts: mt8192: Add usb-phy node
  arm64: dts: mt8192: Add xhci node
  arm64: dts: mt8192: Add audio-related nodes
  arm64: dts: mt8192: Add infracfg_rst node
  arm64: dts: mt8192: Add PCIe node
  arm64: dts: mt8192: Fix nor_flash status disable typo
  arm64: dts: mt8192: Add efuse node
  arm64: dts: mt8192: Add mmc device nodes
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add m4u and smi nodes
  arm64: dts: mt8192: Add H264 venc device node
  arm64: dts: mt8192: Add vcodec lat and core nodes
  arm64: dts: mt8192: Add dpi node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add gce info for display nodes
  arm64: dts: mt8192: Add pwm node

 arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 783 +++++++++++++++++++++-
 include/dt-bindings/reset/mt8192-resets.h |   3 +
 2 files changed, 775 insertions(+), 11 deletions(-)

-- 
2.18.0

[PATCH v4 00/22] Add driver nodes for MT8192 SoC

[Allen-KH Cheng]

Add driver nodes for MT8192 SoC and this series are based on tag: next-20220318, linux-next/master.

The current mmsys dt-binding,
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't define mboxes or mediatek,gce-client-reg.
Need to reference the below link
https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$ 

changes since v3:
- add patch: add the mmsys reset bit to reset the dsi0
- dsi0: use mmsys for reset controller support
- mmc: reorder clocks as specified in the dt-bindings
- vcodec: use ranges for regs of subnodes

changes since v2:
- rebase on next-20220304
- remove power domains controller patch from series (already in linux-next)
- scp: fix indentation
- t-phy: change node name from usb-phy to t-phy and set ranges address
- usb: change node name from xhci to usb and add disabled status
- audsys: syscon: add increasing the address range's length info in commit message
- infracfg_rst: add simple-mfd info in commit message
- nor_flash: add Fixes tag d0a197a0d064a in  commit message
- efuse: use lower case characters
- mmc: use single line for reg
- mipi_tx: change node name from mipi-dphy to dsi-phy, drop clock-names and add disabled status
- m4u and smi: fixing the formatting of the mediatek,larbs properties and remove smi-id property
- H264 venc: fix indentation, remove '0x' prefix for node address
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
  set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
- dpi: add disabled status
- display: appended "mediatek,mt8183-disp-aal" for ccorr
- dsi: fix indentation and add disabled status
- gce info: add drivers' CMDQ support inn commit message
- pwm: add disabled status
- i2c aliases: move the aliases at the board level.

changes since v1:
- add usb-phy node for xhci node
- move infracfg_rst patch in front of PCIe patch
- add display nodes, i2c aliases and pwm node.

Allen-KH Cheng (22):
  arm64: dts: mt8192: Add pwrap node
  arm64: dts: mt8192: Add spmi node
  arm64: dts: mt8192: Add gce node
  arm64: dts: mt8192: Add SCP node
  arm64: dts: mt8192: Add usb-phy node
  arm64: dts: mt8192: Add xhci node
  arm64: dts: mt8192: Add audio-related nodes
  arm64: dts: mt8192: Add infracfg_rst node
  arm64: dts: mt8192: Add PCIe node
  arm64: dts: mt8192: Fix nor_flash status disable typo
  arm64: dts: mt8192: Add efuse node
  arm64: dts: mt8192: Add mmc device nodes
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add m4u and smi nodes
  arm64: dts: mt8192: Add H264 venc device node
  arm64: dts: mt8192: Add vcodec lat and core nodes
  arm64: dts: mt8192: Add dpi node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add gce info for display nodes
  arm64: dts: mt8192: Add pwm node

 arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 783 +++++++++++++++++++++-
 include/dt-bindings/reset/mt8192-resets.h |   3 +
 2 files changed, 775 insertions(+), 11 deletions(-)

-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 00/22] Add driver nodes for MT8192 SoC

[Allen-KH Cheng]

Add driver nodes for MT8192 SoC and this series are based on tag: next-20220318, linux-next/master.

The current mmsys dt-binding,
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml, doesn't define mboxes or mediatek,gce-client-reg.
Need to reference the below link
https://urldefense.com/v3/__https://lore.kernel.org/all/20220126071932.32615-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zNfQkN-YYjiqPCd5m9DsLhrQDymgEZJoY4oSl24nC3R95P0gIXEmNjyJMhjQZXkWX7mZPa5QS7KIMlGXMbDjDA1_2A$ 

changes since v3:
- add patch: add the mmsys reset bit to reset the dsi0
- dsi0: use mmsys for reset controller support
- mmc: reorder clocks as specified in the dt-bindings
- vcodec: use ranges for regs of subnodes

changes since v2:
- rebase on next-20220304
- remove power domains controller patch from series (already in linux-next)
- scp: fix indentation
- t-phy: change node name from usb-phy to t-phy and set ranges address
- usb: change node name from xhci to usb and add disabled status
- audsys: syscon: add increasing the address range's length info in commit message
- infracfg_rst: add simple-mfd info in commit message
- nor_flash: add Fixes tag d0a197a0d064a in  commit message
- efuse: use lower case characters
- mmc: use single line for reg
- mipi_tx: change node name from mipi-dphy to dsi-phy, drop clock-names and add disabled status
- m4u and smi: fixing the formatting of the mediatek,larbs properties and remove smi-id property
- H264 venc: fix indentation, remove '0x' prefix for node address
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
  set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
- dpi: add disabled status
- display: appended "mediatek,mt8183-disp-aal" for ccorr
- dsi: fix indentation and add disabled status
- gce info: add drivers' CMDQ support inn commit message
- pwm: add disabled status
- i2c aliases: move the aliases at the board level.

changes since v1:
- add usb-phy node for xhci node
- move infracfg_rst patch in front of PCIe patch
- add display nodes, i2c aliases and pwm node.

Allen-KH Cheng (22):
  arm64: dts: mt8192: Add pwrap node
  arm64: dts: mt8192: Add spmi node
  arm64: dts: mt8192: Add gce node
  arm64: dts: mt8192: Add SCP node
  arm64: dts: mt8192: Add usb-phy node
  arm64: dts: mt8192: Add xhci node
  arm64: dts: mt8192: Add audio-related nodes
  arm64: dts: mt8192: Add infracfg_rst node
  arm64: dts: mt8192: Add PCIe node
  arm64: dts: mt8192: Fix nor_flash status disable typo
  arm64: dts: mt8192: Add efuse node
  arm64: dts: mt8192: Add mmc device nodes
  arm64: dts: mt8192: Add mipi_tx node
  arm64: dts: mt8192: Add m4u and smi nodes
  arm64: dts: mt8192: Add H264 venc device node
  arm64: dts: mt8192: Add vcodec lat and core nodes
  arm64: dts: mt8192: Add dpi node
  arm64: dts: mt8192: Add display nodes
  arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0
  arm64: dts: mt8192: Add dsi node
  arm64: dts: mt8192: Add gce info for display nodes
  arm64: dts: mt8192: Add pwm node

 arch/arm64/boot/dts/mediatek/mt8192.dtsi  | 783 +++++++++++++++++++++-
 include/dt-bindings/reset/mt8192-resets.h |   3 +
 2 files changed, 775 insertions(+), 11 deletions(-)

-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node

[Allen-KH Cheng]

Add pwrap node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb294613..76428599444e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
 			clock-names = "clk13m";
 		};
 
+		pwrap: pwrap@10026000 {
+			compatible = "mediatek,mt6873-pwrap";
+			reg = <0 0x10026000 0 0x1000>;
+			reg-names = "pwrap";
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>;
+			clock-names = "spi", "wrap";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0

[PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node

[Allen-KH Cheng]

Add pwrap node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb294613..76428599444e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
 			clock-names = "clk13m";
 		};
 
+		pwrap: pwrap@10026000 {
+			compatible = "mediatek,mt6873-pwrap";
+			reg = <0 0x10026000 0 0x1000>;
+			reg-names = "pwrap";
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>;
+			clock-names = "spi", "wrap";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node

[Allen-KH Cheng]

Add pwrap node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb294613..76428599444e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -523,6 +523,18 @@
 			clock-names = "clk13m";
 		};
 
+		pwrap: pwrap@10026000 {
+			compatible = "mediatek,mt6873-pwrap";
+			reg = <0 0x10026000 0 0x1000>;
+			reg-names = "pwrap";
+			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>;
+			clock-names = "spi", "wrap";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[Allen-KH Cheng]

Add spmi node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 76428599444e..0f9f211ca986 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt6873-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0

[PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[Allen-KH Cheng]

Add spmi node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 76428599444e..0f9f211ca986 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt6873-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[Allen-KH Cheng]

Add spmi node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 76428599444e..0f9f211ca986 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -535,6 +535,23 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt6873-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+				 <&infracfg CLK_INFRA_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Allen-KH Cheng]

Add gce node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 0f9f211ca986..9e1b563bebab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -552,6 +553,15 @@
 			#size-cells = <0>;
 		};
 
+		gce: mailbox@10228000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0

[PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Allen-KH Cheng]

Add gce node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 0f9f211ca986..9e1b563bebab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -552,6 +553,15 @@
 			#size-cells = <0>;
 		};
 
+		gce: mailbox@10228000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Allen-KH Cheng]

Add gce node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 0f9f211ca986..9e1b563bebab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8192-clk.h>
+#include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -552,6 +553,15 @@
 			#size-cells = <0>;
 		};
 
+		gce: mailbox@10228000 {
+			compatible = "mediatek,mt8192-gce";
+			reg = <0 0x10228000 0 0x4000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg CLK_INFRA_GCE>;
+			clock-names = "gce";
+		};
+
 		scp_adsp: clock-controller@10720000 {
 			compatible = "mediatek,mt8192-scp_adsp";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Allen-KH Cheng]

Add SCP node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9e1b563bebab..195d50894df4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
 			status = "disabled";
 		};
 
+		scp: scp@10500000 {
+			compatible = "mediatek,mt8192-scp";
+			reg = <0 0x10500000 0 0x100000>,
+			      <0 0x10700000 0 0x8000>,
+			      <0 0x10720000 0 0xe0000>;
+			reg-names = "sram", "l1tcm", "cfg";
+			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg CLK_INFRA_SCPSYS>;
+			clock-names = "main";
+			status = "disabled";
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0

[PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Allen-KH Cheng]

Add SCP node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9e1b563bebab..195d50894df4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
 			status = "disabled";
 		};
 
+		scp: scp@10500000 {
+			compatible = "mediatek,mt8192-scp";
+			reg = <0 0x10500000 0 0x100000>,
+			      <0 0x10700000 0 0x8000>,
+			      <0 0x10720000 0 0xe0000>;
+			reg-names = "sram", "l1tcm", "cfg";
+			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg CLK_INFRA_SCPSYS>;
+			clock-names = "main";
+			status = "disabled";
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Allen-KH Cheng]

Add SCP node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9e1b563bebab..195d50894df4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -706,6 +706,18 @@
 			status = "disabled";
 		};
 
+		scp: scp@10500000 {
+			compatible = "mediatek,mt8192-scp";
+			reg = <0 0x10500000 0 0x100000>,
+			      <0 0x10700000 0 0x8000>,
+			      <0 0x10720000 0 0xe0000>;
+			reg-names = "sram", "l1tcm", "cfg";
+			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg CLK_INFRA_SCPSYS>;
+			clock-names = "main";
+			status = "disabled";
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


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[PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Allen-KH Cheng]

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 195d50894df4..28b93b76fe17 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -875,6 +875,28 @@
 			#clock-cells = <1>;
 		};
 
+		u3phy0: t-phy@11e40000 {
+			compatible = "mediatek,mt8192-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x11e40000 0x1000>;
+
+			u2port0: usb-phy@0 {
+				reg = <0x0 0x700>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			u3port0: usb-phy@700 {
+				reg = <0x700 0x900>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0

[PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Allen-KH Cheng]

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 195d50894df4..28b93b76fe17 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -875,6 +875,28 @@
 			#clock-cells = <1>;
 		};
 
+		u3phy0: t-phy@11e40000 {
+			compatible = "mediatek,mt8192-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x11e40000 0x1000>;
+
+			u2port0: usb-phy@0 {
+				reg = <0x0 0x700>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			u3port0: usb-phy@700 {
+				reg = <0x700 0x900>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Allen-KH Cheng]

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 195d50894df4..28b93b76fe17 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -875,6 +875,28 @@
 			#clock-cells = <1>;
 		};
 
+		u3phy0: t-phy@11e40000 {
+			compatible = "mediatek,mt8192-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x11e40000 0x1000>;
+
+			u2port0: usb-phy@0 {
+				reg = <0x0 0x700>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			u3port0: usb-phy@700 {
+				reg = <0x700 0x900>;
+				clocks = <&clk26m>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0


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[PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Allen-KH Cheng]

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 28b93b76fe17..6bc36a4076f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
 
 / {
@@ -718,6 +719,29 @@
 			status = "disabled";
 		};
 
+		xhci: usb@11200000 {
+			compatible = "mediatek,mt8192-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x1000>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "host";
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&infracfg CLK_INFRA_SSUSB>,
+				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
+				 <&apmixedsys CLK_APMIXED_USBPLL>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+			status = "disabled";
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0

[PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Allen-KH Cheng]

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 28b93b76fe17..6bc36a4076f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
 
 / {
@@ -718,6 +719,29 @@
 			status = "disabled";
 		};
 
+		xhci: usb@11200000 {
+			compatible = "mediatek,mt8192-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x1000>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "host";
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&infracfg CLK_INFRA_SSUSB>,
+				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
+				 <&apmixedsys CLK_APMIXED_USBPLL>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+			status = "disabled";
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


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[PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Allen-KH Cheng]

Add xhci node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 28b93b76fe17..6bc36a4076f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
 
 / {
@@ -718,6 +719,29 @@
 			status = "disabled";
 		};
 
+		xhci: usb@11200000 {
+			compatible = "mediatek,mt8192-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x1000>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "host";
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&infracfg CLK_INFRA_SSUSB>,
+				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
+				 <&apmixedsys CLK_APMIXED_USBPLL>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+			status = "disabled";
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[Allen-KH Cheng]

Add audio-related nodes in audsys for mt8192 SoC.
 - Move audsys node in ascending order.
 - Increase the address range's length from 0x1000 to 0x2000.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
 1 file changed, 128 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6bc36a4076f4..40cf6dacca3e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -742,6 +742,134 @@
 			status = "disabled";
 		};
 
+		audsys: syscon@11210000 {
+			compatible = "mediatek,mt8192-audsys", "syscon";
+			reg = <0 0x11210000 0 0x2000>;
+			#clock-cells = <1>;
+			afe: mt8192-afe-pcm {
+				compatible = "mediatek,mt8192-audio";
+				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+				resets = <&watchdog 17>;
+				reset-names = "audiosys";
+				mediatek,apmixedsys = <&apmixedsys>;
+				mediatek,infracfg = <&infracfg>;
+				mediatek,topckgen = <&topckgen>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+				clocks = <&audsys CLK_AUD_AFE>,
+					 <&audsys CLK_AUD_DAC>,
+					 <&audsys CLK_AUD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_ADC>,
+					 <&audsys CLK_AUD_ADDA6_ADC>,
+					 <&audsys CLK_AUD_22M>,
+					 <&audsys CLK_AUD_24M>,
+					 <&audsys CLK_AUD_APLL_TUNER>,
+					 <&audsys CLK_AUD_APLL2_TUNER>,
+					 <&audsys CLK_AUD_TDM>,
+					 <&audsys CLK_AUD_TML>,
+					 <&audsys CLK_AUD_NLE>,
+					 <&audsys CLK_AUD_DAC_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES_TML>,
+					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+					 <&audsys CLK_AUD_3RD_DAC>,
+					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_3RD_DAC_TML>,
+					 <&audsys CLK_AUD_3RD_DAC_HIRES>,
+					 <&infracfg CLK_INFRA_AUDIO>,
+					 <&infracfg CLK_INFRA_AUDIO_26M_B>,
+					 <&topckgen CLK_TOP_AUDIO_SEL>,
+					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+					 <&topckgen CLK_TOP_AUD_1_SEL>,
+					 <&topckgen CLK_TOP_APLL1>,
+					 <&topckgen CLK_TOP_AUD_2_SEL>,
+					 <&topckgen CLK_TOP_APLL2>,
+					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+					 <&topckgen CLK_TOP_APLL1_D4>,
+					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+					 <&topckgen CLK_TOP_APLL2_D4>,
+					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+					 <&topckgen CLK_TOP_APLL12_DIV0>,
+					 <&topckgen CLK_TOP_APLL12_DIV1>,
+					 <&topckgen CLK_TOP_APLL12_DIV2>,
+					 <&topckgen CLK_TOP_APLL12_DIV3>,
+					 <&topckgen CLK_TOP_APLL12_DIV4>,
+					 <&topckgen CLK_TOP_APLL12_DIVB>,
+					 <&topckgen CLK_TOP_APLL12_DIV5>,
+					 <&topckgen CLK_TOP_APLL12_DIV6>,
+					 <&topckgen CLK_TOP_APLL12_DIV7>,
+					 <&topckgen CLK_TOP_APLL12_DIV8>,
+					 <&topckgen CLK_TOP_APLL12_DIV9>,
+					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
+					 <&clk26m>;
+				clock-names = "aud_afe_clk",
+					      "aud_dac_clk",
+					      "aud_dac_predis_clk",
+					      "aud_adc_clk",
+					      "aud_adda6_adc_clk",
+					      "aud_apll22m_clk",
+					      "aud_apll24m_clk",
+					      "aud_apll1_tuner_clk",
+					      "aud_apll2_tuner_clk",
+					      "aud_tdm_clk",
+					      "aud_tml_clk",
+					      "aud_nle",
+					      "aud_dac_hires_clk",
+					      "aud_adc_hires_clk",
+					      "aud_adc_hires_tml",
+					      "aud_adda6_adc_hires_clk",
+					      "aud_3rd_dac_clk",
+					      "aud_3rd_dac_predis_clk",
+					      "aud_3rd_dac_tml",
+					      "aud_3rd_dac_hires_clk",
+					      "aud_infra_clk",
+					      "aud_infra_26m_clk",
+					      "top_mux_audio",
+					      "top_mux_audio_int",
+					      "top_mainpll_d4_d4",
+					      "top_mux_aud_1",
+					      "top_apll1_ck",
+					      "top_mux_aud_2",
+					      "top_apll2_ck",
+					      "top_mux_aud_eng1",
+					      "top_apll1_d4",
+					      "top_mux_aud_eng2",
+					      "top_apll2_d4",
+					      "top_i2s0_m_sel",
+					      "top_i2s1_m_sel",
+					      "top_i2s2_m_sel",
+					      "top_i2s3_m_sel",
+					      "top_i2s4_m_sel",
+					      "top_i2s5_m_sel",
+					      "top_i2s6_m_sel",
+					      "top_i2s7_m_sel",
+					      "top_i2s8_m_sel",
+					      "top_i2s9_m_sel",
+					      "top_apll12_div0",
+					      "top_apll12_div1",
+					      "top_apll12_div2",
+					      "top_apll12_div3",
+					      "top_apll12_div4",
+					      "top_apll12_divb",
+					      "top_apll12_div5",
+					      "top_apll12_div6",
+					      "top_apll12_div7",
+					      "top_apll12_div8",
+					      "top_apll12_div9",
+					      "top_mux_audio_h",
+					      "top_clk26m_clk";
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
@@ -757,12 +885,6 @@
 			status = "disable";
 		};
 
-		audsys: clock-controller@11210000 {
-			compatible = "mediatek,mt8192-audsys", "syscon";
-			reg = <0 0x11210000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
-- 
2.18.0

[PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[Allen-KH Cheng]

Add audio-related nodes in audsys for mt8192 SoC.
 - Move audsys node in ascending order.
 - Increase the address range's length from 0x1000 to 0x2000.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
 1 file changed, 128 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6bc36a4076f4..40cf6dacca3e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -742,6 +742,134 @@
 			status = "disabled";
 		};
 
+		audsys: syscon@11210000 {
+			compatible = "mediatek,mt8192-audsys", "syscon";
+			reg = <0 0x11210000 0 0x2000>;
+			#clock-cells = <1>;
+			afe: mt8192-afe-pcm {
+				compatible = "mediatek,mt8192-audio";
+				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+				resets = <&watchdog 17>;
+				reset-names = "audiosys";
+				mediatek,apmixedsys = <&apmixedsys>;
+				mediatek,infracfg = <&infracfg>;
+				mediatek,topckgen = <&topckgen>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+				clocks = <&audsys CLK_AUD_AFE>,
+					 <&audsys CLK_AUD_DAC>,
+					 <&audsys CLK_AUD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_ADC>,
+					 <&audsys CLK_AUD_ADDA6_ADC>,
+					 <&audsys CLK_AUD_22M>,
+					 <&audsys CLK_AUD_24M>,
+					 <&audsys CLK_AUD_APLL_TUNER>,
+					 <&audsys CLK_AUD_APLL2_TUNER>,
+					 <&audsys CLK_AUD_TDM>,
+					 <&audsys CLK_AUD_TML>,
+					 <&audsys CLK_AUD_NLE>,
+					 <&audsys CLK_AUD_DAC_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES_TML>,
+					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+					 <&audsys CLK_AUD_3RD_DAC>,
+					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_3RD_DAC_TML>,
+					 <&audsys CLK_AUD_3RD_DAC_HIRES>,
+					 <&infracfg CLK_INFRA_AUDIO>,
+					 <&infracfg CLK_INFRA_AUDIO_26M_B>,
+					 <&topckgen CLK_TOP_AUDIO_SEL>,
+					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+					 <&topckgen CLK_TOP_AUD_1_SEL>,
+					 <&topckgen CLK_TOP_APLL1>,
+					 <&topckgen CLK_TOP_AUD_2_SEL>,
+					 <&topckgen CLK_TOP_APLL2>,
+					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+					 <&topckgen CLK_TOP_APLL1_D4>,
+					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+					 <&topckgen CLK_TOP_APLL2_D4>,
+					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+					 <&topckgen CLK_TOP_APLL12_DIV0>,
+					 <&topckgen CLK_TOP_APLL12_DIV1>,
+					 <&topckgen CLK_TOP_APLL12_DIV2>,
+					 <&topckgen CLK_TOP_APLL12_DIV3>,
+					 <&topckgen CLK_TOP_APLL12_DIV4>,
+					 <&topckgen CLK_TOP_APLL12_DIVB>,
+					 <&topckgen CLK_TOP_APLL12_DIV5>,
+					 <&topckgen CLK_TOP_APLL12_DIV6>,
+					 <&topckgen CLK_TOP_APLL12_DIV7>,
+					 <&topckgen CLK_TOP_APLL12_DIV8>,
+					 <&topckgen CLK_TOP_APLL12_DIV9>,
+					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
+					 <&clk26m>;
+				clock-names = "aud_afe_clk",
+					      "aud_dac_clk",
+					      "aud_dac_predis_clk",
+					      "aud_adc_clk",
+					      "aud_adda6_adc_clk",
+					      "aud_apll22m_clk",
+					      "aud_apll24m_clk",
+					      "aud_apll1_tuner_clk",
+					      "aud_apll2_tuner_clk",
+					      "aud_tdm_clk",
+					      "aud_tml_clk",
+					      "aud_nle",
+					      "aud_dac_hires_clk",
+					      "aud_adc_hires_clk",
+					      "aud_adc_hires_tml",
+					      "aud_adda6_adc_hires_clk",
+					      "aud_3rd_dac_clk",
+					      "aud_3rd_dac_predis_clk",
+					      "aud_3rd_dac_tml",
+					      "aud_3rd_dac_hires_clk",
+					      "aud_infra_clk",
+					      "aud_infra_26m_clk",
+					      "top_mux_audio",
+					      "top_mux_audio_int",
+					      "top_mainpll_d4_d4",
+					      "top_mux_aud_1",
+					      "top_apll1_ck",
+					      "top_mux_aud_2",
+					      "top_apll2_ck",
+					      "top_mux_aud_eng1",
+					      "top_apll1_d4",
+					      "top_mux_aud_eng2",
+					      "top_apll2_d4",
+					      "top_i2s0_m_sel",
+					      "top_i2s1_m_sel",
+					      "top_i2s2_m_sel",
+					      "top_i2s3_m_sel",
+					      "top_i2s4_m_sel",
+					      "top_i2s5_m_sel",
+					      "top_i2s6_m_sel",
+					      "top_i2s7_m_sel",
+					      "top_i2s8_m_sel",
+					      "top_i2s9_m_sel",
+					      "top_apll12_div0",
+					      "top_apll12_div1",
+					      "top_apll12_div2",
+					      "top_apll12_div3",
+					      "top_apll12_div4",
+					      "top_apll12_divb",
+					      "top_apll12_div5",
+					      "top_apll12_div6",
+					      "top_apll12_div7",
+					      "top_apll12_div8",
+					      "top_apll12_div9",
+					      "top_mux_audio_h",
+					      "top_clk26m_clk";
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
@@ -757,12 +885,6 @@
 			status = "disable";
 		};
 
-		audsys: clock-controller@11210000 {
-			compatible = "mediatek,mt8192-audsys", "syscon";
-			reg = <0 0x11210000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[Allen-KH Cheng]

Add audio-related nodes in audsys for mt8192 SoC.
 - Move audsys node in ascending order.
 - Increase the address range's length from 0x1000 to 0x2000.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
 1 file changed, 128 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6bc36a4076f4..40cf6dacca3e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -742,6 +742,134 @@
 			status = "disabled";
 		};
 
+		audsys: syscon@11210000 {
+			compatible = "mediatek,mt8192-audsys", "syscon";
+			reg = <0 0x11210000 0 0x2000>;
+			#clock-cells = <1>;
+			afe: mt8192-afe-pcm {
+				compatible = "mediatek,mt8192-audio";
+				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+				resets = <&watchdog 17>;
+				reset-names = "audiosys";
+				mediatek,apmixedsys = <&apmixedsys>;
+				mediatek,infracfg = <&infracfg>;
+				mediatek,topckgen = <&topckgen>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+				clocks = <&audsys CLK_AUD_AFE>,
+					 <&audsys CLK_AUD_DAC>,
+					 <&audsys CLK_AUD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_ADC>,
+					 <&audsys CLK_AUD_ADDA6_ADC>,
+					 <&audsys CLK_AUD_22M>,
+					 <&audsys CLK_AUD_24M>,
+					 <&audsys CLK_AUD_APLL_TUNER>,
+					 <&audsys CLK_AUD_APLL2_TUNER>,
+					 <&audsys CLK_AUD_TDM>,
+					 <&audsys CLK_AUD_TML>,
+					 <&audsys CLK_AUD_NLE>,
+					 <&audsys CLK_AUD_DAC_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES_TML>,
+					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+					 <&audsys CLK_AUD_3RD_DAC>,
+					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_3RD_DAC_TML>,
+					 <&audsys CLK_AUD_3RD_DAC_HIRES>,
+					 <&infracfg CLK_INFRA_AUDIO>,
+					 <&infracfg CLK_INFRA_AUDIO_26M_B>,
+					 <&topckgen CLK_TOP_AUDIO_SEL>,
+					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+					 <&topckgen CLK_TOP_AUD_1_SEL>,
+					 <&topckgen CLK_TOP_APLL1>,
+					 <&topckgen CLK_TOP_AUD_2_SEL>,
+					 <&topckgen CLK_TOP_APLL2>,
+					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+					 <&topckgen CLK_TOP_APLL1_D4>,
+					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+					 <&topckgen CLK_TOP_APLL2_D4>,
+					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+					 <&topckgen CLK_TOP_APLL12_DIV0>,
+					 <&topckgen CLK_TOP_APLL12_DIV1>,
+					 <&topckgen CLK_TOP_APLL12_DIV2>,
+					 <&topckgen CLK_TOP_APLL12_DIV3>,
+					 <&topckgen CLK_TOP_APLL12_DIV4>,
+					 <&topckgen CLK_TOP_APLL12_DIVB>,
+					 <&topckgen CLK_TOP_APLL12_DIV5>,
+					 <&topckgen CLK_TOP_APLL12_DIV6>,
+					 <&topckgen CLK_TOP_APLL12_DIV7>,
+					 <&topckgen CLK_TOP_APLL12_DIV8>,
+					 <&topckgen CLK_TOP_APLL12_DIV9>,
+					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
+					 <&clk26m>;
+				clock-names = "aud_afe_clk",
+					      "aud_dac_clk",
+					      "aud_dac_predis_clk",
+					      "aud_adc_clk",
+					      "aud_adda6_adc_clk",
+					      "aud_apll22m_clk",
+					      "aud_apll24m_clk",
+					      "aud_apll1_tuner_clk",
+					      "aud_apll2_tuner_clk",
+					      "aud_tdm_clk",
+					      "aud_tml_clk",
+					      "aud_nle",
+					      "aud_dac_hires_clk",
+					      "aud_adc_hires_clk",
+					      "aud_adc_hires_tml",
+					      "aud_adda6_adc_hires_clk",
+					      "aud_3rd_dac_clk",
+					      "aud_3rd_dac_predis_clk",
+					      "aud_3rd_dac_tml",
+					      "aud_3rd_dac_hires_clk",
+					      "aud_infra_clk",
+					      "aud_infra_26m_clk",
+					      "top_mux_audio",
+					      "top_mux_audio_int",
+					      "top_mainpll_d4_d4",
+					      "top_mux_aud_1",
+					      "top_apll1_ck",
+					      "top_mux_aud_2",
+					      "top_apll2_ck",
+					      "top_mux_aud_eng1",
+					      "top_apll1_d4",
+					      "top_mux_aud_eng2",
+					      "top_apll2_d4",
+					      "top_i2s0_m_sel",
+					      "top_i2s1_m_sel",
+					      "top_i2s2_m_sel",
+					      "top_i2s3_m_sel",
+					      "top_i2s4_m_sel",
+					      "top_i2s5_m_sel",
+					      "top_i2s6_m_sel",
+					      "top_i2s7_m_sel",
+					      "top_i2s8_m_sel",
+					      "top_i2s9_m_sel",
+					      "top_apll12_div0",
+					      "top_apll12_div1",
+					      "top_apll12_div2",
+					      "top_apll12_div3",
+					      "top_apll12_div4",
+					      "top_apll12_divb",
+					      "top_apll12_div5",
+					      "top_apll12_div6",
+					      "top_apll12_div7",
+					      "top_apll12_div8",
+					      "top_apll12_div9",
+					      "top_mux_audio_h",
+					      "top_clk26m_clk";
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
@@ -757,12 +885,6 @@
 			status = "disable";
 		};
 
-		audsys: clock-controller@11210000 {
-			compatible = "mediatek,mt8192-audsys", "syscon";
-			reg = <0 0x11210000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
-- 
2.18.0


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[PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Allen-KH Cheng]

Add infracfg_rst node for mt8192 SoC.
 - Add simple-mfd to allow probing the ti,syscon-reset node.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 40cf6dacca3e..82de1af3f6aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@
 			#clock-cells = <1>;
 		};
 
-		infracfg: syscon@10001000 {
-			compatible = "mediatek,mt8192-infracfg", "syscon";
+		infracfg: infracfg@10001000 {
+			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+
+			infracfg_rst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+
+				ti,reset-bits = <
+					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+				>;
+			};
 		};
 
 		pericfg: syscon@10003000 {
-- 
2.18.0

[PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Allen-KH Cheng]

Add infracfg_rst node for mt8192 SoC.
 - Add simple-mfd to allow probing the ti,syscon-reset node.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 40cf6dacca3e..82de1af3f6aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@
 			#clock-cells = <1>;
 		};
 
-		infracfg: syscon@10001000 {
-			compatible = "mediatek,mt8192-infracfg", "syscon";
+		infracfg: infracfg@10001000 {
+			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+
+			infracfg_rst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+
+				ti,reset-bits = <
+					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+				>;
+			};
 		};
 
 		pericfg: syscon@10003000 {
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Allen-KH Cheng]

Add infracfg_rst node for mt8192 SoC.
 - Add simple-mfd to allow probing the ti,syscon-reset node.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 40cf6dacca3e..82de1af3f6aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	compatible = "mediatek,mt8192";
@@ -267,10 +268,23 @@
 			#clock-cells = <1>;
 		};
 
-		infracfg: syscon@10001000 {
-			compatible = "mediatek,mt8192-infracfg", "syscon";
+		infracfg: infracfg@10001000 {
+			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+
+			infracfg_rst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+
+				ti,reset-bits = <
+					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
+					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
+					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
+					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
+					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
+				>;
+			};
 		};
 
 		pericfg: syscon@10003000 {
-- 
2.18.0


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[PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Allen-KH Cheng]

Add PCIe node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 82de1af3f6aa..3a7f93d8eeaa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -884,6 +884,44 @@
 			};
 		};
 
+		pcie: pcie@11230000 {
+			compatible = "mediatek,mt8192-pcie";
+			device_type = "pci";
+			reg = <0 0x11230000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+				      "obff_ck0", "axi_ck0", "pipe_ck0";
+			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+			resets = <&infracfg_rst 2>,
+				 <&infracfg_rst 3>;
+			reset-names = "phy", "mac";
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0

[PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Allen-KH Cheng]

Add PCIe node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 82de1af3f6aa..3a7f93d8eeaa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -884,6 +884,44 @@
 			};
 		};
 
+		pcie: pcie@11230000 {
+			compatible = "mediatek,mt8192-pcie";
+			device_type = "pci";
+			reg = <0 0x11230000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+				      "obff_ck0", "axi_ck0", "pipe_ck0";
+			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+			resets = <&infracfg_rst 2>,
+				 <&infracfg_rst 3>;
+			reset-names = "phy", "mac";
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


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[PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Allen-KH Cheng]

Add PCIe node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 82de1af3f6aa..3a7f93d8eeaa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -884,6 +884,44 @@
 			};
 		};
 
+		pcie: pcie@11230000 {
+			compatible = "mediatek,mt8192-pcie";
+			device_type = "pci";
+			reg = <0 0x11230000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
+				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
+				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
+			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
+				      "obff_ck0", "axi_ck0", "pipe_ck0";
+			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+			resets = <&infracfg_rst 2>,
+				 <&infracfg_rst 3>;
+			reset-names = "phy", "mac";
+			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: spi@11234000 {
 			compatible = "mediatek,mt8192-nor";
 			reg = <0 0x11234000 0 0xe0>;
-- 
2.18.0


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[PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Allen-KH Cheng]

Correct nor_flash status disable typo of mt8192 SoC.

Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 3a7f93d8eeaa..75c21edccf85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -934,7 +934,7 @@
 			assigned-clock-parents = <&clk26m>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			status = "disable";
+			status = "disabled";
 		};
 
 		i2c3: i2c@11cb0000 {
-- 
2.18.0

[PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Allen-KH Cheng]

Correct nor_flash status disable typo of mt8192 SoC.

Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 3a7f93d8eeaa..75c21edccf85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -934,7 +934,7 @@
 			assigned-clock-parents = <&clk26m>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			status = "disable";
+			status = "disabled";
 		};
 
 		i2c3: i2c@11cb0000 {
-- 
2.18.0


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[PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Allen-KH Cheng]

Correct nor_flash status disable typo of mt8192 SoC.

Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 3a7f93d8eeaa..75c21edccf85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -934,7 +934,7 @@
 			assigned-clock-parents = <&clk26m>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			status = "disable";
+			status = "disabled";
 		};
 
 		i2c3: i2c@11cb0000 {
-- 
2.18.0


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[PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Allen-KH Cheng]

Add efuse node for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 75c21edccf85..6220d6962f58 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -937,6 +937,21 @@
 			status = "disabled";
 		};
 
+		efuse: efuse@11c10000 {
+			compatible = "mediatek,efuse";
+			reg = <0 0x11c10000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			lvts_e_data1: data1@1c0 {
+				reg = <0x1c0 0x58>;
+			};
+
+			svs_calibration: calib@580 {
+				reg = <0x580 0x68>;
+			};
+		};
+
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
-- 
2.18.0

[PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Allen-KH Cheng]

Add efuse node for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 75c21edccf85..6220d6962f58 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -937,6 +937,21 @@
 			status = "disabled";
 		};
 
+		efuse: efuse@11c10000 {
+			compatible = "mediatek,efuse";
+			reg = <0 0x11c10000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			lvts_e_data1: data1@1c0 {
+				reg = <0x1c0 0x58>;
+			};
+
+			svs_calibration: calib@580 {
+				reg = <0x580 0x68>;
+			};
+		};
+
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Allen-KH Cheng]

Add efuse node for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 75c21edccf85..6220d6962f58 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -937,6 +937,21 @@
 			status = "disabled";
 		};
 
+		efuse: efuse@11c10000 {
+			compatible = "mediatek,efuse";
+			reg = <0 0x11c10000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			lvts_e_data1: data1@1c0 {
+				reg = <0x1c0 0x58>;
+			};
+
+			svs_calibration: calib@580 {
+				reg = <0x580 0x68>;
+			};
+		};
+
 		i2c3: i2c@11cb0000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11cb0000 0 0x1000>,
-- 
2.18.0


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[PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Allen-KH Cheng]

Add mmc nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6220d6962f58..2648f2847993 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1150,10 +1150,36 @@
 			#clock-cells = <1>;
 		};
 
-		msdc: clock-controller@11f60000 {
-			compatible = "mediatek,mt8192-msdc";
-			reg = <0 0x11f60000 0 0x1000>;
-			#clock-cells = <1>;
+		mmc0: mmc@11f60000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11f70000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
 		};
 
 		mfgcfg: clock-controller@13fbf000 {
-- 
2.18.0

[PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Allen-KH Cheng]

Add mmc nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6220d6962f58..2648f2847993 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1150,10 +1150,36 @@
 			#clock-cells = <1>;
 		};
 
-		msdc: clock-controller@11f60000 {
-			compatible = "mediatek,mt8192-msdc";
-			reg = <0 0x11f60000 0 0x1000>;
-			#clock-cells = <1>;
+		mmc0: mmc@11f60000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11f70000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
 		};
 
 		mfgcfg: clock-controller@13fbf000 {
-- 
2.18.0


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[PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Allen-KH Cheng]

Add mmc nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6220d6962f58..2648f2847993 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1150,10 +1150,36 @@
 			#clock-cells = <1>;
 		};
 
-		msdc: clock-controller@11f60000 {
-			compatible = "mediatek,mt8192-msdc";
-			reg = <0 0x11f60000 0 0x1000>;
-			#clock-cells = <1>;
+		mmc0: mmc@11f60000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11f70000 {
+			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
+				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+				 <&msdc_top CLK_MSDC_TOP_AXI>,
+				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+			clock-names = "source", "hclk", "source_cg", "sys_cg",
+				      "pclk_cg", "axi_cg", "ahb_cg";
+			status = "disabled";
 		};
 
 		mfgcfg: clock-controller@13fbf000 {
-- 
2.18.0


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[PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[Allen-KH Cheng]

Add mipi_tx node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 2648f2847993..6b769fa5b427 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1110,6 +1110,16 @@
 			};
 		};
 
+		mipi_tx0: dsi-dphy@11e50000 {
+			compatible = "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11e50000 0 0x1000>;
+			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clock-output-names = "mipi_tx0_pll";
+			status = "disabled";
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0

[PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[Allen-KH Cheng]

Add mipi_tx node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 2648f2847993..6b769fa5b427 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1110,6 +1110,16 @@
 			};
 		};
 
+		mipi_tx0: dsi-dphy@11e50000 {
+			compatible = "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11e50000 0 0x1000>;
+			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clock-output-names = "mipi_tx0_pll";
+			status = "disabled";
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0


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[PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[Allen-KH Cheng]

Add mipi_tx node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 2648f2847993..6b769fa5b427 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1110,6 +1110,16 @@
 			};
 		};
 
+		mipi_tx0: dsi-dphy@11e50000 {
+			compatible = "mediatek,mt8183-mipi-tx";
+			reg = <0 0x11e50000 0 0x1000>;
+			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			clock-output-names = "mipi_tx0_pll";
+			status = "disabled";
+		};
+
 		i2c0: i2c@11f00000 {
 			compatible = "mediatek,mt8192-i2c";
 			reg = <0 0x11f00000 0 0x1000>,
-- 
2.18.0


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[PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes

[Allen-KH Cheng]

Add m4u and smi nodes for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b769fa5b427..4addf6ddd86d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
@@ -1204,24 +1205,114 @@
 			#clock-cells = <1>;
 		};
 
+		smi_common: smi@14002000 {
+			compatible = "mediatek,mt8192-smi-common";
+			reg = <0 0x14002000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_SMI_COMMON>,
+				 <&mmsys CLK_MM_SMI_INFRA>,
+				 <&mmsys CLK_MM_SMI_GALS>,
+				 <&mmsys CLK_MM_SMI_GALS>;
+			clock-names = "apb", "smi", "gals0", "gals1";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		larb0: larb@14003000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,larb-id = <0>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		larb1: larb@14004000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,larb-id = <1>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		iommu0: m4u@1401d000 {
+			compatible = "mediatek,mt8192-m4u";
+			reg = <0 0x1401d000 0 0x1000>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+					 <&larb4>, <&larb5>, <&larb7>,
+					 <&larb9>, <&larb11>, <&larb13>,
+					 <&larb14>, <&larb16>, <&larb17>,
+					 <&larb18>, <&larb19>, <&larb20>;
+			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+			clock-names = "bclk";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			#iommu-cells = <1>;
+		};
+
 		imgsys: clock-controller@15020000 {
 			compatible = "mediatek,mt8192-imgsys";
 			reg = <0 0x15020000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb9: larb@1502e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1502e000 0 0x1000>;
+			mediatek,larb-id = <9>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_LARB9>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+		};
+
 		imgsys2: clock-controller@15820000 {
 			compatible = "mediatek,mt8192-imgsys2";
 			reg = <0 0x15820000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb11: larb@1582e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1582e000 0 0x1000>;
+			mediatek,larb-id = <11>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&imgsys2 CLK_IMG2_LARB11>,
+				 <&imgsys2 CLK_IMG2_LARB11>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+		};
+
+		larb5: larb@1600d000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1600d000 0 0x1000>;
+			mediatek,larb-id = <5>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+		};
+
 		vdecsys_soc: clock-controller@1600f000 {
 			compatible = "mediatek,mt8192-vdecsys_soc";
 			reg = <0 0x1600f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb4: larb@1602e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1602e000 0 0x1000>;
+			mediatek,larb-id = <4>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+		};
+
 		vdecsys: clock-controller@1602f000 {
 			compatible = "mediatek,mt8192-vdecsys";
 			reg = <0 0x1602f000 0 0x1000>;
@@ -1234,12 +1325,78 @@
 			#clock-cells = <1>;
 		};
 
+		larb7: larb@17010000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x17010000 0 0x1000>;
+			mediatek,larb-id = <7>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vencsys CLK_VENC_SET0_LARB>,
+				 <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb13: larb@1a001000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a001000 0 0x1000>;
+			mediatek,larb-id = <13>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys CLK_CAM_CAM>,
+				 <&camsys CLK_CAM_LARB13>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+		};
+
+		larb14: larb@1a002000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a002000 0 0x1000>;
+			mediatek,larb-id = <14>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys CLK_CAM_CAM>,
+				 <&camsys CLK_CAM_LARB14>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+		};
+
+		larb16: larb@1a00f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a00f000 0 0x1000>;
+			mediatek,larb-id = <16>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+		};
+
+		larb17: larb@1a010000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a010000 0 0x1000>;
+			mediatek,larb-id = <17>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+		};
+
+		larb18: larb@1a011000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a011000 0 0x1000>;
+			mediatek,larb-id = <18>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+		};
+
 		camsys_rawa: clock-controller@1a04f000 {
 			compatible = "mediatek,mt8192-camsys_rawa";
 			reg = <0 0x1a04f000 0 0x1000>;
@@ -1264,10 +1421,43 @@
 			#clock-cells = <1>;
 		};
 
+		larb20: larb@1b00f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1b00f000 0 0x1000>;
+			mediatek,larb-id = <20>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+				 <&ipesys CLK_IPE_LARB20>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+		};
+
+		larb19: larb@1b10f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1b10f000 0 0x1000>;
+			mediatek,larb-id = <19>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+				 <&ipesys CLK_IPE_LARB19>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+		};
+
 		mdpsys: clock-controller@1f000000 {
 			compatible = "mediatek,mt8192-mdpsys";
 			reg = <0 0x1f000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
+
+		larb2: larb@1f002000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1f002000 0 0x1000>;
+			mediatek,larb-id = <2>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&mdpsys CLK_MDP_SMI0>,
+				 <&mdpsys CLK_MDP_SMI0>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+		};
 	};
 };
-- 
2.18.0

[PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes

[Allen-KH Cheng]

Add m4u and smi nodes for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b769fa5b427..4addf6ddd86d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
@@ -1204,24 +1205,114 @@
 			#clock-cells = <1>;
 		};
 
+		smi_common: smi@14002000 {
+			compatible = "mediatek,mt8192-smi-common";
+			reg = <0 0x14002000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_SMI_COMMON>,
+				 <&mmsys CLK_MM_SMI_INFRA>,
+				 <&mmsys CLK_MM_SMI_GALS>,
+				 <&mmsys CLK_MM_SMI_GALS>;
+			clock-names = "apb", "smi", "gals0", "gals1";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		larb0: larb@14003000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,larb-id = <0>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		larb1: larb@14004000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,larb-id = <1>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		iommu0: m4u@1401d000 {
+			compatible = "mediatek,mt8192-m4u";
+			reg = <0 0x1401d000 0 0x1000>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+					 <&larb4>, <&larb5>, <&larb7>,
+					 <&larb9>, <&larb11>, <&larb13>,
+					 <&larb14>, <&larb16>, <&larb17>,
+					 <&larb18>, <&larb19>, <&larb20>;
+			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+			clock-names = "bclk";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			#iommu-cells = <1>;
+		};
+
 		imgsys: clock-controller@15020000 {
 			compatible = "mediatek,mt8192-imgsys";
 			reg = <0 0x15020000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb9: larb@1502e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1502e000 0 0x1000>;
+			mediatek,larb-id = <9>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_LARB9>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+		};
+
 		imgsys2: clock-controller@15820000 {
 			compatible = "mediatek,mt8192-imgsys2";
 			reg = <0 0x15820000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb11: larb@1582e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1582e000 0 0x1000>;
+			mediatek,larb-id = <11>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&imgsys2 CLK_IMG2_LARB11>,
+				 <&imgsys2 CLK_IMG2_LARB11>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+		};
+
+		larb5: larb@1600d000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1600d000 0 0x1000>;
+			mediatek,larb-id = <5>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+		};
+
 		vdecsys_soc: clock-controller@1600f000 {
 			compatible = "mediatek,mt8192-vdecsys_soc";
 			reg = <0 0x1600f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb4: larb@1602e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1602e000 0 0x1000>;
+			mediatek,larb-id = <4>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+		};
+
 		vdecsys: clock-controller@1602f000 {
 			compatible = "mediatek,mt8192-vdecsys";
 			reg = <0 0x1602f000 0 0x1000>;
@@ -1234,12 +1325,78 @@
 			#clock-cells = <1>;
 		};
 
+		larb7: larb@17010000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x17010000 0 0x1000>;
+			mediatek,larb-id = <7>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vencsys CLK_VENC_SET0_LARB>,
+				 <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb13: larb@1a001000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a001000 0 0x1000>;
+			mediatek,larb-id = <13>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys CLK_CAM_CAM>,
+				 <&camsys CLK_CAM_LARB13>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+		};
+
+		larb14: larb@1a002000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a002000 0 0x1000>;
+			mediatek,larb-id = <14>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys CLK_CAM_CAM>,
+				 <&camsys CLK_CAM_LARB14>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+		};
+
+		larb16: larb@1a00f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a00f000 0 0x1000>;
+			mediatek,larb-id = <16>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+		};
+
+		larb17: larb@1a010000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a010000 0 0x1000>;
+			mediatek,larb-id = <17>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+		};
+
+		larb18: larb@1a011000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a011000 0 0x1000>;
+			mediatek,larb-id = <18>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+		};
+
 		camsys_rawa: clock-controller@1a04f000 {
 			compatible = "mediatek,mt8192-camsys_rawa";
 			reg = <0 0x1a04f000 0 0x1000>;
@@ -1264,10 +1421,43 @@
 			#clock-cells = <1>;
 		};
 
+		larb20: larb@1b00f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1b00f000 0 0x1000>;
+			mediatek,larb-id = <20>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+				 <&ipesys CLK_IPE_LARB20>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+		};
+
+		larb19: larb@1b10f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1b10f000 0 0x1000>;
+			mediatek,larb-id = <19>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+				 <&ipesys CLK_IPE_LARB19>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+		};
+
 		mdpsys: clock-controller@1f000000 {
 			compatible = "mediatek,mt8192-mdpsys";
 			reg = <0 0x1f000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
+
+		larb2: larb@1f002000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1f002000 0 0x1000>;
+			mediatek,larb-id = <2>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&mdpsys CLK_MDP_SMI0>,
+				 <&mdpsys CLK_MDP_SMI0>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+		};
 	};
 };
-- 
2.18.0


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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes

[Allen-KH Cheng]

Add m4u and smi nodes for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b769fa5b427..4addf6ddd86d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gce/mt8192-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
@@ -1204,24 +1205,114 @@
 			#clock-cells = <1>;
 		};
 
+		smi_common: smi@14002000 {
+			compatible = "mediatek,mt8192-smi-common";
+			reg = <0 0x14002000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_SMI_COMMON>,
+				 <&mmsys CLK_MM_SMI_INFRA>,
+				 <&mmsys CLK_MM_SMI_GALS>,
+				 <&mmsys CLK_MM_SMI_GALS>;
+			clock-names = "apb", "smi", "gals0", "gals1";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		larb0: larb@14003000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,larb-id = <0>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		larb1: larb@14004000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,larb-id = <1>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&clk26m>, <&clk26m>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		iommu0: m4u@1401d000 {
+			compatible = "mediatek,mt8192-m4u";
+			reg = <0 0x1401d000 0 0x1000>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+					 <&larb4>, <&larb5>, <&larb7>,
+					 <&larb9>, <&larb11>, <&larb13>,
+					 <&larb14>, <&larb16>, <&larb17>,
+					 <&larb18>, <&larb19>, <&larb20>;
+			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+			clock-names = "bclk";
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			#iommu-cells = <1>;
+		};
+
 		imgsys: clock-controller@15020000 {
 			compatible = "mediatek,mt8192-imgsys";
 			reg = <0 0x15020000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb9: larb@1502e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1502e000 0 0x1000>;
+			mediatek,larb-id = <9>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_LARB9>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+		};
+
 		imgsys2: clock-controller@15820000 {
 			compatible = "mediatek,mt8192-imgsys2";
 			reg = <0 0x15820000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb11: larb@1582e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1582e000 0 0x1000>;
+			mediatek,larb-id = <11>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&imgsys2 CLK_IMG2_LARB11>,
+				 <&imgsys2 CLK_IMG2_LARB11>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+		};
+
+		larb5: larb@1600d000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1600d000 0 0x1000>;
+			mediatek,larb-id = <5>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+		};
+
 		vdecsys_soc: clock-controller@1600f000 {
 			compatible = "mediatek,mt8192-vdecsys_soc";
 			reg = <0 0x1600f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb4: larb@1602e000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1602e000 0 0x1000>;
+			mediatek,larb-id = <4>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+		};
+
 		vdecsys: clock-controller@1602f000 {
 			compatible = "mediatek,mt8192-vdecsys";
 			reg = <0 0x1602f000 0 0x1000>;
@@ -1234,12 +1325,78 @@
 			#clock-cells = <1>;
 		};
 
+		larb7: larb@17010000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x17010000 0 0x1000>;
+			mediatek,larb-id = <7>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&vencsys CLK_VENC_SET0_LARB>,
+				 <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb13: larb@1a001000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a001000 0 0x1000>;
+			mediatek,larb-id = <13>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys CLK_CAM_CAM>,
+				 <&camsys CLK_CAM_LARB13>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+		};
+
+		larb14: larb@1a002000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a002000 0 0x1000>;
+			mediatek,larb-id = <14>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys CLK_CAM_CAM>,
+				 <&camsys CLK_CAM_LARB14>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+		};
+
+		larb16: larb@1a00f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a00f000 0 0x1000>;
+			mediatek,larb-id = <16>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+		};
+
+		larb17: larb@1a010000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a010000 0 0x1000>;
+			mediatek,larb-id = <17>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+		};
+
+		larb18: larb@1a011000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1a011000 0 0x1000>;
+			mediatek,larb-id = <18>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+		};
+
 		camsys_rawa: clock-controller@1a04f000 {
 			compatible = "mediatek,mt8192-camsys_rawa";
 			reg = <0 0x1a04f000 0 0x1000>;
@@ -1264,10 +1421,43 @@
 			#clock-cells = <1>;
 		};
 
+		larb20: larb@1b00f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1b00f000 0 0x1000>;
+			mediatek,larb-id = <20>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+				 <&ipesys CLK_IPE_LARB20>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+		};
+
+		larb19: larb@1b10f000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1b10f000 0 0x1000>;
+			mediatek,larb-id = <19>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+				 <&ipesys CLK_IPE_LARB19>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+		};
+
 		mdpsys: clock-controller@1f000000 {
 			compatible = "mediatek,mt8192-mdpsys";
 			reg = <0 0x1f000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
+
+		larb2: larb@1f002000 {
+			compatible = "mediatek,mt8192-smi-larb";
+			reg = <0 0x1f002000 0 0x1000>;
+			mediatek,larb-id = <2>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&mdpsys CLK_MDP_SMI0>,
+				 <&mdpsys CLK_MDP_SMI0>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+		};
 	};
 };
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node

[Allen-KH Cheng]

Adds H264 venc node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 4addf6ddd86d..63893779b193 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1336,6 +1336,29 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
 		};
 
+		vcodec_enc: vcodec@17020000 {
+			compatible = "mediatek,mt8192-vcodec-enc";
+			reg = <0 0x17020000 0 0x2000>;
+			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+				 <&iommu0 M4U_PORT_L7_VENC_REC>,
+				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,scp = <&scp>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+			clocks = <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "venc-set1";
+			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
-- 
2.18.0

[PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node

[Allen-KH Cheng]

Adds H264 venc node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 4addf6ddd86d..63893779b193 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1336,6 +1336,29 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
 		};
 
+		vcodec_enc: vcodec@17020000 {
+			compatible = "mediatek,mt8192-vcodec-enc";
+			reg = <0 0x17020000 0 0x2000>;
+			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+				 <&iommu0 M4U_PORT_L7_VENC_REC>,
+				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,scp = <&scp>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+			clocks = <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "venc-set1";
+			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node

[Allen-KH Cheng]

Adds H264 venc node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 4addf6ddd86d..63893779b193 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1336,6 +1336,29 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
 		};
 
+		vcodec_enc: vcodec@17020000 {
+			compatible = "mediatek,mt8192-vcodec-enc";
+			reg = <0 0x17020000 0 0x2000>;
+			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+				 <&iommu0 M4U_PORT_L7_VENC_REC>,
+				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,scp = <&scp>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+			clocks = <&vencsys CLK_VENC_SET1_VENC>;
+			clock-names = "venc-set1";
+			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+		};
+
 		camsys: clock-controller@1a000000 {
 			compatible = "mediatek,mt8192-camsys";
 			reg = <0 0x1a000000 0 0x1000>;
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Allen-KH Cheng]

Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 63893779b193..71ad3adeed51 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1285,6 +1285,67 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: vcodec-dec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			vcodec_lat: vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+					      "vdec-vdec", "vdec-top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			vcodec_core: vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+					      "vdec-vdec", "vdec-top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;
-- 
2.18.0

[PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Allen-KH Cheng]

Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 63893779b193..71ad3adeed51 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1285,6 +1285,67 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: vcodec-dec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			vcodec_lat: vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+					      "vdec-vdec", "vdec-top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			vcodec_core: vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+					      "vdec-vdec", "vdec-top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Allen-KH Cheng]

Add vcodec lat and core nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 63893779b193..71ad3adeed51 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1285,6 +1285,67 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
 		};
 
+		vcodec_dec: vcodec-dec@16000000 {
+			compatible = "mediatek,mt8192-vcodec-dec";
+			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
+			mediatek,scp = <&scp>;
+			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0 0 0 0x16000000 0 0x26000>;
+
+			vcodec_lat: vcodec-lat@10000 {
+				compatible = "mediatek,mtk-vcodec-lat";
+				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
+				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+					      "vdec-vdec", "vdec-top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+			};
+
+			vcodec_core: vcodec-core@25000 {
+				compatible = "mediatek,mtk-vcodec-core";
+				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
+				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+					 <&vdecsys CLK_VDEC_VDEC>,
+					 <&vdecsys CLK_VDEC_LAT>,
+					 <&vdecsys CLK_VDEC_LARB1>,
+					 <&topckgen CLK_TOP_MAINPLL_D4>;
+				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+					      "vdec-vdec", "vdec-top";
+				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb5: larb@1600d000 {
 			compatible = "mediatek,mt8192-smi-larb";
 			reg = <0 0x1600d000 0 0x1000>;
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Allen-KH Cheng]

Add dpi node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 71ad3adeed51..a77d405dd508 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1236,6 +1236,17 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		dpi0: dpi@14016000 {
+			compatible = "mediatek,mt8192-dpi";
+			reg = <0 0x14016000 0 0x1000>;
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DPI_DPI0>,
+				 <&mmsys CLK_MM_DISP_DPI0>,
+				 <&apmixedsys CLK_APMIXED_TVDPLL>;
+			clock-names = "pixel", "engine", "pll";
+			status = "disabled";
+		};
+
 		iommu0: m4u@1401d000 {
 			compatible = "mediatek,mt8192-m4u";
 			reg = <0 0x1401d000 0 0x1000>;
-- 
2.18.0

[PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Allen-KH Cheng]

Add dpi node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 71ad3adeed51..a77d405dd508 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1236,6 +1236,17 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		dpi0: dpi@14016000 {
+			compatible = "mediatek,mt8192-dpi";
+			reg = <0 0x14016000 0 0x1000>;
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DPI_DPI0>,
+				 <&mmsys CLK_MM_DISP_DPI0>,
+				 <&apmixedsys CLK_APMIXED_TVDPLL>;
+			clock-names = "pixel", "engine", "pll";
+			status = "disabled";
+		};
+
 		iommu0: m4u@1401d000 {
 			compatible = "mediatek,mt8192-m4u";
 			reg = <0 0x1401d000 0 0x1000>;
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Allen-KH Cheng]

Add dpi node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 71ad3adeed51..a77d405dd508 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1236,6 +1236,17 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		dpi0: dpi@14016000 {
+			compatible = "mediatek,mt8192-dpi";
+			reg = <0 0x14016000 0 0x1000>;
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DPI_DPI0>,
+				 <&mmsys CLK_MM_DISP_DPI0>,
+				 <&apmixedsys CLK_APMIXED_TVDPLL>;
+			clock-names = "pixel", "engine", "pll";
+			status = "disabled";
+		};
+
 		iommu0: m4u@1401d000 {
 			compatible = "mediatek,mt8192-m4u";
 			reg = <0 0x1401d000 0 0x1000>;
-- 
2.18.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Allen-KH Cheng]

Add display nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a77d405dd508..59183fb6c80b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1205,6 +1205,13 @@
 			#clock-cells = <1>;
 		};
 
+		mutex: mutex@14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+		};
+
 		smi_common: smi@14002000 {
 			compatible = "mediatek,mt8192-smi-common";
 			reg = <0 0x14002000 0 0x1000>;
@@ -1236,6 +1243,110 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		ovl0: ovl@14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		ovl_2l0: ovl@14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+		};
+
+		rdma0: rdma@14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,larb = <&larb0>;
+			mediatek,rdma-fifo-size = <5120>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		color0: color@14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+		};
+
+		ccorr0: ccorr@1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+		};
+
+		aal0: aal@1400b000 {
+			compatible = "mediatek,mt8192-disp-aal",
+				     "mediatek,mt8193-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+		};
+
+		gamma0: gamma@1400c000 {
+			compatible = "mediatek,mt8192-disp-gamma",
+				     "mediatek,mt8183-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+		};
+
+		postmask0: postmask@1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+		};
+
+		dither0: dither@1400e000 {
+			compatible = "mediatek,mt8192-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+		};
+
+		ovl_2l2: ovl@14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+		};
+
+		rdma4: rdma@14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			mediatek,rdma-fifo-size = <2048>;
+		};
+
 		dpi0: dpi@14016000 {
 			compatible = "mediatek,mt8192-dpi";
 			reg = <0 0x14016000 0 0x1000>;
-- 
2.18.0

[PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Allen-KH Cheng]

Add display nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a77d405dd508..59183fb6c80b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1205,6 +1205,13 @@
 			#clock-cells = <1>;
 		};
 
+		mutex: mutex@14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+		};
+
 		smi_common: smi@14002000 {
 			compatible = "mediatek,mt8192-smi-common";
 			reg = <0 0x14002000 0 0x1000>;
@@ -1236,6 +1243,110 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		ovl0: ovl@14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		ovl_2l0: ovl@14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+		};
+
+		rdma0: rdma@14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,larb = <&larb0>;
+			mediatek,rdma-fifo-size = <5120>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		color0: color@14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+		};
+
+		ccorr0: ccorr@1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+		};
+
+		aal0: aal@1400b000 {
+			compatible = "mediatek,mt8192-disp-aal",
+				     "mediatek,mt8193-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+		};
+
+		gamma0: gamma@1400c000 {
+			compatible = "mediatek,mt8192-disp-gamma",
+				     "mediatek,mt8183-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+		};
+
+		postmask0: postmask@1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+		};
+
+		dither0: dither@1400e000 {
+			compatible = "mediatek,mt8192-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+		};
+
+		ovl_2l2: ovl@14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+		};
+
+		rdma4: rdma@14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			mediatek,rdma-fifo-size = <2048>;
+		};
+
 		dpi0: dpi@14016000 {
 			compatible = "mediatek,mt8192-dpi";
 			reg = <0 0x14016000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Allen-KH Cheng]

Add display nodes for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a77d405dd508..59183fb6c80b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1205,6 +1205,13 @@
 			#clock-cells = <1>;
 		};
 
+		mutex: mutex@14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+		};
+
 		smi_common: smi@14002000 {
 			compatible = "mediatek,mt8192-smi-common";
 			reg = <0 0x14002000 0 0x1000>;
@@ -1236,6 +1243,110 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 		};
 
+		ovl0: ovl@14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		ovl_2l0: ovl@14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+		};
+
+		rdma0: rdma@14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,larb = <&larb0>;
+			mediatek,rdma-fifo-size = <5120>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+		};
+
+		color0: color@14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+		};
+
+		ccorr0: ccorr@1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+		};
+
+		aal0: aal@1400b000 {
+			compatible = "mediatek,mt8192-disp-aal",
+				     "mediatek,mt8193-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+		};
+
+		gamma0: gamma@1400c000 {
+			compatible = "mediatek,mt8192-disp-gamma",
+				     "mediatek,mt8183-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+		};
+
+		postmask0: postmask@1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+		};
+
+		dither0: dither@1400e000 {
+			compatible = "mediatek,mt8192-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+		};
+
+		ovl_2l2: ovl@14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+		};
+
+		rdma4: rdma@14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			mediatek,rdma-fifo-size = <2048>;
+		};
+
 		dpi0: dpi@14016000 {
 			compatible = "mediatek,mt8192-dpi";
 			reg = <0 0x14016000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Allen-KH Cheng]

Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..764ca9910fa9 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,7 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* MMSYS resets */
+#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0

[PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Allen-KH Cheng]

Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..764ca9910fa9 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,7 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* MMSYS resets */
+#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0


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http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Allen-KH Cheng]

Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 include/dt-bindings/reset/mt8192-resets.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca245b9..764ca9910fa9 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,7 @@
 
 #define MT8192_TOPRGU_SW_RST_NUM				23
 
+/* MMSYS resets */
+#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
+
 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
-- 
2.18.0


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[PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Allen-KH Cheng]

Add dsi ndoe for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 59183fb6c80b..08e0dd2483d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/mt8192-resets.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
@@ -1203,6 +1204,7 @@
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		mutex: mutex@14001000 {
@@ -1327,6 +1329,20 @@
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
 		};
 
+		dsi0: dsi@14010000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14010000 0 0x1000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI_DSI0>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+		};
+
 		ovl_2l2: ovl@14014000 {
 			compatible = "mediatek,mt8192-disp-ovl-2l";
 			reg = <0 0x14014000 0 0x1000>;
-- 
2.18.0

[PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Allen-KH Cheng]

Add dsi ndoe for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 59183fb6c80b..08e0dd2483d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/mt8192-resets.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
@@ -1203,6 +1204,7 @@
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		mutex: mutex@14001000 {
@@ -1327,6 +1329,20 @@
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
 		};
 
+		dsi0: dsi@14010000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14010000 0 0x1000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI_DSI0>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+		};
+
 		ovl_2l2: ovl@14014000 {
 			compatible = "mediatek,mt8192-disp-ovl-2l";
 			reg = <0 0x14014000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Allen-KH Cheng]

Add dsi ndoe for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 59183fb6c80b..08e0dd2483d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/reset/mt8192-resets.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
@@ -1203,6 +1204,7 @@
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		mutex: mutex@14001000 {
@@ -1327,6 +1329,20 @@
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
 		};
 
+		dsi0: dsi@14010000 {
+			compatible = "mediatek,mt8183-dsi";
+			reg = <0 0x14010000 0 0x1000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI_DSI0>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+		};
+
 		ovl_2l2: ovl@14014000 {
 			compatible = "mediatek,mt8192-disp-ovl-2l";
 			reg = <0 0x14014000 0 0x1000>;
-- 
2.18.0


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[PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Allen-KH Cheng]

Add gce info for display nodes
- It's required to get drivers' CMDQ support

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 08e0dd2483d1..f0f0f067c023 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1203,6 +1203,9 @@
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
@@ -1212,6 +1215,8 @@
 			reg = <0 0x14001000 0 0x1000>;
 			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
 		};
 
 		smi_common: smi@14002000 {
@@ -1253,6 +1258,7 @@
 			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
 				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14006000 {
@@ -1263,6 +1269,7 @@
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
 			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
 				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
 		};
 
 		rdma0: rdma@14007000 {
@@ -1274,6 +1281,7 @@
 			mediatek,larb = <&larb0>;
 			mediatek,rdma-fifo-size = <5120>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
 		};
 
 		color0: color@14009000 {
@@ -1283,6 +1291,7 @@
 			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400a000 {
@@ -1291,6 +1300,7 @@
 			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		aal0: aal@1400b000 {
@@ -1300,6 +1310,7 @@
 			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		gamma0: gamma@1400c000 {
@@ -1309,6 +1320,7 @@
 			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		postmask0: postmask@1400d000 {
@@ -1318,6 +1330,7 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
 			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
 		};
 
 		dither0: dither@1400e000 {
@@ -1327,6 +1340,7 @@
 			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		dsi0: dsi@14010000 {
@@ -1351,6 +1365,7 @@
 			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
 			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
 				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
 		};
 
 		rdma4: rdma@14015000 {
@@ -1361,6 +1376,7 @@
 			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
 			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
 			mediatek,rdma-fifo-size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
 		};
 
 		dpi0: dpi@14016000 {
-- 
2.18.0

[PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Allen-KH Cheng]

Add gce info for display nodes
- It's required to get drivers' CMDQ support

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 08e0dd2483d1..f0f0f067c023 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1203,6 +1203,9 @@
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
@@ -1212,6 +1215,8 @@
 			reg = <0 0x14001000 0 0x1000>;
 			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
 		};
 
 		smi_common: smi@14002000 {
@@ -1253,6 +1258,7 @@
 			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
 				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14006000 {
@@ -1263,6 +1269,7 @@
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
 			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
 				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
 		};
 
 		rdma0: rdma@14007000 {
@@ -1274,6 +1281,7 @@
 			mediatek,larb = <&larb0>;
 			mediatek,rdma-fifo-size = <5120>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
 		};
 
 		color0: color@14009000 {
@@ -1283,6 +1291,7 @@
 			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400a000 {
@@ -1291,6 +1300,7 @@
 			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		aal0: aal@1400b000 {
@@ -1300,6 +1310,7 @@
 			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		gamma0: gamma@1400c000 {
@@ -1309,6 +1320,7 @@
 			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		postmask0: postmask@1400d000 {
@@ -1318,6 +1330,7 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
 			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
 		};
 
 		dither0: dither@1400e000 {
@@ -1327,6 +1340,7 @@
 			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		dsi0: dsi@14010000 {
@@ -1351,6 +1365,7 @@
 			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
 			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
 				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
 		};
 
 		rdma4: rdma@14015000 {
@@ -1361,6 +1376,7 @@
 			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
 			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
 			mediatek,rdma-fifo-size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
 		};
 
 		dpi0: dpi@14016000 {
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Allen-KH Cheng]

Add gce info for display nodes
- It's required to get drivers' CMDQ support

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 08e0dd2483d1..f0f0f067c023 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1203,6 +1203,9 @@
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
@@ -1212,6 +1215,8 @@
 			reg = <0 0x14001000 0 0x1000>;
 			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
 		};
 
 		smi_common: smi@14002000 {
@@ -1253,6 +1258,7 @@
 			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
 				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
 		};
 
 		ovl_2l0: ovl@14006000 {
@@ -1263,6 +1269,7 @@
 			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
 			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
 				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
 		};
 
 		rdma0: rdma@14007000 {
@@ -1274,6 +1281,7 @@
 			mediatek,larb = <&larb0>;
 			mediatek,rdma-fifo-size = <5120>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
 		};
 
 		color0: color@14009000 {
@@ -1283,6 +1291,7 @@
 			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
 		};
 
 		ccorr0: ccorr@1400a000 {
@@ -1291,6 +1300,7 @@
 			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
 		};
 
 		aal0: aal@1400b000 {
@@ -1300,6 +1310,7 @@
 			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
 		};
 
 		gamma0: gamma@1400c000 {
@@ -1309,6 +1320,7 @@
 			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
 		};
 
 		postmask0: postmask@1400d000 {
@@ -1318,6 +1330,7 @@
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
 			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
 		};
 
 		dither0: dither@1400e000 {
@@ -1327,6 +1340,7 @@
 			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
 			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
 		};
 
 		dsi0: dsi@14010000 {
@@ -1351,6 +1365,7 @@
 			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
 			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
 				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
 		};
 
 		rdma4: rdma@14015000 {
@@ -1361,6 +1376,7 @@
 			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
 			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
 			mediatek,rdma-fifo-size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
 		};
 
 		dpi0: dpi@14016000 {
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Allen-KH Cheng]

Add pwm node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f0f0f067c023..ea98b2230f18 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -625,6 +625,17 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+				 <&infracfg CLK_INFRA_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8192-spi",
 				     "mediatek,mt6765-spi";
-- 
2.18.0

[PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Allen-KH Cheng]

Add pwm node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f0f0f067c023..ea98b2230f18 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -625,6 +625,17 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+				 <&infracfg CLK_INFRA_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8192-spi",
 				     "mediatek,mt6765-spi";
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Allen-KH Cheng]

Add pwm node for mt8192 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index f0f0f067c023..ea98b2230f18 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -625,6 +625,17 @@
 			status = "disabled";
 		};
 
+		pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
+				 <&infracfg CLK_INFRA_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8192-spi",
 				     "mediatek,mt6765-spi";
-- 
2.18.0


_______________________________________________
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Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Miles Chen]

> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Miles Chen <miles.chen@mediatek.com>

Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Miles Chen]

> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Miles Chen <miles.chen@mediatek.com>

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Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Miles Chen]

> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Miles Chen <miles.chen@mediatek.com>

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 

Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 

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Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 

Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 

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Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 

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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add dpi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 

Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add dpi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 

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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add dpi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 

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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
> 

Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
> 

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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
> 

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Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 

Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 

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Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 

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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 

Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 

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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 

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Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 

Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 

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Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 

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Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 

Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 

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Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 

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Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 

Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 

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Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:34PM +0800, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
>  			status = "disabled";
>  		};
>  
> +		pwm0: pwm@1100e000 {
> +			compatible = "mediatek,mt8183-disp-pwm";
> +			reg = <0 0x1100e000 0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#pwm-cells = <2>;
> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> +				 <&infracfg CLK_INFRA_DISP_PWM>;
> +			clock-names = "main", "mm";
> +			status = "disabled";
> +		};
> +
>  		spi1: spi@11010000 {
>  			compatible = "mediatek,mt8192-spi",
>  				     "mediatek,mt6765-spi";
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:34PM +0800, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
>  			status = "disabled";
>  		};
>  
> +		pwm0: pwm@1100e000 {
> +			compatible = "mediatek,mt8183-disp-pwm";
> +			reg = <0 0x1100e000 0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#pwm-cells = <2>;
> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> +				 <&infracfg CLK_INFRA_DISP_PWM>;
> +			clock-names = "main", "mm";
> +			status = "disabled";
> +		};
> +
>  		spi1: spi@11010000 {
>  			compatible = "mediatek,mt8192-spi",
>  				     "mediatek,mt6765-spi";
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:34PM +0800, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
>  			status = "disabled";
>  		};
>  
> +		pwm0: pwm@1100e000 {
> +			compatible = "mediatek,mt8183-disp-pwm";
> +			reg = <0 0x1100e000 0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#pwm-cells = <2>;
> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> +				 <&infracfg CLK_INFRA_DISP_PWM>;
> +			clock-names = "main", "mm";
> +			status = "disabled";
> +		};
> +
>  		spi1: spi@11010000 {
>  			compatible = "mediatek,mt8192-spi",
>  				     "mediatek,mt6765-spi";
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:17PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 195d50894df4..28b93b76fe17 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,28 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8192-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x11e40000 0x1000>;
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>  		i2c0: i2c@11f00000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11f00000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:17PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 195d50894df4..28b93b76fe17 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,28 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8192-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x11e40000 0x1000>;
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>  		i2c0: i2c@11f00000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11f00000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:17PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 195d50894df4..28b93b76fe17 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,28 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8192-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x11e40000 0x1000>;
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>  		i2c0: i2c@11f00000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11f00000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:18PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 28b93b76fe17..6bc36a4076f4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
>  
>  / {
> @@ -718,6 +719,29 @@
>  			status = "disabled";
>  		};
>  
> +		xhci: usb@11200000 {
> +			compatible = "mediatek,mt8192-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "host";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg CLK_INFRA_SSUSB>,
> +				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
> +				 <&apmixedsys CLK_APMIXED_USBPLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			wakeup-source;
> +			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> +			status = "disabled";
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:18PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 28b93b76fe17..6bc36a4076f4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
>  
>  / {
> @@ -718,6 +719,29 @@
>  			status = "disabled";
>  		};
>  
> +		xhci: usb@11200000 {
> +			compatible = "mediatek,mt8192-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "host";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg CLK_INFRA_SSUSB>,
> +				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
> +				 <&apmixedsys CLK_APMIXED_USBPLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			wakeup-source;
> +			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> +			status = "disabled";
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:18PM +0800, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 28b93b76fe17..6bc36a4076f4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
>  
>  / {
> @@ -718,6 +719,29 @@
>  			status = "disabled";
>  		};
>  
> +		xhci: usb@11200000 {
> +			compatible = "mediatek,mt8192-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "host";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg CLK_INFRA_SSUSB>,
> +				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
> +				 <&apmixedsys CLK_APMIXED_USBPLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			wakeup-source;
> +			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> +			status = "disabled";
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:22PM +0800, Allen-KH Cheng wrote:
> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3a7f93d8eeaa..75c21edccf85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -934,7 +934,7 @@
>  			assigned-clock-parents = <&clk26m>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -			status = "disable";
> +			status = "disabled";
>  		};
>  
>  		i2c3: i2c@11cb0000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:22PM +0800, Allen-KH Cheng wrote:
> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3a7f93d8eeaa..75c21edccf85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -934,7 +934,7 @@
>  			assigned-clock-parents = <&clk26m>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -			status = "disable";
> +			status = "disabled";
>  		};
>  
>  		i2c3: i2c@11cb0000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:22PM +0800, Allen-KH Cheng wrote:
> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3a7f93d8eeaa..75c21edccf85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -934,7 +934,7 @@
>  			assigned-clock-parents = <&clk26m>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> -			status = "disable";
> +			status = "disabled";
>  		};
>  
>  		i2c3: i2c@11cb0000 {
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 2648f2847993..6b769fa5b427 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1110,6 +1110,16 @@
>  			};
>  		};
>  
> +		mipi_tx0: dsi-dphy@11e50000 {

Typo here, should be dsi-phy, not dsi-dphy.

Other than that,

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> +			compatible = "mediatek,mt8183-mipi-tx";
> +			reg = <0 0x11e50000 0 0x1000>;
> +			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> +			#clock-cells = <0>;
> +			#phy-cells = <0>;
> +			clock-output-names = "mipi_tx0_pll";
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@11f00000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11f00000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 2648f2847993..6b769fa5b427 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1110,6 +1110,16 @@
>  			};
>  		};
>  
> +		mipi_tx0: dsi-dphy@11e50000 {

Typo here, should be dsi-phy, not dsi-dphy.

Other than that,

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> +			compatible = "mediatek,mt8183-mipi-tx";
> +			reg = <0 0x11e50000 0 0x1000>;
> +			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> +			#clock-cells = <0>;
> +			#phy-cells = <0>;
> +			clock-output-names = "mipi_tx0_pll";
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@11f00000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11f00000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote:
> Add mipi_tx node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 2648f2847993..6b769fa5b427 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1110,6 +1110,16 @@
>  			};
>  		};
>  
> +		mipi_tx0: dsi-dphy@11e50000 {

Typo here, should be dsi-phy, not dsi-dphy.

Other than that,

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> +			compatible = "mediatek,mt8183-mipi-tx";
> +			reg = <0 0x11e50000 0 0x1000>;
> +			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> +			#clock-cells = <0>;
> +			#phy-cells = <0>;
> +			clock-output-names = "mipi_tx0_pll";
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@11f00000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11f00000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

Hi Allen,

please see my comment below.

On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +		};
> +
>  		smi_common: smi@14002000 {
>  			compatible = "mediatek,mt8192-smi-common";
>  			reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  		};
>  
> +		ovl0: ovl@14005000 {
> +			compatible = "mediatek,mt8192-disp-ovl";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		ovl_2l0: ovl@14006000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14006000 0 0x1000>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +		};
> +
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;
> +			mediatek,rdma-fifo-size = <5120>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		color0: color@14009000 {
> +			compatible = "mediatek,mt8192-disp-color",
> +				     "mediatek,mt8173-disp-color";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +		};
> +
> +		ccorr0: ccorr@1400a000 {
> +			compatible = "mediatek,mt8192-disp-ccorr";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +		};
> +
> +		aal0: aal@1400b000 {
> +			compatible = "mediatek,mt8192-disp-aal",
> +				     "mediatek,mt8193-disp-aal";

Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-aal", otherwise 
the drm driver doesn't even probe. Typos happen, just please make sure you're
testing before sending to the list so these kind of issues can be caught
earlier.

Thanks,
Nícolas

> +			reg = <0 0x1400b000 0 0x1000>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +		};

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

Hi Allen,

please see my comment below.

On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +		};
> +
>  		smi_common: smi@14002000 {
>  			compatible = "mediatek,mt8192-smi-common";
>  			reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  		};
>  
> +		ovl0: ovl@14005000 {
> +			compatible = "mediatek,mt8192-disp-ovl";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		ovl_2l0: ovl@14006000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14006000 0 0x1000>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +		};
> +
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;
> +			mediatek,rdma-fifo-size = <5120>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		color0: color@14009000 {
> +			compatible = "mediatek,mt8192-disp-color",
> +				     "mediatek,mt8173-disp-color";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +		};
> +
> +		ccorr0: ccorr@1400a000 {
> +			compatible = "mediatek,mt8192-disp-ccorr";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +		};
> +
> +		aal0: aal@1400b000 {
> +			compatible = "mediatek,mt8192-disp-aal",
> +				     "mediatek,mt8193-disp-aal";

Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-aal", otherwise 
the drm driver doesn't even probe. Typos happen, just please make sure you're
testing before sending to the list so these kind of issues can be caught
earlier.

Thanks,
Nícolas

> +			reg = <0 0x1400b000 0 0x1000>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +		};

Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

Hi Allen,

please see my comment below.

On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
>  			#clock-cells = <1>;
>  		};
>  
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +		};
> +
>  		smi_common: smi@14002000 {
>  			compatible = "mediatek,mt8192-smi-common";
>  			reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  		};
>  
> +		ovl0: ovl@14005000 {
> +			compatible = "mediatek,mt8192-disp-ovl";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		ovl_2l0: ovl@14006000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14006000 0 0x1000>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +		};
> +
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;
> +			mediatek,rdma-fifo-size = <5120>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		color0: color@14009000 {
> +			compatible = "mediatek,mt8192-disp-color",
> +				     "mediatek,mt8173-disp-color";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +		};
> +
> +		ccorr0: ccorr@1400a000 {
> +			compatible = "mediatek,mt8192-disp-ccorr";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +		};
> +
> +		aal0: aal@1400b000 {
> +			compatible = "mediatek,mt8192-disp-aal",
> +				     "mediatek,mt8193-disp-aal";

Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-aal", otherwise 
the drm driver doesn't even probe. Typos happen, just please make sure you're
testing before sending to the list so these kind of issues can be caught
earlier.

Thanks,
Nícolas

> +			reg = <0 0x1400b000 0 0x1000>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +		};

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Rob Herring]

On Fri, 18 Mar 2022 22:45:31 +0800, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Rob Herring]

On Fri, 18 Mar 2022 22:45:31 +0800, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Rob Herring]

On Fri, 18 Mar 2022 22:45:31 +0800, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>  include/dt-bindings/reset/mt8192-resets.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[allen-kh.cheng]

On Mon, 2022-03-21 at 18:41 -0400, Nícolas F. R. A. Prado wrote:
> On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 2648f2847993..6b769fa5b427 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1110,6 +1110,16 @@
> >  			};
> >  		};
> >  
> > +		mipi_tx0: dsi-dphy@11e50000 {
> 
> Typo here, should be dsi-phy, not dsi-dphy.
> 
> Other than that,
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Hi Nícolas

Thanks for reminding me. 

I will pay attention next time and update in v5.

Best regards,
Allen

> 
> > +			compatible = "mediatek,mt8183-mipi-tx";
> > +			reg = <0 0x11e50000 0 0x1000>;
> > +			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > +			#clock-cells = <0>;
> > +			#phy-cells = <0>;
> > +			clock-output-names = "mipi_tx0_pll";
> > +			status = "disabled";
> > +		};
> > +
> >  		i2c0: i2c@11f00000 {
> >  			compatible = "mediatek,mt8192-i2c";
> >  			reg = <0 0x11f00000 0 0x1000>,
> > -- 
> > 2.18.0
> > 
> > 


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Re: [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node

[allen-kh.cheng]

On Mon, 2022-03-21 at 18:41 -0400, Nícolas F. R. A. Prado wrote:
> On Fri, Mar 18, 2022 at 10:45:25PM +0800, Allen-KH Cheng wrote:
> > Add mipi_tx node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 2648f2847993..6b769fa5b427 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1110,6 +1110,16 @@
> >  			};
> >  		};
> >  
> > +		mipi_tx0: dsi-dphy@11e50000 {
> 
> Typo here, should be dsi-phy, not dsi-dphy.
> 
> Other than that,
> 
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Hi Nícolas

Thanks for reminding me. 

I will pay attention next time and update in v5.

Best regards,
Allen

> 
> > +			compatible = "mediatek,mt8183-mipi-tx";
> > +			reg = <0 0x11e50000 0 0x1000>;
> > +			clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
> > +			#clock-cells = <0>;
> > +			#phy-cells = <0>;
> > +			clock-output-names = "mipi_tx0_pll";
> > +			status = "disabled";
> > +		};
> > +
> >  		i2c0: i2c@11f00000 {
> >  			compatible = "mediatek,mt8192-i2c";
> >  			reg = <0 0x11f00000 0 0x1000>,
> > -- 
> > 2.18.0
> > 
> > 


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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
> 
> please see my comment below.
> 
> On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> > Add display nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111
> > +++++++++++++++++++++++
> >  1 file changed, 111 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a77d405dd508..59183fb6c80b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1205,6 +1205,13 @@
> >  			#clock-cells = <1>;
> >  		};
> >  
> > +		mutex: mutex@14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +		};
> > +
> >  		smi_common: smi@14002000 {
> >  			compatible = "mediatek,mt8192-smi-common";
> >  			reg = <0 0x14002000 0 0x1000>;
> > @@ -1236,6 +1243,110 @@
> >  			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >  		};
> >  
> > +		ovl0: ovl@14005000 {
> > +			compatible = "mediatek,mt8192-disp-ovl";
> > +			reg = <0 0x14005000 0 0x1000>;
> > +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		ovl_2l0: ovl@14006000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14006000 0 0x1000>;
> > +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > +		};
> > +
> > +		rdma0: rdma@14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> > +			mediatek,rdma-fifo-size = <5120>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		color0: color@14009000 {
> > +			compatible = "mediatek,mt8192-disp-color",
> > +				     "mediatek,mt8173-disp-color";
> > +			reg = <0 0x14009000 0 0x1000>;
> > +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +		};
> > +
> > +		ccorr0: ccorr@1400a000 {
> > +			compatible = "mediatek,mt8192-disp-ccorr";
> > +			reg = <0 0x1400a000 0 0x1000>;
> > +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +		};
> > +
> > +		aal0: aal@1400b000 {
> > +			compatible = "mediatek,mt8192-disp-aal",
> > +				     "mediatek,mt8193-disp-aal";
> 
> Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-
> aal", otherwise 
> the drm driver doesn't even probe. Typos happen, just please make
> sure you're
> testing before sending to the list so these kind of issues can be
> caught
> earlier.
> 
> Thanks,
> Nícolas
> 
Hi Nícolas,

Thanks for your kindly reminder.

There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c
(mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal)

In 8192, We should use mediatek,mt8183-disp-aal because of design.

Do I need to add some information for this in mediatek,disp.txt?

Best regards,
Allen

> > +			reg = <0 0x1400b000 0 0x1000>;
> > +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +		};


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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[allen-kh.cheng]

On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
> 
> please see my comment below.
> 
> On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> > Add display nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111
> > +++++++++++++++++++++++
> >  1 file changed, 111 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a77d405dd508..59183fb6c80b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1205,6 +1205,13 @@
> >  			#clock-cells = <1>;
> >  		};
> >  
> > +		mutex: mutex@14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +		};
> > +
> >  		smi_common: smi@14002000 {
> >  			compatible = "mediatek,mt8192-smi-common";
> >  			reg = <0 0x14002000 0 0x1000>;
> > @@ -1236,6 +1243,110 @@
> >  			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >  		};
> >  
> > +		ovl0: ovl@14005000 {
> > +			compatible = "mediatek,mt8192-disp-ovl";
> > +			reg = <0 0x14005000 0 0x1000>;
> > +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		ovl_2l0: ovl@14006000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14006000 0 0x1000>;
> > +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > +		};
> > +
> > +		rdma0: rdma@14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> > +			mediatek,rdma-fifo-size = <5120>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		color0: color@14009000 {
> > +			compatible = "mediatek,mt8192-disp-color",
> > +				     "mediatek,mt8173-disp-color";
> > +			reg = <0 0x14009000 0 0x1000>;
> > +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +		};
> > +
> > +		ccorr0: ccorr@1400a000 {
> > +			compatible = "mediatek,mt8192-disp-ccorr";
> > +			reg = <0 0x1400a000 0 0x1000>;
> > +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +		};
> > +
> > +		aal0: aal@1400b000 {
> > +			compatible = "mediatek,mt8192-disp-aal",
> > +				     "mediatek,mt8193-disp-aal";
> 
> Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-
> aal", otherwise 
> the drm driver doesn't even probe. Typos happen, just please make
> sure you're
> testing before sending to the list so these kind of issues can be
> caught
> earlier.
> 
> Thanks,
> Nícolas
> 
Hi Nícolas,

Thanks for your kindly reminder.

There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c
(mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal)

In 8192, We should use mediatek,mt8183-disp-aal because of design.

Do I need to add some information for this in mediatek,disp.txt?

Best regards,
Allen

> > +			reg = <0 0x1400b000 0 0x1000>;
> > +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +		};


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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Tue, Mar 22, 2022 at 02:15:28PM +0800, allen-kh.cheng wrote:
> On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote:
> > On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> > > +		aal0: aal@1400b000 {
> > > +			compatible = "mediatek,mt8192-disp-aal",
> > > +				     "mediatek,mt8193-disp-aal";
> > 
> > Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-
> > aal", otherwise 
> > the drm driver doesn't even probe. Typos happen, just please make
> > sure you're
> > testing before sending to the list so these kind of issues can be
> > caught
> > earlier.
> > 
> > Thanks,
> > Nícolas
> > 
> Hi Nícolas,
> 
> Thanks for your kindly reminder.
> 
> There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c
> (mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal)
> 
> In 8192, We should use mediatek,mt8183-disp-aal because of design.

If that's the case, then the mediatek,aal.yaml binding should be fixed. As it
currently is, the mt8173 compatible is expected as a fallback for mt8192. [1]

> 
> Do I need to add some information for this in mediatek,disp.txt?

Note that the mediatek,disp.txt binding was split into several yaml bindings.
The binding for this node is now mediatek,aal.yaml and can be seen in Chun-Kuang
Hu's tree [1].

Thanks,
Nícolas

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml?h=mediatek-drm-next

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Tue, Mar 22, 2022 at 02:15:28PM +0800, allen-kh.cheng wrote:
> On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote:
> > On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> > > +		aal0: aal@1400b000 {
> > > +			compatible = "mediatek,mt8192-disp-aal",
> > > +				     "mediatek,mt8193-disp-aal";
> > 
> > Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-
> > aal", otherwise 
> > the drm driver doesn't even probe. Typos happen, just please make
> > sure you're
> > testing before sending to the list so these kind of issues can be
> > caught
> > earlier.
> > 
> > Thanks,
> > Nícolas
> > 
> Hi Nícolas,
> 
> Thanks for your kindly reminder.
> 
> There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c
> (mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal)
> 
> In 8192, We should use mediatek,mt8183-disp-aal because of design.

If that's the case, then the mediatek,aal.yaml binding should be fixed. As it
currently is, the mt8173 compatible is expected as a fallback for mt8192. [1]

> 
> Do I need to add some information for this in mediatek,disp.txt?

Note that the mediatek,disp.txt binding was split into several yaml bindings.
The binding for this node is now mediatek,aal.yaml and can be seen in Chun-Kuang
Hu's tree [1].

Thanks,
Nícolas

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml?h=mediatek-drm-next

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Nícolas F. R. A. Prado]

On Tue, Mar 22, 2022 at 02:15:28PM +0800, allen-kh.cheng wrote:
> On Mon, 2022-03-21 at 19:26 -0400, Nícolas F. R. A. Prado wrote:
> > On Fri, Mar 18, 2022 at 10:45:30PM +0800, Allen-KH Cheng wrote:
> > > +		aal0: aal@1400b000 {
> > > +			compatible = "mediatek,mt8192-disp-aal",
> > > +				     "mediatek,mt8193-disp-aal";
> > 
> > Typo: "mediatek,mt8193-disp-aal" should be "mediatek,mt8173-disp-
> > aal", otherwise 
> > the drm driver doesn't even probe. Typos happen, just please make
> > sure you're
> > testing before sending to the list so these kind of issues can be
> > caught
> > earlier.
> > 
> > Thanks,
> > Nícolas
> > 
> Hi Nícolas,
> 
> Thanks for your kindly reminder.
> 
> There are two compatibles in drivers/gpu/drm/mediatek/mtk_disp_aal.c
> (mediatek,mt8173-disp-aal adn mediatek,mt8183-disp-aal)
> 
> In 8192, We should use mediatek,mt8183-disp-aal because of design.

If that's the case, then the mediatek,aal.yaml binding should be fixed. As it
currently is, the mt8173 compatible is expected as a fallback for mt8192. [1]

> 
> Do I need to add some information for this in mediatek,disp.txt?

Note that the mediatek,disp.txt binding was split into several yaml bindings.
The binding for this node is now mediatek,aal.yaml and can be seen in Chun-Kuang
Hu's tree [1].

Thanks,
Nícolas

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/tree/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml?h=mediatek-drm-next

Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:24PM +0800, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6220d6962f58..2648f2847993 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1150,10 +1150,36 @@
>  			#clock-cells = <1>;
>  		};
>  
> -		msdc: clock-controller@11f60000 {
> -			compatible = "mediatek,mt8192-msdc";
> -			reg = <0 0x11f60000 0 0x1000>;
> -			#clock-cells = <1>;
> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
>  		};
>  
>  		mfgcfg: clock-controller@13fbf000 {
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:24PM +0800, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6220d6962f58..2648f2847993 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1150,10 +1150,36 @@
>  			#clock-cells = <1>;
>  		};
>  
> -		msdc: clock-controller@11f60000 {
> -			compatible = "mediatek,mt8192-msdc";
> -			reg = <0 0x11f60000 0 0x1000>;
> -			#clock-cells = <1>;
> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
>  		};
>  
>  		mfgcfg: clock-controller@13fbf000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:24PM +0800, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6220d6962f58..2648f2847993 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1150,10 +1150,36 @@
>  			#clock-cells = <1>;
>  		};
>  
> -		msdc: clock-controller@11f60000 {
> -			compatible = "mediatek,mt8192-msdc";
> -			reg = <0 0x11f60000 0 0x1000>;
> -			#clock-cells = <1>;
> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
>  		};
>  
>  		mfgcfg: clock-controller@13fbf000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:23PM +0800, Allen-KH Cheng wrote:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 75c21edccf85..6220d6962f58 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -937,6 +937,21 @@
>  			status = "disabled";
>  		};
>  
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			lvts_e_data1: data1@1c0 {
> +				reg = <0x1c0 0x58>;
> +			};
> +
> +			svs_calibration: calib@580 {
> +				reg = <0x580 0x68>;
> +			};
> +		};
> +
>  		i2c3: i2c@11cb0000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11cb0000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:23PM +0800, Allen-KH Cheng wrote:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 75c21edccf85..6220d6962f58 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -937,6 +937,21 @@
>  			status = "disabled";
>  		};
>  
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			lvts_e_data1: data1@1c0 {
> +				reg = <0x1c0 0x58>;
> +			};
> +
> +			svs_calibration: calib@580 {
> +				reg = <0x580 0x68>;
> +			};
> +		};
> +
>  		i2c3: i2c@11cb0000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11cb0000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:23PM +0800, Allen-KH Cheng wrote:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 75c21edccf85..6220d6962f58 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -937,6 +937,21 @@
>  			status = "disabled";
>  		};
>  
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			lvts_e_data1: data1@1c0 {
> +				reg = <0x1c0 0x58>;
> +			};
> +
> +			svs_calibration: calib@580 {
> +				reg = <0x580 0x68>;
> +			};
> +		};
> +
>  		i2c3: i2c@11cb0000 {
>  			compatible = "mediatek,mt8192-i2c";
>  			reg = <0 0x11cb0000 0 0x1000>,
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:32PM +0800, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.

Minor typo: ndoe -> node.

> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 59183fb6c80b..08e0dd2483d1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -13,6 +13,7 @@
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>  #include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
> @@ -1203,6 +1204,7 @@
>  			compatible = "mediatek,mt8192-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
>  			#clock-cells = <1>;
> +			#reset-cells = <1>;
>  		};
>  
>  		mutex: mutex@14001000 {
> @@ -1327,6 +1329,20 @@
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>  		};
>  
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";
> +		};
> +
>  		ovl_2l2: ovl@14014000 {
>  			compatible = "mediatek,mt8192-disp-ovl-2l";
>  			reg = <0 0x14014000 0 0x1000>;
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:32PM +0800, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.

Minor typo: ndoe -> node.

> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 59183fb6c80b..08e0dd2483d1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -13,6 +13,7 @@
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>  #include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
> @@ -1203,6 +1204,7 @@
>  			compatible = "mediatek,mt8192-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
>  			#clock-cells = <1>;
> +			#reset-cells = <1>;
>  		};
>  
>  		mutex: mutex@14001000 {
> @@ -1327,6 +1329,20 @@
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>  		};
>  
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";
> +		};
> +
>  		ovl_2l2: ovl@14014000 {
>  			compatible = "mediatek,mt8192-disp-ovl-2l";
>  			reg = <0 0x14014000 0 0x1000>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:32PM +0800, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.

Minor typo: ndoe -> node.

> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 59183fb6c80b..08e0dd2483d1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -13,6 +13,7 @@
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>  #include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
> @@ -1203,6 +1204,7 @@
>  			compatible = "mediatek,mt8192-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
>  			#clock-cells = <1>;
> +			#reset-cells = <1>;
>  		};
>  
>  		mutex: mutex@14001000 {
> @@ -1327,6 +1329,20 @@
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>  		};
>  
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";
> +		};
> +
>  		ovl_2l2: ovl@14014000 {
>  			compatible = "mediatek,mt8192-disp-ovl-2l";
>  			reg = <0 0x14014000 0 0x1000>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:31PM +0800, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  include/dt-bindings/reset/mt8192-resets.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>  
>  #define MT8192_TOPRGU_SW_RST_NUM				23
>  
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:31PM +0800, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  include/dt-bindings/reset/mt8192-resets.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>  
>  #define MT8192_TOPRGU_SW_RST_NUM				23
>  
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:31PM +0800, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  include/dt-bindings/reset/mt8192-resets.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>  
>  #define MT8192_TOPRGU_SW_RST_NUM				23
>  
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:16PM +0800, Allen-KH Cheng wrote:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9e1b563bebab..195d50894df4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
>  			status = "disabled";
>  		};
>  
> +		scp: scp@10500000 {
> +			compatible = "mediatek,mt8192-scp";
> +			reg = <0 0x10500000 0 0x100000>,
> +			      <0 0x10700000 0 0x8000>,
> +			      <0 0x10720000 0 0xe0000>;
> +			reg-names = "sram", "l1tcm", "cfg";
> +			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_SCPSYS>;
> +			clock-names = "main";
> +			status = "disabled";
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:16PM +0800, Allen-KH Cheng wrote:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9e1b563bebab..195d50894df4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
>  			status = "disabled";
>  		};
>  
> +		scp: scp@10500000 {
> +			compatible = "mediatek,mt8192-scp";
> +			reg = <0 0x10500000 0 0x100000>,
> +			      <0 0x10700000 0 0x8000>,
> +			      <0 0x10720000 0 0xe0000>;
> +			reg-names = "sram", "l1tcm", "cfg";
> +			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_SCPSYS>;
> +			clock-names = "main";
> +			status = "disabled";
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:16PM +0800, Allen-KH Cheng wrote:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9e1b563bebab..195d50894df4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
>  			status = "disabled";
>  		};
>  
> +		scp: scp@10500000 {
> +			compatible = "mediatek,mt8192-scp";
> +			reg = <0 0x10500000 0 0x100000>,
> +			      <0 0x10700000 0 0x8000>,
> +			      <0 0x10720000 0 0xe0000>;
> +			reg-names = "sram", "l1tcm", "cfg";
> +			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_SCPSYS>;
> +			clock-names = "main";
> +			status = "disabled";
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:33PM +0800, Allen-KH Cheng wrote:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support

It's better to use complete sentences instead of bullet points like this. Also
you could be more descriptive in the commit message. Suggestion:

Add GCE (Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for operating
the display.

> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08e0dd2483d1..f0f0f067c023 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1203,6 +1203,9 @@
>  		mmsys: syscon@14000000 {
>  			compatible = "mediatek,mt8192-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  		};
> @@ -1212,6 +1215,8 @@
>  			reg = <0 0x14001000 0 0x1000>;
>  			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>  			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
>  		};
>  
>  		smi_common: smi@14002000 {
> @@ -1253,6 +1258,7 @@
>  			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>  				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14006000 {
> @@ -1263,6 +1269,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>  			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>  				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
>  		};
>  
>  		rdma0: rdma@14007000 {
> @@ -1274,6 +1281,7 @@
>  			mediatek,larb = <&larb0>;
>  			mediatek,rdma-fifo-size = <5120>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
>  		};
>  
>  		color0: color@14009000 {
> @@ -1283,6 +1291,7 @@
>  			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400a000 {
> @@ -1291,6 +1300,7 @@
>  			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		aal0: aal@1400b000 {
> @@ -1300,6 +1310,7 @@
>  			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		gamma0: gamma@1400c000 {
> @@ -1309,6 +1320,7 @@
>  			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		postmask0: postmask@1400d000 {
> @@ -1318,6 +1330,7 @@
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>  			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>  		};
>  
>  		dither0: dither@1400e000 {
> @@ -1327,6 +1340,7 @@
>  			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		dsi0: dsi@14010000 {
> @@ -1351,6 +1365,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>  			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>  				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>  		};
>  
>  		rdma4: rdma@14015000 {
> @@ -1361,6 +1376,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>  			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>  			mediatek,rdma-fifo-size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>  		};
>  
>  		dpi0: dpi@14016000 {
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:33PM +0800, Allen-KH Cheng wrote:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support

It's better to use complete sentences instead of bullet points like this. Also
you could be more descriptive in the commit message. Suggestion:

Add GCE (Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for operating
the display.

> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08e0dd2483d1..f0f0f067c023 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1203,6 +1203,9 @@
>  		mmsys: syscon@14000000 {
>  			compatible = "mediatek,mt8192-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  		};
> @@ -1212,6 +1215,8 @@
>  			reg = <0 0x14001000 0 0x1000>;
>  			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>  			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
>  		};
>  
>  		smi_common: smi@14002000 {
> @@ -1253,6 +1258,7 @@
>  			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>  				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14006000 {
> @@ -1263,6 +1269,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>  			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>  				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
>  		};
>  
>  		rdma0: rdma@14007000 {
> @@ -1274,6 +1281,7 @@
>  			mediatek,larb = <&larb0>;
>  			mediatek,rdma-fifo-size = <5120>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
>  		};
>  
>  		color0: color@14009000 {
> @@ -1283,6 +1291,7 @@
>  			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400a000 {
> @@ -1291,6 +1300,7 @@
>  			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		aal0: aal@1400b000 {
> @@ -1300,6 +1310,7 @@
>  			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		gamma0: gamma@1400c000 {
> @@ -1309,6 +1320,7 @@
>  			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		postmask0: postmask@1400d000 {
> @@ -1318,6 +1330,7 @@
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>  			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>  		};
>  
>  		dither0: dither@1400e000 {
> @@ -1327,6 +1340,7 @@
>  			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		dsi0: dsi@14010000 {
> @@ -1351,6 +1365,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>  			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>  				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>  		};
>  
>  		rdma4: rdma@14015000 {
> @@ -1361,6 +1376,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>  			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>  			mediatek,rdma-fifo-size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>  		};
>  
>  		dpi0: dpi@14016000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:33PM +0800, Allen-KH Cheng wrote:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support

It's better to use complete sentences instead of bullet points like this. Also
you could be more descriptive in the commit message. Suggestion:

Add GCE (Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for operating
the display.

> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08e0dd2483d1..f0f0f067c023 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1203,6 +1203,9 @@
>  		mmsys: syscon@14000000 {
>  			compatible = "mediatek,mt8192-mmsys", "syscon";
>  			reg = <0 0x14000000 0 0x1000>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  		};
> @@ -1212,6 +1215,8 @@
>  			reg = <0 0x14001000 0 0x1000>;
>  			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>  			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
>  		};
>  
>  		smi_common: smi@14002000 {
> @@ -1253,6 +1258,7 @@
>  			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>  				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
>  		};
>  
>  		ovl_2l0: ovl@14006000 {
> @@ -1263,6 +1269,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>  			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>  				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
>  		};
>  
>  		rdma0: rdma@14007000 {
> @@ -1274,6 +1281,7 @@
>  			mediatek,larb = <&larb0>;
>  			mediatek,rdma-fifo-size = <5120>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
>  		};
>  
>  		color0: color@14009000 {
> @@ -1283,6 +1291,7 @@
>  			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>  		};
>  
>  		ccorr0: ccorr@1400a000 {
> @@ -1291,6 +1300,7 @@
>  			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>  		};
>  
>  		aal0: aal@1400b000 {
> @@ -1300,6 +1310,7 @@
>  			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>  		};
>  
>  		gamma0: gamma@1400c000 {
> @@ -1309,6 +1320,7 @@
>  			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>  		};
>  
>  		postmask0: postmask@1400d000 {
> @@ -1318,6 +1330,7 @@
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>  			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>  		};
>  
>  		dither0: dither@1400e000 {
> @@ -1327,6 +1340,7 @@
>  			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>  			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>  			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>  		};
>  
>  		dsi0: dsi@14010000 {
> @@ -1351,6 +1365,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>  			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>  				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>  		};
>  
>  		rdma4: rdma@14015000 {
> @@ -1361,6 +1376,7 @@
>  			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>  			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>  			mediatek,rdma-fifo-size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>  		};
>  
>  		dpi0: dpi@14016000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Nícolas F. R. A. Prado]

Hi Allen,

please see my comment below.

On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> Add infracfg_rst node for mt8192 SoC.
>  - Add simple-mfd to allow probing the ti,syscon-reset node.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 40cf6dacca3e..82de1af3f6aa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
>  	compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
>  			#clock-cells = <1>;
>  		};
>  
> -		infracfg: syscon@10001000 {
> -			compatible = "mediatek,mt8192-infracfg", "syscon";
> +		infracfg: infracfg@10001000 {
> +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
>  			reg = <0 0x10001000 0 0x1000>;
>  			#clock-cells = <1>;
> +
> +			infracfg_rst: reset-controller {
> +				compatible = "ti,syscon-reset";
> +				#reset-cells = <1>;
> +
> +				ti,reset-bits = <
> +					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> +					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> +					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> +					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> +					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> +				>;

If you see [1], Rob has previously said that there shouldn't be new users of the
ti,reset-bits property. I suggest doing like proposed on [2]: moving these bit
definitions to the reset-ti-syscon driver, and have them selected through the
compatible. You'd need to add a mt8192 specific compatible here too for that.

[1] https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/
[2] https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo+h7cs7kCts3DeKGU5axeX2t+OaJFHyBg@mail.gmail.com/

Thanks,
Nícolas

> +			};
>  		};
>  
>  		pericfg: syscon@10003000 {
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Nícolas F. R. A. Prado]

Hi Allen,

please see my comment below.

On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> Add infracfg_rst node for mt8192 SoC.
>  - Add simple-mfd to allow probing the ti,syscon-reset node.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 40cf6dacca3e..82de1af3f6aa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
>  	compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
>  			#clock-cells = <1>;
>  		};
>  
> -		infracfg: syscon@10001000 {
> -			compatible = "mediatek,mt8192-infracfg", "syscon";
> +		infracfg: infracfg@10001000 {
> +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
>  			reg = <0 0x10001000 0 0x1000>;
>  			#clock-cells = <1>;
> +
> +			infracfg_rst: reset-controller {
> +				compatible = "ti,syscon-reset";
> +				#reset-cells = <1>;
> +
> +				ti,reset-bits = <
> +					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> +					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> +					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> +					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> +					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> +				>;

If you see [1], Rob has previously said that there shouldn't be new users of the
ti,reset-bits property. I suggest doing like proposed on [2]: moving these bit
definitions to the reset-ti-syscon driver, and have them selected through the
compatible. You'd need to add a mt8192 specific compatible here too for that.

[1] https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/
[2] https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo+h7cs7kCts3DeKGU5axeX2t+OaJFHyBg@mail.gmail.com/

Thanks,
Nícolas

> +			};
>  		};
>  
>  		pericfg: syscon@10003000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Nícolas F. R. A. Prado]

Hi Allen,

please see my comment below.

On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> Add infracfg_rst node for mt8192 SoC.
>  - Add simple-mfd to allow probing the ti,syscon-reset node.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
>  1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 40cf6dacca3e..82de1af3f6aa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -12,6 +12,7 @@
>  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>  #include <dt-bindings/phy/phy.h>
>  #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
>  	compatible = "mediatek,mt8192";
> @@ -267,10 +268,23 @@
>  			#clock-cells = <1>;
>  		};
>  
> -		infracfg: syscon@10001000 {
> -			compatible = "mediatek,mt8192-infracfg", "syscon";
> +		infracfg: infracfg@10001000 {
> +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
>  			reg = <0 0x10001000 0 0x1000>;
>  			#clock-cells = <1>;
> +
> +			infracfg_rst: reset-controller {
> +				compatible = "ti,syscon-reset";
> +				#reset-cells = <1>;
> +
> +				ti,reset-bits = <
> +					0x120 0 0x124 0 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> +					0x730 12 0x734 12 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> +					0x140 15 0x144 15 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> +					0x730 1 0x734 1 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> +					0x150 5 0x154 5 0 0	(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> +				>;

If you see [1], Rob has previously said that there shouldn't be new users of the
ti,reset-bits property. I suggest doing like proposed on [2]: moving these bit
definitions to the reset-ti-syscon driver, and have them selected through the
compatible. You'd need to add a mt8192 specific compatible here too for that.

[1] https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/
[2] https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo+h7cs7kCts3DeKGU5axeX2t+OaJFHyBg@mail.gmail.com/

Thanks,
Nícolas

> +			};
>  		};
>  
>  		pericfg: syscon@10003000 {
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:21PM +0800, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
>  			};
>  		};
>  
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> +				      "obff_ck0", "axi_ck0", "pipe_ck0";
> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			resets = <&infracfg_rst 2>,
> +				 <&infracfg_rst 3>;
> +			reset-names = "phy", "mac";
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:21PM +0800, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
>  			};
>  		};
>  
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> +				      "obff_ck0", "axi_ck0", "pipe_ck0";
> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			resets = <&infracfg_rst 2>,
> +				 <&infracfg_rst 3>;
> +			reset-names = "phy", "mac";
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Nícolas F. R. A. Prado]

On Fri, Mar 18, 2022 at 10:45:21PM +0800, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
>  			};
>  		};
>  
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> +				      "obff_ck0", "axi_ck0", "pipe_ck0";
> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			resets = <&infracfg_rst 2>,
> +				 <&infracfg_rst 3>;
> +			reset-names = "phy", "mac";
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>  		nor_flash: spi@11234000 {
>  			compatible = "mediatek,mt8192-nor";
>  			reg = <0 0x11234000 0 0xe0>;
> -- 
> 2.18.0
> 
> 

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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[allen-kh.cheng]

Hi Nícolas,

On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
> 
> please see my comment below.
> 
> On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > Add infracfg_rst node for mt8192 SoC.
> >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> >  1 file changed, 16 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 40cf6dacca3e..82de1af3f6aa 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -12,6 +12,7 @@
> >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> >  #include <dt-bindings/phy/phy.h>
> >  #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >  
> >  / {
> >  	compatible = "mediatek,mt8192";
> > @@ -267,10 +268,23 @@
> >  			#clock-cells = <1>;
> >  		};
> >  
> > -		infracfg: syscon@10001000 {
> > -			compatible = "mediatek,mt8192-infracfg",
> > "syscon";
> > +		infracfg: infracfg@10001000 {
> > +			compatible = "mediatek,mt8192-infracfg",
> > "syscon", "simple-mfd";
> >  			reg = <0 0x10001000 0 0x1000>;
> >  			#clock-cells = <1>;
> > +
> > +			infracfg_rst: reset-controller {
> > +				compatible = "ti,syscon-reset";
> > +				#reset-cells = <1>;
> > +
> > +				ti,reset-bits = <
> > +					0x120 0 0x124 0 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > +					0x730 12 0x734 12 0 0	(AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > +					0x140 15 0x144 15 0 0	(AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > +					0x730 1 0x734 1 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > +					0x150 5 0x154 5 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > +				>;
> 
> If you see [1], Rob has previously said that there shouldn't be new
> users of the
> ti,reset-bits property. I suggest doing like proposed on [2]: moving
> these bit
> definitions to the reset-ti-syscon driver, and have them selected
> through the
> compatible. You'd need to add a mt8192 specific compatible here too
> for that.
> 
> [1] 
> https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
>  
> [2] 
> https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
>  
> 
> Thanks,
> Nícolas
> 

Thanks for your comment.

For nfracfg_rst node, I prefer remove it from this series and
send another patch series(dts and driver).

Based on [2], is it ok that we can add mt8192 compatible in reset-ti
syscon driver? (even if mt8192 is a mediatek platform)

best regards,
Allen

> > +			};
> >  		};
> >  
> >  		pericfg: syscon@10003000 {
> > -- 
> > 2.18.0
> > 
> > 


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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[allen-kh.cheng]

Hi Nícolas,

On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
> 
> please see my comment below.
> 
> On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > Add infracfg_rst node for mt8192 SoC.
> >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> >  1 file changed, 16 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 40cf6dacca3e..82de1af3f6aa 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -12,6 +12,7 @@
> >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> >  #include <dt-bindings/phy/phy.h>
> >  #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >  
> >  / {
> >  	compatible = "mediatek,mt8192";
> > @@ -267,10 +268,23 @@
> >  			#clock-cells = <1>;
> >  		};
> >  
> > -		infracfg: syscon@10001000 {
> > -			compatible = "mediatek,mt8192-infracfg",
> > "syscon";
> > +		infracfg: infracfg@10001000 {
> > +			compatible = "mediatek,mt8192-infracfg",
> > "syscon", "simple-mfd";
> >  			reg = <0 0x10001000 0 0x1000>;
> >  			#clock-cells = <1>;
> > +
> > +			infracfg_rst: reset-controller {
> > +				compatible = "ti,syscon-reset";
> > +				#reset-cells = <1>;
> > +
> > +				ti,reset-bits = <
> > +					0x120 0 0x124 0 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > +					0x730 12 0x734 12 0 0	(AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > +					0x140 15 0x144 15 0 0	(AS
> > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > +					0x730 1 0x734 1 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > +					0x150 5 0x154 5 0 0	(ASSERT_SET
> > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > +				>;
> 
> If you see [1], Rob has previously said that there shouldn't be new
> users of the
> ti,reset-bits property. I suggest doing like proposed on [2]: moving
> these bit
> definitions to the reset-ti-syscon driver, and have them selected
> through the
> compatible. You'd need to add a mt8192 specific compatible here too
> for that.
> 
> [1] 
> https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
>  
> [2] 
> https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
>  
> 
> Thanks,
> Nícolas
> 

Thanks for your comment.

For nfracfg_rst node, I prefer remove it from this series and
send another patch series(dts and driver).

Based on [2], is it ok that we can add mt8192 compatible in reset-ti
syscon driver? (even if mt8192 is a mediatek platform)

best regards,
Allen

> > +			};
> >  		};
> >  
> >  		pericfg: syscon@10003000 {
> > -- 
> > 2.18.0
> > 
> > 


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Re: [PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwrap node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied

Thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 411feb294613..76428599444e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -523,6 +523,18 @@
>   			clock-names = "clk13m";
>   		};
>   
> +		pwrap: pwrap@10026000 {
> +			compatible = "mediatek,mt6873-pwrap";
> +			reg = <0 0x10026000 0 0x1000>;
> +			reg-names = "pwrap";
> +			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> +				 <&infracfg CLK_INFRA_PMIC_TMR>;
> +			clock-names = "spi", "wrap";
> +			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

Re: [PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwrap node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied

Thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 411feb294613..76428599444e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -523,6 +523,18 @@
>   			clock-names = "clk13m";
>   		};
>   
> +		pwrap: pwrap@10026000 {
> +			compatible = "mediatek,mt6873-pwrap";
> +			reg = <0 0x10026000 0 0x1000>;
> +			reg-names = "pwrap";
> +			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> +				 <&infracfg CLK_INFRA_PMIC_TMR>;
> +			clock-names = "spi", "wrap";
> +			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

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Re: [PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwrap node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied

Thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 411feb294613..76428599444e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -523,6 +523,18 @@
>   			clock-names = "clk13m";
>   		};
>   
> +		pwrap: pwrap@10026000 {
> +			compatible = "mediatek,mt6873-pwrap";
> +			reg = <0 0x10026000 0 0x1000>;
> +			reg-names = "pwrap";
> +			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> +				 <&infracfg CLK_INFRA_PMIC_TMR>;
> +			clock-names = "spi", "wrap";
> +			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

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Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 76428599444e..0f9f211ca986 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -535,6 +535,23 @@
>   			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
>   		};
>   
> +		spmi: spmi@10027000 {
> +			compatible = "mediatek,mt6873-spmi";
> +			reg = <0 0x10027000 0 0x000e00>,
> +			      <0 0x10029000 0 0x000100>;
> +			reg-names = "pmif", "spmimst";
> +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> +			clock-names = "pmif_sys_ck",
> +				      "pmif_tmr_ck",
> +				      "spmimst_clk_mux";
> +			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> +			#address-cells = <2>;
> +			#size-cells = <0>;

What do we need the address-cells and size-cells for?

Regards,
Matthias

> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 76428599444e..0f9f211ca986 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -535,6 +535,23 @@
>   			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
>   		};
>   
> +		spmi: spmi@10027000 {
> +			compatible = "mediatek,mt6873-spmi";
> +			reg = <0 0x10027000 0 0x000e00>,
> +			      <0 0x10029000 0 0x000100>;
> +			reg-names = "pmif", "spmimst";
> +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> +			clock-names = "pmif_sys_ck",
> +				      "pmif_tmr_ck",
> +				      "spmimst_clk_mux";
> +			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> +			#address-cells = <2>;
> +			#size-cells = <0>;

What do we need the address-cells and size-cells for?

Regards,
Matthias

> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

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Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add spmi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 76428599444e..0f9f211ca986 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -535,6 +535,23 @@
>   			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
>   		};
>   
> +		spmi: spmi@10027000 {
> +			compatible = "mediatek,mt6873-spmi";
> +			reg = <0 0x10027000 0 0x000e00>,
> +			      <0 0x10029000 0 0x000100>;
> +			reg-names = "pmif", "spmimst";
> +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> +			clock-names = "pmif_sys_ck",
> +				      "pmif_tmr_ck",
> +				      "spmimst_clk_mux";
> +			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
> +			#address-cells = <2>;
> +			#size-cells = <0>;

What do we need the address-cells and size-cells for?

Regards,
Matthias

> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

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Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add gce node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 0f9f211ca986..9e1b563bebab 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -6,6 +6,7 @@
>   
>   /dts-v1/;
>   #include <dt-bindings/clock/mt8192-clk.h>
> +#include <dt-bindings/gce/mt8192-gce.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> @@ -552,6 +553,15 @@
>   			#size-cells = <0>;
>   		};
>   
> +		gce: mailbox@10228000 {
> +			compatible = "mediatek,mt8192-gce";
> +			reg = <0 0x10228000 0 0x4000>;
> +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#mbox-cells = <3>;

#mbox-cells should be 2, right?

Regards,
Matthias

> +			clocks = <&infracfg CLK_INFRA_GCE>;
> +			clock-names = "gce";
> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add gce node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 0f9f211ca986..9e1b563bebab 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -6,6 +6,7 @@
>   
>   /dts-v1/;
>   #include <dt-bindings/clock/mt8192-clk.h>
> +#include <dt-bindings/gce/mt8192-gce.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> @@ -552,6 +553,15 @@
>   			#size-cells = <0>;
>   		};
>   
> +		gce: mailbox@10228000 {
> +			compatible = "mediatek,mt8192-gce";
> +			reg = <0 0x10228000 0 0x4000>;
> +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#mbox-cells = <3>;

#mbox-cells should be 2, right?

Regards,
Matthias

> +			clocks = <&infracfg CLK_INFRA_GCE>;
> +			clock-names = "gce";
> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

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Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add gce node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 0f9f211ca986..9e1b563bebab 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -6,6 +6,7 @@
>   
>   /dts-v1/;
>   #include <dt-bindings/clock/mt8192-clk.h>
> +#include <dt-bindings/gce/mt8192-gce.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> @@ -552,6 +553,15 @@
>   			#size-cells = <0>;
>   		};
>   
> +		gce: mailbox@10228000 {
> +			compatible = "mediatek,mt8192-gce";
> +			reg = <0 0x10228000 0 0x4000>;
> +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#mbox-cells = <3>;

#mbox-cells should be 2, right?

Regards,
Matthias

> +			clocks = <&infracfg CLK_INFRA_GCE>;
> +			clock-names = "gce";
> +		};
> +
>   		scp_adsp: clock-controller@10720000 {
>   			compatible = "mediatek,mt8192-scp_adsp";
>   			reg = <0 0x10720000 0 0x1000>;

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Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9e1b563bebab..195d50894df4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
>   			status = "disabled";
>   		};
>   
> +		scp: scp@10500000 {
> +			compatible = "mediatek,mt8192-scp";
> +			reg = <0 0x10500000 0 0x100000>,
> +			      <0 0x10700000 0 0x8000>,
> +			      <0 0x10720000 0 0xe0000>;
> +			reg-names = "sram", "l1tcm", "cfg";
> +			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_SCPSYS>;
> +			clock-names = "main";
> +			status = "disabled";
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9e1b563bebab..195d50894df4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
>   			status = "disabled";
>   		};
>   
> +		scp: scp@10500000 {
> +			compatible = "mediatek,mt8192-scp";
> +			reg = <0 0x10500000 0 0x100000>,
> +			      <0 0x10700000 0 0x8000>,
> +			      <0 0x10720000 0 0xe0000>;
> +			reg-names = "sram", "l1tcm", "cfg";
> +			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_SCPSYS>;
> +			clock-names = "main";
> +			status = "disabled";
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

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Re: [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add SCP node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9e1b563bebab..195d50894df4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -706,6 +706,18 @@
>   			status = "disabled";
>   		};
>   
> +		scp: scp@10500000 {
> +			compatible = "mediatek,mt8192-scp";
> +			reg = <0 0x10500000 0 0x100000>,
> +			      <0 0x10700000 0 0x8000>,
> +			      <0 0x10720000 0 0xe0000>;
> +			reg-names = "sram", "l1tcm", "cfg";
> +			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&infracfg CLK_INFRA_SCPSYS>;
> +			clock-names = "main";
> +			status = "disabled";
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

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Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 195d50894df4..28b93b76fe17 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,28 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8192-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x11e40000 0x1000>;
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>   		i2c0: i2c@11f00000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11f00000 0 0x1000>,

Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 195d50894df4..28b93b76fe17 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,28 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8192-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x11e40000 0x1000>;
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>   		i2c0: i2c@11f00000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11f00000 0 0x1000>,

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Re: [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 195d50894df4..28b93b76fe17 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -875,6 +875,28 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8192-tphy",
> +				     "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x0 0x11e40000 0x1000>;
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x900>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>   		i2c0: i2c@11f00000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11f00000 0 0x1000>,

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Re: [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 28b93b76fe17..6bc36a4076f4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
>   
>   / {
> @@ -718,6 +719,29 @@
>   			status = "disabled";
>   		};
>   
> +		xhci: usb@11200000 {
> +			compatible = "mediatek,mt8192-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "host";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg CLK_INFRA_SSUSB>,
> +				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
> +				 <&apmixedsys CLK_APMIXED_USBPLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			wakeup-source;
> +			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> +			status = "disabled";
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

Re: [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 28b93b76fe17..6bc36a4076f4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
>   
>   / {
> @@ -718,6 +719,29 @@
>   			status = "disabled";
>   		};
>   
> +		xhci: usb@11200000 {
> +			compatible = "mediatek,mt8192-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "host";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg CLK_INFRA_SSUSB>,
> +				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
> +				 <&apmixedsys CLK_APMIXED_USBPLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			wakeup-source;
> +			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> +			status = "disabled";
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

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Re: [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add xhci node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 28b93b76fe17..6bc36a4076f4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -10,6 +10,7 @@
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> +#include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
>   
>   / {
> @@ -718,6 +719,29 @@
>   			status = "disabled";
>   		};
>   
> +		xhci: usb@11200000 {
> +			compatible = "mediatek,mt8192-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "host";
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg CLK_INFRA_SSUSB>,
> +				 <&infracfg CLK_INFRA_SSUSB_XHCI>,
> +				 <&apmixedsys CLK_APMIXED_USBPLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			wakeup-source;
> +			mediatek,syscon-wakeup = <&pericfg 0x420 102>;
> +			status = "disabled";
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Nícolas F. R. A. Prado]

On Wed, Mar 23, 2022 at 02:27:00PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
> 
> On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> > 
> > please see my comment below.
> > 
> > On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > > Add infracfg_rst node for mt8192 SoC.
> > >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> > >  1 file changed, 16 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 40cf6dacca3e..82de1af3f6aa 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -12,6 +12,7 @@
> > >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > >  #include <dt-bindings/phy/phy.h>
> > >  #include <dt-bindings/power/mt8192-power.h>
> > > +#include <dt-bindings/reset/ti-syscon.h>
> > >  
> > >  / {
> > >  	compatible = "mediatek,mt8192";
> > > @@ -267,10 +268,23 @@
> > >  			#clock-cells = <1>;
> > >  		};
> > >  
> > > -		infracfg: syscon@10001000 {
> > > -			compatible = "mediatek,mt8192-infracfg",
> > > "syscon";
> > > +		infracfg: infracfg@10001000 {
> > > +			compatible = "mediatek,mt8192-infracfg",
> > > "syscon", "simple-mfd";
> > >  			reg = <0 0x10001000 0 0x1000>;
> > >  			#clock-cells = <1>;
> > > +
> > > +			infracfg_rst: reset-controller {
> > > +				compatible = "ti,syscon-reset";
> > > +				#reset-cells = <1>;
> > > +
> > > +				ti,reset-bits = <
> > > +					0x120 0 0x124 0 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > > +					0x730 12 0x734 12 0 0	(AS
> > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > > +					0x140 15 0x144 15 0 0	(AS
> > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > > +					0x730 1 0x734 1 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > > +					0x150 5 0x154 5 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > > +				>;
> > 
> > If you see [1], Rob has previously said that there shouldn't be new
> > users of the
> > ti,reset-bits property. I suggest doing like proposed on [2]: moving
> > these bit
> > definitions to the reset-ti-syscon driver, and have them selected
> > through the
> > compatible. You'd need to add a mt8192 specific compatible here too
> > for that.
> > 
> > [1] 
> > https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
> >  
> > [2] 
> > https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
> >  
> > 
> > Thanks,
> > Nícolas
> > 
> 
> Thanks for your comment.
> 
> For nfracfg_rst node, I prefer remove it from this series and
> send another patch series(dts and driver).

Yes, that sounds the best approach to me as well.

> 
> Based on [2], is it ok that we can add mt8192 compatible in reset-ti
> syscon driver? (even if mt8192 is a mediatek platform)

Actually, I think there's an even better way of handling this. Instead of using
the TI syscon reset controller, you could give reset controller capabilities to
the infracfg node directly. This means adding reset controller support to the
common mtk clock driver (clk-mtk.c) and registering the reset controller on
clk-mt8192.c for infracfg. By making this common code you'll also be able to
reuse it for mt8195 as well. And there would no longer be a infracfg_rst node.

Thanks,
Nícolas

> 
> best regards,
> Allen
> 
> > > +			};
> > >  		};
> > >  
> > >  		pericfg: syscon@10003000 {
> > > -- 
> > > 2.18.0
> > > 
> > > 
> 

Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Nícolas F. R. A. Prado]

On Wed, Mar 23, 2022 at 02:27:00PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
> 
> On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> > 
> > please see my comment below.
> > 
> > On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > > Add infracfg_rst node for mt8192 SoC.
> > >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> > >  1 file changed, 16 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 40cf6dacca3e..82de1af3f6aa 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -12,6 +12,7 @@
> > >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > >  #include <dt-bindings/phy/phy.h>
> > >  #include <dt-bindings/power/mt8192-power.h>
> > > +#include <dt-bindings/reset/ti-syscon.h>
> > >  
> > >  / {
> > >  	compatible = "mediatek,mt8192";
> > > @@ -267,10 +268,23 @@
> > >  			#clock-cells = <1>;
> > >  		};
> > >  
> > > -		infracfg: syscon@10001000 {
> > > -			compatible = "mediatek,mt8192-infracfg",
> > > "syscon";
> > > +		infracfg: infracfg@10001000 {
> > > +			compatible = "mediatek,mt8192-infracfg",
> > > "syscon", "simple-mfd";
> > >  			reg = <0 0x10001000 0 0x1000>;
> > >  			#clock-cells = <1>;
> > > +
> > > +			infracfg_rst: reset-controller {
> > > +				compatible = "ti,syscon-reset";
> > > +				#reset-cells = <1>;
> > > +
> > > +				ti,reset-bits = <
> > > +					0x120 0 0x124 0 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > > +					0x730 12 0x734 12 0 0	(AS
> > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > > +					0x140 15 0x144 15 0 0	(AS
> > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > > +					0x730 1 0x734 1 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > > +					0x150 5 0x154 5 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > > +				>;
> > 
> > If you see [1], Rob has previously said that there shouldn't be new
> > users of the
> > ti,reset-bits property. I suggest doing like proposed on [2]: moving
> > these bit
> > definitions to the reset-ti-syscon driver, and have them selected
> > through the
> > compatible. You'd need to add a mt8192 specific compatible here too
> > for that.
> > 
> > [1] 
> > https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
> >  
> > [2] 
> > https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
> >  
> > 
> > Thanks,
> > Nícolas
> > 
> 
> Thanks for your comment.
> 
> For nfracfg_rst node, I prefer remove it from this series and
> send another patch series(dts and driver).

Yes, that sounds the best approach to me as well.

> 
> Based on [2], is it ok that we can add mt8192 compatible in reset-ti
> syscon driver? (even if mt8192 is a mediatek platform)

Actually, I think there's an even better way of handling this. Instead of using
the TI syscon reset controller, you could give reset controller capabilities to
the infracfg node directly. This means adding reset controller support to the
common mtk clock driver (clk-mtk.c) and registering the reset controller on
clk-mt8192.c for infracfg. By making this common code you'll also be able to
reuse it for mt8195 as well. And there would no longer be a infracfg_rst node.

Thanks,
Nícolas

> 
> best regards,
> Allen
> 
> > > +			};
> > >  		};
> > >  
> > >  		pericfg: syscon@10003000 {
> > > -- 
> > > 2.18.0
> > > 
> > > 
> 

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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[Nícolas F. R. A. Prado]

On Wed, Mar 23, 2022 at 02:27:00PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
> 
> On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> > 
> > please see my comment below.
> > 
> > On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > > Add infracfg_rst node for mt8192 SoC.
> > >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18 ++++++++++++++++--
> > >  1 file changed, 16 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 40cf6dacca3e..82de1af3f6aa 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -12,6 +12,7 @@
> > >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > >  #include <dt-bindings/phy/phy.h>
> > >  #include <dt-bindings/power/mt8192-power.h>
> > > +#include <dt-bindings/reset/ti-syscon.h>
> > >  
> > >  / {
> > >  	compatible = "mediatek,mt8192";
> > > @@ -267,10 +268,23 @@
> > >  			#clock-cells = <1>;
> > >  		};
> > >  
> > > -		infracfg: syscon@10001000 {
> > > -			compatible = "mediatek,mt8192-infracfg",
> > > "syscon";
> > > +		infracfg: infracfg@10001000 {
> > > +			compatible = "mediatek,mt8192-infracfg",
> > > "syscon", "simple-mfd";
> > >  			reg = <0 0x10001000 0 0x1000>;
> > >  			#clock-cells = <1>;
> > > +
> > > +			infracfg_rst: reset-controller {
> > > +				compatible = "ti,syscon-reset";
> > > +				#reset-cells = <1>;
> > > +
> > > +				ti,reset-bits = <
> > > +					0x120 0 0x124 0 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > > +					0x730 12 0x734 12 0 0	(AS
> > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > > +					0x140 15 0x144 15 0 0	(AS
> > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > > +					0x730 1 0x734 1 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > > +					0x150 5 0x154 5 0 0	(ASSERT_SET
> > > | DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > > +				>;
> > 
> > If you see [1], Rob has previously said that there shouldn't be new
> > users of the
> > ti,reset-bits property. I suggest doing like proposed on [2]: moving
> > these bit
> > definitions to the reset-ti-syscon driver, and have them selected
> > through the
> > compatible. You'd need to add a mt8192 specific compatible here too
> > for that.
> > 
> > [1] 
> > https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
> >  
> > [2] 
> > https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
> >  
> > 
> > Thanks,
> > Nícolas
> > 
> 
> Thanks for your comment.
> 
> For nfracfg_rst node, I prefer remove it from this series and
> send another patch series(dts and driver).

Yes, that sounds the best approach to me as well.

> 
> Based on [2], is it ok that we can add mt8192 compatible in reset-ti
> syscon driver? (even if mt8192 is a mediatek platform)

Actually, I think there's an even better way of handling this. Instead of using
the TI syscon reset controller, you could give reset controller capabilities to
the infracfg node directly. This means adding reset controller support to the
common mtk clock driver (clk-mtk.c) and registering the reset controller on
clk-mt8192.c for infracfg. By making this common code you'll also be able to
reuse it for mt8195 as well. And there would no longer be a infracfg_rst node.

Thanks,
Nícolas

> 
> best regards,
> Allen
> 
> > > +			};
> > >  		};
> > >  
> > >  		pericfg: syscon@10003000 {
> > > -- 
> > > 2.18.0
> > > 
> > > 
> 

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Re: [PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
>   - Move audsys node in ascending order.
>   - Increase the address range's length from 0x1000 to 0x2000.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
>   1 file changed, 128 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6bc36a4076f4..40cf6dacca3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -742,6 +742,134 @@
>   			status = "disabled";
>   		};
>   
> +		audsys: syscon@11210000 {
> +			compatible = "mediatek,mt8192-audsys", "syscon";
> +			reg = <0 0x11210000 0 0x2000>;
> +			#clock-cells = <1>;

New line here please.

> +			afe: mt8192-afe-pcm {
> +				compatible = "mediatek,mt8192-audio";
> +				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> +				resets = <&watchdog 17>;
> +				reset-names = "audiosys";
> +				mediatek,apmixedsys = <&apmixedsys>;
> +				mediatek,infracfg = <&infracfg>;
> +				mediatek,topckgen = <&topckgen>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> +				clocks = <&audsys CLK_AUD_AFE>,

There are many more clocks then in the bindings, can please fix that.

Regards,
Matthias

> +					 <&audsys CLK_AUD_DAC>,
> +					 <&audsys CLK_AUD_DAC_PREDIS>,
> +					 <&audsys CLK_AUD_ADC>,
> +					 <&audsys CLK_AUD_ADDA6_ADC>,
> +					 <&audsys CLK_AUD_22M>,
> +					 <&audsys CLK_AUD_24M>,
> +					 <&audsys CLK_AUD_APLL_TUNER>,
> +					 <&audsys CLK_AUD_APLL2_TUNER>,
> +					 <&audsys CLK_AUD_TDM>,
> +					 <&audsys CLK_AUD_TML>,
> +					 <&audsys CLK_AUD_NLE>,
> +					 <&audsys CLK_AUD_DAC_HIRES>,
> +					 <&audsys CLK_AUD_ADC_HIRES>,
> +					 <&audsys CLK_AUD_ADC_HIRES_TML>,
> +					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> +					 <&audsys CLK_AUD_3RD_DAC>,
> +					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> +					 <&audsys CLK_AUD_3RD_DAC_TML>,
> +					 <&audsys CLK_AUD_3RD_DAC_HIRES>,
> +					 <&infracfg CLK_INFRA_AUDIO>,
> +					 <&infracfg CLK_INFRA_AUDIO_26M_B>,
> +					 <&topckgen CLK_TOP_AUDIO_SEL>,
> +					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> +					 <&topckgen CLK_TOP_AUD_1_SEL>,
> +					 <&topckgen CLK_TOP_APLL1>,
> +					 <&topckgen CLK_TOP_AUD_2_SEL>,
> +					 <&topckgen CLK_TOP_APLL2>,
> +					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> +					 <&topckgen CLK_TOP_APLL1_D4>,
> +					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> +					 <&topckgen CLK_TOP_APLL2_D4>,
> +					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL12_DIV0>,
> +					 <&topckgen CLK_TOP_APLL12_DIV1>,
> +					 <&topckgen CLK_TOP_APLL12_DIV2>,
> +					 <&topckgen CLK_TOP_APLL12_DIV3>,
> +					 <&topckgen CLK_TOP_APLL12_DIV4>,
> +					 <&topckgen CLK_TOP_APLL12_DIVB>,
> +					 <&topckgen CLK_TOP_APLL12_DIV5>,
> +					 <&topckgen CLK_TOP_APLL12_DIV6>,
> +					 <&topckgen CLK_TOP_APLL12_DIV7>,
> +					 <&topckgen CLK_TOP_APLL12_DIV8>,
> +					 <&topckgen CLK_TOP_APLL12_DIV9>,
> +					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
> +					 <&clk26m>;
> +				clock-names = "aud_afe_clk",
> +					      "aud_dac_clk",
> +					      "aud_dac_predis_clk",
> +					      "aud_adc_clk",
> +					      "aud_adda6_adc_clk",
> +					      "aud_apll22m_clk",
> +					      "aud_apll24m_clk",
> +					      "aud_apll1_tuner_clk",
> +					      "aud_apll2_tuner_clk",
> +					      "aud_tdm_clk",
> +					      "aud_tml_clk",
> +					      "aud_nle",
> +					      "aud_dac_hires_clk",
> +					      "aud_adc_hires_clk",
> +					      "aud_adc_hires_tml",
> +					      "aud_adda6_adc_hires_clk",
> +					      "aud_3rd_dac_clk",
> +					      "aud_3rd_dac_predis_clk",
> +					      "aud_3rd_dac_tml",
> +					      "aud_3rd_dac_hires_clk",
> +					      "aud_infra_clk",
> +					      "aud_infra_26m_clk",
> +					      "top_mux_audio",
> +					      "top_mux_audio_int",
> +					      "top_mainpll_d4_d4",
> +					      "top_mux_aud_1",
> +					      "top_apll1_ck",
> +					      "top_mux_aud_2",
> +					      "top_apll2_ck",
> +					      "top_mux_aud_eng1",
> +					      "top_apll1_d4",
> +					      "top_mux_aud_eng2",
> +					      "top_apll2_d4",
> +					      "top_i2s0_m_sel",
> +					      "top_i2s1_m_sel",
> +					      "top_i2s2_m_sel",
> +					      "top_i2s3_m_sel",
> +					      "top_i2s4_m_sel",
> +					      "top_i2s5_m_sel",
> +					      "top_i2s6_m_sel",
> +					      "top_i2s7_m_sel",
> +					      "top_i2s8_m_sel",
> +					      "top_i2s9_m_sel",
> +					      "top_apll12_div0",
> +					      "top_apll12_div1",
> +					      "top_apll12_div2",
> +					      "top_apll12_div3",
> +					      "top_apll12_div4",
> +					      "top_apll12_divb",
> +					      "top_apll12_div5",
> +					      "top_apll12_div6",
> +					      "top_apll12_div7",
> +					      "top_apll12_div8",
> +					      "top_apll12_div9",
> +					      "top_mux_audio_h",
> +					      "top_clk26m_clk";
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;
> @@ -757,12 +885,6 @@
>   			status = "disable";
>   		};
>   
> -		audsys: clock-controller@11210000 {
> -			compatible = "mediatek,mt8192-audsys", "syscon";
> -			reg = <0 0x11210000 0 0x1000>;
> -			#clock-cells = <1>;
> -		};
> -
>   		i2c3: i2c@11cb0000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11cb0000 0 0x1000>,

Re: [PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
>   - Move audsys node in ascending order.
>   - Increase the address range's length from 0x1000 to 0x2000.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
>   1 file changed, 128 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6bc36a4076f4..40cf6dacca3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -742,6 +742,134 @@
>   			status = "disabled";
>   		};
>   
> +		audsys: syscon@11210000 {
> +			compatible = "mediatek,mt8192-audsys", "syscon";
> +			reg = <0 0x11210000 0 0x2000>;
> +			#clock-cells = <1>;

New line here please.

> +			afe: mt8192-afe-pcm {
> +				compatible = "mediatek,mt8192-audio";
> +				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> +				resets = <&watchdog 17>;
> +				reset-names = "audiosys";
> +				mediatek,apmixedsys = <&apmixedsys>;
> +				mediatek,infracfg = <&infracfg>;
> +				mediatek,topckgen = <&topckgen>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> +				clocks = <&audsys CLK_AUD_AFE>,

There are many more clocks then in the bindings, can please fix that.

Regards,
Matthias

> +					 <&audsys CLK_AUD_DAC>,
> +					 <&audsys CLK_AUD_DAC_PREDIS>,
> +					 <&audsys CLK_AUD_ADC>,
> +					 <&audsys CLK_AUD_ADDA6_ADC>,
> +					 <&audsys CLK_AUD_22M>,
> +					 <&audsys CLK_AUD_24M>,
> +					 <&audsys CLK_AUD_APLL_TUNER>,
> +					 <&audsys CLK_AUD_APLL2_TUNER>,
> +					 <&audsys CLK_AUD_TDM>,
> +					 <&audsys CLK_AUD_TML>,
> +					 <&audsys CLK_AUD_NLE>,
> +					 <&audsys CLK_AUD_DAC_HIRES>,
> +					 <&audsys CLK_AUD_ADC_HIRES>,
> +					 <&audsys CLK_AUD_ADC_HIRES_TML>,
> +					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> +					 <&audsys CLK_AUD_3RD_DAC>,
> +					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> +					 <&audsys CLK_AUD_3RD_DAC_TML>,
> +					 <&audsys CLK_AUD_3RD_DAC_HIRES>,
> +					 <&infracfg CLK_INFRA_AUDIO>,
> +					 <&infracfg CLK_INFRA_AUDIO_26M_B>,
> +					 <&topckgen CLK_TOP_AUDIO_SEL>,
> +					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> +					 <&topckgen CLK_TOP_AUD_1_SEL>,
> +					 <&topckgen CLK_TOP_APLL1>,
> +					 <&topckgen CLK_TOP_AUD_2_SEL>,
> +					 <&topckgen CLK_TOP_APLL2>,
> +					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> +					 <&topckgen CLK_TOP_APLL1_D4>,
> +					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> +					 <&topckgen CLK_TOP_APLL2_D4>,
> +					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL12_DIV0>,
> +					 <&topckgen CLK_TOP_APLL12_DIV1>,
> +					 <&topckgen CLK_TOP_APLL12_DIV2>,
> +					 <&topckgen CLK_TOP_APLL12_DIV3>,
> +					 <&topckgen CLK_TOP_APLL12_DIV4>,
> +					 <&topckgen CLK_TOP_APLL12_DIVB>,
> +					 <&topckgen CLK_TOP_APLL12_DIV5>,
> +					 <&topckgen CLK_TOP_APLL12_DIV6>,
> +					 <&topckgen CLK_TOP_APLL12_DIV7>,
> +					 <&topckgen CLK_TOP_APLL12_DIV8>,
> +					 <&topckgen CLK_TOP_APLL12_DIV9>,
> +					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
> +					 <&clk26m>;
> +				clock-names = "aud_afe_clk",
> +					      "aud_dac_clk",
> +					      "aud_dac_predis_clk",
> +					      "aud_adc_clk",
> +					      "aud_adda6_adc_clk",
> +					      "aud_apll22m_clk",
> +					      "aud_apll24m_clk",
> +					      "aud_apll1_tuner_clk",
> +					      "aud_apll2_tuner_clk",
> +					      "aud_tdm_clk",
> +					      "aud_tml_clk",
> +					      "aud_nle",
> +					      "aud_dac_hires_clk",
> +					      "aud_adc_hires_clk",
> +					      "aud_adc_hires_tml",
> +					      "aud_adda6_adc_hires_clk",
> +					      "aud_3rd_dac_clk",
> +					      "aud_3rd_dac_predis_clk",
> +					      "aud_3rd_dac_tml",
> +					      "aud_3rd_dac_hires_clk",
> +					      "aud_infra_clk",
> +					      "aud_infra_26m_clk",
> +					      "top_mux_audio",
> +					      "top_mux_audio_int",
> +					      "top_mainpll_d4_d4",
> +					      "top_mux_aud_1",
> +					      "top_apll1_ck",
> +					      "top_mux_aud_2",
> +					      "top_apll2_ck",
> +					      "top_mux_aud_eng1",
> +					      "top_apll1_d4",
> +					      "top_mux_aud_eng2",
> +					      "top_apll2_d4",
> +					      "top_i2s0_m_sel",
> +					      "top_i2s1_m_sel",
> +					      "top_i2s2_m_sel",
> +					      "top_i2s3_m_sel",
> +					      "top_i2s4_m_sel",
> +					      "top_i2s5_m_sel",
> +					      "top_i2s6_m_sel",
> +					      "top_i2s7_m_sel",
> +					      "top_i2s8_m_sel",
> +					      "top_i2s9_m_sel",
> +					      "top_apll12_div0",
> +					      "top_apll12_div1",
> +					      "top_apll12_div2",
> +					      "top_apll12_div3",
> +					      "top_apll12_div4",
> +					      "top_apll12_divb",
> +					      "top_apll12_div5",
> +					      "top_apll12_div6",
> +					      "top_apll12_div7",
> +					      "top_apll12_div8",
> +					      "top_apll12_div9",
> +					      "top_mux_audio_h",
> +					      "top_clk26m_clk";
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;
> @@ -757,12 +885,6 @@
>   			status = "disable";
>   		};
>   
> -		audsys: clock-controller@11210000 {
> -			compatible = "mediatek,mt8192-audsys", "syscon";
> -			reg = <0 0x11210000 0 0x1000>;
> -			#clock-cells = <1>;
> -		};
> -
>   		i2c3: i2c@11cb0000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11cb0000 0 0x1000>,

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Re: [PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
>   - Move audsys node in ascending order.
>   - Increase the address range's length from 0x1000 to 0x2000.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 ++++++++++++++++++++++-
>   1 file changed, 128 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6bc36a4076f4..40cf6dacca3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -742,6 +742,134 @@
>   			status = "disabled";
>   		};
>   
> +		audsys: syscon@11210000 {
> +			compatible = "mediatek,mt8192-audsys", "syscon";
> +			reg = <0 0x11210000 0 0x2000>;
> +			#clock-cells = <1>;

New line here please.

> +			afe: mt8192-afe-pcm {
> +				compatible = "mediatek,mt8192-audio";
> +				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> +				resets = <&watchdog 17>;
> +				reset-names = "audiosys";
> +				mediatek,apmixedsys = <&apmixedsys>;
> +				mediatek,infracfg = <&infracfg>;
> +				mediatek,topckgen = <&topckgen>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> +				clocks = <&audsys CLK_AUD_AFE>,

There are many more clocks then in the bindings, can please fix that.

Regards,
Matthias

> +					 <&audsys CLK_AUD_DAC>,
> +					 <&audsys CLK_AUD_DAC_PREDIS>,
> +					 <&audsys CLK_AUD_ADC>,
> +					 <&audsys CLK_AUD_ADDA6_ADC>,
> +					 <&audsys CLK_AUD_22M>,
> +					 <&audsys CLK_AUD_24M>,
> +					 <&audsys CLK_AUD_APLL_TUNER>,
> +					 <&audsys CLK_AUD_APLL2_TUNER>,
> +					 <&audsys CLK_AUD_TDM>,
> +					 <&audsys CLK_AUD_TML>,
> +					 <&audsys CLK_AUD_NLE>,
> +					 <&audsys CLK_AUD_DAC_HIRES>,
> +					 <&audsys CLK_AUD_ADC_HIRES>,
> +					 <&audsys CLK_AUD_ADC_HIRES_TML>,
> +					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> +					 <&audsys CLK_AUD_3RD_DAC>,
> +					 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> +					 <&audsys CLK_AUD_3RD_DAC_TML>,
> +					 <&audsys CLK_AUD_3RD_DAC_HIRES>,
> +					 <&infracfg CLK_INFRA_AUDIO>,
> +					 <&infracfg CLK_INFRA_AUDIO_26M_B>,
> +					 <&topckgen CLK_TOP_AUDIO_SEL>,
> +					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> +					 <&topckgen CLK_TOP_AUD_1_SEL>,
> +					 <&topckgen CLK_TOP_APLL1>,
> +					 <&topckgen CLK_TOP_AUD_2_SEL>,
> +					 <&topckgen CLK_TOP_APLL2>,
> +					 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> +					 <&topckgen CLK_TOP_APLL1_D4>,
> +					 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> +					 <&topckgen CLK_TOP_APLL2_D4>,
> +					 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> +					 <&topckgen CLK_TOP_APLL12_DIV0>,
> +					 <&topckgen CLK_TOP_APLL12_DIV1>,
> +					 <&topckgen CLK_TOP_APLL12_DIV2>,
> +					 <&topckgen CLK_TOP_APLL12_DIV3>,
> +					 <&topckgen CLK_TOP_APLL12_DIV4>,
> +					 <&topckgen CLK_TOP_APLL12_DIVB>,
> +					 <&topckgen CLK_TOP_APLL12_DIV5>,
> +					 <&topckgen CLK_TOP_APLL12_DIV6>,
> +					 <&topckgen CLK_TOP_APLL12_DIV7>,
> +					 <&topckgen CLK_TOP_APLL12_DIV8>,
> +					 <&topckgen CLK_TOP_APLL12_DIV9>,
> +					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
> +					 <&clk26m>;
> +				clock-names = "aud_afe_clk",
> +					      "aud_dac_clk",
> +					      "aud_dac_predis_clk",
> +					      "aud_adc_clk",
> +					      "aud_adda6_adc_clk",
> +					      "aud_apll22m_clk",
> +					      "aud_apll24m_clk",
> +					      "aud_apll1_tuner_clk",
> +					      "aud_apll2_tuner_clk",
> +					      "aud_tdm_clk",
> +					      "aud_tml_clk",
> +					      "aud_nle",
> +					      "aud_dac_hires_clk",
> +					      "aud_adc_hires_clk",
> +					      "aud_adc_hires_tml",
> +					      "aud_adda6_adc_hires_clk",
> +					      "aud_3rd_dac_clk",
> +					      "aud_3rd_dac_predis_clk",
> +					      "aud_3rd_dac_tml",
> +					      "aud_3rd_dac_hires_clk",
> +					      "aud_infra_clk",
> +					      "aud_infra_26m_clk",
> +					      "top_mux_audio",
> +					      "top_mux_audio_int",
> +					      "top_mainpll_d4_d4",
> +					      "top_mux_aud_1",
> +					      "top_apll1_ck",
> +					      "top_mux_aud_2",
> +					      "top_apll2_ck",
> +					      "top_mux_aud_eng1",
> +					      "top_apll1_d4",
> +					      "top_mux_aud_eng2",
> +					      "top_apll2_d4",
> +					      "top_i2s0_m_sel",
> +					      "top_i2s1_m_sel",
> +					      "top_i2s2_m_sel",
> +					      "top_i2s3_m_sel",
> +					      "top_i2s4_m_sel",
> +					      "top_i2s5_m_sel",
> +					      "top_i2s6_m_sel",
> +					      "top_i2s7_m_sel",
> +					      "top_i2s8_m_sel",
> +					      "top_i2s9_m_sel",
> +					      "top_apll12_div0",
> +					      "top_apll12_div1",
> +					      "top_apll12_div2",
> +					      "top_apll12_div3",
> +					      "top_apll12_div4",
> +					      "top_apll12_divb",
> +					      "top_apll12_div5",
> +					      "top_apll12_div6",
> +					      "top_apll12_div7",
> +					      "top_apll12_div8",
> +					      "top_apll12_div9",
> +					      "top_mux_audio_h",
> +					      "top_clk26m_clk";
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;
> @@ -757,12 +885,6 @@
>   			status = "disable";
>   		};
>   
> -		audsys: clock-controller@11210000 {
> -			compatible = "mediatek,mt8192-audsys", "syscon";
> -			reg = <0 0x11210000 0 0x1000>;
> -			#clock-cells = <1>;
> -		};
> -
>   		i2c3: i2c@11cb0000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11cb0000 0 0x1000>,

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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
>   			};
>   		};
>   
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> +				      "obff_ck0", "axi_ck0", "pipe_ck0";

Also not mandated by the bindings nor the driver clock-names don't match the 
binding. How comes? Shall we update the bindings to have more sound names?

Regards,
Matthias

> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			resets = <&infracfg_rst 2>,
> +				 <&infracfg_rst 3>;
> +			reset-names = "phy", "mac";
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
>   			};
>   		};
>   
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> +				      "obff_ck0", "axi_ck0", "pipe_ck0";

Also not mandated by the bindings nor the driver clock-names don't match the 
binding. How comes? Shall we update the bindings to have more sound names?

Regards,
Matthias

> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			resets = <&infracfg_rst 2>,
> +				 <&infracfg_rst 3>;
> +			reset-names = "phy", "mac";
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add PCIe node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38 ++++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 82de1af3f6aa..3a7f93d8eeaa 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -884,6 +884,44 @@
>   			};
>   		};
>   
> +		pcie: pcie@11230000 {
> +			compatible = "mediatek,mt8192-pcie";
> +			device_type = "pci";
> +			reg = <0 0x11230000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> +				      "obff_ck0", "axi_ck0", "pipe_ck0";

Also not mandated by the bindings nor the driver clock-names don't match the 
binding. How comes? Shall we update the bindings to have more sound names?

Regards,
Matthias

> +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
> +			resets = <&infracfg_rst 2>,
> +				 <&infracfg_rst 3>;
> +			reset-names = "phy", "mac";
> +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
> +			bus-range = <0x00 0xff>;
> +			ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
> +				 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> +					<0 0 0 2 &pcie_intc0 1>,
> +					<0 0 0 3 &pcie_intc0 2>,
> +					<0 0 0 4 &pcie_intc0 3>;
> +
> +			pcie_intc0: interrupt-controller {
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
>   		nor_flash: spi@11234000 {
>   			compatible = "mediatek,mt8192-nor";
>   			reg = <0 0x11234000 0 0xe0>;

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Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3a7f93d8eeaa..75c21edccf85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -934,7 +934,7 @@
>   			assigned-clock-parents = <&clk26m>;
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> -			status = "disable";
> +			status = "disabled";
>   		};
>   
>   		i2c3: i2c@11cb0000 {

Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3a7f93d8eeaa..75c21edccf85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -934,7 +934,7 @@
>   			assigned-clock-parents = <&clk26m>;
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> -			status = "disable";
> +			status = "disabled";
>   		};
>   
>   		i2c3: i2c@11cb0000 {

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Re: [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Correct nor_flash status disable typo of mt8192 SoC.
> 
> Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node")
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 3a7f93d8eeaa..75c21edccf85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -934,7 +934,7 @@
>   			assigned-clock-parents = <&clk26m>;
>   			#address-cells = <1>;
>   			#size-cells = <0>;
> -			status = "disable";
> +			status = "disabled";
>   		};
>   
>   		i2c3: i2c@11cb0000 {

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Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 75c21edccf85..6220d6962f58 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -937,6 +937,21 @@
>   			status = "disabled";
>   		};
>   
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			lvts_e_data1: data1@1c0 {
> +				reg = <0x1c0 0x58>;
> +			};
> +
> +			svs_calibration: calib@580 {
> +				reg = <0x580 0x68>;
> +			};
> +		};
> +
>   		i2c3: i2c@11cb0000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11cb0000 0 0x1000>,

Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 75c21edccf85..6220d6962f58 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -937,6 +937,21 @@
>   			status = "disabled";
>   		};
>   
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			lvts_e_data1: data1@1c0 {
> +				reg = <0x1c0 0x58>;
> +			};
> +
> +			svs_calibration: calib@580 {
> +				reg = <0x580 0x68>;
> +			};
> +		};
> +
>   		i2c3: i2c@11cb0000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11cb0000 0 0x1000>,

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Re: [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add efuse node for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 75c21edccf85..6220d6962f58 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -937,6 +937,21 @@
>   			status = "disabled";
>   		};
>   
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			lvts_e_data1: data1@1c0 {
> +				reg = <0x1c0 0x58>;
> +			};
> +
> +			svs_calibration: calib@580 {
> +				reg = <0x580 0x68>;
> +			};
> +		};
> +
>   		i2c3: i2c@11cb0000 {
>   			compatible = "mediatek,mt8192-i2c";
>   			reg = <0 0x11cb0000 0 0x1000>,

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Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
>   1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6220d6962f58..2648f2847993 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1150,10 +1150,36 @@
>   			#clock-cells = <1>;
>   		};
>   
> -		msdc: clock-controller@11f60000 {
> -			compatible = "mediatek,mt8192-msdc";
> -			reg = <0 0x11f60000 0 0x1000>;
> -			#clock-cells = <1>;

We don't need the msdc_axi_wrap clock and that's why we delete the node, 
correct? In that case we could only disable the node, as DTS should describe the 
HW as it is. Please also add a line in the commit message explaining that.

Regards,
Matthias

> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
>   		};
>   
>   		mfgcfg: clock-controller@13fbf000 {

Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
>   1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6220d6962f58..2648f2847993 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1150,10 +1150,36 @@
>   			#clock-cells = <1>;
>   		};
>   
> -		msdc: clock-controller@11f60000 {
> -			compatible = "mediatek,mt8192-msdc";
> -			reg = <0 0x11f60000 0 0x1000>;
> -			#clock-cells = <1>;

We don't need the msdc_axi_wrap clock and that's why we delete the node, 
correct? In that case we could only disable the node, as DTS should describe the 
HW as it is. Please also add a line in the commit message explaining that.

Regards,
Matthias

> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
>   		};
>   
>   		mfgcfg: clock-controller@13fbf000 {

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Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add mmc nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 +++++++++++++++++++++---
>   1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6220d6962f58..2648f2847993 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1150,10 +1150,36 @@
>   			#clock-cells = <1>;
>   		};
>   
> -		msdc: clock-controller@11f60000 {
> -			compatible = "mediatek,mt8192-msdc";
> -			reg = <0 0x11f60000 0 0x1000>;
> -			#clock-cells = <1>;

We don't need the msdc_axi_wrap clock and that's why we delete the node, 
correct? In that case we could only disable the node, as DTS should describe the 
HW as it is. Please also add a line in the commit message explaining that.

Regards,
Matthias

> +		mmc0: mmc@11f60000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
> +		};
> +
> +		mmc1: mmc@11f70000 {
> +			compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
> +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> +				 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> +			clock-names = "source", "hclk", "source_cg", "sys_cg",
> +				      "pclk_cg", "axi_cg", "ahb_cg";
> +			status = "disabled";
>   		};
>   
>   		mfgcfg: clock-controller@13fbf000 {

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Re: [PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add m4u and smi nodes for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
>   1 file changed, 190 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6b769fa5b427..4addf6ddd86d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -9,6 +9,7 @@
>   #include <dt-bindings/gce/mt8192-gce.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/memory/mt8192-larb-port.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> @@ -1204,24 +1205,114 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		smi_common: smi@14002000 {
> +			compatible = "mediatek,mt8192-smi-common";
> +			reg = <0 0x14002000 0 0x1000>;
> +			clocks = <&mmsys CLK_MM_SMI_COMMON>,
> +				 <&mmsys CLK_MM_SMI_INFRA>,
> +				 <&mmsys CLK_MM_SMI_GALS>,
> +				 <&mmsys CLK_MM_SMI_GALS>;
> +			clock-names = "apb", "smi", "gals0", "gals1";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		larb0: larb@14003000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x14003000 0 0x1000>;
> +			mediatek,larb-id = <0>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		larb1: larb@14004000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x14004000 0 0x1000>;
> +			mediatek,larb-id = <1>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		iommu0: m4u@1401d000 {
> +			compatible = "mediatek,mt8192-m4u";
> +			reg = <0 0x1401d000 0 0x1000>;
> +			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> +					 <&larb4>, <&larb5>, <&larb7>,
> +					 <&larb9>, <&larb11>, <&larb13>,
> +					 <&larb14>, <&larb16>, <&larb17>,
> +					 <&larb18>, <&larb19>, <&larb20>;
> +			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
> +			clock-names = "bclk";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			#iommu-cells = <1>;
> +		};
> +
>   		imgsys: clock-controller@15020000 {
>   			compatible = "mediatek,mt8192-imgsys";
>   			reg = <0 0x15020000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb9: larb@1502e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1502e000 0 0x1000>;
> +			mediatek,larb-id = <9>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&imgsys CLK_IMG_LARB9>,
> +				 <&imgsys CLK_IMG_LARB9>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
> +		};
> +
>   		imgsys2: clock-controller@15820000 {
>   			compatible = "mediatek,mt8192-imgsys2";
>   			reg = <0 0x15820000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb11: larb@1582e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1582e000 0 0x1000>;
> +			mediatek,larb-id = <11>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&imgsys2 CLK_IMG2_LARB11>,
> +				 <&imgsys2 CLK_IMG2_LARB11>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> +		};
> +
> +		larb5: larb@1600d000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1600d000 0 0x1000>;
> +			mediatek,larb-id = <5>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +		};
> +
>   		vdecsys_soc: clock-controller@1600f000 {
>   			compatible = "mediatek,mt8192-vdecsys_soc";
>   			reg = <0 0x1600f000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb4: larb@1602e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1602e000 0 0x1000>;
> +			mediatek,larb-id = <4>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
> +				 <&vdecsys CLK_VDEC_SOC_LARB1>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +		};
> +
>   		vdecsys: clock-controller@1602f000 {
>   			compatible = "mediatek,mt8192-vdecsys";
>   			reg = <0 0x1602f000 0 0x1000>;
> @@ -1234,12 +1325,78 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		larb7: larb@17010000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x17010000 0 0x1000>;
> +			mediatek,larb-id = <7>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vencsys CLK_VENC_SET0_LARB>,
> +				 <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb13: larb@1a001000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a001000 0 0x1000>;
> +			mediatek,larb-id = <13>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys CLK_CAM_CAM>,
> +				 <&camsys CLK_CAM_LARB13>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> +		};
> +
> +		larb14: larb@1a002000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a002000 0 0x1000>;
> +			mediatek,larb-id = <14>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys CLK_CAM_CAM>,
> +				 <&camsys CLK_CAM_LARB14>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> +		};
> +
> +		larb16: larb@1a00f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a00f000 0 0x1000>;
> +			mediatek,larb-id = <16>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> +				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
> +		};
> +
> +		larb17: larb@1a010000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a010000 0 0x1000>;
> +			mediatek,larb-id = <17>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
> +				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
> +		};
> +
> +		larb18: larb@1a011000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a011000 0 0x1000>;
> +			mediatek,larb-id = <18>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
> +				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
> +		};
> +
>   		camsys_rawa: clock-controller@1a04f000 {
>   			compatible = "mediatek,mt8192-camsys_rawa";
>   			reg = <0 0x1a04f000 0 0x1000>;
> @@ -1264,10 +1421,43 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		larb20: larb@1b00f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1b00f000 0 0x1000>;
> +			mediatek,larb-id = <20>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> +				 <&ipesys CLK_IPE_LARB20>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> +		};
> +
> +		larb19: larb@1b10f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1b10f000 0 0x1000>;
> +			mediatek,larb-id = <19>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> +				 <&ipesys CLK_IPE_LARB19>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> +		};
> +
>   		mdpsys: clock-controller@1f000000 {
>   			compatible = "mediatek,mt8192-mdpsys";
>   			reg = <0 0x1f000000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
> +
> +		larb2: larb@1f002000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1f002000 0 0x1000>;
> +			mediatek,larb-id = <2>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&mdpsys CLK_MDP_SMI0>,
> +				 <&mdpsys CLK_MDP_SMI0>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
> +		};
>   	};
>   };

Re: [PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add m4u and smi nodes for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
>   1 file changed, 190 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6b769fa5b427..4addf6ddd86d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -9,6 +9,7 @@
>   #include <dt-bindings/gce/mt8192-gce.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/memory/mt8192-larb-port.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> @@ -1204,24 +1205,114 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		smi_common: smi@14002000 {
> +			compatible = "mediatek,mt8192-smi-common";
> +			reg = <0 0x14002000 0 0x1000>;
> +			clocks = <&mmsys CLK_MM_SMI_COMMON>,
> +				 <&mmsys CLK_MM_SMI_INFRA>,
> +				 <&mmsys CLK_MM_SMI_GALS>,
> +				 <&mmsys CLK_MM_SMI_GALS>;
> +			clock-names = "apb", "smi", "gals0", "gals1";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		larb0: larb@14003000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x14003000 0 0x1000>;
> +			mediatek,larb-id = <0>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		larb1: larb@14004000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x14004000 0 0x1000>;
> +			mediatek,larb-id = <1>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		iommu0: m4u@1401d000 {
> +			compatible = "mediatek,mt8192-m4u";
> +			reg = <0 0x1401d000 0 0x1000>;
> +			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> +					 <&larb4>, <&larb5>, <&larb7>,
> +					 <&larb9>, <&larb11>, <&larb13>,
> +					 <&larb14>, <&larb16>, <&larb17>,
> +					 <&larb18>, <&larb19>, <&larb20>;
> +			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
> +			clock-names = "bclk";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			#iommu-cells = <1>;
> +		};
> +
>   		imgsys: clock-controller@15020000 {
>   			compatible = "mediatek,mt8192-imgsys";
>   			reg = <0 0x15020000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb9: larb@1502e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1502e000 0 0x1000>;
> +			mediatek,larb-id = <9>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&imgsys CLK_IMG_LARB9>,
> +				 <&imgsys CLK_IMG_LARB9>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
> +		};
> +
>   		imgsys2: clock-controller@15820000 {
>   			compatible = "mediatek,mt8192-imgsys2";
>   			reg = <0 0x15820000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb11: larb@1582e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1582e000 0 0x1000>;
> +			mediatek,larb-id = <11>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&imgsys2 CLK_IMG2_LARB11>,
> +				 <&imgsys2 CLK_IMG2_LARB11>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> +		};
> +
> +		larb5: larb@1600d000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1600d000 0 0x1000>;
> +			mediatek,larb-id = <5>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +		};
> +
>   		vdecsys_soc: clock-controller@1600f000 {
>   			compatible = "mediatek,mt8192-vdecsys_soc";
>   			reg = <0 0x1600f000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb4: larb@1602e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1602e000 0 0x1000>;
> +			mediatek,larb-id = <4>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
> +				 <&vdecsys CLK_VDEC_SOC_LARB1>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +		};
> +
>   		vdecsys: clock-controller@1602f000 {
>   			compatible = "mediatek,mt8192-vdecsys";
>   			reg = <0 0x1602f000 0 0x1000>;
> @@ -1234,12 +1325,78 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		larb7: larb@17010000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x17010000 0 0x1000>;
> +			mediatek,larb-id = <7>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vencsys CLK_VENC_SET0_LARB>,
> +				 <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb13: larb@1a001000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a001000 0 0x1000>;
> +			mediatek,larb-id = <13>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys CLK_CAM_CAM>,
> +				 <&camsys CLK_CAM_LARB13>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> +		};
> +
> +		larb14: larb@1a002000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a002000 0 0x1000>;
> +			mediatek,larb-id = <14>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys CLK_CAM_CAM>,
> +				 <&camsys CLK_CAM_LARB14>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> +		};
> +
> +		larb16: larb@1a00f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a00f000 0 0x1000>;
> +			mediatek,larb-id = <16>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> +				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
> +		};
> +
> +		larb17: larb@1a010000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a010000 0 0x1000>;
> +			mediatek,larb-id = <17>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
> +				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
> +		};
> +
> +		larb18: larb@1a011000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a011000 0 0x1000>;
> +			mediatek,larb-id = <18>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
> +				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
> +		};
> +
>   		camsys_rawa: clock-controller@1a04f000 {
>   			compatible = "mediatek,mt8192-camsys_rawa";
>   			reg = <0 0x1a04f000 0 0x1000>;
> @@ -1264,10 +1421,43 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		larb20: larb@1b00f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1b00f000 0 0x1000>;
> +			mediatek,larb-id = <20>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> +				 <&ipesys CLK_IPE_LARB20>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> +		};
> +
> +		larb19: larb@1b10f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1b10f000 0 0x1000>;
> +			mediatek,larb-id = <19>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> +				 <&ipesys CLK_IPE_LARB19>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> +		};
> +
>   		mdpsys: clock-controller@1f000000 {
>   			compatible = "mediatek,mt8192-mdpsys";
>   			reg = <0 0x1f000000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
> +
> +		larb2: larb@1f002000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1f002000 0 0x1000>;
> +			mediatek,larb-id = <2>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&mdpsys CLK_MDP_SMI0>,
> +				 <&mdpsys CLK_MDP_SMI0>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
> +		};
>   	};
>   };

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Re: [PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add m4u and smi nodes for mt8192 SoC
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
>   1 file changed, 190 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 6b769fa5b427..4addf6ddd86d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -9,6 +9,7 @@
>   #include <dt-bindings/gce/mt8192-gce.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/memory/mt8192-larb-port.h>
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> @@ -1204,24 +1205,114 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		smi_common: smi@14002000 {
> +			compatible = "mediatek,mt8192-smi-common";
> +			reg = <0 0x14002000 0 0x1000>;
> +			clocks = <&mmsys CLK_MM_SMI_COMMON>,
> +				 <&mmsys CLK_MM_SMI_INFRA>,
> +				 <&mmsys CLK_MM_SMI_GALS>,
> +				 <&mmsys CLK_MM_SMI_GALS>;
> +			clock-names = "apb", "smi", "gals0", "gals1";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		larb0: larb@14003000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x14003000 0 0x1000>;
> +			mediatek,larb-id = <0>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		larb1: larb@14004000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x14004000 0 0x1000>;
> +			mediatek,larb-id = <1>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		iommu0: m4u@1401d000 {
> +			compatible = "mediatek,mt8192-m4u";
> +			reg = <0 0x1401d000 0 0x1000>;
> +			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
> +					 <&larb4>, <&larb5>, <&larb7>,
> +					 <&larb9>, <&larb11>, <&larb13>,
> +					 <&larb14>, <&larb16>, <&larb17>,
> +					 <&larb18>, <&larb19>, <&larb20>;
> +			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
> +			clock-names = "bclk";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			#iommu-cells = <1>;
> +		};
> +
>   		imgsys: clock-controller@15020000 {
>   			compatible = "mediatek,mt8192-imgsys";
>   			reg = <0 0x15020000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb9: larb@1502e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1502e000 0 0x1000>;
> +			mediatek,larb-id = <9>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&imgsys CLK_IMG_LARB9>,
> +				 <&imgsys CLK_IMG_LARB9>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
> +		};
> +
>   		imgsys2: clock-controller@15820000 {
>   			compatible = "mediatek,mt8192-imgsys2";
>   			reg = <0 0x15820000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb11: larb@1582e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1582e000 0 0x1000>;
> +			mediatek,larb-id = <11>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&imgsys2 CLK_IMG2_LARB11>,
> +				 <&imgsys2 CLK_IMG2_LARB11>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> +		};
> +
> +		larb5: larb@1600d000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1600d000 0 0x1000>;
> +			mediatek,larb-id = <5>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +		};
> +
>   		vdecsys_soc: clock-controller@1600f000 {
>   			compatible = "mediatek,mt8192-vdecsys_soc";
>   			reg = <0 0x1600f000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb4: larb@1602e000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1602e000 0 0x1000>;
> +			mediatek,larb-id = <4>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
> +				 <&vdecsys CLK_VDEC_SOC_LARB1>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +		};
> +
>   		vdecsys: clock-controller@1602f000 {
>   			compatible = "mediatek,mt8192-vdecsys";
>   			reg = <0 0x1602f000 0 0x1000>;
> @@ -1234,12 +1325,78 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		larb7: larb@17010000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x17010000 0 0x1000>;
> +			mediatek,larb-id = <7>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&vencsys CLK_VENC_SET0_LARB>,
> +				 <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
>   
> +		larb13: larb@1a001000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a001000 0 0x1000>;
> +			mediatek,larb-id = <13>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys CLK_CAM_CAM>,
> +				 <&camsys CLK_CAM_LARB13>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> +		};
> +
> +		larb14: larb@1a002000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a002000 0 0x1000>;
> +			mediatek,larb-id = <14>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys CLK_CAM_CAM>,
> +				 <&camsys CLK_CAM_LARB14>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
> +		};
> +
> +		larb16: larb@1a00f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a00f000 0 0x1000>;
> +			mediatek,larb-id = <16>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
> +				 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
> +		};
> +
> +		larb17: larb@1a010000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a010000 0 0x1000>;
> +			mediatek,larb-id = <17>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
> +				 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
> +		};
> +
> +		larb18: larb@1a011000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1a011000 0 0x1000>;
> +			mediatek,larb-id = <18>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
> +				 <&camsys_rawc CLK_CAM_RAWC_CAM>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
> +		};
> +
>   		camsys_rawa: clock-controller@1a04f000 {
>   			compatible = "mediatek,mt8192-camsys_rawa";
>   			reg = <0 0x1a04f000 0 0x1000>;
> @@ -1264,10 +1421,43 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		larb20: larb@1b00f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1b00f000 0 0x1000>;
> +			mediatek,larb-id = <20>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> +				 <&ipesys CLK_IPE_LARB20>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> +		};
> +
> +		larb19: larb@1b10f000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1b10f000 0 0x1000>;
> +			mediatek,larb-id = <19>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
> +				 <&ipesys CLK_IPE_LARB19>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
> +		};
> +
>   		mdpsys: clock-controller@1f000000 {
>   			compatible = "mediatek,mt8192-mdpsys";
>   			reg = <0 0x1f000000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};
> +
> +		larb2: larb@1f002000 {
> +			compatible = "mediatek,mt8192-smi-larb";
> +			reg = <0 0x1f002000 0 0x1000>;
> +			mediatek,larb-id = <2>;
> +			mediatek,smi = <&smi_common>;
> +			clocks = <&mdpsys CLK_MDP_SMI0>,
> +				 <&mdpsys CLK_MDP_SMI0>;
> +			clock-names = "apb", "smi";
> +			power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
> +		};
>   	};
>   };

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Re: [PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 4addf6ddd86d..63893779b193 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1336,6 +1336,29 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
>   		};
>   
> +		vcodec_enc: vcodec@17020000 {
> +			compatible = "mediatek,mt8192-vcodec-enc";
> +			reg = <0 0x17020000 0 0x2000>;
> +			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REC>,
> +				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> +			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,scp = <&scp>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +			clocks = <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "venc-set1";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;

Re: [PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 4addf6ddd86d..63893779b193 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1336,6 +1336,29 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
>   		};
>   
> +		vcodec_enc: vcodec@17020000 {
> +			compatible = "mediatek,mt8192-vcodec-enc";
> +			reg = <0 0x17020000 0 0x2000>;
> +			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REC>,
> +				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> +			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,scp = <&scp>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +			clocks = <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "venc-set1";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;

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Re: [PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Adds H264 venc node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


Applied thanks

> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 4addf6ddd86d..63893779b193 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1336,6 +1336,29 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
>   		};
>   
> +		vcodec_enc: vcodec@17020000 {
> +			compatible = "mediatek,mt8192-vcodec-enc";
> +			reg = <0 0x17020000 0 0x2000>;
> +			iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REC>,
> +				 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
> +				 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
> +			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,scp = <&scp>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
> +			clocks = <&vencsys CLK_VENC_SET1_VENC>;
> +			clock-names = "venc-set1";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +		};
> +
>   		camsys: clock-controller@1a000000 {
>   			compatible = "mediatek,mt8192-camsys";
>   			reg = <0 0x1a000000 0 0x1000>;

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Note: since there were some mtk-mmsys.c updates in the meanwhile, this patch
requires [1] to be merged in order to work correctly.

Aside from that:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


[1]: 
https://patchwork.kernel.org/project/linux-mediatek/patch/20220323091932.10648-1-angelogioacchino.delregno@collabora.com/

> ---
>   include/dt-bindings/reset/mt8192-resets.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>   
>   #define MT8192_TOPRGU_SW_RST_NUM				23
>   
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Note: since there were some mtk-mmsys.c updates in the meanwhile, this patch
requires [1] to be merged in order to work correctly.

Aside from that:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


[1]: 
https://patchwork.kernel.org/project/linux-mediatek/patch/20220323091932.10648-1-angelogioacchino.delregno@collabora.com/

> ---
>   include/dt-bindings/reset/mt8192-resets.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>   
>   #define MT8192_TOPRGU_SW_RST_NUM				23
>   
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */



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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Note: since there were some mtk-mmsys.c updates in the meanwhile, this patch
requires [1] to be merged in order to work correctly.

Aside from that:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


[1]: 
https://patchwork.kernel.org/project/linux-mediatek/patch/20220323091932.10648-1-angelogioacchino.delregno@collabora.com/

> ---
>   include/dt-bindings/reset/mt8192-resets.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>   
>   #define MT8192_TOPRGU_SW_RST_NUM				23
>   
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */



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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[AngeloGioacchino Del Regno]

Il 18/03/22 15:45, Allen-KH Cheng ha scritto:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 63893779b193..71ad3adeed51 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1285,6 +1285,67 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
>   		};
>   
> +		vcodec_dec: vcodec-dec@16000000 {
> +			compatible = "mediatek,mt8192-vcodec-dec";
> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
> +			mediatek,scp = <&scp>;
> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> +			vcodec_lat: vcodec-lat@10000 {
> +				compatible = "mediatek,mtk-vcodec-lat";
> +				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
> +				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> +					      "vdec-vdec", "vdec-top";

Clock names do not match binding description. We have superfluous "vdec-" 
prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as the driver 
does not care about the clock name. In any case it would be good if you could 
send a follow-up patch to fix the clock name.

Applied, thanks

> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +			};
> +
> +			vcodec_core: vcodec-core@25000 {
> +				compatible = "mediatek,mtk-vcodec-core";
> +				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
> +				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys CLK_VDEC_VDEC>,
> +					 <&vdecsys CLK_VDEC_LAT>,
> +					 <&vdecsys CLK_VDEC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> +					      "vdec-vdec", "vdec-top";
> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +			};
> +		};
> +
>   		larb5: larb@1600d000 {
>   			compatible = "mediatek,mt8192-smi-larb";
>   			reg = <0 0x1600d000 0 0x1000>;

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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 63893779b193..71ad3adeed51 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1285,6 +1285,67 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
>   		};
>   
> +		vcodec_dec: vcodec-dec@16000000 {
> +			compatible = "mediatek,mt8192-vcodec-dec";
> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
> +			mediatek,scp = <&scp>;
> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> +			vcodec_lat: vcodec-lat@10000 {
> +				compatible = "mediatek,mtk-vcodec-lat";
> +				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
> +				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> +					      "vdec-vdec", "vdec-top";

Clock names do not match binding description. We have superfluous "vdec-" 
prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as the driver 
does not care about the clock name. In any case it would be good if you could 
send a follow-up patch to fix the clock name.

Applied, thanks

> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +			};
> +
> +			vcodec_core: vcodec-core@25000 {
> +				compatible = "mediatek,mtk-vcodec-core";
> +				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
> +				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys CLK_VDEC_VDEC>,
> +					 <&vdecsys CLK_VDEC_LAT>,
> +					 <&vdecsys CLK_VDEC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> +					      "vdec-vdec", "vdec-top";
> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +			};
> +		};
> +
>   		larb5: larb@1600d000 {
>   			compatible = "mediatek,mt8192-smi-larb";
>   			reg = <0 0x1600d000 0 0x1000>;

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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61 ++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 63893779b193..71ad3adeed51 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1285,6 +1285,67 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
>   		};
>   
> +		vcodec_dec: vcodec-dec@16000000 {
> +			compatible = "mediatek,mt8192-vcodec-dec";
> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS */
> +			mediatek,scp = <&scp>;
> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> +			vcodec_lat: vcodec-lat@10000 {
> +				compatible = "mediatek,mtk-vcodec-lat";
> +				reg = <0x0 0x10000 0 0x800>;		/* VDEC_MISC */
> +				interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> +					 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> +					 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> +					      "vdec-vdec", "vdec-top";

Clock names do not match binding description. We have superfluous "vdec-" 
prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as the driver 
does not care about the clock name. In any case it would be good if you could 
send a follow-up patch to fix the clock name.

Applied, thanks

> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> +			};
> +
> +			vcodec_core: vcodec-core@25000 {
> +				compatible = "mediatek,mtk-vcodec-core";
> +				reg = <0 0x25000 0 0x1000>;	/* VDEC_CORE_MISC */
> +				interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> +				iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> +					 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> +					 <&vdecsys CLK_VDEC_VDEC>,
> +					 <&vdecsys CLK_VDEC_LAT>,
> +					 <&vdecsys CLK_VDEC_LARB1>,
> +					 <&topckgen CLK_TOP_MAINPLL_D4>;
> +				clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> +					      "vdec-vdec", "vdec-top";
> +				assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> +				power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> +			};
> +		};
> +
>   		larb5: larb@1600d000 {
>   			compatible = "mediatek,mt8192-smi-larb";
>   			reg = <0 0x1600d000 0 0x1000>;

Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add dpi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 71ad3adeed51..a77d405dd508 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1236,6 +1236,17 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   		};
>   
> +		dpi0: dpi@14016000 {
> +			compatible = "mediatek,mt8192-dpi";
> +			reg = <0 0x14016000 0 0x1000>;
> +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
> +				 <&mmsys CLK_MM_DISP_DPI0>,
> +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
> +			clock-names = "pixel", "engine", "pll";
> +			status = "disabled";

We are missing the output port node here.

Regards,
Matthias

> +		};
> +
>   		iommu0: m4u@1401d000 {
>   			compatible = "mediatek,mt8192-m4u";
>   			reg = <0 0x1401d000 0 0x1000>;

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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add dpi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 71ad3adeed51..a77d405dd508 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1236,6 +1236,17 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   		};
>   
> +		dpi0: dpi@14016000 {
> +			compatible = "mediatek,mt8192-dpi";
> +			reg = <0 0x14016000 0 0x1000>;
> +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
> +				 <&mmsys CLK_MM_DISP_DPI0>,
> +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
> +			clock-names = "pixel", "engine", "pll";
> +			status = "disabled";

We are missing the output port node here.

Regards,
Matthias

> +		};
> +
>   		iommu0: m4u@1401d000 {
>   			compatible = "mediatek,mt8192-m4u";
>   			reg = <0 0x1401d000 0 0x1000>;

Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add dpi node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 71ad3adeed51..a77d405dd508 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1236,6 +1236,17 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   		};
>   
> +		dpi0: dpi@14016000 {
> +			compatible = "mediatek,mt8192-dpi";
> +			reg = <0 0x14016000 0 0x1000>;
> +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
> +				 <&mmsys CLK_MM_DISP_DPI0>,
> +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
> +			clock-names = "pixel", "engine", "pll";
> +			status = "disabled";

We are missing the output port node here.

Regards,
Matthias

> +		};
> +
>   		iommu0: m4u@1401d000 {
>   			compatible = "mediatek,mt8192-m4u";
>   			reg = <0 0x1401d000 0 0x1000>;

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>   1 file changed, 111 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;

We are missing power-domains property.

> +		};
> +
>   		smi_common: smi@14002000 {
>   			compatible = "mediatek,mt8192-smi-common";
>   			reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   		};
>   
> +		ovl0: ovl@14005000 {
> +			compatible = "mediatek,mt8192-disp-ovl";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		ovl_2l0: ovl@14006000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14006000 0 0x1000>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;

olv and ovl-2l binding mention that the node should be a sibling of mmsys, but 
this does not hold anymore, correct? Chun-Kuang can you help to fix the binding 
description?

> +		};
> +
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;
> +			mediatek,rdma-fifo-size = <5120>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

Same here, bindings says it should be a sibling of mmsys. Apart from that the 
maximal rdma-fifo-size isn't specified for all SoCs including mt1892.

> +		};
> +
> +		color0: color@14009000 {
> +			compatible = "mediatek,mt8192-disp-color",
> +				     "mediatek,mt8173-disp-color";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +		};

Same here, binding description needs fixed, please check for other bindings as 
well. The node here looks good.

> +
> +		ccorr0: ccorr@1400a000 {
> +			compatible = "mediatek,mt8192-disp-ccorr";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +		};
> +
> +		aal0: aal@1400b000 {
> +			compatible = "mediatek,mt8192-disp-aal",
> +				     "mediatek,mt8193-disp-aal";
> +			reg = <0 0x1400b000 0 0x1000>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +		};
> +
> +		gamma0: gamma@1400c000 {
> +			compatible = "mediatek,mt8192-disp-gamma",
> +				     "mediatek,mt8183-disp-gamma";
> +			reg = <0 0x1400c000 0 0x1000>;
> +			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +		};
> +
> +		postmask0: postmask@1400d000 {
> +			compatible = "mediatek,mt8192-disp-postmask";
> +			reg = <0 0x1400d000 0 0x1000>;
> +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;

No iommus mentioned in binding description.

Regards,
Matthias

> +		};
> +
> +		dither0: dither@1400e000 {
> +			compatible = "mediatek,mt8192-disp-dither",
> +				     "mediatek,mt8183-disp-dither";
> +			reg = <0 0x1400e000 0 0x1000>;
> +			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +		};
> +
> +		ovl_2l2: ovl@14014000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14014000 0 0x1000>;
> +			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +		};
> +
> +		rdma4: rdma@14015000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14015000 0 0x1000>;
> +			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> +			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> +			mediatek,rdma-fifo-size = <2048>;
> +		};
> +
>   		dpi0: dpi@14016000 {
>   			compatible = "mediatek,mt8192-dpi";
>   			reg = <0 0x14016000 0 0x1000>;

Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>   1 file changed, 111 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;

We are missing power-domains property.

> +		};
> +
>   		smi_common: smi@14002000 {
>   			compatible = "mediatek,mt8192-smi-common";
>   			reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   		};
>   
> +		ovl0: ovl@14005000 {
> +			compatible = "mediatek,mt8192-disp-ovl";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		ovl_2l0: ovl@14006000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14006000 0 0x1000>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;

olv and ovl-2l binding mention that the node should be a sibling of mmsys, but 
this does not hold anymore, correct? Chun-Kuang can you help to fix the binding 
description?

> +		};
> +
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;
> +			mediatek,rdma-fifo-size = <5120>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

Same here, bindings says it should be a sibling of mmsys. Apart from that the 
maximal rdma-fifo-size isn't specified for all SoCs including mt1892.

> +		};
> +
> +		color0: color@14009000 {
> +			compatible = "mediatek,mt8192-disp-color",
> +				     "mediatek,mt8173-disp-color";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +		};

Same here, binding description needs fixed, please check for other bindings as 
well. The node here looks good.

> +
> +		ccorr0: ccorr@1400a000 {
> +			compatible = "mediatek,mt8192-disp-ccorr";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +		};
> +
> +		aal0: aal@1400b000 {
> +			compatible = "mediatek,mt8192-disp-aal",
> +				     "mediatek,mt8193-disp-aal";
> +			reg = <0 0x1400b000 0 0x1000>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +		};
> +
> +		gamma0: gamma@1400c000 {
> +			compatible = "mediatek,mt8192-disp-gamma",
> +				     "mediatek,mt8183-disp-gamma";
> +			reg = <0 0x1400c000 0 0x1000>;
> +			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +		};
> +
> +		postmask0: postmask@1400d000 {
> +			compatible = "mediatek,mt8192-disp-postmask";
> +			reg = <0 0x1400d000 0 0x1000>;
> +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;

No iommus mentioned in binding description.

Regards,
Matthias

> +		};
> +
> +		dither0: dither@1400e000 {
> +			compatible = "mediatek,mt8192-disp-dither",
> +				     "mediatek,mt8183-disp-dither";
> +			reg = <0 0x1400e000 0 0x1000>;
> +			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +		};
> +
> +		ovl_2l2: ovl@14014000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14014000 0 0x1000>;
> +			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +		};
> +
> +		rdma4: rdma@14015000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14015000 0 0x1000>;
> +			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> +			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> +			mediatek,rdma-fifo-size = <2048>;
> +		};
> +
>   		dpi0: dpi@14016000 {
>   			compatible = "mediatek,mt8192-dpi";
>   			reg = <0 0x14016000 0 0x1000>;

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>   1 file changed, 111 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
>   			#clock-cells = <1>;
>   		};
>   
> +		mutex: mutex@14001000 {
> +			compatible = "mediatek,mt8192-disp-mutex";
> +			reg = <0 0x14001000 0 0x1000>;
> +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;

We are missing power-domains property.

> +		};
> +
>   		smi_common: smi@14002000 {
>   			compatible = "mediatek,mt8192-smi-common";
>   			reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   		};
>   
> +		ovl0: ovl@14005000 {
> +			compatible = "mediatek,mt8192-disp-ovl";
> +			reg = <0 0x14005000 0 0x1000>;
> +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +		};
> +
> +		ovl_2l0: ovl@14006000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14006000 0 0x1000>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;

olv and ovl-2l binding mention that the node should be a sibling of mmsys, but 
this does not hold anymore, correct? Chun-Kuang can you help to fix the binding 
description?

> +		};
> +
> +		rdma0: rdma@14007000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14007000 0 0x1000>;
> +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> +			mediatek,larb = <&larb0>;
> +			mediatek,rdma-fifo-size = <5120>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

Same here, bindings says it should be a sibling of mmsys. Apart from that the 
maximal rdma-fifo-size isn't specified for all SoCs including mt1892.

> +		};
> +
> +		color0: color@14009000 {
> +			compatible = "mediatek,mt8192-disp-color",
> +				     "mediatek,mt8173-disp-color";
> +			reg = <0 0x14009000 0 0x1000>;
> +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +		};

Same here, binding description needs fixed, please check for other bindings as 
well. The node here looks good.

> +
> +		ccorr0: ccorr@1400a000 {
> +			compatible = "mediatek,mt8192-disp-ccorr";
> +			reg = <0 0x1400a000 0 0x1000>;
> +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +		};
> +
> +		aal0: aal@1400b000 {
> +			compatible = "mediatek,mt8192-disp-aal",
> +				     "mediatek,mt8193-disp-aal";
> +			reg = <0 0x1400b000 0 0x1000>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +		};
> +
> +		gamma0: gamma@1400c000 {
> +			compatible = "mediatek,mt8192-disp-gamma",
> +				     "mediatek,mt8183-disp-gamma";
> +			reg = <0 0x1400c000 0 0x1000>;
> +			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +		};
> +
> +		postmask0: postmask@1400d000 {
> +			compatible = "mediatek,mt8192-disp-postmask";
> +			reg = <0 0x1400d000 0 0x1000>;
> +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> +			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;

No iommus mentioned in binding description.

Regards,
Matthias

> +		};
> +
> +		dither0: dither@1400e000 {
> +			compatible = "mediatek,mt8192-disp-dither",
> +				     "mediatek,mt8183-disp-dither";
> +			reg = <0 0x1400e000 0 0x1000>;
> +			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +		};
> +
> +		ovl_2l2: ovl@14014000 {
> +			compatible = "mediatek,mt8192-disp-ovl-2l";
> +			reg = <0 0x14014000 0 0x1000>;
> +			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> +				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +		};
> +
> +		rdma4: rdma@14015000 {
> +			compatible = "mediatek,mt8192-disp-rdma";
> +			reg = <0 0x14015000 0 0x1000>;
> +			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> +			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> +			mediatek,rdma-fifo-size = <2048>;
> +		};
> +
>   		dpi0: dpi@14016000 {
>   			compatible = "mediatek,mt8192-dpi";
>   			reg = <0 0x14016000 0 0x1000>;

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[CK Hu]

Hi, Allen and Jason:

On Fri, 2022-03-25 at 16:47 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add display nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111
> > +++++++++++++++++++++++
> >   1 file changed, 111 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a77d405dd508..59183fb6c80b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1205,6 +1205,13 @@
> >   			#clock-cells = <1>;
> >   		};
> >   
> > +		mutex: mutex@14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> 
> We are missing power-domains property.
> 
> > +		};
> > +
> >   		smi_common: smi@14002000 {
> >   			compatible = "mediatek,mt8192-smi-common";
> >   			reg = <0 0x14002000 0 0x1000>;
> > @@ -1236,6 +1243,110 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   		};
> >   
> > +		ovl0: ovl@14005000 {
> > +			compatible = "mediatek,mt8192-disp-ovl";
> > +			reg = <0 0x14005000 0 0x1000>;
> > +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		ovl_2l0: ovl@14006000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14006000 0 0x1000>;
> > +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> 
> olv and ovl-2l binding mention that the node should be a sibling of
> mmsys, but 
> this does not hold anymore, correct? Chun-Kuang can you help to fix
> the binding 
> description?

The sibling problem since the first version binding document. Would you
help to fix this problem? But now the binding patch are in chaos, so
you may send patch base on mediatek-drm-fixes [1].

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes

Regards,
CK

> 
> > +		};
> > +
> > +		rdma0: rdma@14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> > +			mediatek,rdma-fifo-size = <5120>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> 
> Same here, bindings says it should be a sibling of mmsys. Apart from
> that the 
> maximal rdma-fifo-size isn't specified for all SoCs including mt1892.
> 
> > +		};
> > +
> > +		color0: color@14009000 {
> > +			compatible = "mediatek,mt8192-disp-color",
> > +				     "mediatek,mt8173-disp-color";
> > +			reg = <0 0x14009000 0 0x1000>;
> > +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +		};
> 
> Same here, binding description needs fixed, please check for other
> bindings as 
> well. The node here looks good.
> 
> > +
> > +		ccorr0: ccorr@1400a000 {
> > +			compatible = "mediatek,mt8192-disp-ccorr";
> > +			reg = <0 0x1400a000 0 0x1000>;
> > +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +		};
> > +
> > +		aal0: aal@1400b000 {
> > +			compatible = "mediatek,mt8192-disp-aal",
> > +				     "mediatek,mt8193-disp-aal";
> > +			reg = <0 0x1400b000 0 0x1000>;
> > +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +		};
> > +
> > +		gamma0: gamma@1400c000 {
> > +			compatible = "mediatek,mt8192-disp-gamma",
> > +				     "mediatek,mt8183-disp-gamma";
> > +			reg = <0 0x1400c000 0 0x1000>;
> > +			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > +		};
> > +
> > +		postmask0: postmask@1400d000 {
> > +			compatible = "mediatek,mt8192-disp-postmask";
> > +			reg = <0 0x1400d000 0 0x1000>;
> > +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> 
> No iommus mentioned in binding description.
> 
> Regards,
> Matthias
> 
> > +		};
> > +
> > +		dither0: dither@1400e000 {
> > +			compatible = "mediatek,mt8192-disp-dither",
> > +				     "mediatek,mt8183-disp-dither";
> > +			reg = <0 0x1400e000 0 0x1000>;
> > +			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > +		};
> > +
> > +		ovl_2l2: ovl@14014000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14014000 0 0x1000>;
> > +			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > +		};
> > +
> > +		rdma4: rdma@14015000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14015000 0 0x1000>;
> > +			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> > +			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> > +			mediatek,rdma-fifo-size = <2048>;
> > +		};
> > +
> >   		dpi0: dpi@14016000 {
> >   			compatible = "mediatek,mt8192-dpi";
> >   			reg = <0 0x14016000 0 0x1000>;
> 
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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[CK Hu]

Hi, Allen and Jason:

On Fri, 2022-03-25 at 16:47 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add display nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111
> > +++++++++++++++++++++++
> >   1 file changed, 111 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index a77d405dd508..59183fb6c80b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1205,6 +1205,13 @@
> >   			#clock-cells = <1>;
> >   		};
> >   
> > +		mutex: mutex@14001000 {
> > +			compatible = "mediatek,mt8192-disp-mutex";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> 
> We are missing power-domains property.
> 
> > +		};
> > +
> >   		smi_common: smi@14002000 {
> >   			compatible = "mediatek,mt8192-smi-common";
> >   			reg = <0 0x14002000 0 0x1000>;
> > @@ -1236,6 +1243,110 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   		};
> >   
> > +		ovl0: ovl@14005000 {
> > +			compatible = "mediatek,mt8192-disp-ovl";
> > +			reg = <0 0x14005000 0 0x1000>;
> > +			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> > +				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +		};
> > +
> > +		ovl_2l0: ovl@14006000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14006000 0 0x1000>;
> > +			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> 
> olv and ovl-2l binding mention that the node should be a sibling of
> mmsys, but 
> this does not hold anymore, correct? Chun-Kuang can you help to fix
> the binding 
> description?

The sibling problem since the first version binding document. Would you
help to fix this problem? But now the binding patch are in chaos, so
you may send patch base on mediatek-drm-fixes [1].

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes

Regards,
CK

> 
> > +		};
> > +
> > +		rdma0: rdma@14007000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14007000 0 0x1000>;
> > +			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> > +			mediatek,larb = <&larb0>;
> > +			mediatek,rdma-fifo-size = <5120>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> 
> Same here, bindings says it should be a sibling of mmsys. Apart from
> that the 
> maximal rdma-fifo-size isn't specified for all SoCs including mt1892.
> 
> > +		};
> > +
> > +		color0: color@14009000 {
> > +			compatible = "mediatek,mt8192-disp-color",
> > +				     "mediatek,mt8173-disp-color";
> > +			reg = <0 0x14009000 0 0x1000>;
> > +			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +		};
> 
> Same here, binding description needs fixed, please check for other
> bindings as 
> well. The node here looks good.
> 
> > +
> > +		ccorr0: ccorr@1400a000 {
> > +			compatible = "mediatek,mt8192-disp-ccorr";
> > +			reg = <0 0x1400a000 0 0x1000>;
> > +			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +		};
> > +
> > +		aal0: aal@1400b000 {
> > +			compatible = "mediatek,mt8192-disp-aal",
> > +				     "mediatek,mt8193-disp-aal";
> > +			reg = <0 0x1400b000 0 0x1000>;
> > +			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +		};
> > +
> > +		gamma0: gamma@1400c000 {
> > +			compatible = "mediatek,mt8192-disp-gamma",
> > +				     "mediatek,mt8183-disp-gamma";
> > +			reg = <0 0x1400c000 0 0x1000>;
> > +			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > +		};
> > +
> > +		postmask0: postmask@1400d000 {
> > +			compatible = "mediatek,mt8192-disp-postmask";
> > +			reg = <0 0x1400d000 0 0x1000>;
> > +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > +			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> 
> No iommus mentioned in binding description.
> 
> Regards,
> Matthias
> 
> > +		};
> > +
> > +		dither0: dither@1400e000 {
> > +			compatible = "mediatek,mt8192-disp-dither",
> > +				     "mediatek,mt8183-disp-dither";
> > +			reg = <0 0x1400e000 0 0x1000>;
> > +			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > +		};
> > +
> > +		ovl_2l2: ovl@14014000 {
> > +			compatible = "mediatek,mt8192-disp-ovl-2l";
> > +			reg = <0 0x14014000 0 0x1000>;
> > +			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> > +			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> > +				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > +		};
> > +
> > +		rdma4: rdma@14015000 {
> > +			compatible = "mediatek,mt8192-disp-rdma";
> > +			reg = <0 0x14015000 0 0x1000>;
> > +			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> > +			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> > +			mediatek,rdma-fifo-size = <2048>;
> > +		};
> > +
> >   		dpi0: dpi@14016000 {
> >   			compatible = "mediatek,mt8192-dpi";
> >   			reg = <0 0x14016000 0 0x1000>;
> 
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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Matthias Brugger]

On 25/03/2022 16:47, Matthias Brugger wrote:
> 
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>> Add display nodes for mt8192 SoC.
>>
>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>>   1 file changed, 111 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> index a77d405dd508..59183fb6c80b 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> @@ -1205,6 +1205,13 @@
>>               #clock-cells = <1>;
>>           };
>> +        mutex: mutex@14001000 {
>> +            compatible = "mediatek,mt8192-disp-mutex";
>> +            reg = <0 0x14001000 0 0x1000>;
>> +            interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> 
> We are missing power-domains property.
> 
>> +        };
>> +
>>           smi_common: smi@14002000 {
>>               compatible = "mediatek,mt8192-smi-common";
>>               reg = <0 0x14002000 0 0x1000>;
>> @@ -1236,6 +1243,110 @@
>>               power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>>           };
>> +        ovl0: ovl@14005000 {
>> +            compatible = "mediatek,mt8192-disp-ovl";
>> +            reg = <0 0x14005000 0 0x1000>;
>> +            interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>> +                 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +        };
>> +
>> +        ovl_2l0: ovl@14006000 {
>> +            compatible = "mediatek,mt8192-disp-ovl-2l";
>> +            reg = <0 0x14006000 0 0x1000>;
>> +            interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +            iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>> +                 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> 
> olv and ovl-2l binding mention that the node should be a sibling of mmsys, but 
> this does not hold anymore, correct? Chun-Kuang can you help to fix the binding 
> description?
> 

Forget about the sibling problem I mentioned, the problem is my poor English not 
the binding description.

Regards,
Matthias

>> +        };
>> +
>> +        rdma0: rdma@14007000 {
>> +            compatible = "mediatek,mt8192-disp-rdma";
>> +            reg = <0 0x14007000 0 0x1000>;
>> +            interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
>> +            mediatek,larb = <&larb0>;
>> +            mediatek,rdma-fifo-size = <5120>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> 
> Same here, bindings says it should be a sibling of mmsys. Apart from that the 
> maximal rdma-fifo-size isn't specified for all SoCs including mt1892.
> 
>> +        };
>> +
>> +        color0: color@14009000 {
>> +            compatible = "mediatek,mt8192-disp-color",
>> +                     "mediatek,mt8173-disp-color";
>> +            reg = <0 0x14009000 0 0x1000>;
>> +            interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +        };
> 
> Same here, binding description needs fixed, please check for other bindings as 
> well. The node here looks good.
> 
>> +
>> +        ccorr0: ccorr@1400a000 {
>> +            compatible = "mediatek,mt8192-disp-ccorr";
>> +            reg = <0 0x1400a000 0 0x1000>;
>> +            interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +        };
>> +
>> +        aal0: aal@1400b000 {
>> +            compatible = "mediatek,mt8192-disp-aal",
>> +                     "mediatek,mt8193-disp-aal";
>> +            reg = <0 0x1400b000 0 0x1000>;
>> +            interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +        };
>> +
>> +        gamma0: gamma@1400c000 {
>> +            compatible = "mediatek,mt8192-disp-gamma",
>> +                     "mediatek,mt8183-disp-gamma";
>> +            reg = <0 0x1400c000 0 0x1000>;
>> +            interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +        };
>> +
>> +        postmask0: postmask@1400d000 {
>> +            compatible = "mediatek,mt8192-disp-postmask";
>> +            reg = <0 0x1400d000 0 0x1000>;
>> +            interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> 
> No iommus mentioned in binding description.
> 
> Regards,
> Matthias
> 
>> +        };
>> +
>> +        dither0: dither@1400e000 {
>> +            compatible = "mediatek,mt8192-disp-dither",
>> +                     "mediatek,mt8183-disp-dither";
>> +            reg = <0 0x1400e000 0 0x1000>;
>> +            interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +        };
>> +
>> +        ovl_2l2: ovl@14014000 {
>> +            compatible = "mediatek,mt8192-disp-ovl-2l";
>> +            reg = <0 0x14014000 0 0x1000>;
>> +            interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>> +            iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>> +                 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
>> +        };
>> +
>> +        rdma4: rdma@14015000 {
>> +            compatible = "mediatek,mt8192-disp-rdma";
>> +            reg = <0 0x14015000 0 0x1000>;
>> +            interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>> +            iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>> +            mediatek,rdma-fifo-size = <2048>;
>> +        };
>> +
>>           dpi0: dpi@14016000 {
>>               compatible = "mediatek,mt8192-dpi";
>>               reg = <0 0x14016000 0 0x1000>;

Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Matthias Brugger]

On 25/03/2022 16:47, Matthias Brugger wrote:
> 
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>> Add display nodes for mt8192 SoC.
>>
>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>>   1 file changed, 111 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> index a77d405dd508..59183fb6c80b 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> @@ -1205,6 +1205,13 @@
>>               #clock-cells = <1>;
>>           };
>> +        mutex: mutex@14001000 {
>> +            compatible = "mediatek,mt8192-disp-mutex";
>> +            reg = <0 0x14001000 0 0x1000>;
>> +            interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> 
> We are missing power-domains property.
> 
>> +        };
>> +
>>           smi_common: smi@14002000 {
>>               compatible = "mediatek,mt8192-smi-common";
>>               reg = <0 0x14002000 0 0x1000>;
>> @@ -1236,6 +1243,110 @@
>>               power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>>           };
>> +        ovl0: ovl@14005000 {
>> +            compatible = "mediatek,mt8192-disp-ovl";
>> +            reg = <0 0x14005000 0 0x1000>;
>> +            interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>> +                 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +        };
>> +
>> +        ovl_2l0: ovl@14006000 {
>> +            compatible = "mediatek,mt8192-disp-ovl-2l";
>> +            reg = <0 0x14006000 0 0x1000>;
>> +            interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +            iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>> +                 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> 
> olv and ovl-2l binding mention that the node should be a sibling of mmsys, but 
> this does not hold anymore, correct? Chun-Kuang can you help to fix the binding 
> description?
> 

Forget about the sibling problem I mentioned, the problem is my poor English not 
the binding description.

Regards,
Matthias

>> +        };
>> +
>> +        rdma0: rdma@14007000 {
>> +            compatible = "mediatek,mt8192-disp-rdma";
>> +            reg = <0 0x14007000 0 0x1000>;
>> +            interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
>> +            mediatek,larb = <&larb0>;
>> +            mediatek,rdma-fifo-size = <5120>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> 
> Same here, bindings says it should be a sibling of mmsys. Apart from that the 
> maximal rdma-fifo-size isn't specified for all SoCs including mt1892.
> 
>> +        };
>> +
>> +        color0: color@14009000 {
>> +            compatible = "mediatek,mt8192-disp-color",
>> +                     "mediatek,mt8173-disp-color";
>> +            reg = <0 0x14009000 0 0x1000>;
>> +            interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +        };
> 
> Same here, binding description needs fixed, please check for other bindings as 
> well. The node here looks good.
> 
>> +
>> +        ccorr0: ccorr@1400a000 {
>> +            compatible = "mediatek,mt8192-disp-ccorr";
>> +            reg = <0 0x1400a000 0 0x1000>;
>> +            interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +        };
>> +
>> +        aal0: aal@1400b000 {
>> +            compatible = "mediatek,mt8192-disp-aal",
>> +                     "mediatek,mt8193-disp-aal";
>> +            reg = <0 0x1400b000 0 0x1000>;
>> +            interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +        };
>> +
>> +        gamma0: gamma@1400c000 {
>> +            compatible = "mediatek,mt8192-disp-gamma",
>> +                     "mediatek,mt8183-disp-gamma";
>> +            reg = <0 0x1400c000 0 0x1000>;
>> +            interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +        };
>> +
>> +        postmask0: postmask@1400d000 {
>> +            compatible = "mediatek,mt8192-disp-postmask";
>> +            reg = <0 0x1400d000 0 0x1000>;
>> +            interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> 
> No iommus mentioned in binding description.
> 
> Regards,
> Matthias
> 
>> +        };
>> +
>> +        dither0: dither@1400e000 {
>> +            compatible = "mediatek,mt8192-disp-dither",
>> +                     "mediatek,mt8183-disp-dither";
>> +            reg = <0 0x1400e000 0 0x1000>;
>> +            interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +        };
>> +
>> +        ovl_2l2: ovl@14014000 {
>> +            compatible = "mediatek,mt8192-disp-ovl-2l";
>> +            reg = <0 0x14014000 0 0x1000>;
>> +            interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>> +            iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>> +                 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
>> +        };
>> +
>> +        rdma4: rdma@14015000 {
>> +            compatible = "mediatek,mt8192-disp-rdma";
>> +            reg = <0 0x14015000 0 0x1000>;
>> +            interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>> +            iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>> +            mediatek,rdma-fifo-size = <2048>;
>> +        };
>> +
>>           dpi0: dpi@14016000 {
>>               compatible = "mediatek,mt8192-dpi";
>>               reg = <0 0x14016000 0 0x1000>;

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Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes

[Matthias Brugger]

On 25/03/2022 16:47, Matthias Brugger wrote:
> 
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>> Add display nodes for mt8192 SoC.
>>
>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
>>   1 file changed, 111 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> index a77d405dd508..59183fb6c80b 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> @@ -1205,6 +1205,13 @@
>>               #clock-cells = <1>;
>>           };
>> +        mutex: mutex@14001000 {
>> +            compatible = "mediatek,mt8192-disp-mutex";
>> +            reg = <0 0x14001000 0 0x1000>;
>> +            interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> 
> We are missing power-domains property.
> 
>> +        };
>> +
>>           smi_common: smi@14002000 {
>>               compatible = "mediatek,mt8192-smi-common";
>>               reg = <0 0x14002000 0 0x1000>;
>> @@ -1236,6 +1243,110 @@
>>               power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>>           };
>> +        ovl0: ovl@14005000 {
>> +            compatible = "mediatek,mt8192-disp-ovl";
>> +            reg = <0 0x14005000 0 0x1000>;
>> +            interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>> +                 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +        };
>> +
>> +        ovl_2l0: ovl@14006000 {
>> +            compatible = "mediatek,mt8192-disp-ovl-2l";
>> +            reg = <0 0x14006000 0 0x1000>;
>> +            interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>> +            iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>> +                 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> 
> olv and ovl-2l binding mention that the node should be a sibling of mmsys, but 
> this does not hold anymore, correct? Chun-Kuang can you help to fix the binding 
> description?
> 

Forget about the sibling problem I mentioned, the problem is my poor English not 
the binding description.

Regards,
Matthias

>> +        };
>> +
>> +        rdma0: rdma@14007000 {
>> +            compatible = "mediatek,mt8192-disp-rdma";
>> +            reg = <0 0x14007000 0 0x1000>;
>> +            interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
>> +            mediatek,larb = <&larb0>;
>> +            mediatek,rdma-fifo-size = <5120>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> 
> Same here, bindings says it should be a sibling of mmsys. Apart from that the 
> maximal rdma-fifo-size isn't specified for all SoCs including mt1892.
> 
>> +        };
>> +
>> +        color0: color@14009000 {
>> +            compatible = "mediatek,mt8192-disp-color",
>> +                     "mediatek,mt8173-disp-color";
>> +            reg = <0 0x14009000 0 0x1000>;
>> +            interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
>> +        };
> 
> Same here, binding description needs fixed, please check for other bindings as 
> well. The node here looks good.
> 
>> +
>> +        ccorr0: ccorr@1400a000 {
>> +            compatible = "mediatek,mt8192-disp-ccorr";
>> +            reg = <0 0x1400a000 0 0x1000>;
>> +            interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_CCORR0>;
>> +        };
>> +
>> +        aal0: aal@1400b000 {
>> +            compatible = "mediatek,mt8192-disp-aal",
>> +                     "mediatek,mt8193-disp-aal";
>> +            reg = <0 0x1400b000 0 0x1000>;
>> +            interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_AAL0>;
>> +        };
>> +
>> +        gamma0: gamma@1400c000 {
>> +            compatible = "mediatek,mt8192-disp-gamma",
>> +                     "mediatek,mt8183-disp-gamma";
>> +            reg = <0 0x1400c000 0 0x1000>;
>> +            interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
>> +        };
>> +
>> +        postmask0: postmask@1400d000 {
>> +            compatible = "mediatek,mt8192-disp-postmask";
>> +            reg = <0 0x1400d000 0 0x1000>;
>> +            interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>> +            iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> 
> No iommus mentioned in binding description.
> 
> Regards,
> Matthias
> 
>> +        };
>> +
>> +        dither0: dither@1400e000 {
>> +            compatible = "mediatek,mt8192-disp-dither",
>> +                     "mediatek,mt8183-disp-dither";
>> +            reg = <0 0x1400e000 0 0x1000>;
>> +            interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>> +        };
>> +
>> +        ovl_2l2: ovl@14014000 {
>> +            compatible = "mediatek,mt8192-disp-ovl-2l";
>> +            reg = <0 0x14014000 0 0x1000>;
>> +            interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>> +            iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>> +                 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
>> +        };
>> +
>> +        rdma4: rdma@14015000 {
>> +            compatible = "mediatek,mt8192-disp-rdma";
>> +            reg = <0 0x14015000 0 0x1000>;
>> +            interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
>> +            power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>> +            clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>> +            iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>> +            mediatek,rdma-fifo-size = <2048>;
>> +        };
>> +
>>           dpi0: dpi@14016000 {
>>               compatible = "mediatek,mt8192-dpi";
>>               reg = <0 0x14016000 0 0x1000>;

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied thanks

> ---
>   include/dt-bindings/reset/mt8192-resets.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>   
>   #define MT8192_TOPRGU_SW_RST_NUM				23
>   
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied thanks

> ---
>   include/dt-bindings/reset/mt8192-resets.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>   
>   #define MT8192_TOPRGU_SW_RST_NUM				23
>   
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

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Re: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Reset the DSI hardware is needed to prevent different settings between
> the bootloader and the kernel.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied thanks

> ---
>   include/dt-bindings/reset/mt8192-resets.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
> index be9a7ca245b9..764ca9910fa9 100644
> --- a/include/dt-bindings/reset/mt8192-resets.h
> +++ b/include/dt-bindings/reset/mt8192-resets.h
> @@ -27,4 +27,7 @@
>   
>   #define MT8192_TOPRGU_SW_RST_NUM				23
>   
> +/* MMSYS resets */
> +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
> +
>   #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

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Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 59183fb6c80b..08e0dd2483d1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -13,6 +13,7 @@
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>   #include <dt-bindings/reset/ti-syscon.h>
>   
>   / {
> @@ -1203,6 +1204,7 @@
>   			compatible = "mediatek,mt8192-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
>   			#clock-cells = <1>;
> +			#reset-cells = <1>;
>   		};
>   
>   		mutex: mutex@14001000 {
> @@ -1327,6 +1329,20 @@
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>   		};
>   
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";

We are missing the output port node.

Regards,
Matthias

> +		};
> +
>   		ovl_2l2: ovl@14014000 {
>   			compatible = "mediatek,mt8192-disp-ovl-2l";
>   			reg = <0 0x14014000 0 0x1000>;

Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 59183fb6c80b..08e0dd2483d1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -13,6 +13,7 @@
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>   #include <dt-bindings/reset/ti-syscon.h>
>   
>   / {
> @@ -1203,6 +1204,7 @@
>   			compatible = "mediatek,mt8192-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
>   			#clock-cells = <1>;
> +			#reset-cells = <1>;
>   		};
>   
>   		mutex: mutex@14001000 {
> @@ -1327,6 +1329,20 @@
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>   		};
>   
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";

We are missing the output port node.

Regards,
Matthias

> +		};
> +
>   		ovl_2l2: ovl@14014000 {
>   			compatible = "mediatek,mt8192-disp-ovl-2l";
>   			reg = <0 0x14014000 0 0x1000>;

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Re: [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add dsi ndoe for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 59183fb6c80b..08e0dd2483d1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -13,6 +13,7 @@
>   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8192-power.h>
> +#include <dt-bindings/reset/mt8192-resets.h>
>   #include <dt-bindings/reset/ti-syscon.h>
>   
>   / {
> @@ -1203,6 +1204,7 @@
>   			compatible = "mediatek,mt8192-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
>   			#clock-cells = <1>;
> +			#reset-cells = <1>;
>   		};
>   
>   		mutex: mutex@14001000 {
> @@ -1327,6 +1329,20 @@
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
>   		};
>   
> +		dsi0: dsi@14010000 {
> +			compatible = "mediatek,mt8183-dsi";
> +			reg = <0 0x14010000 0 0x1000>;
> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI_DSI0>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";

We are missing the output port node.

Regards,
Matthias

> +		};
> +
>   		ovl_2l2: ovl@14014000 {
>   			compatible = "mediatek,mt8192-disp-ovl-2l";
>   			reg = <0 0x14014000 0 0x1000>;

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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support
> 

What keeps us from adding that in the display nodes in patch 18/22 of this 
series? When doing so, please mention in the commit message that we then need to 
add the GCE to the mmsys node.

Regards,
Matthias

> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08e0dd2483d1..f0f0f067c023 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1203,6 +1203,9 @@
>   		mmsys: syscon@14000000 {
>   			compatible = "mediatek,mt8192-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>   			#clock-cells = <1>;
>   			#reset-cells = <1>;
>   		};
> @@ -1212,6 +1215,8 @@
>   			reg = <0 0x14001000 0 0x1000>;
>   			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>   			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
>   		};
>   
>   		smi_common: smi@14002000 {
> @@ -1253,6 +1258,7 @@
>   			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>   				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
>   		};
>   
>   		ovl_2l0: ovl@14006000 {
> @@ -1263,6 +1269,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>   				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
>   		};
>   
>   		rdma0: rdma@14007000 {
> @@ -1274,6 +1281,7 @@
>   			mediatek,larb = <&larb0>;
>   			mediatek,rdma-fifo-size = <5120>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
>   		};
>   
>   		color0: color@14009000 {
> @@ -1283,6 +1291,7 @@
>   			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>   		};
>   
>   		ccorr0: ccorr@1400a000 {
> @@ -1291,6 +1300,7 @@
>   			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>   		};
>   
>   		aal0: aal@1400b000 {
> @@ -1300,6 +1310,7 @@
>   			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>   		};
>   
>   		gamma0: gamma@1400c000 {
> @@ -1309,6 +1320,7 @@
>   			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>   		};
>   
>   		postmask0: postmask@1400d000 {
> @@ -1318,6 +1330,7 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>   			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>   		};
>   
>   		dither0: dither@1400e000 {
> @@ -1327,6 +1340,7 @@
>   			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>   		};
>   
>   		dsi0: dsi@14010000 {
> @@ -1351,6 +1365,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>   				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>   		};
>   
>   		rdma4: rdma@14015000 {
> @@ -1361,6 +1376,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>   			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>   			mediatek,rdma-fifo-size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>   		};
>   
>   		dpi0: dpi@14016000 {

Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support
> 

What keeps us from adding that in the display nodes in patch 18/22 of this 
series? When doing so, please mention in the commit message that we then need to 
add the GCE to the mmsys node.

Regards,
Matthias

> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08e0dd2483d1..f0f0f067c023 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1203,6 +1203,9 @@
>   		mmsys: syscon@14000000 {
>   			compatible = "mediatek,mt8192-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>   			#clock-cells = <1>;
>   			#reset-cells = <1>;
>   		};
> @@ -1212,6 +1215,8 @@
>   			reg = <0 0x14001000 0 0x1000>;
>   			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>   			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
>   		};
>   
>   		smi_common: smi@14002000 {
> @@ -1253,6 +1258,7 @@
>   			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>   				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
>   		};
>   
>   		ovl_2l0: ovl@14006000 {
> @@ -1263,6 +1269,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>   				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
>   		};
>   
>   		rdma0: rdma@14007000 {
> @@ -1274,6 +1281,7 @@
>   			mediatek,larb = <&larb0>;
>   			mediatek,rdma-fifo-size = <5120>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
>   		};
>   
>   		color0: color@14009000 {
> @@ -1283,6 +1291,7 @@
>   			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>   		};
>   
>   		ccorr0: ccorr@1400a000 {
> @@ -1291,6 +1300,7 @@
>   			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>   		};
>   
>   		aal0: aal@1400b000 {
> @@ -1300,6 +1310,7 @@
>   			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>   		};
>   
>   		gamma0: gamma@1400c000 {
> @@ -1309,6 +1320,7 @@
>   			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>   		};
>   
>   		postmask0: postmask@1400d000 {
> @@ -1318,6 +1330,7 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>   			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>   		};
>   
>   		dither0: dither@1400e000 {
> @@ -1327,6 +1340,7 @@
>   			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>   		};
>   
>   		dsi0: dsi@14010000 {
> @@ -1351,6 +1365,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>   				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>   		};
>   
>   		rdma4: rdma@14015000 {
> @@ -1361,6 +1376,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>   			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>   			mediatek,rdma-fifo-size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>   		};
>   
>   		dpi0: dpi@14016000 {

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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add gce info for display nodes
> - It's required to get drivers' CMDQ support
> 

What keeps us from adding that in the display nodes in patch 18/22 of this 
series? When doing so, please mention in the commit message that we then need to 
add the GCE to the mmsys node.

Regards,
Matthias

> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 08e0dd2483d1..f0f0f067c023 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1203,6 +1203,9 @@
>   		mmsys: syscon@14000000 {
>   			compatible = "mediatek,mt8192-mmsys", "syscon";
>   			reg = <0 0x14000000 0 0x1000>;
> +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>   			#clock-cells = <1>;
>   			#reset-cells = <1>;
>   		};
> @@ -1212,6 +1215,8 @@
>   			reg = <0 0x14001000 0 0x1000>;
>   			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
>   			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> +			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> +					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
>   		};
>   
>   		smi_common: smi@14002000 {
> @@ -1253,6 +1258,7 @@
>   			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
>   				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
>   		};
>   
>   		ovl_2l0: ovl@14006000 {
> @@ -1263,6 +1269,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
>   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
>   				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
>   		};
>   
>   		rdma0: rdma@14007000 {
> @@ -1274,6 +1281,7 @@
>   			mediatek,larb = <&larb0>;
>   			mediatek,rdma-fifo-size = <5120>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
>   		};
>   
>   		color0: color@14009000 {
> @@ -1283,6 +1291,7 @@
>   			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
>   		};
>   
>   		ccorr0: ccorr@1400a000 {
> @@ -1291,6 +1300,7 @@
>   			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
>   		};
>   
>   		aal0: aal@1400b000 {
> @@ -1300,6 +1310,7 @@
>   			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
>   		};
>   
>   		gamma0: gamma@1400c000 {
> @@ -1309,6 +1320,7 @@
>   			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
>   		};
>   
>   		postmask0: postmask@1400d000 {
> @@ -1318,6 +1330,7 @@
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
>   			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
>   		};
>   
>   		dither0: dither@1400e000 {
> @@ -1327,6 +1340,7 @@
>   			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
>   			power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
>   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
>   		};
>   
>   		dsi0: dsi@14010000 {
> @@ -1351,6 +1365,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
>   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
>   				 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
>   		};
>   
>   		rdma4: rdma@14015000 {
> @@ -1361,6 +1376,7 @@
>   			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
>   			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
>   			mediatek,rdma-fifo-size = <2048>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
>   		};
>   
>   		dpi0: dpi@14016000 {

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
>   			status = "disabled";
>   		};
>   
> +		pwm0: pwm@1100e000 {
> +			compatible = "mediatek,mt8183-disp-pwm";
> +			reg = <0 0x1100e000 0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;

Binding description is missing interrupt property. Remeber that the DT should 
describe the HW, so we need to update the binding description.
I just wonder what the IRQ signals, as it is not used by the driver. Definitely 
a good candidate to make the commit message more sound. So please add it there.

Thanks!
Matthias

> +			#pwm-cells = <2>;
> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> +				 <&infracfg CLK_INFRA_DISP_PWM>;
> +			clock-names = "main", "mm";
> +			status = "disabled";
> +		};
> +
>   		spi1: spi@11010000 {
>   			compatible = "mediatek,mt8192-spi",
>   				     "mediatek,mt6765-spi";

Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
>   			status = "disabled";
>   		};
>   
> +		pwm0: pwm@1100e000 {
> +			compatible = "mediatek,mt8183-disp-pwm";
> +			reg = <0 0x1100e000 0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;

Binding description is missing interrupt property. Remeber that the DT should 
describe the HW, so we need to update the binding description.
I just wonder what the IRQ signals, as it is not used by the driver. Definitely 
a good candidate to make the commit message more sound. So please add it there.

Thanks!
Matthias

> +			#pwm-cells = <2>;
> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> +				 <&infracfg CLK_INFRA_DISP_PWM>;
> +			clock-names = "main", "mm";
> +			status = "disabled";
> +		};
> +
>   		spi1: spi@11010000 {
>   			compatible = "mediatek,mt8192-spi",
>   				     "mediatek,mt6765-spi";

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Matthias Brugger]

On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
>   			status = "disabled";
>   		};
>   
> +		pwm0: pwm@1100e000 {
> +			compatible = "mediatek,mt8183-disp-pwm";
> +			reg = <0 0x1100e000 0 0x1000>;
> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;

Binding description is missing interrupt property. Remeber that the DT should 
describe the HW, so we need to update the binding description.
I just wonder what the IRQ signals, as it is not used by the driver. Definitely 
a good candidate to make the commit message more sound. So please add it there.

Thanks!
Matthias

> +			#pwm-cells = <2>;
> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> +				 <&infracfg CLK_INFRA_DISP_PWM>;
> +			clock-names = "main", "mm";
> +			status = "disabled";
> +		};
> +
>   		spi1: spi@11010000 {
>   			compatible = "mediatek,mt8192-spi",
>   				     "mediatek,mt6765-spi";

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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[allen-kh.cheng]

On Thu, 2022-03-24 at 09:57 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Mar 23, 2022 at 02:27:00PM +0800, allen-kh.cheng wrote:
> > Hi Nícolas,
> > 
> > On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> > > Hi Allen,
> > > 
> > > please see my comment below.
> > > 
> > > On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > > > Add infracfg_rst node for mt8192 SoC.
> > > >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > > > 
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18
> > > > ++++++++++++++++--
> > > >  1 file changed, 16 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index 40cf6dacca3e..82de1af3f6aa 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > @@ -12,6 +12,7 @@
> > > >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > > >  #include <dt-bindings/phy/phy.h>
> > > >  #include <dt-bindings/power/mt8192-power.h>
> > > > +#include <dt-bindings/reset/ti-syscon.h>
> > > >  
> > > >  / {
> > > >  	compatible = "mediatek,mt8192";
> > > > @@ -267,10 +268,23 @@
> > > >  			#clock-cells = <1>;
> > > >  		};
> > > >  
> > > > -		infracfg: syscon@10001000 {
> > > > -			compatible = "mediatek,mt8192-
> > > > infracfg",
> > > > "syscon";
> > > > +		infracfg: infracfg@10001000 {
> > > > +			compatible = "mediatek,mt8192-
> > > > infracfg",
> > > > "syscon", "simple-mfd";
> > > >  			reg = <0 0x10001000 0 0x1000>;
> > > >  			#clock-cells = <1>;
> > > > +
> > > > +			infracfg_rst: reset-controller {
> > > > +				compatible = "ti,syscon-reset";
> > > > +				#reset-cells = <1>;
> > > > +
> > > > +				ti,reset-bits = <
> > > > +					0x120 0 0x124 0 0 0	
> > > > (ASSERT_SET
> > > > > DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > > > 
> > > > +					0x730 12 0x734 12 0 0	
> > > > (AS
> > > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > > > +					0x140 15 0x144 15 0 0	
> > > > (AS
> > > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > > > +					0x730 1 0x734 1 0 0	
> > > > (ASSERT_SET
> > > > > DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > > > 
> > > > +					0x150 5 0x154 5 0 0	
> > > > (ASSERT_SET
> > > > > DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > > > 
> > > > +				>;
> > > 
> > > If you see [1], Rob has previously said that there shouldn't be
> > > new
> > > users of the
> > > ti,reset-bits property. I suggest doing like proposed on [2]:
> > > moving
> > > these bit
> > > definitions to the reset-ti-syscon driver, and have them selected
> > > through the
> > > compatible. You'd need to add a mt8192 specific compatible here
> > > too
> > > for that.
> > > 
> > > [1] 
> > > 
https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
> > >  
> > > [2] 
> > > 
https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
> > >  
> > > 
> > > Thanks,
> > > Nícolas
> > > 
> > 
> > Thanks for your comment.
> > 
> > For nfracfg_rst node, I prefer remove it from this series and
> > send another patch series(dts and driver).
> 
> Yes, that sounds the best approach to me as well.
> 
> > 
> > Based on [2], is it ok that we can add mt8192 compatible in reset-
> > ti
> > syscon driver? (even if mt8192 is a mediatek platform)
> 
> Actually, I think there's an even better way of handling this.
> Instead of using
> the TI syscon reset controller, you could give reset controller
> capabilities to
> the infracfg node directly. This means adding reset controller
> support to the
> common mtk clock driver (clk-mtk.c) and registering the reset
> controller on
> clk-mt8192.c for infracfg. By making this common code you'll also be
> able to
> reuse it for mt8195 as well. And there would no longer be a
> infracfg_rst node.
> 
> Thanks,
> Nícolas
> 

HI Nícolas,

Thanks for your suggestion.

We will send another patch for reset conroller.


Best regards,
Allenn

> > 
> > best regards,
> > Allen
> > 
> > > > +			};
> > > >  		};
> > > >  
> > > >  		pericfg: syscon@10003000 {
> > > > -- 
> > > > 2.18.0
> > > > 
> > > > 


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Re: [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node

[allen-kh.cheng]

On Thu, 2022-03-24 at 09:57 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Mar 23, 2022 at 02:27:00PM +0800, allen-kh.cheng wrote:
> > Hi Nícolas,
> > 
> > On Tue, 2022-03-22 at 17:57 -0400, Nícolas F. R. A. Prado wrote:
> > > Hi Allen,
> > > 
> > > please see my comment below.
> > > 
> > > On Fri, Mar 18, 2022 at 10:45:20PM +0800, Allen-KH Cheng wrote:
> > > > Add infracfg_rst node for mt8192 SoC.
> > > >  - Add simple-mfd to allow probing the ti,syscon-reset node.
> > > > 
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > >  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 18
> > > > ++++++++++++++++--
> > > >  1 file changed, 16 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index 40cf6dacca3e..82de1af3f6aa 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > @@ -12,6 +12,7 @@
> > > >  #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > > >  #include <dt-bindings/phy/phy.h>
> > > >  #include <dt-bindings/power/mt8192-power.h>
> > > > +#include <dt-bindings/reset/ti-syscon.h>
> > > >  
> > > >  / {
> > > >  	compatible = "mediatek,mt8192";
> > > > @@ -267,10 +268,23 @@
> > > >  			#clock-cells = <1>;
> > > >  		};
> > > >  
> > > > -		infracfg: syscon@10001000 {
> > > > -			compatible = "mediatek,mt8192-
> > > > infracfg",
> > > > "syscon";
> > > > +		infracfg: infracfg@10001000 {
> > > > +			compatible = "mediatek,mt8192-
> > > > infracfg",
> > > > "syscon", "simple-mfd";
> > > >  			reg = <0 0x10001000 0 0x1000>;
> > > >  			#clock-cells = <1>;
> > > > +
> > > > +			infracfg_rst: reset-controller {
> > > > +				compatible = "ti,syscon-reset";
> > > > +				#reset-cells = <1>;
> > > > +
> > > > +				ti,reset-bits = <
> > > > +					0x120 0 0x124 0 0 0	
> > > > (ASSERT_SET
> > > > > DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
> > > > 
> > > > +					0x730 12 0x734 12 0 0	
> > > > (AS
> > > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
> > > > +					0x140 15 0x144 15 0 0	
> > > > (AS
> > > > SERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: pcie phy */
> > > > +					0x730 1 0x734 1 0 0	
> > > > (ASSERT_SET
> > > > > DEASSERT_SET | STATUS_NONE) /* 3: pcie top */
> > > > 
> > > > +					0x150 5 0x154 5 0 0	
> > > > (ASSERT_SET
> > > > > DEASSERT_SET | STATUS_NONE) /* 4: svs */
> > > > 
> > > > +				>;
> > > 
> > > If you see [1], Rob has previously said that there shouldn't be
> > > new
> > > users of the
> > > ti,reset-bits property. I suggest doing like proposed on [2]:
> > > moving
> > > these bit
> > > definitions to the reset-ti-syscon driver, and have them selected
> > > through the
> > > compatible. You'd need to add a mt8192 specific compatible here
> > > too
> > > for that.
> > > 
> > > [1] 
> > > 
https://urldefense.com/v3/__https://lore.kernel.org/all/CAL_JsqJq6gqoXtvG1U7UDsOQpz7oMLMunZHq2njN6nvPr8PZMA@mail.gmail.com/__;!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OABdRVOzg$
> > >  
> > > [2] 
> > > 
https://urldefense.com/v3/__https://lore.kernel.org/all/CAATdQgA5pKhjOf5gxo*h7cs7kCts3DeKGU5axeX2t*OaJFHyBg@mail.gmail.com/__;Kys!!CTRNKA9wMg0ARbw!1wQAhHnu8bAxe2O51XZ61oWVQU7EFEZcgluzwgP4x4VHRxtb6kAySvsKCGzv8cs8IzVjanDNzBQvOa_Y4OBLvOYlyQ$
> > >  
> > > 
> > > Thanks,
> > > Nícolas
> > > 
> > 
> > Thanks for your comment.
> > 
> > For nfracfg_rst node, I prefer remove it from this series and
> > send another patch series(dts and driver).
> 
> Yes, that sounds the best approach to me as well.
> 
> > 
> > Based on [2], is it ok that we can add mt8192 compatible in reset-
> > ti
> > syscon driver? (even if mt8192 is a mediatek platform)
> 
> Actually, I think there's an even better way of handling this.
> Instead of using
> the TI syscon reset controller, you could give reset controller
> capabilities to
> the infracfg node directly. This means adding reset controller
> support to the
> common mtk clock driver (clk-mtk.c) and registering the reset
> controller on
> clk-mt8192.c for infracfg. By making this common code you'll also be
> able to
> reuse it for mt8195 as well. And there would no longer be a
> infracfg_rst node.
> 
> Thanks,
> Nícolas
> 

HI Nícolas,

Thanks for your suggestion.

We will send another patch for reset conroller.


Best regards,
Allenn

> > 
> > best regards,
> > Allen
> > 
> > > > +			};
> > > >  		};
> > > >  
> > > >  		pericfg: syscon@10003000 {
> > > > -- 
> > > > 2.18.0
> > > > 
> > > > 


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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[allen-kh.cheng]

Hi Matthias,

On Thu, 2022-03-24 at 18:44 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add PCIe node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38
> > ++++++++++++++++++++++++
> >   1 file changed, 38 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 82de1af3f6aa..3a7f93d8eeaa 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -884,6 +884,44 @@
> >   			};
> >   		};
> >   
> > +		pcie: pcie@11230000 {
> > +			compatible = "mediatek,mt8192-pcie";
> > +			device_type = "pci";
> > +			reg = <0 0x11230000 0 0x2000>;
> > +			reg-names = "pcie-mac";
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> > +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> > +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> > +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> > +				      "obff_ck0", "axi_ck0",
> > "pipe_ck0";
> 
> Also not mandated by the bindings nor the driver clock-names don't
> match the 
> binding. How comes? Shall we update the bindings to have more sound
> names?
> 
> Regards,
> Matthias
> 

Thanks for your reminder.

You're right. The driver clock-names are wrong.

I will correct those in next version.

Best regards,
Allen 

> > +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D6_D4>;
> > +			resets = <&infracfg_rst 2>,
> > +				 <&infracfg_rst 3>;
> > +			reset-names = "phy", "mac";
> > +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			bus-range = <0x00 0xff>;
> > +			ranges = <0x82000000 0 0x12000000 0x0
> > 0x12000000 0 0x0800000>,
> > +				 <0x81000000 0 0x12800000 0x0
> > 0x12800000 0 0x0800000>;
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 7>;
> > +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> > +					<0 0 0 2 &pcie_intc0 1>,
> > +					<0 0 0 3 &pcie_intc0 2>,
> > +					<0 0 0 4 &pcie_intc0 3>;
> > +
> > +			pcie_intc0: interrupt-controller {
> > +				interrupt-controller;
> > +				#address-cells = <0>;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> >   		nor_flash: spi@11234000 {
> >   			compatible = "mediatek,mt8192-nor";
> >   			reg = <0 0x11234000 0 0xe0>;


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Re: [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node

[allen-kh.cheng]

Hi Matthias,

On Thu, 2022-03-24 at 18:44 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add PCIe node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 38
> > ++++++++++++++++++++++++
> >   1 file changed, 38 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 82de1af3f6aa..3a7f93d8eeaa 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -884,6 +884,44 @@
> >   			};
> >   		};
> >   
> > +		pcie: pcie@11230000 {
> > +			compatible = "mediatek,mt8192-pcie";
> > +			device_type = "pci";
> > +			reg = <0 0x11230000 0 0x2000>;
> > +			reg-names = "pcie-mac";
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +			clocks = <&infracfg CLK_INFRA_PCIE_TL_26M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_96M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TL_32K>,
> > +				 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
> > +				 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>,
> > +				 <&infracfg CLK_INFRA_PCIE_PL_P_250M>;
> > +			clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> > +				      "obff_ck0", "axi_ck0",
> > "pipe_ck0";
> 
> Also not mandated by the bindings nor the driver clock-names don't
> match the 
> binding. How comes? Shall we update the bindings to have more sound
> names?
> 
> Regards,
> Matthias
> 

Thanks for your reminder.

You're right. The driver clock-names are wrong.

I will correct those in next version.

Best regards,
Allen 

> > +			assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D6_D4>;
> > +			resets = <&infracfg_rst 2>,
> > +				 <&infracfg_rst 3>;
> > +			reset-names = "phy", "mac";
> > +			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			bus-range = <0x00 0xff>;
> > +			ranges = <0x82000000 0 0x12000000 0x0
> > 0x12000000 0 0x0800000>,
> > +				 <0x81000000 0 0x12800000 0x0
> > 0x12800000 0 0x0800000>;
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 7>;
> > +			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> > +					<0 0 0 2 &pcie_intc0 1>,
> > +					<0 0 0 3 &pcie_intc0 2>,
> > +					<0 0 0 4 &pcie_intc0 3>;
> > +
> > +			pcie_intc0: interrupt-controller {
> > +				interrupt-controller;
> > +				#address-cells = <0>;
> > +				#interrupt-cells = <1>;
> > +			};
> > +		};
> > +
> >   		nor_flash: spi@11234000 {
> >   			compatible = "mediatek,mt8192-nor";
> >   			reg = <0 0x11234000 0 0xe0>;


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Re: [PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[allen-kh.cheng]

Hi Matthias,

On Thu, 2022-03-24 at 15:45 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add audio-related nodes in audsys for mt8192 SoC.
> >   - Move audsys node in ascending order.
> >   - Increase the address range's length from 0x1000 to 0x2000.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134
> > ++++++++++++++++++++++-
> >   1 file changed, 128 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 6bc36a4076f4..40cf6dacca3e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -742,6 +742,134 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		audsys: syscon@11210000 {
> > +			compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > +			reg = <0 0x11210000 0 0x2000>;
> > +			#clock-cells = <1>;
> 
> New line here please.
> 

ok.

> > +			afe: mt8192-afe-pcm {
> > +				compatible = "mediatek,mt8192-audio";
> > +				interrupts = <GIC_SPI 202
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				resets = <&watchdog 17>;
> > +				reset-names = "audiosys";
> > +				mediatek,apmixedsys = <&apmixedsys>;
> > +				mediatek,infracfg = <&infracfg>;
> > +				mediatek,topckgen = <&topckgen>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_AUDIO>;
> > +				clocks = <&audsys CLK_AUD_AFE>,
> 
> There are many more clocks then in the bindings, can please fix that.
> 
> Regards,
> Matthias
> 

About those clock names, we will send anther patch for bindings
(mt8192-afe-pcm.yam).

Thanks,
Allen

> > +					 <&audsys CLK_AUD_DAC>,
> > +					 <&audsys CLK_AUD_DAC_PREDIS>,
> > +					 <&audsys CLK_AUD_ADC>,
> > +					 <&audsys CLK_AUD_ADDA6_ADC>,
> > +					 <&audsys CLK_AUD_22M>,
> > +					 <&audsys CLK_AUD_24M>,
> > +					 <&audsys CLK_AUD_APLL_TUNER>,
> > +					 <&audsys CLK_AUD_APLL2_TUNER>,
> > +					 <&audsys CLK_AUD_TDM>,
> > +					 <&audsys CLK_AUD_TML>,
> > +					 <&audsys CLK_AUD_NLE>,
> > +					 <&audsys CLK_AUD_DAC_HIRES>,
> > +					 <&audsys CLK_AUD_ADC_HIRES>,
> > +					 <&audsys
> > CLK_AUD_ADC_HIRES_TML>,
> > +					 <&audsys
> > CLK_AUD_ADDA6_ADC_HIRES>,
> > +					 <&audsys CLK_AUD_3RD_DAC>,
> > +					 <&audsys
> > CLK_AUD_3RD_DAC_PREDIS>,
> > +					 <&audsys CLK_AUD_3RD_DAC_TML>,
> > +					 <&audsys
> > CLK_AUD_3RD_DAC_HIRES>,
> > +					 <&infracfg CLK_INFRA_AUDIO>,
> > +					 <&infracfg
> > CLK_INFRA_AUDIO_26M_B>,
> > +					 <&topckgen CLK_TOP_AUDIO_SEL>,
> > +					 <&topckgen
> > CLK_TOP_AUD_INTBUS_SEL>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4_D4>,
> > +					 <&topckgen CLK_TOP_AUD_1_SEL>,
> > +					 <&topckgen CLK_TOP_APLL1>,
> > +					 <&topckgen CLK_TOP_AUD_2_SEL>,
> > +					 <&topckgen CLK_TOP_APLL2>,
> > +					 <&topckgen
> > CLK_TOP_AUD_ENGEN1_SEL>,
> > +					 <&topckgen CLK_TOP_APLL1_D4>,
> > +					 <&topckgen
> > CLK_TOP_AUD_ENGEN2_SEL>,
> > +					 <&topckgen CLK_TOP_APLL2_D4>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S0_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S1_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S2_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S3_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S4_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S5_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S6_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S7_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S8_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S9_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV0>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV1>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV2>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV3>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV4>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIVB>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV5>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV6>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV7>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV8>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV9>,
> > +					 <&topckgen
> > CLK_TOP_AUDIO_H_SEL>,
> > +					 <&clk26m>;
> > +				clock-names = "aud_afe_clk",
> > +					      "aud_dac_clk",
> > +					      "aud_dac_predis_clk",
> > +					      "aud_adc_clk",
> > +					      "aud_adda6_adc_clk",
> > +					      "aud_apll22m_clk",
> > +					      "aud_apll24m_clk",
> > +					      "aud_apll1_tuner_clk",
> > +					      "aud_apll2_tuner_clk",
> > +					      "aud_tdm_clk",
> > +					      "aud_tml_clk",
> > +					      "aud_nle",
> > +					      "aud_dac_hires_clk",
> > +					      "aud_adc_hires_clk",
> > +					      "aud_adc_hires_tml",
> > +					      "aud_adda6_adc_hires_clk"
> > ,
> > +					      "aud_3rd_dac_clk",
> > +					      "aud_3rd_dac_predis_clk",
> > +					      "aud_3rd_dac_tml",
> > +					      "aud_3rd_dac_hires_clk",
> > +					      "aud_infra_clk",
> > +					      "aud_infra_26m_clk",
> > +					      "top_mux_audio",
> > +					      "top_mux_audio_int",
> > +					      "top_mainpll_d4_d4",
> > +					      "top_mux_aud_1",
> > +					      "top_apll1_ck",
> > +					      "top_mux_aud_2",
> > +					      "top_apll2_ck",
> > +					      "top_mux_aud_eng1",
> > +					      "top_apll1_d4",
> > +					      "top_mux_aud_eng2",
> > +					      "top_apll2_d4",
> > +					      "top_i2s0_m_sel",
> > +					      "top_i2s1_m_sel",
> > +					      "top_i2s2_m_sel",
> > +					      "top_i2s3_m_sel",
> > +					      "top_i2s4_m_sel",
> > +					      "top_i2s5_m_sel",
> > +					      "top_i2s6_m_sel",
> > +					      "top_i2s7_m_sel",
> > +					      "top_i2s8_m_sel",
> > +					      "top_i2s9_m_sel",
> > +					      "top_apll12_div0",
> > +					      "top_apll12_div1",
> > +					      "top_apll12_div2",
> > +					      "top_apll12_div3",
> > +					      "top_apll12_div4",
> > +					      "top_apll12_divb",
> > +					      "top_apll12_div5",
> > +					      "top_apll12_div6",
> > +					      "top_apll12_div7",
> > +					      "top_apll12_div8",
> > +					      "top_apll12_div9",
> > +					      "top_mux_audio_h",
> > +					      "top_clk26m_clk";
> > +			};
> > +		};
> > +
> >   		nor_flash: spi@11234000 {
> >   			compatible = "mediatek,mt8192-nor";
> >   			reg = <0 0x11234000 0 0xe0>;
> > @@ -757,12 +885,6 @@
> >   			status = "disable";
> >   		};
> >   
> > -		audsys: clock-controller@11210000 {
> > -			compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > -			reg = <0 0x11210000 0 0x1000>;
> > -			#clock-cells = <1>;
> > -		};
> > -
> >   		i2c3: i2c@11cb0000 {
> >   			compatible = "mediatek,mt8192-i2c";
> >   			reg = <0 0x11cb0000 0 0x1000>,


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Re: [PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes

[allen-kh.cheng]

Hi Matthias,

On Thu, 2022-03-24 at 15:45 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add audio-related nodes in audsys for mt8192 SoC.
> >   - Move audsys node in ascending order.
> >   - Increase the address range's length from 0x1000 to 0x2000.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134
> > ++++++++++++++++++++++-
> >   1 file changed, 128 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 6bc36a4076f4..40cf6dacca3e 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -742,6 +742,134 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		audsys: syscon@11210000 {
> > +			compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > +			reg = <0 0x11210000 0 0x2000>;
> > +			#clock-cells = <1>;
> 
> New line here please.
> 

ok.

> > +			afe: mt8192-afe-pcm {
> > +				compatible = "mediatek,mt8192-audio";
> > +				interrupts = <GIC_SPI 202
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				resets = <&watchdog 17>;
> > +				reset-names = "audiosys";
> > +				mediatek,apmixedsys = <&apmixedsys>;
> > +				mediatek,infracfg = <&infracfg>;
> > +				mediatek,topckgen = <&topckgen>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_AUDIO>;
> > +				clocks = <&audsys CLK_AUD_AFE>,
> 
> There are many more clocks then in the bindings, can please fix that.
> 
> Regards,
> Matthias
> 

About those clock names, we will send anther patch for bindings
(mt8192-afe-pcm.yam).

Thanks,
Allen

> > +					 <&audsys CLK_AUD_DAC>,
> > +					 <&audsys CLK_AUD_DAC_PREDIS>,
> > +					 <&audsys CLK_AUD_ADC>,
> > +					 <&audsys CLK_AUD_ADDA6_ADC>,
> > +					 <&audsys CLK_AUD_22M>,
> > +					 <&audsys CLK_AUD_24M>,
> > +					 <&audsys CLK_AUD_APLL_TUNER>,
> > +					 <&audsys CLK_AUD_APLL2_TUNER>,
> > +					 <&audsys CLK_AUD_TDM>,
> > +					 <&audsys CLK_AUD_TML>,
> > +					 <&audsys CLK_AUD_NLE>,
> > +					 <&audsys CLK_AUD_DAC_HIRES>,
> > +					 <&audsys CLK_AUD_ADC_HIRES>,
> > +					 <&audsys
> > CLK_AUD_ADC_HIRES_TML>,
> > +					 <&audsys
> > CLK_AUD_ADDA6_ADC_HIRES>,
> > +					 <&audsys CLK_AUD_3RD_DAC>,
> > +					 <&audsys
> > CLK_AUD_3RD_DAC_PREDIS>,
> > +					 <&audsys CLK_AUD_3RD_DAC_TML>,
> > +					 <&audsys
> > CLK_AUD_3RD_DAC_HIRES>,
> > +					 <&infracfg CLK_INFRA_AUDIO>,
> > +					 <&infracfg
> > CLK_INFRA_AUDIO_26M_B>,
> > +					 <&topckgen CLK_TOP_AUDIO_SEL>,
> > +					 <&topckgen
> > CLK_TOP_AUD_INTBUS_SEL>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4_D4>,
> > +					 <&topckgen CLK_TOP_AUD_1_SEL>,
> > +					 <&topckgen CLK_TOP_APLL1>,
> > +					 <&topckgen CLK_TOP_AUD_2_SEL>,
> > +					 <&topckgen CLK_TOP_APLL2>,
> > +					 <&topckgen
> > CLK_TOP_AUD_ENGEN1_SEL>,
> > +					 <&topckgen CLK_TOP_APLL1_D4>,
> > +					 <&topckgen
> > CLK_TOP_AUD_ENGEN2_SEL>,
> > +					 <&topckgen CLK_TOP_APLL2_D4>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S0_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S1_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S2_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S3_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S4_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S5_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S6_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S7_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S8_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL_I2S9_M_SEL>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV0>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV1>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV2>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV3>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV4>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIVB>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV5>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV6>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV7>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV8>,
> > +					 <&topckgen
> > CLK_TOP_APLL12_DIV9>,
> > +					 <&topckgen
> > CLK_TOP_AUDIO_H_SEL>,
> > +					 <&clk26m>;
> > +				clock-names = "aud_afe_clk",
> > +					      "aud_dac_clk",
> > +					      "aud_dac_predis_clk",
> > +					      "aud_adc_clk",
> > +					      "aud_adda6_adc_clk",
> > +					      "aud_apll22m_clk",
> > +					      "aud_apll24m_clk",
> > +					      "aud_apll1_tuner_clk",
> > +					      "aud_apll2_tuner_clk",
> > +					      "aud_tdm_clk",
> > +					      "aud_tml_clk",
> > +					      "aud_nle",
> > +					      "aud_dac_hires_clk",
> > +					      "aud_adc_hires_clk",
> > +					      "aud_adc_hires_tml",
> > +					      "aud_adda6_adc_hires_clk"
> > ,
> > +					      "aud_3rd_dac_clk",
> > +					      "aud_3rd_dac_predis_clk",
> > +					      "aud_3rd_dac_tml",
> > +					      "aud_3rd_dac_hires_clk",
> > +					      "aud_infra_clk",
> > +					      "aud_infra_26m_clk",
> > +					      "top_mux_audio",
> > +					      "top_mux_audio_int",
> > +					      "top_mainpll_d4_d4",
> > +					      "top_mux_aud_1",
> > +					      "top_apll1_ck",
> > +					      "top_mux_aud_2",
> > +					      "top_apll2_ck",
> > +					      "top_mux_aud_eng1",
> > +					      "top_apll1_d4",
> > +					      "top_mux_aud_eng2",
> > +					      "top_apll2_d4",
> > +					      "top_i2s0_m_sel",
> > +					      "top_i2s1_m_sel",
> > +					      "top_i2s2_m_sel",
> > +					      "top_i2s3_m_sel",
> > +					      "top_i2s4_m_sel",
> > +					      "top_i2s5_m_sel",
> > +					      "top_i2s6_m_sel",
> > +					      "top_i2s7_m_sel",
> > +					      "top_i2s8_m_sel",
> > +					      "top_i2s9_m_sel",
> > +					      "top_apll12_div0",
> > +					      "top_apll12_div1",
> > +					      "top_apll12_div2",
> > +					      "top_apll12_div3",
> > +					      "top_apll12_div4",
> > +					      "top_apll12_divb",
> > +					      "top_apll12_div5",
> > +					      "top_apll12_div6",
> > +					      "top_apll12_div7",
> > +					      "top_apll12_div8",
> > +					      "top_apll12_div9",
> > +					      "top_mux_audio_h",
> > +					      "top_clk26m_clk";
> > +			};
> > +		};
> > +
> >   		nor_flash: spi@11234000 {
> >   			compatible = "mediatek,mt8192-nor";
> >   			reg = <0 0x11234000 0 0xe0>;
> > @@ -757,12 +885,6 @@
> >   			status = "disable";
> >   		};
> >   
> > -		audsys: clock-controller@11210000 {
> > -			compatible = "mediatek,mt8192-audsys",
> > "syscon";
> > -			reg = <0 0x11210000 0 0x1000>;
> > -			#clock-cells = <1>;
> > -		};
> > -
> >   		i2c3: i2c@11cb0000 {
> >   			compatible = "mediatek,mt8192-i2c";
> >   			reg = <0 0x11cb0000 0 0x1000>,


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Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[allen-kh.cheng]

Hi Matthias,

On Thu, 2022-03-24 at 18:53 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add mmc nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
> > +++++++++++++++++++++---
> >   1 file changed, 30 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 6220d6962f58..2648f2847993 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1150,10 +1150,36 @@
> >   			#clock-cells = <1>;
> >   		};
> >   
> > -		msdc: clock-controller@11f60000 {
> > -			compatible = "mediatek,mt8192-msdc";
> > -			reg = <0 0x11f60000 0 0x1000>;
> > -			#clock-cells = <1>;
> 
> We don't need the msdc_axi_wrap clock and that's why we delete the
> node, 
> correct? In that case we could only disable the node, as DTS should
> describe the 
> HW as it is. Please also add a line in the commit message explaining
> that.
> 
> Regards,
> Matthias
> 

Yes, in mt8192, mmc driver don't need msdc clock.

I will disable msdc node and mention it in commit message in next
version.

Thanks,
Allen

> > +		mmc0: mmc@11f60000 {
> > +			compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0
> > 0x1000>;
> > +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> > +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> > +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> > +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> > +				 <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> > +			clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > +				      "pclk_cg", "axi_cg", "ahb_cg";
> > +			status = "disabled";
> > +		};
> > +
> > +		mmc1: mmc@11f70000 {
> > +			compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0
> > 0x1000>;
> > +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> > +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> > +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> > +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> > +				 <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> > +			clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > +				      "pclk_cg", "axi_cg", "ahb_cg";
> > +			status = "disabled";
> >   		};
> >   
> >   		mfgcfg: clock-controller@13fbf000 {


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Re: [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes

[allen-kh.cheng]

Hi Matthias,

On Thu, 2022-03-24 at 18:53 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add mmc nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
> > +++++++++++++++++++++---
> >   1 file changed, 30 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 6220d6962f58..2648f2847993 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1150,10 +1150,36 @@
> >   			#clock-cells = <1>;
> >   		};
> >   
> > -		msdc: clock-controller@11f60000 {
> > -			compatible = "mediatek,mt8192-msdc";
> > -			reg = <0 0x11f60000 0 0x1000>;
> > -			#clock-cells = <1>;
> 
> We don't need the msdc_axi_wrap clock and that's why we delete the
> node, 
> correct? In that case we could only disable the node, as DTS should
> describe the 
> HW as it is. Please also add a line in the commit message explaining
> that.
> 
> Regards,
> Matthias
> 

Yes, in mt8192, mmc driver don't need msdc clock.

I will disable msdc node and mention it in commit message in next
version.

Thanks,
Allen

> > +		mmc0: mmc@11f60000 {
> > +			compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > +			reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0
> > 0x1000>;
> > +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> > +				 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
> > +				 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
> > +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> > +				 <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> > +			clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > +				      "pclk_cg", "axi_cg", "ahb_cg";
> > +			status = "disabled";
> > +		};
> > +
> > +		mmc1: mmc@11f70000 {
> > +			compatible = "mediatek,mt8192-mmc",
> > "mediatek,mt8183-mmc";
> > +			reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0
> > 0x1000>;
> > +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> > +				 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
> > +				 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_CFG>,
> > +				 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
> > +				 <&msdc_top CLK_MSDC_TOP_AXI>,
> > +				 <&msdc_top
> > CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
> > +			clock-names = "source", "hclk", "source_cg",
> > "sys_cg",
> > +				      "pclk_cg", "axi_cg", "ahb_cg";
> > +			status = "disabled";
> >   		};
> >   
> >   		mfgcfg: clock-controller@13fbf000 {


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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[allen-kh.cheng]

Hi Matthias,

On Mon, 2022-03-28 at 13:10 +0200, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add pwm node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
> >   1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f0f0f067c023..ea98b2230f18 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -625,6 +625,17 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		pwm0: pwm@1100e000 {
> > +			compatible = "mediatek,mt8183-disp-pwm";
> > +			reg = <0 0x1100e000 0 0x1000>;
> > +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> 
> Binding description is missing interrupt property. Remeber that the
> DT should 
> describe the HW, so we need to update the binding description.
> I just wonder what the IRQ signals, as it is not used by the driver.
> Definitely 
> a good candidate to make the commit message more sound. So please add
> it there.
> 
> Thanks!
> Matthias
> 

For interrupt property, we will send anther patch to update binding
and add some information for IRQ into commit message in next version. 

Thanks,
Allen

> > +			#pwm-cells = <2>;
> > +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> > +				 <&infracfg CLK_INFRA_DISP_PWM>;
> > +			clock-names = "main", "mm";
> > +			status = "disabled";
> > +		};
> > +
> >   		spi1: spi@11010000 {
> >   			compatible = "mediatek,mt8192-spi",
> >   				     "mediatek,mt6765-spi";


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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[allen-kh.cheng]

Hi Matthias,

On Mon, 2022-03-28 at 13:10 +0200, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add pwm node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
> >   1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index f0f0f067c023..ea98b2230f18 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -625,6 +625,17 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		pwm0: pwm@1100e000 {
> > +			compatible = "mediatek,mt8183-disp-pwm";
> > +			reg = <0 0x1100e000 0 0x1000>;
> > +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> 
> Binding description is missing interrupt property. Remeber that the
> DT should 
> describe the HW, so we need to update the binding description.
> I just wonder what the IRQ signals, as it is not used by the driver.
> Definitely 
> a good candidate to make the commit message more sound. So please add
> it there.
> 
> Thanks!
> Matthias
> 

For interrupt property, we will send anther patch to update binding
and add some information for IRQ into commit message in next version. 

Thanks,
Allen

> > +			#pwm-cells = <2>;
> > +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> > +				 <&infracfg CLK_INFRA_DISP_PWM>;
> > +			clock-names = "main", "mm";
> > +			status = "disabled";
> > +		};
> > +
> >   		spi1: spi@11010000 {
> >   			compatible = "mediatek,mt8192-spi",
> >   				     "mediatek,mt6765-spi";


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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[allen-kh.cheng]

Hi

On Mon, 2022-03-28 at 13:06 +0200, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add gce info for display nodes
> > - It's required to get drivers' CMDQ support
> > 
> 
> What keeps us from adding that in the display nodes in patch 18/22 of
> this 
> series? When doing so, please mention in the commit message that we
> then need to 
> add the GCE to the mmsys node.
> 
> Regards,
> Matthias
> 

There is no particular reason for this patch.

I will squash this patch into 18/22([PATCH v4 18/22] arm64: dts:
mt8192: Add display nodes)


Thanks,
Allen

> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> >   1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 08e0dd2483d1..f0f0f067c023 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1203,6 +1203,9 @@
> >   		mmsys: syscon@14000000 {
> >   			compatible = "mediatek,mt8192-mmsys", "syscon";
> >   			reg = <0 0x14000000 0 0x1000>;
> > +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> >   			#clock-cells = <1>;
> >   			#reset-cells = <1>;
> >   		};
> > @@ -1212,6 +1215,8 @@
> >   			reg = <0 0x14001000 0 0x1000>;
> >   			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +			mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > +					      <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> >   		};
> >   
> >   		smi_common: smi@14002000 {
> > @@ -1253,6 +1258,7 @@
> >   			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> >   				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> >   		};
> >   
> >   		ovl_2l0: ovl@14006000 {
> > @@ -1263,6 +1269,7 @@
> >   			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> >   				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> >   		};
> >   
> >   		rdma0: rdma@14007000 {
> > @@ -1274,6 +1281,7 @@
> >   			mediatek,larb = <&larb0>;
> >   			mediatek,rdma-fifo-size = <5120>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x7000 0x1000>;
> >   		};
> >   
> >   		color0: color@14009000 {
> > @@ -1283,6 +1291,7 @@
> >   			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x9000 0x1000>;
> >   		};
> >   
> >   		ccorr0: ccorr@1400a000 {
> > @@ -1291,6 +1300,7 @@
> >   			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xa000 0x1000>;
> >   		};
> >   
> >   		aal0: aal@1400b000 {
> > @@ -1300,6 +1310,7 @@
> >   			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xb000 0x1000>;
> >   		};
> >   
> >   		gamma0: gamma@1400c000 {
> > @@ -1309,6 +1320,7 @@
> >   			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xc000 0x1000>;
> >   		};
> >   
> >   		postmask0: postmask@1400d000 {
> > @@ -1318,6 +1330,7 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> >   			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xd000 0x1000>;
> >   		};
> >   
> >   		dither0: dither@1400e000 {
> > @@ -1327,6 +1340,7 @@
> >   			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xe000 0x1000>;
> >   		};
> >   
> >   		dsi0: dsi@14010000 {
> > @@ -1351,6 +1365,7 @@
> >   			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> >   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> >   				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x4000 0x1000>;
> >   		};
> >   
> >   		rdma4: rdma@14015000 {
> > @@ -1361,6 +1376,7 @@
> >   			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> >   			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> >   			mediatek,rdma-fifo-size = <2048>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x5000 0x1000>;
> >   		};
> >   
> >   		dpi0: dpi@14016000 {


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Re: [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes

[allen-kh.cheng]

Hi

On Mon, 2022-03-28 at 13:06 +0200, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add gce info for display nodes
> > - It's required to get drivers' CMDQ support
> > 
> 
> What keeps us from adding that in the display nodes in patch 18/22 of
> this 
> series? When doing so, please mention in the commit message that we
> then need to 
> add the GCE to the mmsys node.
> 
> Regards,
> Matthias
> 

There is no particular reason for this patch.

I will squash this patch into 18/22([PATCH v4 18/22] arm64: dts:
mt8192: Add display nodes)


Thanks,
Allen

> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 16 ++++++++++++++++
> >   1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 08e0dd2483d1..f0f0f067c023 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1203,6 +1203,9 @@
> >   		mmsys: syscon@14000000 {
> >   			compatible = "mediatek,mt8192-mmsys", "syscon";
> >   			reg = <0 0x14000000 0 0x1000>;
> > +			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> > +				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> >   			#clock-cells = <1>;
> >   			#reset-cells = <1>;
> >   		};
> > @@ -1212,6 +1215,8 @@
> >   			reg = <0 0x14001000 0 0x1000>;
> >   			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> > +			mediatek,gce-events =
> > <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> > +					      <CMDQ_EVENT_DISP_STREAM_D
> > ONE_ENG_EVENT_1>;
> >   		};
> >   
> >   		smi_common: smi@14002000 {
> > @@ -1253,6 +1258,7 @@
> >   			iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> >   				 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> >   		};
> >   
> >   		ovl_2l0: ovl@14006000 {
> > @@ -1263,6 +1269,7 @@
> >   			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> >   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> >   				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> >   		};
> >   
> >   		rdma0: rdma@14007000 {
> > @@ -1274,6 +1281,7 @@
> >   			mediatek,larb = <&larb0>;
> >   			mediatek,rdma-fifo-size = <5120>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x7000 0x1000>;
> >   		};
> >   
> >   		color0: color@14009000 {
> > @@ -1283,6 +1291,7 @@
> >   			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x9000 0x1000>;
> >   		};
> >   
> >   		ccorr0: ccorr@1400a000 {
> > @@ -1291,6 +1300,7 @@
> >   			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xa000 0x1000>;
> >   		};
> >   
> >   		aal0: aal@1400b000 {
> > @@ -1300,6 +1310,7 @@
> >   			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_AAL0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xb000 0x1000>;
> >   		};
> >   
> >   		gamma0: gamma@1400c000 {
> > @@ -1309,6 +1320,7 @@
> >   			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xc000 0x1000>;
> >   		};
> >   
> >   		postmask0: postmask@1400d000 {
> > @@ -1318,6 +1330,7 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> >   			iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xd000 0x1000>;
> >   		};
> >   
> >   		dither0: dither@1400e000 {
> > @@ -1327,6 +1340,7 @@
> >   			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0xe000 0x1000>;
> >   		};
> >   
> >   		dsi0: dsi@14010000 {
> > @@ -1351,6 +1365,7 @@
> >   			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> >   			iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> >   				 <&iommu0
> > M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x4000 0x1000>;
> >   		};
> >   
> >   		rdma4: rdma@14015000 {
> > @@ -1361,6 +1376,7 @@
> >   			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> >   			iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> >   			mediatek,rdma-fifo-size = <2048>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x5000 0x1000>;
> >   		};
> >   
> >   		dpi0: dpi@14016000 {


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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[allen-kh.cheng]

Hi Matthias,

On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add dpi node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
> >   1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 71ad3adeed51..a77d405dd508 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1236,6 +1236,17 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   		};
> >   
> > +		dpi0: dpi@14016000 {
> > +			compatible = "mediatek,mt8192-dpi";
> > +			reg = <0 0x14016000 0 0x1000>;
> > +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
> > +				 <&mmsys CLK_MM_DISP_DPI0>,
> > +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
> > +			clock-names = "pixel", "engine", "pll";
> > +			status = "disabled";
> 
> We are missing the output port node here.
> 
> Regards,
> Matthias
> 

We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for
board level.

Do we need to add any futher information in binding?

Thanks,
Allen

> > +		};
> > +
> >   		iommu0: m4u@1401d000 {
> >   			compatible = "mediatek,mt8192-m4u";
> >   			reg = <0 0x1401d000 0 0x1000>;


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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[allen-kh.cheng]

Hi Matthias,

On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add dpi node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
> >   1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 71ad3adeed51..a77d405dd508 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1236,6 +1236,17 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_DISP>;
> >   		};
> >   
> > +		dpi0: dpi@14016000 {
> > +			compatible = "mediatek,mt8192-dpi";
> > +			reg = <0 0x14016000 0 0x1000>;
> > +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
> > +				 <&mmsys CLK_MM_DISP_DPI0>,
> > +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
> > +			clock-names = "pixel", "engine", "pll";
> > +			status = "disabled";
> 
> We are missing the output port node here.
> 
> Regards,
> Matthias
> 

We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for
board level.

Do we need to add any futher information in binding?

Thanks,
Allen

> > +		};
> > +
> >   		iommu0: m4u@1401d000 {
> >   			compatible = "mediatek,mt8192-m4u";
> >   			reg = <0 0x1401d000 0 0x1000>;


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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[allen-kh.cheng]

Hi Matthias,

On Fri, 2022-03-25 at 16:22 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61
> > ++++++++++++++++++++++++
> >   1 file changed, 61 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 63893779b193..71ad3adeed51 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1285,6 +1285,67 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> >   		};
> >   
> > +		vcodec_dec: vcodec-dec@16000000 {
> > +			compatible = "mediatek,mt8192-vcodec-dec";
> > +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS
> > */
> > +			mediatek,scp = <&scp>;
> > +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges = <0 0 0 0x16000000 0 0x26000>;
> > +
> > +			vcodec_lat: vcodec-lat@10000 {
> > +				compatible = "mediatek,mtk-vcodec-lat";
> > +				reg = <0x0 0x10000 0 0x800>;		
> > /* VDEC_MISC */
> > +				interrupts = <GIC_SPI 426
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_VDEC>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_LAT>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_LARB1>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				clock-names = "vdec-sel", "vdec-soc-
> > vdec", "vdec-soc-lat",
> > +					      "vdec-vdec", "vdec-top";
> 
> Clock names do not match binding description. We have superfluous
> "vdec-" 
> prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as
> the driver 
> does not care about the clock name. In any case it would be good if
> you could 
> send a follow-up patch to fix the clock name.
> 
> Applied, thanks
> 

Sorry, This is our mistake. those clk names should not append "vdec-"
prefix from Rob's suggestion [1]. ('vdec-' is redundant)

Please drop this patch in v5.18-next/dts64.  I will send the corrected
version.

I apologize any inconvenience caused.

[1] https://lore.kernel.org/all/YYFCaHI%2FDASUz+Vu@robh.at.kernel.org/

Thanks,
Allen

> > +				assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > +				assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > +			};
> > +
> > +			vcodec_core: vcodec-core@25000 {
> > +				compatible = "mediatek,mtk-vcodec-
> > core";
> > +				reg = <0 0x25000 0 0x1000>;	/*
> > VDEC_CORE_MISC */
> > +				interrupts = <GIC_SPI 425
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				iommus = <&iommu0
> > M4U_PORT_L4_VDEC_MC_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_UFO_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PP_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_TILE_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_VLD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > +					 <&vdecsys CLK_VDEC_VDEC>,
> > +					 <&vdecsys CLK_VDEC_LAT>,
> > +					 <&vdecsys CLK_VDEC_LARB1>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				clock-names = "vdec-sel", "vdec-soc-
> > vdec", "vdec-soc-lat",
> > +					      "vdec-vdec", "vdec-top";
> > +				assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > +				assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > +			};
> > +		};
> > +
> >   		larb5: larb@1600d000 {
> >   			compatible = "mediatek,mt8192-smi-larb";
> >   			reg = <0 0x1600d000 0 0x1000>;


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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[allen-kh.cheng]

Hi Matthias,

On Fri, 2022-03-25 at 16:22 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61
> > ++++++++++++++++++++++++
> >   1 file changed, 61 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 63893779b193..71ad3adeed51 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1285,6 +1285,67 @@
> >   			power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> >   		};
> >   
> > +		vcodec_dec: vcodec-dec@16000000 {
> > +			compatible = "mediatek,mt8192-vcodec-dec";
> > +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS
> > */
> > +			mediatek,scp = <&scp>;
> > +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges = <0 0 0 0x16000000 0 0x26000>;
> > +
> > +			vcodec_lat: vcodec-lat@10000 {
> > +				compatible = "mediatek,mtk-vcodec-lat";
> > +				reg = <0x0 0x10000 0 0x800>;		
> > /* VDEC_MISC */
> > +				interrupts = <GIC_SPI 426
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_VDEC>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_LAT>,
> > +					 <&vdecsys_soc
> > CLK_VDEC_SOC_LARB1>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				clock-names = "vdec-sel", "vdec-soc-
> > vdec", "vdec-soc-lat",
> > +					      "vdec-vdec", "vdec-top";
> 
> Clock names do not match binding description. We have superfluous
> "vdec-" 
> prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as
> the driver 
> does not care about the clock name. In any case it would be good if
> you could 
> send a follow-up patch to fix the clock name.
> 
> Applied, thanks
> 

Sorry, This is our mistake. those clk names should not append "vdec-"
prefix from Rob's suggestion [1]. ('vdec-' is redundant)

Please drop this patch in v5.18-next/dts64.  I will send the corrected
version.

I apologize any inconvenience caused.

[1] https://lore.kernel.org/all/YYFCaHI%2FDASUz+Vu@robh.at.kernel.org/

Thanks,
Allen

> > +				assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > +				assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > +			};
> > +
> > +			vcodec_core: vcodec-core@25000 {
> > +				compatible = "mediatek,mtk-vcodec-
> > core";
> > +				reg = <0 0x25000 0 0x1000>;	/*
> > VDEC_CORE_MISC */
> > +				interrupts = <GIC_SPI 425
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > +				iommus = <&iommu0
> > M4U_PORT_L4_VDEC_MC_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_UFO_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PP_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_TILE_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_VLD_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > +					 <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > +					 <&vdecsys CLK_VDEC_VDEC>,
> > +					 <&vdecsys CLK_VDEC_LAT>,
> > +					 <&vdecsys CLK_VDEC_LARB1>,
> > +					 <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				clock-names = "vdec-sel", "vdec-soc-
> > vdec", "vdec-soc-lat",
> > +					      "vdec-vdec", "vdec-top";
> > +				assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > +				assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > +				power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > +			};
> > +		};
> > +
> >   		larb5: larb@1600d000 {
> >   			compatible = "mediatek,mt8192-smi-larb";
> >   			reg = <0 0x1600d000 0 0x1000>;


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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 29/03/2022 11:09, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:22 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add vcodec lat and core nodes for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61
>>> ++++++++++++++++++++++++
>>>    1 file changed, 61 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 63893779b193..71ad3adeed51 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1285,6 +1285,67 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_ISP2>;
>>>    		};
>>>    
>>> +		vcodec_dec: vcodec-dec@16000000 {
>>> +			compatible = "mediatek,mt8192-vcodec-dec";
>>> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS
>>> */
>>> +			mediatek,scp = <&scp>;
>>> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <2>;
>>> +			ranges = <0 0 0 0x16000000 0 0x26000>;
>>> +
>>> +			vcodec_lat: vcodec-lat@10000 {
>>> +				compatible = "mediatek,mtk-vcodec-lat";
>>> +				reg = <0x0 0x10000 0 0x800>;		
>>> /* VDEC_MISC */
>>> +				interrupts = <GIC_SPI 426
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_VDEC>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LAT>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>
>> Clock names do not match binding description. We have superfluous
>> "vdec-"
>> prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as
>> the driver
>> does not care about the clock name. In any case it would be good if
>> you could
>> send a follow-up patch to fix the clock name.
>>
>> Applied, thanks
>>
> 
> Sorry, This is our mistake. those clk names should not append "vdec-"
> prefix from Rob's suggestion [1]. ('vdec-' is redundant)
> 
> Please drop this patch in v5.18-next/dts64.  I will send the corrected
> version.
> 

Ok, I dropped the commit from the branch for now.

> I apologize any inconvenience caused.
> 

No worries.

Regards,
Matthias

> [1] https://lore.kernel.org/all/YYFCaHI%2FDASUz+Vu@robh.at.kernel.org/
> 
> Thanks,
> Allen
> 
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC>;
>>> +			};
>>> +
>>> +			vcodec_core: vcodec-core@25000 {
>>> +				compatible = "mediatek,mtk-vcodec-
>>> core";
>>> +				reg = <0 0x25000 0 0x1000>;	/*
>>> VDEC_CORE_MISC */
>>> +				interrupts = <GIC_SPI 425
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L4_VDEC_MC_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_UFO_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_WR_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PPWRAP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys CLK_VDEC_VDEC>,
>>> +					 <&vdecsys CLK_VDEC_LAT>,
>>> +					 <&vdecsys CLK_VDEC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC2>;
>>> +			};
>>> +		};
>>> +
>>>    		larb5: larb@1600d000 {
>>>    			compatible = "mediatek,mt8192-smi-larb";
>>>    			reg = <0 0x1600d000 0 0x1000>;
> 

Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 29/03/2022 11:09, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:22 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add vcodec lat and core nodes for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61
>>> ++++++++++++++++++++++++
>>>    1 file changed, 61 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 63893779b193..71ad3adeed51 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1285,6 +1285,67 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_ISP2>;
>>>    		};
>>>    
>>> +		vcodec_dec: vcodec-dec@16000000 {
>>> +			compatible = "mediatek,mt8192-vcodec-dec";
>>> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS
>>> */
>>> +			mediatek,scp = <&scp>;
>>> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <2>;
>>> +			ranges = <0 0 0 0x16000000 0 0x26000>;
>>> +
>>> +			vcodec_lat: vcodec-lat@10000 {
>>> +				compatible = "mediatek,mtk-vcodec-lat";
>>> +				reg = <0x0 0x10000 0 0x800>;		
>>> /* VDEC_MISC */
>>> +				interrupts = <GIC_SPI 426
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_VDEC>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LAT>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>
>> Clock names do not match binding description. We have superfluous
>> "vdec-"
>> prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as
>> the driver
>> does not care about the clock name. In any case it would be good if
>> you could
>> send a follow-up patch to fix the clock name.
>>
>> Applied, thanks
>>
> 
> Sorry, This is our mistake. those clk names should not append "vdec-"
> prefix from Rob's suggestion [1]. ('vdec-' is redundant)
> 
> Please drop this patch in v5.18-next/dts64.  I will send the corrected
> version.
> 

Ok, I dropped the commit from the branch for now.

> I apologize any inconvenience caused.
> 

No worries.

Regards,
Matthias

> [1] https://lore.kernel.org/all/YYFCaHI%2FDASUz+Vu@robh.at.kernel.org/
> 
> Thanks,
> Allen
> 
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC>;
>>> +			};
>>> +
>>> +			vcodec_core: vcodec-core@25000 {
>>> +				compatible = "mediatek,mtk-vcodec-
>>> core";
>>> +				reg = <0 0x25000 0 0x1000>;	/*
>>> VDEC_CORE_MISC */
>>> +				interrupts = <GIC_SPI 425
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L4_VDEC_MC_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_UFO_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_WR_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PPWRAP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys CLK_VDEC_VDEC>,
>>> +					 <&vdecsys CLK_VDEC_LAT>,
>>> +					 <&vdecsys CLK_VDEC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC2>;
>>> +			};
>>> +		};
>>> +
>>>    		larb5: larb@1600d000 {
>>>    			compatible = "mediatek,mt8192-smi-larb";
>>>    			reg = <0 0x1600d000 0 0x1000>;
> 

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Re: [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 29/03/2022 11:09, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:22 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add vcodec lat and core nodes for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61
>>> ++++++++++++++++++++++++
>>>    1 file changed, 61 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 63893779b193..71ad3adeed51 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1285,6 +1285,67 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_ISP2>;
>>>    		};
>>>    
>>> +		vcodec_dec: vcodec-dec@16000000 {
>>> +			compatible = "mediatek,mt8192-vcodec-dec";
>>> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS
>>> */
>>> +			mediatek,scp = <&scp>;
>>> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <2>;
>>> +			ranges = <0 0 0 0x16000000 0 0x26000>;
>>> +
>>> +			vcodec_lat: vcodec-lat@10000 {
>>> +				compatible = "mediatek,mtk-vcodec-lat";
>>> +				reg = <0x0 0x10000 0 0x800>;		
>>> /* VDEC_MISC */
>>> +				interrupts = <GIC_SPI 426
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_VDEC>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LAT>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>
>> Clock names do not match binding description. We have superfluous
>> "vdec-"
>> prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as
>> the driver
>> does not care about the clock name. In any case it would be good if
>> you could
>> send a follow-up patch to fix the clock name.
>>
>> Applied, thanks
>>
> 
> Sorry, This is our mistake. those clk names should not append "vdec-"
> prefix from Rob's suggestion [1]. ('vdec-' is redundant)
> 
> Please drop this patch in v5.18-next/dts64.  I will send the corrected
> version.
> 

Ok, I dropped the commit from the branch for now.

> I apologize any inconvenience caused.
> 

No worries.

Regards,
Matthias

> [1] https://lore.kernel.org/all/YYFCaHI%2FDASUz+Vu@robh.at.kernel.org/
> 
> Thanks,
> Allen
> 
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC>;
>>> +			};
>>> +
>>> +			vcodec_core: vcodec-core@25000 {
>>> +				compatible = "mediatek,mtk-vcodec-
>>> core";
>>> +				reg = <0 0x25000 0 0x1000>;	/*
>>> VDEC_CORE_MISC */
>>> +				interrupts = <GIC_SPI 425
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L4_VDEC_MC_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_UFO_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_WR_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PPWRAP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys CLK_VDEC_VDEC>,
>>> +					 <&vdecsys CLK_VDEC_LAT>,
>>> +					 <&vdecsys CLK_VDEC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC2>;
>>> +			};
>>> +		};
>>> +
>>>    		larb5: larb@1600d000 {
>>>    			compatible = "mediatek,mt8192-smi-larb";
>>>    			reg = <0 0x1600d000 0 0x1000>;
> 

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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Matthias Brugger]

On 29/03/2022 09:45, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add dpi node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>>>    1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 71ad3adeed51..a77d405dd508 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1236,6 +1236,17 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_DISP>;
>>>    		};
>>>    
>>> +		dpi0: dpi@14016000 {
>>> +			compatible = "mediatek,mt8192-dpi";
>>> +			reg = <0 0x14016000 0 0x1000>;
>>> +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
>>> +				 <&mmsys CLK_MM_DISP_DPI0>,
>>> +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
>>> +			clock-names = "pixel", "engine", "pll";
>>> +			status = "disabled";
>>
>> We are missing the output port node here.
>>
>> Regards,
>> Matthias
>>
> 
> We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for
> board level.
> 

Got it, patch now applied.

> Do we need to add any futher information in binding?
> 

Hm, probably we should mark the output port as optional? Can you check how other 
bindings manage that?

Thanks,
Matthias

> Thanks,
> Allen
> 
>>> +		};
>>> +
>>>    		iommu0: m4u@1401d000 {
>>>    			compatible = "mediatek,mt8192-m4u";
>>>    			reg = <0 0x1401d000 0 0x1000>;
> 

Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Matthias Brugger]

On 29/03/2022 09:45, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add dpi node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>>>    1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 71ad3adeed51..a77d405dd508 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1236,6 +1236,17 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_DISP>;
>>>    		};
>>>    
>>> +		dpi0: dpi@14016000 {
>>> +			compatible = "mediatek,mt8192-dpi";
>>> +			reg = <0 0x14016000 0 0x1000>;
>>> +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
>>> +				 <&mmsys CLK_MM_DISP_DPI0>,
>>> +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
>>> +			clock-names = "pixel", "engine", "pll";
>>> +			status = "disabled";
>>
>> We are missing the output port node here.
>>
>> Regards,
>> Matthias
>>
> 
> We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for
> board level.
> 

Got it, patch now applied.

> Do we need to add any futher information in binding?
> 

Hm, probably we should mark the output port as optional? Can you check how other 
bindings manage that?

Thanks,
Matthias

> Thanks,
> Allen
> 
>>> +		};
>>> +
>>>    		iommu0: m4u@1401d000 {
>>>    			compatible = "mediatek,mt8192-m4u";
>>>    			reg = <0 0x1401d000 0 0x1000>;
> 

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Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node

[Matthias Brugger]

On 29/03/2022 09:45, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add dpi node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>>>    1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 71ad3adeed51..a77d405dd508 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1236,6 +1236,17 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_DISP>;
>>>    		};
>>>    
>>> +		dpi0: dpi@14016000 {
>>> +			compatible = "mediatek,mt8192-dpi";
>>> +			reg = <0 0x14016000 0 0x1000>;
>>> +			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>> +			clocks = <&mmsys CLK_MM_DPI_DPI0>,
>>> +				 <&mmsys CLK_MM_DISP_DPI0>,
>>> +				 <&apmixedsys CLK_APMIXED_TVDPLL>;
>>> +			clock-names = "pixel", "engine", "pll";
>>> +			status = "disabled";
>>
>> We are missing the output port node here.
>>
>> Regards,
>> Matthias
>>
> 
> We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for
> board level.
> 

Got it, patch now applied.

> Do we need to add any futher information in binding?
> 

Hm, probably we should mark the output port as optional? Can you check how other 
bindings manage that?

Thanks,
Matthias

> Thanks,
> Allen
> 
>>> +		};
>>> +
>>>    		iommu0: m4u@1401d000 {
>>>    			compatible = "mediatek,mt8192-m4u";
>>>    			reg = <0 0x1401d000 0 0x1000>;
> 

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Matthias Brugger]

On 29/03/2022 08:51, allen-kh.cheng wrote:
> 
> Hi Matthias,
> 
> On Mon, 2022-03-28 at 13:10 +0200, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add pwm node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>>>    1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index f0f0f067c023..ea98b2230f18 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -625,6 +625,17 @@
>>>    			status = "disabled";
>>>    		};
>>>    
>>> +		pwm0: pwm@1100e000 {
>>> +			compatible = "mediatek,mt8183-disp-pwm";
>>> +			reg = <0 0x1100e000 0 0x1000>;
>>> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>
>> Binding description is missing interrupt property. Remeber that the
>> DT should
>> describe the HW, so we need to update the binding description.
>> I just wonder what the IRQ signals, as it is not used by the driver.
>> Definitely
>> a good candidate to make the commit message more sound. So please add
>> it there.
>>
>> Thanks!
>> Matthias
>>
> 
> For interrupt property, we will send anther patch to update binding
> and add some information for IRQ into commit message in next version.
> 

Thanks. Would you mind to send the dt-bindings updates in a series together with 
the patches from this series that needs changes? This way it will be easier to 
track the dependencies.

Please beware to send dt-binding patches as first of the series, so that Rob 
Herring can find the rather quick.

Thanks!
Matthias

> Thanks,
> Allen
> 
>>> +			#pwm-cells = <2>;
>>> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
>>> +				 <&infracfg CLK_INFRA_DISP_PWM>;
>>> +			clock-names = "main", "mm";
>>> +			status = "disabled";
>>> +		};
>>> +
>>>    		spi1: spi@11010000 {
>>>    			compatible = "mediatek,mt8192-spi",
>>>    				     "mediatek,mt6765-spi";
> 

Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Matthias Brugger]

On 29/03/2022 08:51, allen-kh.cheng wrote:
> 
> Hi Matthias,
> 
> On Mon, 2022-03-28 at 13:10 +0200, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add pwm node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>>>    1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index f0f0f067c023..ea98b2230f18 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -625,6 +625,17 @@
>>>    			status = "disabled";
>>>    		};
>>>    
>>> +		pwm0: pwm@1100e000 {
>>> +			compatible = "mediatek,mt8183-disp-pwm";
>>> +			reg = <0 0x1100e000 0 0x1000>;
>>> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>
>> Binding description is missing interrupt property. Remeber that the
>> DT should
>> describe the HW, so we need to update the binding description.
>> I just wonder what the IRQ signals, as it is not used by the driver.
>> Definitely
>> a good candidate to make the commit message more sound. So please add
>> it there.
>>
>> Thanks!
>> Matthias
>>
> 
> For interrupt property, we will send anther patch to update binding
> and add some information for IRQ into commit message in next version.
> 

Thanks. Would you mind to send the dt-bindings updates in a series together with 
the patches from this series that needs changes? This way it will be easier to 
track the dependencies.

Please beware to send dt-binding patches as first of the series, so that Rob 
Herring can find the rather quick.

Thanks!
Matthias

> Thanks,
> Allen
> 
>>> +			#pwm-cells = <2>;
>>> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
>>> +				 <&infracfg CLK_INFRA_DISP_PWM>;
>>> +			clock-names = "main", "mm";
>>> +			status = "disabled";
>>> +		};
>>> +
>>>    		spi1: spi@11010000 {
>>>    			compatible = "mediatek,mt8192-spi",
>>>    				     "mediatek,mt6765-spi";
> 

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Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node

[Matthias Brugger]

On 29/03/2022 08:51, allen-kh.cheng wrote:
> 
> Hi Matthias,
> 
> On Mon, 2022-03-28 at 13:10 +0200, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add pwm node for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
>>>    1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index f0f0f067c023..ea98b2230f18 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -625,6 +625,17 @@
>>>    			status = "disabled";
>>>    		};
>>>    
>>> +		pwm0: pwm@1100e000 {
>>> +			compatible = "mediatek,mt8183-disp-pwm";
>>> +			reg = <0 0x1100e000 0 0x1000>;
>>> +			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
>>> 0>;
>>
>> Binding description is missing interrupt property. Remeber that the
>> DT should
>> describe the HW, so we need to update the binding description.
>> I just wonder what the IRQ signals, as it is not used by the driver.
>> Definitely
>> a good candidate to make the commit message more sound. So please add
>> it there.
>>
>> Thanks!
>> Matthias
>>
> 
> For interrupt property, we will send anther patch to update binding
> and add some information for IRQ into commit message in next version.
> 

Thanks. Would you mind to send the dt-bindings updates in a series together with 
the patches from this series that needs changes? This way it will be easier to 
track the dependencies.

Please beware to send dt-binding patches as first of the series, so that Rob 
Herring can find the rather quick.

Thanks!
Matthias

> Thanks,
> Allen
> 
>>> +			#pwm-cells = <2>;
>>> +			clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
>>> +				 <&infracfg CLK_INFRA_DISP_PWM>;
>>> +			clock-names = "main", "mm";
>>> +			status = "disabled";
>>> +		};
>>> +
>>>    		spi1: spi@11010000 {
>>>    			compatible = "mediatek,mt8192-spi",
>>>    				     "mediatek,mt6765-spi";
> 

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Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Nícolas F. R. A. Prado]

On Wed, Mar 23, 2022 at 06:24:03PM +0100, Matthias Brugger wrote:
> 
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add gce node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 0f9f211ca986..9e1b563bebab 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -6,6 +6,7 @@
> >   /dts-v1/;
> >   #include <dt-bindings/clock/mt8192-clk.h>
> > +#include <dt-bindings/gce/mt8192-gce.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > @@ -552,6 +553,15 @@
> >   			#size-cells = <0>;
> >   		};
> > +		gce: mailbox@10228000 {
> > +			compatible = "mediatek,mt8192-gce";
> > +			reg = <0 0x10228000 0 0x4000>;
> > +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> > +			#mbox-cells = <3>;
> 
> #mbox-cells should be 2, right?

It should indeed. The mboxes property in patch 21 should also have the third
argument ("1") dropped.

Thanks,
Nícolas

Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Nícolas F. R. A. Prado]

On Wed, Mar 23, 2022 at 06:24:03PM +0100, Matthias Brugger wrote:
> 
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add gce node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 0f9f211ca986..9e1b563bebab 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -6,6 +6,7 @@
> >   /dts-v1/;
> >   #include <dt-bindings/clock/mt8192-clk.h>
> > +#include <dt-bindings/gce/mt8192-gce.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > @@ -552,6 +553,15 @@
> >   			#size-cells = <0>;
> >   		};
> > +		gce: mailbox@10228000 {
> > +			compatible = "mediatek,mt8192-gce";
> > +			reg = <0 0x10228000 0 0x4000>;
> > +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> > +			#mbox-cells = <3>;
> 
> #mbox-cells should be 2, right?

It should indeed. The mboxes property in patch 21 should also have the third
argument ("1") dropped.

Thanks,
Nícolas

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Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[Nícolas F. R. A. Prado]

On Wed, Mar 23, 2022 at 06:24:03PM +0100, Matthias Brugger wrote:
> 
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add gce node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 0f9f211ca986..9e1b563bebab 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -6,6 +6,7 @@
> >   /dts-v1/;
> >   #include <dt-bindings/clock/mt8192-clk.h>
> > +#include <dt-bindings/gce/mt8192-gce.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > @@ -552,6 +553,15 @@
> >   			#size-cells = <0>;
> >   		};
> > +		gce: mailbox@10228000 {
> > +			compatible = "mediatek,mt8192-gce";
> > +			reg = <0 0x10228000 0 0x4000>;
> > +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> > +			#mbox-cells = <3>;
> 
> #mbox-cells should be 2, right?

It should indeed. The mboxes property in patch 21 should also have the third
argument ("1") dropped.

Thanks,
Nícolas

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Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[allen-kh.cheng]

Hi Mathias,

On Wed, 2022-03-23 at 18:16 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add spmi node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
> >   1 file changed, 17 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 76428599444e..0f9f211ca986 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -535,6 +535,23 @@
> >   			assigned-clock-parents = <&topckgen
> > CLK_TOP_OSC_D10>;
> >   		};
> >   
> > +		spmi: spmi@10027000 {
> > +			compatible = "mediatek,mt6873-spmi";
> > +			reg = <0 0x10027000 0 0x000e00>,
> > +			      <0 0x10029000 0 0x000100>;
> > +			reg-names = "pmif", "spmimst";
> > +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> > +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> > +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> > +			clock-names = "pmif_sys_ck",
> > +				      "pmif_tmr_ck",
> > +				      "spmimst_clk_mux";
> > +			assigned-clocks = <&topckgen
> > CLK_TOP_PWRAP_ULPOSC_SEL>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_OSC_D10>;
> > +			#address-cells = <2>;
> > +			#size-cells = <0>;
> 
> What do we need the address-cells and size-cells for?
> 
> Regards,
> Matthias
> 

We wiil add two regulators for board level (mt8192-asurada.dtsi).

Adress-cells and size-cells are used to dentify regulator.

&spmi {
        grpid = <11>;

        mt6315_6: pmic@6 {
               
compatible = "mediatek,mt6315-regulator";
                reg = <0x6 0>;

		....
        };

        mt6315_7: pmic@7 {
               
compatible = "mediatek,mt6315-regulator";
                reg = <0x7 0>;

		....
        };
};

Thanks,
Allen

> > +
> >   		scp_adsp: clock-controller@10720000 {
> >   			compatible = "mediatek,mt8192-scp_adsp";
> >   			reg = <0 0x10720000 0 0x1000>;


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Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[allen-kh.cheng]

Hi Mathias,

On Wed, 2022-03-23 at 18:16 +0100, Matthias Brugger wrote:
> 
> On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > Add spmi node for mt8192 SoC.
> > 
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
> >   1 file changed, 17 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 76428599444e..0f9f211ca986 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -535,6 +535,23 @@
> >   			assigned-clock-parents = <&topckgen
> > CLK_TOP_OSC_D10>;
> >   		};
> >   
> > +		spmi: spmi@10027000 {
> > +			compatible = "mediatek,mt6873-spmi";
> > +			reg = <0 0x10027000 0 0x000e00>,
> > +			      <0 0x10029000 0 0x000100>;
> > +			reg-names = "pmif", "spmimst";
> > +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> > +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> > +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> > +			clock-names = "pmif_sys_ck",
> > +				      "pmif_tmr_ck",
> > +				      "spmimst_clk_mux";
> > +			assigned-clocks = <&topckgen
> > CLK_TOP_PWRAP_ULPOSC_SEL>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_OSC_D10>;
> > +			#address-cells = <2>;
> > +			#size-cells = <0>;
> 
> What do we need the address-cells and size-cells for?
> 
> Regards,
> Matthias
> 

We wiil add two regulators for board level (mt8192-asurada.dtsi).

Adress-cells and size-cells are used to dentify regulator.

&spmi {
        grpid = <11>;

        mt6315_6: pmic@6 {
               
compatible = "mediatek,mt6315-regulator";
                reg = <0x6 0>;

		....
        };

        mt6315_7: pmic@7 {
               
compatible = "mediatek,mt6315-regulator";
                reg = <0x7 0>;

		....
        };
};

Thanks,
Allen

> > +
> >   		scp_adsp: clock-controller@10720000 {
> >   			compatible = "mediatek,mt8192-scp_adsp";
> >   			reg = <0 0x10720000 0 0x1000>;


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Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[allen-kh.cheng]

Hi,

On Tue, 2022-03-29 at 16:11 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Mar 23, 2022 at 06:24:03PM +0100, Matthias Brugger wrote:
> > 
> > 
> > On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > > Add gce node for mt8192 SoC.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > >   1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 0f9f211ca986..9e1b563bebab 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -6,6 +6,7 @@
> > >   /dts-v1/;
> > >   #include <dt-bindings/clock/mt8192-clk.h>
> > > +#include <dt-bindings/gce/mt8192-gce.h>
> > >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> > >   #include <dt-bindings/interrupt-controller/irq.h>
> > >   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > > @@ -552,6 +553,15 @@
> > >   			#size-cells = <0>;
> > >   		};
> > > +		gce: mailbox@10228000 {
> > > +			compatible = "mediatek,mt8192-gce";
> > > +			reg = <0 0x10228000 0 0x4000>;
> > > +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
> > > 0>;
> > > +			#mbox-cells = <3>;
> > 
> > #mbox-cells should be 2, right?
> 
> It should indeed. The mboxes property in patch 21 should also have
> the third
> argument ("1") dropped.
> 
> Thanks,
> Nícolas 

Thanks for the reminder.

Yes,#mbox-cells should be 2 and patch 21 also need to update for
this.

Best regards,
Allen





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Re: [PATCH v4 03/22] arm64: dts: mt8192: Add gce node

[allen-kh.cheng]

Hi,

On Tue, 2022-03-29 at 16:11 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Mar 23, 2022 at 06:24:03PM +0100, Matthias Brugger wrote:
> > 
> > 
> > On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > > Add gce node for mt8192 SoC.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++
> > >   1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 0f9f211ca986..9e1b563bebab 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -6,6 +6,7 @@
> > >   /dts-v1/;
> > >   #include <dt-bindings/clock/mt8192-clk.h>
> > > +#include <dt-bindings/gce/mt8192-gce.h>
> > >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> > >   #include <dt-bindings/interrupt-controller/irq.h>
> > >   #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > > @@ -552,6 +553,15 @@
> > >   			#size-cells = <0>;
> > >   		};
> > > +		gce: mailbox@10228000 {
> > > +			compatible = "mediatek,mt8192-gce";
> > > +			reg = <0 0x10228000 0 0x4000>;
> > > +			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
> > > 0>;
> > > +			#mbox-cells = <3>;
> > 
> > #mbox-cells should be 2, right?
> 
> It should indeed. The mboxes property in patch 21 should also have
> the third
> argument ("1") dropped.
> 
> Thanks,
> Nícolas 

Thanks for the reminder.

Yes,#mbox-cells should be 2 and patch 21 also need to update for
this.

Best regards,
Allen





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Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[allen-kh.cheng]

Hi Matthias,

On Wed, 2022-03-30 at 15:21 +0800, allen-kh.cheng wrote:
> Hi Mathias,
> 
> On Wed, 2022-03-23 at 18:16 +0100, Matthias Brugger wrote:
> > 
> > On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > > Add spmi node for mt8192 SoC.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
> > >   1 file changed, 17 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 76428599444e..0f9f211ca986 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -535,6 +535,23 @@
> > >   			assigned-clock-parents = <&topckgen
> > > CLK_TOP_OSC_D10>;
> > >   		};
> > >   
> > > +		spmi: spmi@10027000 {
> > > +			compatible = "mediatek,mt6873-spmi";
> > > +			reg = <0 0x10027000 0 0x000e00>,
> > > +			      <0 0x10029000 0 0x000100>;
> > > +			reg-names = "pmif", "spmimst";
> > > +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> > > +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> > > +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> > > +			clock-names = "pmif_sys_ck",
> > > +				      "pmif_tmr_ck",
> > > +				      "spmimst_clk_mux";
> > > +			assigned-clocks = <&topckgen
> > > CLK_TOP_PWRAP_ULPOSC_SEL>;
> > > +			assigned-clock-parents = <&topckgen
> > > CLK_TOP_OSC_D10>;
> > > +			#address-cells = <2>;
> > > +			#size-cells = <0>;
> > 
> > What do we need the address-cells and size-cells for?
> > 
> > Regards,
> > Matthias
> > 
> 
> We wiil add two regulators for board level (mt8192-asurada.dtsi).
> 
> Adress-cells and size-cells are used to dentify regulator.
> 
> &spmi {
>         grpid = <11>;
> 
>         mt6315_6: pmic@6 {
>                
> compatible = "mediatek,mt6315-regulator";
>                 reg = <0x6 0>;
> 
> 		....
>         };
> 
>         mt6315_7: pmic@7 {
>                
> compatible = "mediatek,mt6315-regulator";
>                 reg = <0x7 0>;
> 
> 		....
>         };
> };
> 
> Thanks,
> Allen
> 

I just wanto to confirm with you.

Is this way ok?

Best regards,
Allen

> > > +
> > >   		scp_adsp: clock-controller@10720000 {
> > >   			compatible = "mediatek,mt8192-
> > > scp_adsp";
> > >   			reg = <0 0x10720000 0 0x1000>;
> 
> 


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Re: [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node

[allen-kh.cheng]

Hi Matthias,

On Wed, 2022-03-30 at 15:21 +0800, allen-kh.cheng wrote:
> Hi Mathias,
> 
> On Wed, 2022-03-23 at 18:16 +0100, Matthias Brugger wrote:
> > 
> > On 18/03/2022 15:45, Allen-KH Cheng wrote:
> > > Add spmi node for mt8192 SoC.
> > > 
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
> > >   1 file changed, 17 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 76428599444e..0f9f211ca986 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -535,6 +535,23 @@
> > >   			assigned-clock-parents = <&topckgen
> > > CLK_TOP_OSC_D10>;
> > >   		};
> > >   
> > > +		spmi: spmi@10027000 {
> > > +			compatible = "mediatek,mt6873-spmi";
> > > +			reg = <0 0x10027000 0 0x000e00>,
> > > +			      <0 0x10029000 0 0x000100>;
> > > +			reg-names = "pmif", "spmimst";
> > > +			clocks = <&infracfg CLK_INFRA_PMIC_AP>,
> > > +				 <&infracfg CLK_INFRA_PMIC_TMR>,
> > > +				 <&topckgen CLK_TOP_SPMI_MST_SEL>;
> > > +			clock-names = "pmif_sys_ck",
> > > +				      "pmif_tmr_ck",
> > > +				      "spmimst_clk_mux";
> > > +			assigned-clocks = <&topckgen
> > > CLK_TOP_PWRAP_ULPOSC_SEL>;
> > > +			assigned-clock-parents = <&topckgen
> > > CLK_TOP_OSC_D10>;
> > > +			#address-cells = <2>;
> > > +			#size-cells = <0>;
> > 
> > What do we need the address-cells and size-cells for?
> > 
> > Regards,
> > Matthias
> > 
> 
> We wiil add two regulators for board level (mt8192-asurada.dtsi).
> 
> Adress-cells and size-cells are used to dentify regulator.
> 
> &spmi {
>         grpid = <11>;
> 
>         mt6315_6: pmic@6 {
>                
> compatible = "mediatek,mt6315-regulator";
>                 reg = <0x6 0>;
> 
> 		....
>         };
> 
>         mt6315_7: pmic@7 {
>                
> compatible = "mediatek,mt6315-regulator";
>                 reg = <0x7 0>;
> 
> 		....
>         };
> };
> 
> Thanks,
> Allen
> 

I just wanto to confirm with you.

Is this way ok?

Best regards,
Allen

> > > +
> > >   		scp_adsp: clock-controller@10720000 {
> > >   			compatible = "mediatek,mt8192-
> > > scp_adsp";
> > >   			reg = <0 0x10720000 0 0x1000>;
> 
> 


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