Question on HS400 timing sequence

Question on HS400 timing sequence

[Shah, Nehal-bakulchandra]

Hi Adrian,

as per JESD84-B50 spec for EMMC 5.0 , HS400 timing sequence is following

In order to switch to HS400 mode, host should perform the following steps:
1) Initialize device with “Backward Compatible Timings”
2) Select the device with CMD7.
3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device supports HS400
4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported device Driver Strengths. (Note: This step may be skipped if changes of driver strength is not needed)
5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD register to the appropriate driver strength for HS400 operation and set the “Timing Interface”
parameter to 0x2 to switch to HS200 mode.
6) Perform the Tuning Process at the HS400 target operating frequency (Note: tuning process in HS200 mode is required to synchronize the command response on the CMD line to CLK for HS400 operation).
7) After the Tuning Process has completed, set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to 0x3 to switch to HS400 mode.

But in case of JESD84-B51 spec  EMMC 5.1, HS400 timing sequence is following

1 )Initialize device with “Backward Compatible Timings”,
2) Select the device with CMD7,
3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device
supports HS400,
4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported
device Driver Strengths,
NOTE This step may be skipped if changes of driver strength is not needed.
5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD
register to the appropriate driver strength for HS400 operation and set the “Timing Interface”
parameter to 0x2 to switch to HS200 mode,
6) Perform the Tuning Process at the HS400 target operating frequency,
NOTE Tuning process in HS200 mode is required to synchronize the command response on the CMD line to
CLK for HS400 operation.
7) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to
0x1 to switch to High Speed mode and then set the clock frequency to a value not greater than 52
MHz,
8) Set BUS_WIDTH[183] to 0x06 to select the dual data rate x8 bus mode,
9) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to
0x3 to switch to HS400 mode.

So basically in case EMMC5.1 for HS400 mode selection, there is some difference after tuning. However driver
existing driver always follow spec of EMMC5.1 . Is there any specific reason for the same? So on our some AMD platforms
with EMMC5.0 driver is failing but if we modify the driver as per EMCC5.0 sequencing it is passing. So can you please provide
your inputs?

Thanks
Nehal Shah

Re: Question on HS400 timing sequence

[Adrian Hunter]

On 9/04/21 5:19 pm, Shah, Nehal-bakulchandra wrote:
> Hi Adrian,
> 
> as per JESD84-B50 spec for EMMC 5.0 , HS400 timing sequence is following
> 
> In order to switch to HS400 mode, host should perform the following steps:
> 1) Initialize device with “Backward Compatible Timings”
> 2) Select the device with CMD7.
> 3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device supports HS400
> 4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported device Driver Strengths. (Note: This step may be skipped if changes of driver strength is not needed)
> 5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD register to the appropriate driver strength for HS400 operation and set the “Timing Interface”
> parameter to 0x2 to switch to HS200 mode.
> 6) Perform the Tuning Process at the HS400 target operating frequency (Note: tuning process in HS200 mode is required to synchronize the command response on the CMD line to CLK for HS400 operation).
> 7) After the Tuning Process has completed, set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to 0x3 to switch to HS400 mode.
> 
> But in case of JESD84-B51 spec  EMMC 5.1, HS400 timing sequence is following
> 
> 1 )Initialize device with “Backward Compatible Timings”,
> 2) Select the device with CMD7,
> 3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device
> supports HS400,
> 4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported
> device Driver Strengths,
> NOTE This step may be skipped if changes of driver strength is not needed.
> 5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD
> register to the appropriate driver strength for HS400 operation and set the “Timing Interface”
> parameter to 0x2 to switch to HS200 mode,
> 6) Perform the Tuning Process at the HS400 target operating frequency,
> NOTE Tuning process in HS200 mode is required to synchronize the command response on the CMD line to
> CLK for HS400 operation.
> 7) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to
> 0x1 to switch to High Speed mode and then set the clock frequency to a value not greater than 52
> MHz,
> 8) Set BUS_WIDTH[183] to 0x06 to select the dual data rate x8 bus mode,
> 9) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to
> 0x3 to switch to HS400 mode.
> 
> So basically in case EMMC5.1 for HS400 mode selection, there is some difference after tuning. However driver
> existing driver always follow spec of EMMC5.1 . Is there any specific reason for the same? So on our some AMD platforms
> with EMMC5.0 driver is failing but if we modify the driver as per EMCC5.0 sequencing it is passing. So can you please provide
> your inputs?

Hi Nehal Shah

There was another specification between those two, namely JESD84-B50.1 eMMC 5.01 which has the same procedure as eMMC 5.1

AFAICT the 5.0 text was almost immediately "clarified" in 5.01 to match the 5.1 text.

So we have only 1 HS400 sequence.  But some host controllers do have issues, which is why there are additional hooks like ->hs400_downgrade() and ->hs400_prepare_ddr()

Regards
Adrian

Re: Question on HS400 timing sequence

[Shah, Nehal-bakulchandra]

Hi Adrian
On 4/9/2021 8:52 PM, Adrian Hunter wrote:
> On 9/04/21 5:19 pm, Shah, Nehal-bakulchandra wrote:
>> Hi Adrian,
>>
>> as per JESD84-B50 spec for EMMC 5.0 , HS400 timing sequence is following
>>
>> In order to switch to HS400 mode, host should perform the following steps:
>> 1) Initialize device with “Backward Compatible Timings”
>> 2) Select the device with CMD7.
>> 3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device supports HS400
>> 4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported device Driver Strengths. (Note: This step may be skipped if changes of driver strength is not needed)
>> 5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD register to the appropriate driver strength for HS400 operation and set the “Timing Interface”
>> parameter to 0x2 to switch to HS200 mode.
>> 6) Perform the Tuning Process at the HS400 target operating frequency (Note: tuning process in HS200 mode is required to synchronize the command response on the CMD line to CLK for HS400 operation).
>> 7) After the Tuning Process has completed, set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to 0x3 to switch to HS400 mode.
>>
>> But in case of JESD84-B51 spec  EMMC 5.1, HS400 timing sequence is following
>>
>> 1 )Initialize device with “Backward Compatible Timings”,
>> 2) Select the device with CMD7,
>> 3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device
>> supports HS400,
>> 4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported
>> device Driver Strengths,
>> NOTE This step may be skipped if changes of driver strength is not needed.
>> 5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD
>> register to the appropriate driver strength for HS400 operation and set the “Timing Interface”
>> parameter to 0x2 to switch to HS200 mode,
>> 6) Perform the Tuning Process at the HS400 target operating frequency,
>> NOTE Tuning process in HS200 mode is required to synchronize the command response on the CMD line to
>> CLK for HS400 operation.
>> 7) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to
>> 0x1 to switch to High Speed mode and then set the clock frequency to a value not greater than 52
>> MHz,
>> 8) Set BUS_WIDTH[183] to 0x06 to select the dual data rate x8 bus mode,
>> 9) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to
>> 0x3 to switch to HS400 mode.
>>
>> So basically in case EMMC5.1 for HS400 mode selection, there is some difference after tuning. However driver
>> existing driver always follow spec of EMMC5.1 . Is there any specific reason for the same? So on our some AMD platforms
>> with EMMC5.0 driver is failing but if we modify the driver as per EMCC5.0 sequencing it is passing. So can you please provide
>> your inputs?
> Hi Nehal Shah
>
> There was another specification between those two, namely JESD84-B50.1 eMMC 5.01 which has the same procedure as eMMC 5.1
>
> AFAICT the 5.0 text was almost immediately "clarified" in 5.01 to match the 5.1 text.
>
> So we have only 1 HS400 sequence.  But some host controllers do have issues, which is why there are additional hooks like ->hs400_downgrade() and ->hs400_prepare_ddr()
Sure we will try the same.
> Regards
> Adrian

Regards

Nehal