* [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Support MT8188 VDOSYS1 in display driver.
Changes in v5:
- Reuse .clk_enable/.clk_disable in struct mtk_ddp_comp_funcs
in mtk_disp_ovl_adaptor.c
- Adjust commits order
Changes in v4:
- Add new functions in mtk_disp_ovl_adaptor.c to enable/disable
components and reuse them when clock enable/disable
- Rename components in mtk_disp_ovl_adaptor.c and sort them in
alphabetical order
Changes in v3:
- Define macro MMSYS_RST_NR in mtk-mmsys.h and update reset table
- Fix typos (ETDHR -> ETHDR, VSNYC -> VSYNC)
- Rebase dt-bindings on linux-next
- Refine description of Padding
- Squash reset bit map commits for VDO0 and VDO1 into one
Changes in v2:
- Remove redundant compatibles of MT8188 because it shares the same
configuration with MT8195
- Separate dt-bindings by modules
- Support reset bit mapping in mmsys driver
Hsiao Chien Sung (14):
dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
dt-bindings: display: mediatek: merge: Add compatible for MT8188
dt-bindings: display: mediatek: padding: Add MT8188
dt-bindings: arm: mediatek: Add compatible for MT8188
dt-bindings: reset: mt8188: Add VDOSYS reset control bits
soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys
soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys
soc: mediatek: Support reset bit mapping in mmsys driver
soc: mediatek: Add MT8188 VDOSYS reset bit map
drm/mediatek: Support MT8188 VDOSYS1 in display driver
drm/mediatek: Sort OVL adaptor components in alphabetical order
drm/mediatek: Improve compatibility of display driver
drm/mediatek: Support MT8188 Padding in display driver
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
.../display/mediatek/mediatek,ethdr.yaml | 6 +-
.../display/mediatek/mediatek,mdp-rdma.yaml | 6 +-
.../display/mediatek/mediatek,merge.yaml | 3 +
.../display/mediatek/mediatek,padding.yaml | 81 +++++++
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 226 +++++++++---------
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 +-
drivers/gpu/drm/mediatek/mtk_padding.c | 136 +++++++++++
drivers/soc/mediatek/mt8188-mmsys.h | 210 ++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 23 ++
drivers/soc/mediatek/mtk-mmsys.h | 32 +++
drivers/soc/mediatek/mtk-mutex.c | 51 ++++
include/dt-bindings/reset/mt8188-resets.h | 75 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 8 +
18 files changed, 768 insertions(+), 122 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c
--
2.18.0
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Support MT8188 VDOSYS1 in display driver.
Changes in v5:
- Reuse .clk_enable/.clk_disable in struct mtk_ddp_comp_funcs
in mtk_disp_ovl_adaptor.c
- Adjust commits order
Changes in v4:
- Add new functions in mtk_disp_ovl_adaptor.c to enable/disable
components and reuse them when clock enable/disable
- Rename components in mtk_disp_ovl_adaptor.c and sort them in
alphabetical order
Changes in v3:
- Define macro MMSYS_RST_NR in mtk-mmsys.h and update reset table
- Fix typos (ETDHR -> ETHDR, VSNYC -> VSYNC)
- Rebase dt-bindings on linux-next
- Refine description of Padding
- Squash reset bit map commits for VDO0 and VDO1 into one
Changes in v2:
- Remove redundant compatibles of MT8188 because it shares the same
configuration with MT8195
- Separate dt-bindings by modules
- Support reset bit mapping in mmsys driver
Hsiao Chien Sung (14):
dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
dt-bindings: display: mediatek: merge: Add compatible for MT8188
dt-bindings: display: mediatek: padding: Add MT8188
dt-bindings: arm: mediatek: Add compatible for MT8188
dt-bindings: reset: mt8188: Add VDOSYS reset control bits
soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys
soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys
soc: mediatek: Support reset bit mapping in mmsys driver
soc: mediatek: Add MT8188 VDOSYS reset bit map
drm/mediatek: Support MT8188 VDOSYS1 in display driver
drm/mediatek: Sort OVL adaptor components in alphabetical order
drm/mediatek: Improve compatibility of display driver
drm/mediatek: Support MT8188 Padding in display driver
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
.../display/mediatek/mediatek,ethdr.yaml | 6 +-
.../display/mediatek/mediatek,mdp-rdma.yaml | 6 +-
.../display/mediatek/mediatek,merge.yaml | 3 +
.../display/mediatek/mediatek,padding.yaml | 81 +++++++
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 226 +++++++++---------
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 +-
drivers/gpu/drm/mediatek/mtk_padding.c | 136 +++++++++++
drivers/soc/mediatek/mt8188-mmsys.h | 210 ++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 23 ++
drivers/soc/mediatek/mtk-mmsys.h | 32 +++
drivers/soc/mediatek/mtk-mutex.c | 51 ++++
include/dt-bindings/reset/mt8188-resets.h | 75 ++++++
include/linux/soc/mediatek/mtk-mmsys.h | 8 +
18 files changed, 768 insertions(+), 122 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v5 01/14] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 ETHDR.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
index 801fa66ae615..677882348ede 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -23,7 +23,11 @@ description:
properties:
compatible:
- const: mediatek,mt8195-disp-ethdr
+ oneOf:
+ - const: mediatek,mt8195-disp-ethdr
+ - items:
+ - const: mediatek,mt8188-disp-ethdr
+ - const: mediatek,mt8195-disp-ethdr
reg:
maxItems: 7
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 01/14] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 ETHDR.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
index 801fa66ae615..677882348ede 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -23,7 +23,11 @@ description:
properties:
compatible:
- const: mediatek,mt8195-disp-ethdr
+ oneOf:
+ - const: mediatek,mt8195-disp-ethdr
+ - items:
+ - const: mediatek,mt8188-disp-ethdr
+ - const: mediatek,mt8195-disp-ethdr
reg:
maxItems: 7
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 02/14] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 MDP-RDMA.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
index dd12e2ff685c..7570a0684967 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -21,7 +21,11 @@ description:
properties:
compatible:
- const: mediatek,mt8195-vdo1-rdma
+ oneOf:
+ - const: mediatek,mt8195-vdo1-rdma
+ - items:
+ - const: mediatek,mt8188-vdo1-rdma
+ - const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 02/14] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 MDP-RDMA.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
index dd12e2ff685c..7570a0684967 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
@@ -21,7 +21,11 @@ description:
properties:
compatible:
- const: mediatek,mt8195-vdo1-rdma
+ oneOf:
+ - const: mediatek,mt8195-vdo1-rdma
+ - items:
+ - const: mediatek,mt8188-vdo1-rdma
+ - const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 03/14] dt-bindings: display: mediatek: merge: Add compatible for MT8188
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 MERGE.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index eead5cb8636e..5c678695162e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -27,6 +27,9 @@ properties:
- items:
- const: mediatek,mt6795-disp-merge
- const: mediatek,mt8173-disp-merge
+ - items:
+ - const: mediatek,mt8188-disp-merge
+ - const: mediatek,mt8195-disp-merge
reg:
maxItems: 1
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 03/14] dt-bindings: display: mediatek: merge: Add compatible for MT8188
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 MERGE.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index eead5cb8636e..5c678695162e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -27,6 +27,9 @@ properties:
- items:
- const: mediatek,mt6795-disp-merge
- const: mediatek,mt8173-disp-merge
+ - items:
+ - const: mediatek,mt8188-disp-merge
+ - const: mediatek,mt8195-disp-merge
reg:
maxItems: 1
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 04/14] dt-bindings: display: mediatek: padding: Add MT8188
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Padding is a new hardware module on MediaTek MT8188,
add dt-bindings for it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../display/mediatek/mediatek,padding.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
new file mode 100644
index 000000000000..db24801ebc48
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Padding
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+ Padding provides ability to add pixels to width and height of a layer with
+ specified colors. Due to hardware design, Mixer in VDOSYS1 requires
+ width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
+ we need Padding to deal with odd width.
+ Please notice that even if the Padding is in bypass mode, settings in
+ register must be cleared to 0, or undefined behaviors could happen.
+
+properties:
+ compatible:
+ const: mediatek,mt8188-padding
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ mediatek,gce-client-reg:
+ description:
+ GCE (Global Command Engine) is a multi-core micro processor that helps
+ its clients to execute commands without interrupting CPU. This property
+ describes GCE client's information that is composed by 4 fields.
+ 1. Phandle of the GCE (there may be several GCE processors)
+ 2. Sub-system ID defined in the dt-binding like a user ID
+ (Please refer to include/dt-bindings/gce/<chip>-gce.h)
+ 3. Offset from base address of the subsys you are at
+ 4. Size of the register the client needs
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle of the GCE
+ - description: Subsys ID defined in the dt-binding
+ - description: Offset from base address of the subsys
+ - description: Size of register
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ padding0: padding@1c11d000 {
+ compatible = "mediatek,mt8188-padding";
+ reg = <0 0x1c11d000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+ };
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 04/14] dt-bindings: display: mediatek: padding: Add MT8188
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Padding is a new hardware module on MediaTek MT8188,
add dt-bindings for it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../display/mediatek/mediatek,padding.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
new file mode 100644
index 000000000000..db24801ebc48
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Padding
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+ Padding provides ability to add pixels to width and height of a layer with
+ specified colors. Due to hardware design, Mixer in VDOSYS1 requires
+ width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
+ we need Padding to deal with odd width.
+ Please notice that even if the Padding is in bypass mode, settings in
+ register must be cleared to 0, or undefined behaviors could happen.
+
+properties:
+ compatible:
+ const: mediatek,mt8188-padding
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ mediatek,gce-client-reg:
+ description:
+ GCE (Global Command Engine) is a multi-core micro processor that helps
+ its clients to execute commands without interrupting CPU. This property
+ describes GCE client's information that is composed by 4 fields.
+ 1. Phandle of the GCE (there may be several GCE processors)
+ 2. Sub-system ID defined in the dt-binding like a user ID
+ (Please refer to include/dt-bindings/gce/<chip>-gce.h)
+ 3. Offset from base address of the subsys you are at
+ 4. Size of the register the client needs
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle of the GCE
+ - description: Subsys ID defined in the dt-binding
+ - description: Offset from base address of the subsys
+ - description: Size of register
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ padding0: padding@1c11d000 {
+ compatible = "mediatek,mt8188-padding";
+ reg = <0 0x1c11d000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+ };
+ };
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 05/14] dt-bindings: arm: mediatek: Add compatible for MT8188
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 VDOSYS1.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 536f5a5ebd24..642fa2e4736e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
+ - mediatek,mt8188-vdosys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 05/14] dt-bindings: arm: mediatek: Add compatible for MT8188
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add compatible name for MediaTek MT8188 VDOSYS1.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 536f5a5ebd24..642fa2e4736e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,7 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
+ - mediatek,mt8188-vdosys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 06/14] dt-bindings: reset: mt8188: Add VDOSYS reset control bits
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add MT8188 VDOSYS0 and VDOSYS1 reset control bits.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
include/dt-bindings/reset/mt8188-resets.h | 75 +++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index ba9a5e9b8899..5a58c54e7d20 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -38,4 +38,79 @@
#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1
#define MT8188_INFRA_RST3_PTP_CTRL_RST 2
+#define MT8188_VDO0_RST_DISP_OVL0 0
+#define MT8188_VDO0_RST_FAKE_ENG0 1
+#define MT8188_VDO0_RST_DISP_CCORR0 2
+#define MT8188_VDO0_RST_DISP_MUTEX0 3
+#define MT8188_VDO0_RST_DISP_GAMMA0 4
+#define MT8188_VDO0_RST_DISP_DITHER0 5
+#define MT8188_VDO0_RST_DISP_WDMA0 6
+#define MT8188_VDO0_RST_DISP_RDMA0 7
+#define MT8188_VDO0_RST_DSI0 8
+#define MT8188_VDO0_RST_DSI1 9
+#define MT8188_VDO0_RST_DSC_WRAP0 10
+#define MT8188_VDO0_RST_VPP_MERGE0 11
+#define MT8188_VDO0_RST_DP_INTF0 12
+#define MT8188_VDO0_RST_DISP_AAL0 13
+#define MT8188_VDO0_RST_INLINEROT0 14
+#define MT8188_VDO0_RST_APB_BUS 15
+#define MT8188_VDO0_RST_DISP_COLOR0 16
+#define MT8188_VDO0_RST_MDP_WROT0 17
+#define MT8188_VDO0_RST_DISP_RSZ0 18
+
+#define MT8188_VDO1_RST_SMI_LARB2 0
+#define MT8188_VDO1_RST_SMI_LARB3 1
+#define MT8188_VDO1_RST_GALS 2
+#define MT8188_VDO1_RST_FAKE_ENG0 3
+#define MT8188_VDO1_RST_FAKE_ENG1 4
+#define MT8188_VDO1_RST_MDP_RDMA0 5
+#define MT8188_VDO1_RST_MDP_RDMA1 6
+#define MT8188_VDO1_RST_MDP_RDMA2 7
+#define MT8188_VDO1_RST_MDP_RDMA3 8
+#define MT8188_VDO1_RST_VPP_MERGE0 9
+#define MT8188_VDO1_RST_VPP_MERGE1 10
+#define MT8188_VDO1_RST_VPP_MERGE2 11
+#define MT8188_VDO1_RST_VPP_MERGE3 12
+#define MT8188_VDO1_RST_VPP_MERGE4 13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15
+#define MT8188_VDO1_RST_DISP_MUTEX 16
+#define MT8188_VDO1_RST_MDP_RDMA4 17
+#define MT8188_VDO1_RST_MDP_RDMA5 18
+#define MT8188_VDO1_RST_MDP_RDMA6 19
+#define MT8188_VDO1_RST_MDP_RDMA7 20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK 21
+#define MT8188_VDO1_RST_DPI0_MM_CK 22
+#define MT8188_VDO1_RST_DPI1_MM_CK 23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30
+#define MT8188_VDO1_RST_PADDING0 31
+#define MT8188_VDO1_RST_PADDING1 32
+#define MT8188_VDO1_RST_PADDING2 33
+#define MT8188_VDO1_RST_PADDING3 34
+#define MT8188_VDO1_RST_PADDING4 35
+#define MT8188_VDO1_RST_PADDING5 36
+#define MT8188_VDO1_RST_PADDING6 37
+#define MT8188_VDO1_RST_PADDING7 38
+#define MT8188_VDO1_RST_DISP_RSZ0 39
+#define MT8188_VDO1_RST_DISP_RSZ1 40
+#define MT8188_VDO1_RST_DISP_RSZ2 41
+#define MT8188_VDO1_RST_DISP_RSZ3 42
+#define MT8188_VDO1_RST_HDR_VDO_FE0 43
+#define MT8188_VDO1_RST_HDR_GFX_FE0 44
+#define MT8188_VDO1_RST_HDR_VDO_BE 45
+#define MT8188_VDO1_RST_HDR_VDO_FE1 46
+#define MT8188_VDO1_RST_HDR_GFX_FE1 47
+#define MT8188_VDO1_RST_DISP_MIXER 48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 06/14] dt-bindings: reset: mt8188: Add VDOSYS reset control bits
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add MT8188 VDOSYS0 and VDOSYS1 reset control bits.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
include/dt-bindings/reset/mt8188-resets.h | 75 +++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
index ba9a5e9b8899..5a58c54e7d20 100644
--- a/include/dt-bindings/reset/mt8188-resets.h
+++ b/include/dt-bindings/reset/mt8188-resets.h
@@ -38,4 +38,79 @@
#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1
#define MT8188_INFRA_RST3_PTP_CTRL_RST 2
+#define MT8188_VDO0_RST_DISP_OVL0 0
+#define MT8188_VDO0_RST_FAKE_ENG0 1
+#define MT8188_VDO0_RST_DISP_CCORR0 2
+#define MT8188_VDO0_RST_DISP_MUTEX0 3
+#define MT8188_VDO0_RST_DISP_GAMMA0 4
+#define MT8188_VDO0_RST_DISP_DITHER0 5
+#define MT8188_VDO0_RST_DISP_WDMA0 6
+#define MT8188_VDO0_RST_DISP_RDMA0 7
+#define MT8188_VDO0_RST_DSI0 8
+#define MT8188_VDO0_RST_DSI1 9
+#define MT8188_VDO0_RST_DSC_WRAP0 10
+#define MT8188_VDO0_RST_VPP_MERGE0 11
+#define MT8188_VDO0_RST_DP_INTF0 12
+#define MT8188_VDO0_RST_DISP_AAL0 13
+#define MT8188_VDO0_RST_INLINEROT0 14
+#define MT8188_VDO0_RST_APB_BUS 15
+#define MT8188_VDO0_RST_DISP_COLOR0 16
+#define MT8188_VDO0_RST_MDP_WROT0 17
+#define MT8188_VDO0_RST_DISP_RSZ0 18
+
+#define MT8188_VDO1_RST_SMI_LARB2 0
+#define MT8188_VDO1_RST_SMI_LARB3 1
+#define MT8188_VDO1_RST_GALS 2
+#define MT8188_VDO1_RST_FAKE_ENG0 3
+#define MT8188_VDO1_RST_FAKE_ENG1 4
+#define MT8188_VDO1_RST_MDP_RDMA0 5
+#define MT8188_VDO1_RST_MDP_RDMA1 6
+#define MT8188_VDO1_RST_MDP_RDMA2 7
+#define MT8188_VDO1_RST_MDP_RDMA3 8
+#define MT8188_VDO1_RST_VPP_MERGE0 9
+#define MT8188_VDO1_RST_VPP_MERGE1 10
+#define MT8188_VDO1_RST_VPP_MERGE2 11
+#define MT8188_VDO1_RST_VPP_MERGE3 12
+#define MT8188_VDO1_RST_VPP_MERGE4 13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15
+#define MT8188_VDO1_RST_DISP_MUTEX 16
+#define MT8188_VDO1_RST_MDP_RDMA4 17
+#define MT8188_VDO1_RST_MDP_RDMA5 18
+#define MT8188_VDO1_RST_MDP_RDMA6 19
+#define MT8188_VDO1_RST_MDP_RDMA7 20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK 21
+#define MT8188_VDO1_RST_DPI0_MM_CK 22
+#define MT8188_VDO1_RST_DPI1_MM_CK 23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30
+#define MT8188_VDO1_RST_PADDING0 31
+#define MT8188_VDO1_RST_PADDING1 32
+#define MT8188_VDO1_RST_PADDING2 33
+#define MT8188_VDO1_RST_PADDING3 34
+#define MT8188_VDO1_RST_PADDING4 35
+#define MT8188_VDO1_RST_PADDING5 36
+#define MT8188_VDO1_RST_PADDING6 37
+#define MT8188_VDO1_RST_PADDING7 38
+#define MT8188_VDO1_RST_DISP_RSZ0 39
+#define MT8188_VDO1_RST_DISP_RSZ1 40
+#define MT8188_VDO1_RST_DISP_RSZ2 41
+#define MT8188_VDO1_RST_DISP_RSZ3 42
+#define MT8188_VDO1_RST_HDR_VDO_FE0 43
+#define MT8188_VDO1_RST_HDR_GFX_FE0 44
+#define MT8188_VDO1_RST_HDR_VDO_BE 45
+#define MT8188_VDO1_RST_HDR_VDO_FE1 46
+#define MT8188_VDO1_RST_HDR_GFX_FE1 47
+#define MT8188_VDO1_RST_DISP_MIXER 48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 07/14] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Add register definitions for MT8188
- Add VDOSYS1 routing table
- Update MUTEX definitions accordingly
- Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mt8188-mmsys.h | 126 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 9 ++
drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++
drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++
4 files changed, 199 insertions(+)
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 448cc3761b43..a9490c3c4256 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -67,6 +67,56 @@
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
+#define MT8188_VDO1_HDR_TOP_CFG 0xd00
+#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8188_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c
+#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
+#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
+#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2)
+#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3)
+#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
+#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
+#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8188_SOUT_TO_MIXER_IN1_SEL 1
+#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8188_SOUT_TO_MIXER_IN2_SEL 1
+#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8188_SOUT_TO_MIXER_IN3_SEL 1
+#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8188_SOUT_TO_MIXER_IN4_SEL 1
+#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
+#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -146,4 +196,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
},
};
+static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
+ {
+ DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+ MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+ MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+ MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8188_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
+ MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
+ }
+};
+
#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9619faa796e8..af4235f7a35f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -89,6 +89,14 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8188-vdo1",
+ .routes = mmsys_mt8188_vdo1_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
+ .num_resets = 96,
+ .vsync_len = 1,
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@@ -431,6 +439,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
+ { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
/* "mediatek,mt8195-mmsys" compatible is deprecated */
{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 6725403d2e3a..964b5449d672 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
u32 val;
};
+/**
+ * struct mtk_mmsys_driver_data - settings for the mmsys
+ * @clk_driver: Clock driver name that the mmsys is using
+ * (defined in drivers/clk/mediatek/clk-*.c).
+ * @routes: Routing table of the mmsys.
+ * It provides mux settings from one module to another.
+ * @num_routes: Array size of the routes.
+ * @sw0_rst_offset: Register offset for the reset control.
+ * @num_resets: Number of reset bits that are defined
+ * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
+ * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
+ * @vsync_len: VSYNC length of the MIXER.
+ * VSYNC is usually triggered by the connector, so its length is
+ * a fixed value as long as the frame rate is decided, but ETHDR and
+ * MIXER generate their own VSYNC due to hardware design, therefore
+ * MIXER has to sync with ETHDR by adjusting VSYNC length.
+ * On MT8195, there is no such setting so we use the gap between
+ * falling edge and rising edge of SOF (Start of Frame) signal to
+ * do the job, but since MT8188, VSYNC_LEN setting is introduced to
+ * solve the problem and is given 0x40 (ticks) as the default value.
+ * Please notice that this value has to be set to 1 (minimum) if
+ * ETHDR is bypassed, otherwise MIXER could wait too long and causing
+ * underflow.
+ *
+ * Each MMSYS (multi-media system) may have different settings, they may use
+ * different clock sources, mux settings, reset control ...etc., and these
+ * differences are all stored here.
+ */
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
@@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
const u16 sw0_rst_offset;
const u32 num_resets;
const bool is_vppsys;
+ const u8 vsync_len;
};
/*
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 4aa0913817ae..c3067b3c8ec4 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -134,6 +134,22 @@
#define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
#define MT8188_MUTEX_MOD2_DISP_PWM0 33
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24
+#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30
+#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39
+
#define MT8195_MUTEX_MOD_DISP_OVL0 0
#define MT8195_MUTEX_MOD_DISP_WDMA0 1
#define MT8195_MUTEX_MOD_DISP_RDMA0 2
@@ -265,6 +281,7 @@
#define MT8183_MUTEX_SOF_DPI0 2
#define MT8188_MUTEX_SOF_DSI0 1
#define MT8188_MUTEX_SOF_DP_INTF0 3
+#define MT8188_MUTEX_SOF_DP_INTF1 4
#define MT8195_MUTEX_SOF_DSI0 1
#define MT8195_MUTEX_SOF_DSI1 2
#define MT8195_MUTEX_SOF_DP_INTF0 3
@@ -276,6 +293,7 @@
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
#define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
#define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7)
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
+ [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
+ [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
+ [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
+ [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
+ [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
+ [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
+ [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
+ [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+ [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
+ [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
+ [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
+ [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
+ [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
};
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
[MUTEX_SOF_DP_INTF0] =
MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
};
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 07/14] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Add register definitions for MT8188
- Add VDOSYS1 routing table
- Update MUTEX definitions accordingly
- Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mt8188-mmsys.h | 126 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 9 ++
drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++
drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++
4 files changed, 199 insertions(+)
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index 448cc3761b43..a9490c3c4256 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -67,6 +67,56 @@
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
+#define MT8188_VDO1_HDR_TOP_CFG 0xd00
+#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8188_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c
+#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
+#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1
+#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0
+#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2)
+#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3)
+#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1
+#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1
+#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1
+#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8188_SOUT_TO_MIXER_IN1_SEL 1
+#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8188_SOUT_TO_MIXER_IN2_SEL 1
+#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8188_SOUT_TO_MIXER_IN3_SEL 1
+#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8188_SOUT_TO_MIXER_IN4_SEL 1
+#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1
+#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0
+#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -146,4 +196,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
},
};
+static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
+ {
+ DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
+ MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
+ MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
+ MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8188_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
+ MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
+ MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8188_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
+ MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
+ }
+};
+
#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9619faa796e8..af4235f7a35f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -89,6 +89,14 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8188-vdo1",
+ .routes = mmsys_mt8188_vdo1_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
+ .num_resets = 96,
+ .vsync_len = 1,
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@@ -431,6 +439,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },
{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },
{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },
+ { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data },
{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },
/* "mediatek,mt8195-mmsys" compatible is deprecated */
{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 6725403d2e3a..964b5449d672 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -86,6 +86,34 @@ struct mtk_mmsys_routes {
u32 val;
};
+/**
+ * struct mtk_mmsys_driver_data - settings for the mmsys
+ * @clk_driver: Clock driver name that the mmsys is using
+ * (defined in drivers/clk/mediatek/clk-*.c).
+ * @routes: Routing table of the mmsys.
+ * It provides mux settings from one module to another.
+ * @num_routes: Array size of the routes.
+ * @sw0_rst_offset: Register offset for the reset control.
+ * @num_resets: Number of reset bits that are defined
+ * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
+ * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
+ * @vsync_len: VSYNC length of the MIXER.
+ * VSYNC is usually triggered by the connector, so its length is
+ * a fixed value as long as the frame rate is decided, but ETHDR and
+ * MIXER generate their own VSYNC due to hardware design, therefore
+ * MIXER has to sync with ETHDR by adjusting VSYNC length.
+ * On MT8195, there is no such setting so we use the gap between
+ * falling edge and rising edge of SOF (Start of Frame) signal to
+ * do the job, but since MT8188, VSYNC_LEN setting is introduced to
+ * solve the problem and is given 0x40 (ticks) as the default value.
+ * Please notice that this value has to be set to 1 (minimum) if
+ * ETHDR is bypassed, otherwise MIXER could wait too long and causing
+ * underflow.
+ *
+ * Each MMSYS (multi-media system) may have different settings, they may use
+ * different clock sources, mux settings, reset control ...etc., and these
+ * differences are all stored here.
+ */
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
@@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data {
const u16 sw0_rst_offset;
const u32 num_resets;
const bool is_vppsys;
+ const u8 vsync_len;
};
/*
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 4aa0913817ae..c3067b3c8ec4 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -134,6 +134,22 @@
#define MT8188_MUTEX_MOD_DISP_POSTMASK0 24
#define MT8188_MUTEX_MOD2_DISP_PWM0 33
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
+#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23
+#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24
+#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30
+#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39
+
#define MT8195_MUTEX_MOD_DISP_OVL0 0
#define MT8195_MUTEX_MOD_DISP_WDMA0 1
#define MT8195_MUTEX_MOD_DISP_RDMA0 2
@@ -265,6 +281,7 @@
#define MT8183_MUTEX_SOF_DPI0 2
#define MT8188_MUTEX_SOF_DSI0 1
#define MT8188_MUTEX_SOF_DP_INTF0 3
+#define MT8188_MUTEX_SOF_DP_INTF1 4
#define MT8195_MUTEX_SOF_DSI0 1
#define MT8195_MUTEX_SOF_DSI1 2
#define MT8195_MUTEX_SOF_DP_INTF0 3
@@ -276,6 +293,7 @@
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
#define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7)
#define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7)
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
@@ -446,6 +464,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1,
+ [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0,
+ [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1,
+ [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2,
+ [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3,
+ [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4,
+ [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
+ [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
+ [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+ [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
+ [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
+ [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
+ [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3,
+ [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4,
};
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -606,6 +639,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = {
MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0,
[MUTEX_SOF_DP_INTF0] =
MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1,
};
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 08/14] soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Add Padding components
- Add Mutex module definitions for Padding
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++
include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c3067b3c8ec4..f2460d894d78 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -142,6 +142,14 @@
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
+#define MT8188_MUTEX_MOD_DISP1_PADDING0 8
+#define MT8188_MUTEX_MOD_DISP1_PADDING1 9
+#define MT8188_MUTEX_MOD_DISP1_PADDING2 10
+#define MT8188_MUTEX_MOD_DISP1_PADDING3 11
+#define MT8188_MUTEX_MOD_DISP1_PADDING4 12
+#define MT8188_MUTEX_MOD_DISP1_PADDING5 13
+#define MT8188_MUTEX_MOD_DISP1_PADDING6 14
+#define MT8188_MUTEX_MOD_DISP1_PADDING7 15
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
@@ -474,6 +482,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+ [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
+ [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
+ [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
+ [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
+ [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
+ [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
+ [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
+ [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2475ef914746..4885b065b849 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -62,6 +62,14 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_PADDING0,
+ DDP_COMPONENT_PADDING1,
+ DDP_COMPONENT_PADDING2,
+ DDP_COMPONENT_PADDING3,
+ DDP_COMPONENT_PADDING4,
+ DDP_COMPONENT_PADDING5,
+ DDP_COMPONENT_PADDING6,
+ DDP_COMPONENT_PADDING7,
DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 08/14] soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Add Padding components
- Add Mutex module definitions for Padding
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++
include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c3067b3c8ec4..f2460d894d78 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -142,6 +142,14 @@
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6
#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7
+#define MT8188_MUTEX_MOD_DISP1_PADDING0 8
+#define MT8188_MUTEX_MOD_DISP1_PADDING1 9
+#define MT8188_MUTEX_MOD_DISP1_PADDING2 10
+#define MT8188_MUTEX_MOD_DISP1_PADDING3 11
+#define MT8188_MUTEX_MOD_DISP1_PADDING4 12
+#define MT8188_MUTEX_MOD_DISP1_PADDING5 13
+#define MT8188_MUTEX_MOD_DISP1_PADDING6 14
+#define MT8188_MUTEX_MOD_DISP1_PADDING7 15
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21
#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22
@@ -474,6 +482,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5,
[DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6,
[DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7,
+ [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0,
+ [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1,
+ [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2,
+ [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3,
+ [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4,
+ [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5,
+ [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6,
+ [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7,
[DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0,
[DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1,
[DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2475ef914746..4885b065b849 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -62,6 +62,14 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_PADDING0,
+ DDP_COMPONENT_PADDING1,
+ DDP_COMPONENT_PADDING2,
+ DDP_COMPONENT_PADDING3,
+ DDP_COMPONENT_PADDING4,
+ DDP_COMPONENT_PADDING5,
+ DDP_COMPONENT_PADDING6,
+ DDP_COMPONENT_PADDING7,
DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 09/14] soc: mediatek: Support reset bit mapping in mmsys driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Reset ID must starts from 0 and be consecutive, but
the reset bits in our hardware design is not continuous,
some bits are left unused, we need a map to solve the problem
- Use old style 1-to-1 mapping if .rst_tb is not defined
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++
drivers/soc/mediatek/mtk-mmsys.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index af4235f7a35f..a7d2a21c11b2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -310,6 +310,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
u32 offset;
u32 reg;
+ if (mmsys->data->rst_tb) {
+ if (id >= mmsys->data->num_resets) {
+ dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
+ id, mmsys->data->num_resets);
+ return -EINVAL;
+ }
+ id = mmsys->data->rst_tb[id];
+ }
+
offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
id = id % MMSYS_SW_RESET_PER_REG;
reg = mmsys->data->sw0_rst_offset + offset;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 964b5449d672..dfbb742eaa11 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,6 +78,8 @@
#define DSI_SEL_IN_RDMA 0x1
#define DSI_SEL_IN_MASK 0x1
+#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
+
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
+ const u8 *rst_tb;
const u32 num_resets;
const bool is_vppsys;
const u8 vsync_len;
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 09/14] soc: mediatek: Support reset bit mapping in mmsys driver
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Reset ID must starts from 0 and be consecutive, but
the reset bits in our hardware design is not continuous,
some bits are left unused, we need a map to solve the problem
- Use old style 1-to-1 mapping if .rst_tb is not defined
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++
drivers/soc/mediatek/mtk-mmsys.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index af4235f7a35f..a7d2a21c11b2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -310,6 +310,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
u32 offset;
u32 reg;
+ if (mmsys->data->rst_tb) {
+ if (id >= mmsys->data->num_resets) {
+ dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
+ id, mmsys->data->num_resets);
+ return -EINVAL;
+ }
+ id = mmsys->data->rst_tb[id];
+ }
+
offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
id = id % MMSYS_SW_RESET_PER_REG;
reg = mmsys->data->sw0_rst_offset + offset;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 964b5449d672..dfbb742eaa11 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -78,6 +78,8 @@
#define DSI_SEL_IN_RDMA 0x1
#define DSI_SEL_IN_MASK 0x1
+#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
+
struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
+ const u8 *rst_tb;
const u32 num_resets;
const bool is_vppsys;
const u8 vsync_len;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 10/14] soc: mediatek: Add MT8188 VDOSYS reset bit map
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add MT8188 reset bit map for VDOSYS0 and VDOSYS1.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 7 ++-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index a9490c3c4256..6bebf1a69fc0 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -3,6 +3,10 @@
#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
#define __SOC_MEDIATEK_MT8188_MMSYS_H
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define MT8188_VDO0_SW0_RST_B 0x190
#define MT8188_VDO0_OVL_MOUT_EN 0xf14
#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
@@ -67,6 +71,7 @@
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
+#define MT8188_VDO1_SW0_RST_B 0x1d0
#define MT8188_VDO1_HDR_TOP_CFG 0xd00
#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30
#define MT8188_VDO1_MIXER_IN1_PAD 0xd40
@@ -117,6 +122,85 @@
#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
+ [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0),
+ [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2),
+ [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4),
+ [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6),
+ [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8),
+ [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10),
+ [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17),
+ [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19),
+ [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21),
+ [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22),
+ [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23),
+ [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24),
+ [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25),
+ [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26),
+ [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27),
+ [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28),
+ [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29),
+ [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30),
+ [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31),
+};
+
+static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
+ [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0),
+ [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1),
+ [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2),
+ [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3),
+ [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4),
+ [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5),
+ [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6),
+ [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7),
+ [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8),
+ [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9),
+ [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10),
+ [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11),
+ [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0),
+ [MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1),
+ [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2),
+ [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3),
+ [MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4),
+ [MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5),
+ [MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6),
+ [MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7),
+ [MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8),
+ [MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9),
+ [MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10),
+ [MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11),
+ [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13),
+ [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14),
+ [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15),
+ [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16),
+ [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17),
+ [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18),
+ [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19),
+ [MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20),
+ [MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21),
+ [MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22),
+ [MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23),
+ [MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24),
+ [MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25),
+ [MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26),
+ [MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27),
+ [MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28),
+ [MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29),
+ [MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30),
+ [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31),
+ [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0),
+ [MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1),
+ [MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2),
+ [MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16),
+ [MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17),
+ [MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18),
+ [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19),
+ [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20),
+ [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21),
+ [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22),
+ [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
+};
+
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a7d2a21c11b2..af80dbebbfc3 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -87,13 +87,18 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.clk_driver = "clk-mt8188-vdo0",
.routes = mmsys_mt8188_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
+ .sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
+ .rst_tb = mmsys_mt8188_vdo0_rst_tb,
+ .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
};
static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
.clk_driver = "clk-mt8188-vdo1",
.routes = mmsys_mt8188_vdo1_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
- .num_resets = 96,
+ .sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
+ .rst_tb = mmsys_mt8188_vdo1_rst_tb,
+ .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
.vsync_len = 1,
};
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 10/14] soc: mediatek: Add MT8188 VDOSYS reset bit map
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Add MT8188 reset bit map for VDOSYS0 and VDOSYS1.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 7 ++-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h
index a9490c3c4256..6bebf1a69fc0 100644
--- a/drivers/soc/mediatek/mt8188-mmsys.h
+++ b/drivers/soc/mediatek/mt8188-mmsys.h
@@ -3,6 +3,10 @@
#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H
#define __SOC_MEDIATEK_MT8188_MMSYS_H
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <dt-bindings/reset/mt8188-resets.h>
+
+#define MT8188_VDO0_SW0_RST_B 0x190
#define MT8188_VDO0_OVL_MOUT_EN 0xf14
#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
@@ -67,6 +71,7 @@
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18)
#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19)
+#define MT8188_VDO1_SW0_RST_B 0x1d0
#define MT8188_VDO1_HDR_TOP_CFG 0xd00
#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30
#define MT8188_VDO1_MIXER_IN1_PAD 0xd40
@@ -117,6 +122,85 @@
#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0
+static const u8 mmsys_mt8188_vdo0_rst_tb[] = {
+ [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0),
+ [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2),
+ [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4),
+ [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6),
+ [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8),
+ [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10),
+ [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17),
+ [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19),
+ [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21),
+ [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22),
+ [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23),
+ [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24),
+ [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25),
+ [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26),
+ [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27),
+ [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28),
+ [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29),
+ [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30),
+ [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31),
+};
+
+static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
+ [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0),
+ [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1),
+ [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2),
+ [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3),
+ [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4),
+ [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5),
+ [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6),
+ [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7),
+ [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8),
+ [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9),
+ [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10),
+ [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11),
+ [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0),
+ [MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1),
+ [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2),
+ [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3),
+ [MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4),
+ [MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5),
+ [MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6),
+ [MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7),
+ [MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8),
+ [MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9),
+ [MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10),
+ [MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11),
+ [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13),
+ [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14),
+ [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15),
+ [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16),
+ [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17),
+ [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18),
+ [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19),
+ [MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20),
+ [MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21),
+ [MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22),
+ [MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23),
+ [MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24),
+ [MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25),
+ [MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26),
+ [MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27),
+ [MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28),
+ [MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29),
+ [MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30),
+ [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31),
+ [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0),
+ [MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1),
+ [MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2),
+ [MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16),
+ [MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17),
+ [MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18),
+ [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19),
+ [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20),
+ [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21),
+ [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22),
+ [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23),
+};
+
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a7d2a21c11b2..af80dbebbfc3 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -87,13 +87,18 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.clk_driver = "clk-mt8188-vdo0",
.routes = mmsys_mt8188_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),
+ .sw0_rst_offset = MT8188_VDO0_SW0_RST_B,
+ .rst_tb = mmsys_mt8188_vdo0_rst_tb,
+ .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb),
};
static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = {
.clk_driver = "clk-mt8188-vdo1",
.routes = mmsys_mt8188_vdo1_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table),
- .num_resets = 96,
+ .sw0_rst_offset = MT8188_VDO1_SW0_RST_B,
+ .rst_tb = mmsys_mt8188_vdo1_rst_tb,
+ .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb),
.vsync_len = 1,
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 11/14] drm/mediatek: Support MT8188 VDOSYS1 in display driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since
VDOSYS1 was not available before. Increase it to support
VDOSYS1 in display driver.
- Add compatible name for MT8188 VDOSYS1
(shares the same driver data with MT8195 VDOSYS1)
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6dcb4ba2466c..613093068bb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -287,6 +287,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.main_path = mt8188_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
+ .mmsys_dev_num = 2,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -327,6 +328,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8186_mmsys_driver_data},
{ .compatible = "mediatek,mt8188-vdosys0",
.data = &mt8188_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8188-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-mmsys",
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 11/14] drm/mediatek: Support MT8188 VDOSYS1 in display driver
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since
VDOSYS1 was not available before. Increase it to support
VDOSYS1 in display driver.
- Add compatible name for MT8188 VDOSYS1
(shares the same driver data with MT8195 VDOSYS1)
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6dcb4ba2466c..613093068bb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -287,6 +287,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.main_path = mt8188_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
+ .mmsys_dev_num = 2,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -327,6 +328,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8186_mmsys_driver_data},
{ .compatible = "mediatek,mt8188-vdosys0",
.data = &mt8188_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8188-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-mmsys",
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
to align the naming rule of mtk_ovl_adaptor_comp_id.
- Sort components' names in alphabetical order
- Sort device table in alphabetical order
- Add sentinel to device table
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 61 ++++++++-----------
1 file changed, 27 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index c0a38f5217ee..38f389471f66 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -26,13 +26,14 @@
#define MTK_OVL_ADAPTOR_LAYER_NUM 4
enum mtk_ovl_adaptor_comp_type {
- OVL_ADAPTOR_TYPE_RDMA = 0,
- OVL_ADAPTOR_TYPE_MERGE,
OVL_ADAPTOR_TYPE_ETHDR,
+ OVL_ADAPTOR_TYPE_MDP_RDMA,
+ OVL_ADAPTOR_TYPE_MERGE,
OVL_ADAPTOR_TYPE_NUM,
};
enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_ETHDR0,
OVL_ADAPTOR_MDP_RDMA0,
OVL_ADAPTOR_MDP_RDMA1,
OVL_ADAPTOR_MDP_RDMA2,
@@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id {
OVL_ADAPTOR_MERGE1,
OVL_ADAPTOR_MERGE2,
OVL_ADAPTOR_MERGE3,
- OVL_ADAPTOR_ETHDR0,
OVL_ADAPTOR_ID_MAX
};
@@ -61,25 +61,25 @@ struct mtk_disp_ovl_adaptor {
};
static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
- [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma",
- [OVL_ADAPTOR_TYPE_MERGE] = "merge",
[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
+ [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
};
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -89,10 +89,10 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
struct mtk_plane_pending_state *pending = &state->pending;
struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct device *ethdr;
+ struct device *merge;
struct device *rdma_l;
struct device *rdma_r;
- struct device *merge;
- struct device *ethdr;
const struct drm_format_info *fmt_info = drm_format_info(pending->format);
bool use_dual_pipe = false;
unsigned int align_width;
@@ -105,16 +105,16 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
&pending->addr, (pending->pitch / fmt_info->cpp[0]),
pending->x, pending->y, pending->width, pending->height);
+ ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
- merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
- ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
if (!pending->enable) {
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
mtk_merge_stop_cmdq(merge, cmdq_pkt);
mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
- mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
return;
}
@@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
{
+ mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
@@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
}
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
{
+ mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
@@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
}
void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
{
+ mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
@@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsig
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
}
void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)
{
+ mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
@@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, un
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
}
static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
@@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
}
static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
- {
- .compatible = "mediatek,mt8195-vdo1-rdma",
- .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
- }, {
- .compatible = "mediatek,mt8195-disp-merge",
- .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
- }, {
- .compatible = "mediatek,mt8195-disp-ethdr",
- .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
- },
- {},
+ { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
+ { .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
+ { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
+ { /* sentinel */ }
};
static int compare_of(struct device *dev, void *data)
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
to align the naming rule of mtk_ovl_adaptor_comp_id.
- Sort components' names in alphabetical order
- Sort device table in alphabetical order
- Add sentinel to device table
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 61 ++++++++-----------
1 file changed, 27 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index c0a38f5217ee..38f389471f66 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -26,13 +26,14 @@
#define MTK_OVL_ADAPTOR_LAYER_NUM 4
enum mtk_ovl_adaptor_comp_type {
- OVL_ADAPTOR_TYPE_RDMA = 0,
- OVL_ADAPTOR_TYPE_MERGE,
OVL_ADAPTOR_TYPE_ETHDR,
+ OVL_ADAPTOR_TYPE_MDP_RDMA,
+ OVL_ADAPTOR_TYPE_MERGE,
OVL_ADAPTOR_TYPE_NUM,
};
enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_ETHDR0,
OVL_ADAPTOR_MDP_RDMA0,
OVL_ADAPTOR_MDP_RDMA1,
OVL_ADAPTOR_MDP_RDMA2,
@@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id {
OVL_ADAPTOR_MERGE1,
OVL_ADAPTOR_MERGE2,
OVL_ADAPTOR_MERGE3,
- OVL_ADAPTOR_ETHDR0,
OVL_ADAPTOR_ID_MAX
};
@@ -61,25 +61,25 @@ struct mtk_disp_ovl_adaptor {
};
static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
- [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma",
- [OVL_ADAPTOR_TYPE_MERGE] = "merge",
[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
+ [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
};
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
[OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -89,10 +89,10 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
struct mtk_plane_pending_state *pending = &state->pending;
struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct device *ethdr;
+ struct device *merge;
struct device *rdma_l;
struct device *rdma_r;
- struct device *merge;
- struct device *ethdr;
const struct drm_format_info *fmt_info = drm_format_info(pending->format);
bool use_dual_pipe = false;
unsigned int align_width;
@@ -105,16 +105,16 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
&pending->addr, (pending->pitch / fmt_info->cpp[0]),
pending->x, pending->y, pending->width, pending->height);
+ ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
- merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
- ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
if (!pending->enable) {
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
mtk_merge_stop_cmdq(merge, cmdq_pkt);
mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
- mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
return;
}
@@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
{
+ mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
@@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
}
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
{
+ mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
@@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
}
void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
{
+ mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
@@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsig
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
}
void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)
{
+ mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
@@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, un
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
}
static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
@@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
}
static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
- {
- .compatible = "mediatek,mt8195-vdo1-rdma",
- .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
- }, {
- .compatible = "mediatek,mt8195-disp-merge",
- .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
- }, {
- .compatible = "mediatek,mt8195-disp-ethdr",
- .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
- },
- {},
+ { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
+ { .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
+ { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
+ { /* sentinel */ }
};
static int compare_of(struct device *dev, void *data)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Register functions to enable/disable clock and reuse them
to simplify the code
- Check if the component is defined before using it since
some modules are MT8188 only (ex. PADDING)
- Control components according to its type rather than ID
- Use a for-loop to add/remove components in an arrays,
so we only has to maintain the array to make sure every
component will be initialized properly
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 154 +++++++-----------
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++-
2 files changed, 79 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 38f389471f66..f73a558dcf93 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -51,7 +51,9 @@ enum mtk_ovl_adaptor_comp_id {
struct ovl_adaptor_comp_match {
enum mtk_ovl_adaptor_comp_type type;
+ enum mtk_ddp_comp_id comp_id;
int alias_id;
+ const struct mtk_ddp_comp_funcs *funcs;
};
struct mtk_disp_ovl_adaptor {
@@ -66,20 +68,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_MERGE] = "merge",
};
+static const struct mtk_ddp_comp_funcs _ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs _merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs _rdma = {
+ .clk_enable = mtk_mdp_rdma_clk_enable,
+ .clk_disable = mtk_mdp_rdma_clk_disable,
+};
+
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
- [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
- [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
- [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
- [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &_merge },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -185,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
int mtk_ovl_adaptor_clk_enable(struct device *dev)
{
- struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
- struct device *comp;
- int ret;
int i;
-
- for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- ret = pm_runtime_get_sync(comp);
- if (ret < 0) {
- dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
- goto pwr_err;
- }
- }
+ int ret;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0)
- ret = mtk_mdp_rdma_clk_enable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- ret = mtk_merge_clk_enable(comp);
- else
- ret = mtk_ethdr_clk_enable(comp);
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev)
+ continue;
+ ret = comp_matches[i].funcs->clk_enable(dev);
if (ret) {
- dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
- goto clk_err;
+ while (--i >= 0)
+ comp_matches[i].funcs->clk_disable(dev);
+ return ret;
}
}
-
- return ret;
-
-clk_err:
- while (--i >= 0) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- if (i < OVL_ADAPTOR_MERGE0)
- mtk_mdp_rdma_clk_disable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- mtk_merge_clk_disable(comp);
- else
- mtk_ethdr_clk_disable(comp);
- }
- i = OVL_ADAPTOR_MERGE0;
-
-pwr_err:
- while (--i >= 0)
- pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
-
- return ret;
+ return 0;
}
void mtk_ovl_adaptor_clk_disable(struct device *dev)
{
- struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
- struct device *comp;
int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0) {
- mtk_mdp_rdma_clk_disable(comp);
- pm_runtime_put(comp);
- } else if (i < OVL_ADAPTOR_ETHDR0) {
- mtk_merge_clk_disable(comp);
- } else {
- mtk_ethdr_clk_disable(comp);
- }
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev)
+ continue;
+ comp_matches[i].funcs->clk_disable(dev);
}
}
@@ -313,36 +291,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
{
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
+ int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ if (!ovl_adaptor->ovl_adaptor_comp[i])
+ continue;
+ mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
+ }
}
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
{
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
+ int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ if (!ovl_adaptor->ovl_adaptor_comp[i])
+ continue;
+ mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
+ }
}
void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
index e06db6e56b5f..a37146544e30 100644
--- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -245,10 +245,23 @@ size_t mtk_mdp_rdma_get_num_formats(struct device *dev)
int mtk_mdp_rdma_clk_enable(struct device *dev)
{
+ int ret;
struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
- clk_prepare_enable(rdma->clk);
- return 0;
+ /*
+ * Since LARBs (Local ARBiter) have to be powered on before its users,
+ * to ensure the power-on sequence, we created device link between
+ * RDMA and its LARB, and when pm_runtime_get_sync is called in RDMA,
+ * system will make sure the LARB is powered on, then the RDMA
+ */
+ ret = pm_runtime_get_sync(dev);
+
+ if (ret < 0)
+ dev_err(dev, "pm_runtime_get_sync failed: %d\n", ret);
+ else
+ ret = clk_prepare_enable(rdma->clk);
+
+ return ret;
}
void mtk_mdp_rdma_clk_disable(struct device *dev)
@@ -256,6 +269,9 @@ void mtk_mdp_rdma_clk_disable(struct device *dev)
struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
clk_disable_unprepare(rdma->clk);
+
+ /* Same reason as when enabling clock, turn the LARB off */
+ pm_runtime_put(dev);
}
static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
- Register functions to enable/disable clock and reuse them
to simplify the code
- Check if the component is defined before using it since
some modules are MT8188 only (ex. PADDING)
- Control components according to its type rather than ID
- Use a for-loop to add/remove components in an arrays,
so we only has to maintain the array to make sure every
component will be initialized properly
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 154 +++++++-----------
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++-
2 files changed, 79 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 38f389471f66..f73a558dcf93 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -51,7 +51,9 @@ enum mtk_ovl_adaptor_comp_id {
struct ovl_adaptor_comp_match {
enum mtk_ovl_adaptor_comp_type type;
+ enum mtk_ddp_comp_id comp_id;
int alias_id;
+ const struct mtk_ddp_comp_funcs *funcs;
};
struct mtk_disp_ovl_adaptor {
@@ -66,20 +68,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_MERGE] = "merge",
};
+static const struct mtk_ddp_comp_funcs _ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs _merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+};
+
+static const struct mtk_ddp_comp_funcs _rdma = {
+ .clk_enable = mtk_mdp_rdma_clk_enable,
+ .clk_disable = mtk_mdp_rdma_clk_disable,
+};
+
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
- [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
- [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
- [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
- [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &_merge },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -185,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
int mtk_ovl_adaptor_clk_enable(struct device *dev)
{
- struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
- struct device *comp;
- int ret;
int i;
-
- for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- ret = pm_runtime_get_sync(comp);
- if (ret < 0) {
- dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret);
- goto pwr_err;
- }
- }
+ int ret;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0)
- ret = mtk_mdp_rdma_clk_enable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- ret = mtk_merge_clk_enable(comp);
- else
- ret = mtk_ethdr_clk_enable(comp);
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev)
+ continue;
+ ret = comp_matches[i].funcs->clk_enable(dev);
if (ret) {
- dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret);
- goto clk_err;
+ while (--i >= 0)
+ comp_matches[i].funcs->clk_disable(dev);
+ return ret;
}
}
-
- return ret;
-
-clk_err:
- while (--i >= 0) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
- if (i < OVL_ADAPTOR_MERGE0)
- mtk_mdp_rdma_clk_disable(comp);
- else if (i < OVL_ADAPTOR_ETHDR0)
- mtk_merge_clk_disable(comp);
- else
- mtk_ethdr_clk_disable(comp);
- }
- i = OVL_ADAPTOR_MERGE0;
-
-pwr_err:
- while (--i >= 0)
- pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
-
- return ret;
+ return 0;
}
void mtk_ovl_adaptor_clk_disable(struct device *dev)
{
- struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
- struct device *comp;
int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
- comp = ovl_adaptor->ovl_adaptor_comp[i];
-
- if (i < OVL_ADAPTOR_MERGE0) {
- mtk_mdp_rdma_clk_disable(comp);
- pm_runtime_put(comp);
- } else if (i < OVL_ADAPTOR_ETHDR0) {
- mtk_merge_clk_disable(comp);
- } else {
- mtk_ethdr_clk_disable(comp);
- }
+ dev = ovl_adaptor->ovl_adaptor_comp[i];
+ if (!dev)
+ continue;
+ comp_matches[i].funcs->clk_disable(dev);
}
}
@@ -313,36 +291,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
{
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
- mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
+ int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ if (!ovl_adaptor->ovl_adaptor_comp[i])
+ continue;
+ mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
+ }
}
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
{
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
- mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
+ int i;
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ if (!ovl_adaptor->ovl_adaptor_comp[i])
+ continue;
+ mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
+ }
}
void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
index e06db6e56b5f..a37146544e30 100644
--- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -245,10 +245,23 @@ size_t mtk_mdp_rdma_get_num_formats(struct device *dev)
int mtk_mdp_rdma_clk_enable(struct device *dev)
{
+ int ret;
struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
- clk_prepare_enable(rdma->clk);
- return 0;
+ /*
+ * Since LARBs (Local ARBiter) have to be powered on before its users,
+ * to ensure the power-on sequence, we created device link between
+ * RDMA and its LARB, and when pm_runtime_get_sync is called in RDMA,
+ * system will make sure the LARB is powered on, then the RDMA
+ */
+ ret = pm_runtime_get_sync(dev);
+
+ if (ret < 0)
+ dev_err(dev, "pm_runtime_get_sync failed: %d\n", ret);
+ else
+ ret = clk_prepare_enable(rdma->clk);
+
+ return ret;
}
void mtk_mdp_rdma_clk_disable(struct device *dev)
@@ -256,6 +269,9 @@ void mtk_mdp_rdma_clk_disable(struct device *dev)
struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
clk_disable_unprepare(rdma->clk);
+
+ /* Same reason as when enabling clock, turn the LARB off */
+ pm_runtime_put(dev);
}
static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 14/14] drm/mediatek: Support MT8188 Padding in display driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 6:39 ` Hsiao Chien Sung
-1 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Padding is a new display module on MT8188, it provides ability
to add pixels to width and height of a layer with specified colors.
Due to hardware design, Mixer in VDOSYS1 requires width of a layer
to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
we need Padding to deal with odd width.
Please notice that even if the Padding is in bypass mode,
settings in register must be cleared to 0,
or undefined behaviors could happen.
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 33 +++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
drivers/gpu/drm/mediatek/mtk_padding.c | 136 ++++++++++++++++++
6 files changed, 176 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..5e4436403b8d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_ethdr.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_padding.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..f9fdb1268aa5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
size_t mtk_mdp_rdma_get_num_formats(struct device *dev);
+int mtk_padding_clk_enable(struct device *dev);
+void mtk_padding_clk_disable(struct device *dev);
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt);
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index f73a558dcf93..ca8f3febbf11 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -29,6 +29,7 @@ enum mtk_ovl_adaptor_comp_type {
OVL_ADAPTOR_TYPE_ETHDR,
OVL_ADAPTOR_TYPE_MDP_RDMA,
OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_PADDING,
OVL_ADAPTOR_TYPE_NUM,
};
@@ -46,6 +47,14 @@ enum mtk_ovl_adaptor_comp_id {
OVL_ADAPTOR_MERGE1,
OVL_ADAPTOR_MERGE2,
OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_PADDING0,
+ OVL_ADAPTOR_PADDING1,
+ OVL_ADAPTOR_PADDING2,
+ OVL_ADAPTOR_PADDING3,
+ OVL_ADAPTOR_PADDING4,
+ OVL_ADAPTOR_PADDING5,
+ OVL_ADAPTOR_PADDING6,
+ OVL_ADAPTOR_PADDING7,
OVL_ADAPTOR_ID_MAX
};
@@ -66,6 +75,7 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
[OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
[OVL_ADAPTOR_TYPE_MERGE] = "merge",
+ [OVL_ADAPTOR_TYPE_PADDING] = "padding",
};
static const struct mtk_ddp_comp_funcs _ethdr = {
@@ -78,6 +88,11 @@ static const struct mtk_ddp_comp_funcs _merge = {
.clk_disable = mtk_merge_clk_disable,
};
+static const struct mtk_ddp_comp_funcs _padding = {
+ .clk_enable = mtk_padding_clk_enable,
+ .clk_disable = mtk_padding_clk_disable,
+};
+
static const struct mtk_ddp_comp_funcs _rdma = {
.clk_enable = mtk_mdp_rdma_clk_enable,
.clk_disable = mtk_mdp_rdma_clk_disable,
@@ -97,6 +112,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
+ [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0, &_padding },
+ [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1, &_padding },
+ [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2, &_padding },
+ [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3, &_padding },
+ [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4, &_padding },
+ [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5, &_padding },
+ [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6, &_padding },
+ [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7, &_padding },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -108,6 +131,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
struct mtk_mdp_rdma_cfg rdma_config = {0};
struct device *ethdr;
struct device *merge;
+ struct device *padding_l;
+ struct device *padding_r;
struct device *rdma_l;
struct device *rdma_r;
const struct drm_format_info *fmt_info = drm_format_info(pending->format);
@@ -124,6 +149,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+ padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx];
+ padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx + 1];
rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
@@ -159,10 +186,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
rdma_config.color_encoding = pending->color_encoding;
mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
+ if (padding_l)
+ mtk_padding_config(padding_l, cmdq_pkt);
+
if (use_dual_pipe) {
rdma_config.x_left = l_w;
rdma_config.width = r_w;
mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+ if (padding_r)
+ mtk_padding_config(padding_r, cmdq_pkt);
}
mtk_merge_start_cmdq(merge, cmdq_pkt);
@@ -353,6 +385,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
}
static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ { .compatible = "mediatek,mt8188-padding", .data = (void *)OVL_ADAPTOR_TYPE_PADDING },
{ .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
{ .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
{ .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 613093068bb4..ed5b5b8d6c2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -977,6 +977,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dsi_driver,
&mtk_ethdr_driver,
&mtk_mdp_rdma_driver,
+ &mtk_padding_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index eb2fd45941f0..562f2db47add 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
extern struct platform_driver mtk_ethdr_driver;
extern struct platform_driver mtk_mdp_rdma_driver;
-
+extern struct platform_driver mtk_padding_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c
new file mode 100644
index 000000000000..bbb9c5e286ce
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_padding.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+/**
+ * struct mtk_padding - basic information of Padding
+ * @clk: Clock of the module
+ * @regs: Virtual address of the Padding for CPU to access
+ * @cmdq_reg: CMDQ setting of the Padding
+ *
+ * Every Padding should have different clock source, register base, and
+ * CMDQ settings, we stored these differences all together.
+ */
+struct mtk_padding {
+ struct clk *clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+};
+
+int mtk_padding_clk_enable(struct device *dev)
+{
+ struct mtk_padding *padding = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(padding->clk);
+}
+
+void mtk_padding_clk_disable(struct device *dev)
+{
+ struct mtk_padding *padding = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(padding->clk);
+}
+
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_padding *padding = dev_get_drvdata(dev);
+
+ /* bypass padding */
+ mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->regs, 0,
+ GENMASK(1, 0));
+}
+
+static int mtk_padding_bind(struct device *dev, struct device *master, void *data)
+{
+ return 0;
+}
+
+static void mtk_padding_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_padding_component_ops = {
+ .bind = mtk_padding_bind,
+ .unbind = mtk_padding_unbind,
+};
+
+static int mtk_padding_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_padding *priv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to do ioremap\n");
+ return PTR_ERR(priv->regs);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret) {
+ dev_err(dev, "failed to get gce client reg\n");
+ return ret;
+ }
+#endif
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ ret = component_add(dev, &mtk_padding_component_ops);
+ if (ret) {
+ pm_runtime_disable(dev);
+ return dev_err_probe(dev, ret, "failed to add component\n");
+ }
+
+ return 0;
+}
+
+static int mtk_padding_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_padding_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_padding_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8188-padding" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);
+
+struct platform_driver mtk_padding_driver = {
+ .probe = mtk_padding_probe,
+ .remove = mtk_padding_remove,
+ .driver = {
+ .name = "mediatek-padding",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_padding_driver_dt_match,
+ },
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [PATCH v5 14/14] drm/mediatek: Support MT8188 Padding in display driver
@ 2023-06-27 6:39 ` Hsiao Chien Sung
0 siblings, 0 replies; 45+ messages in thread
From: Hsiao Chien Sung @ 2023-06-27 6:39 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin, Shawn Sung
Padding is a new display module on MT8188, it provides ability
to add pixels to width and height of a layer with specified colors.
Due to hardware design, Mixer in VDOSYS1 requires width of a layer
to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
we need Padding to deal with odd width.
Please notice that even if the Padding is in bypass mode,
settings in register must be cleared to 0,
or undefined behaviors could happen.
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 33 +++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
drivers/gpu/drm/mediatek/mtk_padding.c | 136 ++++++++++++++++++
6 files changed, 176 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..5e4436403b8d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_dsi.o \
mtk_dpi.o \
mtk_ethdr.o \
- mtk_mdp_rdma.o
+ mtk_mdp_rdma.o \
+ mtk_padding.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2254038519e1..f9fdb1268aa5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
size_t mtk_mdp_rdma_get_num_formats(struct device *dev);
+int mtk_padding_clk_enable(struct device *dev);
+void mtk_padding_clk_disable(struct device *dev);
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt);
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index f73a558dcf93..ca8f3febbf11 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -29,6 +29,7 @@ enum mtk_ovl_adaptor_comp_type {
OVL_ADAPTOR_TYPE_ETHDR,
OVL_ADAPTOR_TYPE_MDP_RDMA,
OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_PADDING,
OVL_ADAPTOR_TYPE_NUM,
};
@@ -46,6 +47,14 @@ enum mtk_ovl_adaptor_comp_id {
OVL_ADAPTOR_MERGE1,
OVL_ADAPTOR_MERGE2,
OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_PADDING0,
+ OVL_ADAPTOR_PADDING1,
+ OVL_ADAPTOR_PADDING2,
+ OVL_ADAPTOR_PADDING3,
+ OVL_ADAPTOR_PADDING4,
+ OVL_ADAPTOR_PADDING5,
+ OVL_ADAPTOR_PADDING6,
+ OVL_ADAPTOR_PADDING7,
OVL_ADAPTOR_ID_MAX
};
@@ -66,6 +75,7 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
[OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
[OVL_ADAPTOR_TYPE_MERGE] = "merge",
+ [OVL_ADAPTOR_TYPE_PADDING] = "padding",
};
static const struct mtk_ddp_comp_funcs _ethdr = {
@@ -78,6 +88,11 @@ static const struct mtk_ddp_comp_funcs _merge = {
.clk_disable = mtk_merge_clk_disable,
};
+static const struct mtk_ddp_comp_funcs _padding = {
+ .clk_enable = mtk_padding_clk_enable,
+ .clk_disable = mtk_padding_clk_disable,
+};
+
static const struct mtk_ddp_comp_funcs _rdma = {
.clk_enable = mtk_mdp_rdma_clk_enable,
.clk_disable = mtk_mdp_rdma_clk_disable,
@@ -97,6 +112,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
+ [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0, &_padding },
+ [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1, &_padding },
+ [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2, &_padding },
+ [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3, &_padding },
+ [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4, &_padding },
+ [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5, &_padding },
+ [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6, &_padding },
+ [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7, &_padding },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -108,6 +131,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
struct mtk_mdp_rdma_cfg rdma_config = {0};
struct device *ethdr;
struct device *merge;
+ struct device *padding_l;
+ struct device *padding_r;
struct device *rdma_l;
struct device *rdma_r;
const struct drm_format_info *fmt_info = drm_format_info(pending->format);
@@ -124,6 +149,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+ padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx];
+ padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * idx + 1];
rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
@@ -159,10 +186,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
rdma_config.color_encoding = pending->color_encoding;
mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
+ if (padding_l)
+ mtk_padding_config(padding_l, cmdq_pkt);
+
if (use_dual_pipe) {
rdma_config.x_left = l_w;
rdma_config.width = r_w;
mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+ if (padding_r)
+ mtk_padding_config(padding_r, cmdq_pkt);
}
mtk_merge_start_cmdq(merge, cmdq_pkt);
@@ -353,6 +385,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
}
static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ { .compatible = "mediatek,mt8188-padding", .data = (void *)OVL_ADAPTOR_TYPE_PADDING },
{ .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
{ .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
{ .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 613093068bb4..ed5b5b8d6c2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -977,6 +977,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dsi_driver,
&mtk_ethdr_driver,
&mtk_mdp_rdma_driver,
+ &mtk_padding_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index eb2fd45941f0..562f2db47add 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
extern struct platform_driver mtk_ethdr_driver;
extern struct platform_driver mtk_mdp_rdma_driver;
-
+extern struct platform_driver mtk_padding_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/mediatek/mtk_padding.c
new file mode 100644
index 000000000000..bbb9c5e286ce
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_padding.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+/**
+ * struct mtk_padding - basic information of Padding
+ * @clk: Clock of the module
+ * @regs: Virtual address of the Padding for CPU to access
+ * @cmdq_reg: CMDQ setting of the Padding
+ *
+ * Every Padding should have different clock source, register base, and
+ * CMDQ settings, we stored these differences all together.
+ */
+struct mtk_padding {
+ struct clk *clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+};
+
+int mtk_padding_clk_enable(struct device *dev)
+{
+ struct mtk_padding *padding = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(padding->clk);
+}
+
+void mtk_padding_clk_disable(struct device *dev)
+{
+ struct mtk_padding *padding = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(padding->clk);
+}
+
+void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_padding *padding = dev_get_drvdata(dev);
+
+ /* bypass padding */
+ mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->regs, 0,
+ GENMASK(1, 0));
+}
+
+static int mtk_padding_bind(struct device *dev, struct device *master, void *data)
+{
+ return 0;
+}
+
+static void mtk_padding_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_padding_component_ops = {
+ .bind = mtk_padding_bind,
+ .unbind = mtk_padding_unbind,
+};
+
+static int mtk_padding_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_padding *priv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to do ioremap\n");
+ return PTR_ERR(priv->regs);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret) {
+ dev_err(dev, "failed to get gce client reg\n");
+ return ret;
+ }
+#endif
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ ret = component_add(dev, &mtk_padding_component_ops);
+ if (ret) {
+ pm_runtime_disable(dev);
+ return dev_err_probe(dev, ret, "failed to add component\n");
+ }
+
+ return 0;
+}
+
+static int mtk_padding_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_padding_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_padding_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8188-padding" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);
+
+struct platform_driver mtk_padding_driver = {
+ .probe = mtk_padding_probe,
+ .remove = mtk_padding_remove,
+ .driver = {
+ .name = "mediatek-padding",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_padding_driver_dt_match,
+ },
+};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 10:52 ` Alexandre Mergnat
-1 siblings, 0 replies; 45+ messages in thread
From: Alexandre Mergnat @ 2023-06-27 10:52 UTC (permalink / raw)
To: Hsiao Chien Sung, AngeloGioacchino Del Regno, Chun-Kuang Hu,
Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel,
Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin
On 27/06/2023 08:39, Hsiao Chien Sung wrote:
> - Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
> to align the naming rule of mtk_ovl_adaptor_comp_id.
> - Sort components' names in alphabetical order
> - Sort device table in alphabetical order
> - Add sentinel to device table
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 61 ++++++++-----------
> 1 file changed, 27 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..38f389471f66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -26,13 +26,14 @@
> #define MTK_OVL_ADAPTOR_LAYER_NUM 4
>
> enum mtk_ovl_adaptor_comp_type {
> - OVL_ADAPTOR_TYPE_RDMA = 0,
> - OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_MDP_RDMA,
> + OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_NUM,
> };
>
> enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_MDP_RDMA0,
> OVL_ADAPTOR_MDP_RDMA1,
> OVL_ADAPTOR_MDP_RDMA2,
> @@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id {
> OVL_ADAPTOR_MERGE1,
> OVL_ADAPTOR_MERGE2,
> OVL_ADAPTOR_MERGE3,
> - OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_ID_MAX
> };
>
> @@ -61,25 +61,25 @@ struct mtk_disp_ovl_adaptor {
> };
>
> static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> - [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma",
> - [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> + [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> };
>
> static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> @@ -89,10 +89,10 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> struct mtk_plane_pending_state *pending = &state->pending;
> struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *ethdr;
> + struct device *merge;
> struct device *rdma_l;
> struct device *rdma_r;
> - struct device *merge;
> - struct device *ethdr;
> const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> bool use_dual_pipe = false;
> unsigned int align_width;
> @@ -105,16 +105,16 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> &pending->addr, (pending->pitch / fmt_info->cpp[0]),
> pending->x, pending->y, pending->width, pending->height);
>
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> - merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> - ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
>
> if (!pending->enable) {
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> mtk_merge_stop_cmdq(merge, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> - mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> return;
> }
>
> @@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
>
> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
> {
> + mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
> {
> + mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
> @@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsig
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> }
>
> void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
> @@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, un
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> }
>
> static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> @@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> }
>
> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> - {
> - .compatible = "mediatek,mt8195-vdo1-rdma",
> - .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> - }, {
> - .compatible = "mediatek,mt8195-disp-merge",
> - .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> - }, {
> - .compatible = "mediatek,mt8195-disp-ethdr",
> - .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> - },
> - {},
> + { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
> + { .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
> + { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
The lines is > 80 columns.
https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
Actually, there are other lines in this file greater than 80, but IMHO,
it isn't a reason to continue to do that.
After that, everything looks fine for me.
> + { /* sentinel */ }
> };
>
> static int compare_of(struct device *dev, void *data)
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order
@ 2023-06-27 10:52 ` Alexandre Mergnat
0 siblings, 0 replies; 45+ messages in thread
From: Alexandre Mergnat @ 2023-06-27 10:52 UTC (permalink / raw)
To: Hsiao Chien Sung, AngeloGioacchino Del Regno, Chun-Kuang Hu,
Krzysztof Kozlowski, Matthias Brugger, Philipp Zabel,
Rob Herring
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin
On 27/06/2023 08:39, Hsiao Chien Sung wrote:
> - Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
> to align the naming rule of mtk_ovl_adaptor_comp_id.
> - Sort components' names in alphabetical order
> - Sort device table in alphabetical order
> - Add sentinel to device table
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 61 ++++++++-----------
> 1 file changed, 27 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..38f389471f66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -26,13 +26,14 @@
> #define MTK_OVL_ADAPTOR_LAYER_NUM 4
>
> enum mtk_ovl_adaptor_comp_type {
> - OVL_ADAPTOR_TYPE_RDMA = 0,
> - OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_MDP_RDMA,
> + OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_NUM,
> };
>
> enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_MDP_RDMA0,
> OVL_ADAPTOR_MDP_RDMA1,
> OVL_ADAPTOR_MDP_RDMA2,
> @@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id {
> OVL_ADAPTOR_MERGE1,
> OVL_ADAPTOR_MERGE2,
> OVL_ADAPTOR_MERGE3,
> - OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_ID_MAX
> };
>
> @@ -61,25 +61,25 @@ struct mtk_disp_ovl_adaptor {
> };
>
> static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> - [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma",
> - [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> + [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> };
>
> static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> @@ -89,10 +89,10 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> struct mtk_plane_pending_state *pending = &state->pending;
> struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *ethdr;
> + struct device *merge;
> struct device *rdma_l;
> struct device *rdma_r;
> - struct device *merge;
> - struct device *ethdr;
> const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> bool use_dual_pipe = false;
> unsigned int align_width;
> @@ -105,16 +105,16 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> &pending->addr, (pending->pitch / fmt_info->cpp[0]),
> pending->x, pending->y, pending->width, pending->height);
>
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> - merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> - ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
>
> if (!pending->enable) {
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> mtk_merge_stop_cmdq(merge, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> - mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> return;
> }
>
> @@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev)
>
> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
> {
> + mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
> {
> + mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
> @@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsig
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> }
>
> void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
> @@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, un
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
> }
>
> static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> @@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> }
>
> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> - {
> - .compatible = "mediatek,mt8195-vdo1-rdma",
> - .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> - }, {
> - .compatible = "mediatek,mt8195-disp-merge",
> - .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> - }, {
> - .compatible = "mediatek,mt8195-disp-ethdr",
> - .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> - },
> - {},
> + { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
> + { .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
> + { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
The lines is > 80 columns.
https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
Actually, there are other lines in this file greater than 80, but IMHO,
it isn't a reason to continue to do that.
After that, everything looks fine for me.
> + { /* sentinel */ }
> };
>
> static int compare_of(struct device *dev, void *data)
--
Regards,
Alexandre
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-06-27 13:48 ` Alexandre Mergnat
-1 siblings, 0 replies; 45+ messages in thread
From: Alexandre Mergnat @ 2023-06-27 13:48 UTC (permalink / raw)
To: Hsiao Chien Sung
Cc: Rob Herring, Philipp Zabel, Chun-Kuang Hu, Matthias Brugger,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin
On 27/06/2023 08:39, Hsiao Chien Sung wrote:
> - Register functions to enable/disable clock and reuse them
> to simplify the code
> - Check if the component is defined before using it since
> some modules are MT8188 only (ex. PADDING)
> - Control components according to its type rather than ID
> - Use a for-loop to add/remove components in an arrays,
> so we only has to maintain the array to make sure every
> component will be initialized properly
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 154 +++++++-----------
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++-
> 2 files changed, 79 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index 38f389471f66..f73a558dcf93 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,7 +51,9 @@ enum mtk_ovl_adaptor_comp_id {
>
...
snip
...
> +};
> +
> static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &_merge },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
The lines is > 80 columns.
https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> @@ -185,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
>
> int mtk_ovl_adaptor_clk_enable(struct device *dev)
> {
> - struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> - struct device *comp;
> - int ret;
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
@ 2023-06-27 13:48 ` Alexandre Mergnat
0 siblings, 0 replies; 45+ messages in thread
From: Alexandre Mergnat @ 2023-06-27 13:48 UTC (permalink / raw)
To: Hsiao Chien Sung
Cc: Rob Herring, Philipp Zabel, Chun-Kuang Hu, Matthias Brugger,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin
On 27/06/2023 08:39, Hsiao Chien Sung wrote:
> - Register functions to enable/disable clock and reuse them
> to simplify the code
> - Check if the component is defined before using it since
> some modules are MT8188 only (ex. PADDING)
> - Control components according to its type rather than ID
> - Use a for-loop to add/remove components in an arrays,
> so we only has to maintain the array to make sure every
> component will be initialized properly
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 154 +++++++-----------
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++-
> 2 files changed, 79 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index 38f389471f66..f73a558dcf93 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,7 +51,9 @@ enum mtk_ovl_adaptor_comp_id {
>
...
snip
...
> +};
> +
> static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &_merge },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &_merge },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &_merge },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &_merge },
The lines is > 80 columns.
https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> @@ -185,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
>
> int mtk_ovl_adaptor_clk_enable(struct device *dev)
> {
> - struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> - struct device *comp;
> - int ret;
--
Regards,
Alexandre
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
2023-06-27 13:48 ` Alexandre Mergnat
@ 2023-06-28 4:24 ` Fei Shao
-1 siblings, 0 replies; 45+ messages in thread
From: Fei Shao @ 2023-06-28 4:24 UTC (permalink / raw)
To: Alexandre Mergnat
Cc: Hsiao Chien Sung, Rob Herring, Philipp Zabel, Chun-Kuang Hu,
Matthias Brugger, Krzysztof Kozlowski,
AngeloGioacchino Del Regno, linux-kernel, linux-arm-kernel,
linux-mediatek, devicetree, Project_Global_Chrome_Upstream_Group,
Singo Chang, Nancy Lin, Jason-JH Lin
On Tue, Jun 27, 2023 at 9:48 PM Alexandre Mergnat <amergnat@baylibre.com> wrote:
>
snip
>
> The lines is > 80 columns.
>
> https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
The 80-column convention is preferred but I think this provides better
readability.
Also checkpatch.pl allows up to 100 columns today and the lines fit in.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bdc48fa11e46f
Regards,
Fei
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
@ 2023-06-28 4:24 ` Fei Shao
0 siblings, 0 replies; 45+ messages in thread
From: Fei Shao @ 2023-06-28 4:24 UTC (permalink / raw)
To: Alexandre Mergnat
Cc: Hsiao Chien Sung, Rob Herring, Philipp Zabel, Chun-Kuang Hu,
Matthias Brugger, Krzysztof Kozlowski,
AngeloGioacchino Del Regno, linux-kernel, linux-arm-kernel,
linux-mediatek, devicetree, Project_Global_Chrome_Upstream_Group,
Singo Chang, Nancy Lin, Jason-JH Lin
On Tue, Jun 27, 2023 at 9:48 PM Alexandre Mergnat <amergnat@baylibre.com> wrote:
>
snip
>
> The lines is > 80 columns.
>
> https://www.kernel.org/doc/html/latest/process/coding-style.html#breaking-long-lines-and-strings
The 80-column convention is preferred but I think this provides better
readability.
Also checkpatch.pl allows up to 100 columns today and the lines fit in.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bdc48fa11e46f
Regards,
Fei
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-07-18 8:08 ` Fei Shao
-1 siblings, 0 replies; 45+ messages in thread
From: Fei Shao @ 2023-07-18 8:08 UTC (permalink / raw)
To: Hsiao Chien Sung
Cc: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin
Hi Hsiao-Chien,
On Tue, Jun 27, 2023 at 2:50 PM Hsiao Chien Sung
<shawn.sung@mediatek.com> wrote:
>
> Support MT8188 VDOSYS1 in display driver.
I'm testing this series with my local MT8188 setup + an external 4K
display, and I feel there is something missing in it.
With these patches the external display can be lit up on my end, but I
only see glitches and no meaningful content is rendered.
Could you check again and send the updated series with the fix?
Thanks,
Fei
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1
@ 2023-07-18 8:08 ` Fei Shao
0 siblings, 0 replies; 45+ messages in thread
From: Fei Shao @ 2023-07-18 8:08 UTC (permalink / raw)
To: Hsiao Chien Sung
Cc: AngeloGioacchino Del Regno, Chun-Kuang Hu, Krzysztof Kozlowski,
Matthias Brugger, Philipp Zabel, Rob Herring, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree,
Project_Global_Chrome_Upstream_Group, Singo Chang, Nancy Lin,
Jason-JH Lin
Hi Hsiao-Chien,
On Tue, Jun 27, 2023 at 2:50 PM Hsiao Chien Sung
<shawn.sung@mediatek.com> wrote:
>
> Support MT8188 VDOSYS1 in display driver.
I'm testing this series with my local MT8188 setup + an external 4K
display, and I feel there is something missing in it.
With these patches the external display can be lit up on my end, but I
only see glitches and no meaningful content is rendered.
Could you check again and send the updated series with the fix?
Thanks,
Fei
_______________________________________________
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1
2023-07-18 8:08 ` Fei Shao
(?)
@ 2023-07-18 11:24 ` Shawn Sung (宋孝謙)
-1 siblings, 0 replies; 45+ messages in thread
From: Shawn Sung (宋孝謙) @ 2023-07-18 11:24 UTC (permalink / raw)
To: fshao
Cc: linux-kernel, robh+dt, Singo Chang (張興國),
linux-mediatek, chunkuang.hu, devicetree,
Jason-JH Lin (林睿祥),
Nancy Lin (林欣螢),
p.zabel, Project_Global_Chrome_Upstream_Group, linux-arm-kernel,
krzysztof.kozlowski+dt, matthias.bgg, angelogioacchino.delregno
Hi Fei,
On Tue, 2023-07-18 at 16:08 +0800, Fei Shao wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> Hi Hsiao-Chien,
>
> On Tue, Jun 27, 2023 at 2:50 PM Hsiao Chien Sung
> <shawn.sung@mediatek.com> wrote:
> >
> > Support MT8188 VDOSYS1 in display driver.
>
> I'm testing this series with my local MT8188 setup + an external 4K
> display, and I feel there is something missing in it.
Yes, there is a patch for fixing DPI misconfiguration (.input_2pixel =
true), but since I'm not DPI owner, didn't include that in this patch.
> With these patches the external display can be lit up on my end, but
> I
> only see glitches and no meaningful content is rendered.
> Could you check again and send the updated series with the fix?
Will discuss with DPI owner and merge that fix into this series and re-
send it again if you would like to.
>
> Thanks,
> Fei
Thanks,
Hsiao Chien Sung
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-07-31 8:45 ` CK Hu (胡俊光)
-1 siblings, 0 replies; 45+ messages in thread
From: CK Hu (胡俊光) @ 2023-07-31 8:45 UTC (permalink / raw)
To: p.zabel, Shawn Sung (宋孝謙),
matthias.bgg, robh+dt, angelogioacchino.delregno, chunkuang.hu,
krzysztof.kozlowski+dt
Cc: linux-kernel, linux-mediatek,
Singo Chang (張興國),
Jason-JH Lin (林睿祥),
devicetree, Nancy Lin (林欣螢),
Project_Global_Chrome_Upstream_Group, linux-arm-kernel
Hi, Hsiao-chien:
On Tue, 2023-06-27 at 14:39 +0800, Hsiao Chien Sung wrote:
> - Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
> to align the naming rule of mtk_ovl_adaptor_comp_id.
> - Sort components' names in alphabetical order
> - Sort device table in alphabetical order
> - Add sentinel to device table
Separate each modification into one patch.
Regards,
CK
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 61 ++++++++---------
> --
> 1 file changed, 27 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..38f389471f66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -26,13 +26,14 @@
> #define MTK_OVL_ADAPTOR_LAYER_NUM 4
>
> enum mtk_ovl_adaptor_comp_type {
> - OVL_ADAPTOR_TYPE_RDMA = 0,
> - OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_MDP_RDMA,
> + OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_NUM,
> };
>
> enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_MDP_RDMA0,
> OVL_ADAPTOR_MDP_RDMA1,
> OVL_ADAPTOR_MDP_RDMA2,
> @@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id {
> OVL_ADAPTOR_MERGE1,
> OVL_ADAPTOR_MERGE2,
> OVL_ADAPTOR_MERGE3,
> - OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_ID_MAX
> };
>
> @@ -61,25 +61,25 @@ struct mtk_disp_ovl_adaptor {
> };
>
> static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] =
> {
> - [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma",
> - [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> + [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> };
>
> static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -89,10 +89,10 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> struct mtk_plane_pending_state *pending = &state->pending;
> struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *ethdr;
> + struct device *merge;
> struct device *rdma_l;
> struct device *rdma_r;
> - struct device *merge;
> - struct device *ethdr;
> const struct drm_format_info *fmt_info =
> drm_format_info(pending->format);
> bool use_dual_pipe = false;
> unsigned int align_width;
> @@ -105,16 +105,16 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> &pending->addr, (pending->pitch / fmt_info->cpp[0]),
> pending->x, pending->y, pending->width, pending-
> >height);
>
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> idx];
> rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx];
> rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx + 1];
> - merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> idx];
> - ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
>
> if (!pending->enable) {
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> mtk_merge_stop_cmdq(merge, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> - mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> return;
> }
>
> @@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct
> device *dev)
>
> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex
> *mutex)
> {
> + mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device
> *dev, struct mtk_mutex *mutex)
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct
> mtk_mutex *mutex)
> {
> + mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device
> *dev, struct mtk_mutex *mutex)
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_connect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2,
> DDP_COMPONENT_MERGE2);
> @@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device
> *dev, struct device *mmsys_dev, unsig
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4,
> DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> }
>
> void mtk_ovl_adaptor_disconnect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2,
> DDP_COMPONENT_MERGE2);
> @@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device
> *dev, struct device *mmsys_dev, un
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4,
> DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> }
>
> static int ovl_adaptor_comp_get_id(struct device *dev, struct
> device_node *node,
> @@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct
> device *dev, struct device_node *node,
> }
>
> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> - {
> - .compatible = "mediatek,mt8195-vdo1-rdma",
> - .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> - }, {
> - .compatible = "mediatek,mt8195-disp-merge",
> - .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> - }, {
> - .compatible = "mediatek,mt8195-disp-ethdr",
> - .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> - },
> - {},
> + { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void
> *)OVL_ADAPTOR_TYPE_ETHDR },
> + { .compatible = "mediatek,mt8195-disp-merge", .data = (void
> *)OVL_ADAPTOR_TYPE_MERGE },
> + { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void
> *)OVL_ADAPTOR_TYPE_MDP_RDMA },
> + { /* sentinel */ }
> };
>
> static int compare_of(struct device *dev, void *data)
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order
@ 2023-07-31 8:45 ` CK Hu (胡俊光)
0 siblings, 0 replies; 45+ messages in thread
From: CK Hu (胡俊光) @ 2023-07-31 8:45 UTC (permalink / raw)
To: p.zabel, Shawn Sung (宋孝謙),
matthias.bgg, robh+dt, angelogioacchino.delregno, chunkuang.hu,
krzysztof.kozlowski+dt
Cc: linux-kernel, linux-mediatek,
Singo Chang (張興國),
Jason-JH Lin (林睿祥),
devicetree, Nancy Lin (林欣螢),
Project_Global_Chrome_Upstream_Group, linux-arm-kernel
Hi, Hsiao-chien:
On Tue, 2023-06-27 at 14:39 +0800, Hsiao Chien Sung wrote:
> - Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA
> to align the naming rule of mtk_ovl_adaptor_comp_id.
> - Sort components' names in alphabetical order
> - Sort device table in alphabetical order
> - Add sentinel to device table
Separate each modification into one patch.
Regards,
CK
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 61 ++++++++---------
> --
> 1 file changed, 27 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index c0a38f5217ee..38f389471f66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -26,13 +26,14 @@
> #define MTK_OVL_ADAPTOR_LAYER_NUM 4
>
> enum mtk_ovl_adaptor_comp_type {
> - OVL_ADAPTOR_TYPE_RDMA = 0,
> - OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_MDP_RDMA,
> + OVL_ADAPTOR_TYPE_MERGE,
> OVL_ADAPTOR_TYPE_NUM,
> };
>
> enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_MDP_RDMA0,
> OVL_ADAPTOR_MDP_RDMA1,
> OVL_ADAPTOR_MDP_RDMA2,
> @@ -45,7 +46,6 @@ enum mtk_ovl_adaptor_comp_id {
> OVL_ADAPTOR_MERGE1,
> OVL_ADAPTOR_MERGE2,
> OVL_ADAPTOR_MERGE3,
> - OVL_ADAPTOR_ETHDR0,
> OVL_ADAPTOR_ID_MAX
> };
>
> @@ -61,25 +61,25 @@ struct mtk_disp_ovl_adaptor {
> };
>
> static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] =
> {
> - [OVL_ADAPTOR_TYPE_RDMA] = "vdo1-rdma",
> - [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> + [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> };
>
> static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -89,10 +89,10 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> struct mtk_plane_pending_state *pending = &state->pending;
> struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *ethdr;
> + struct device *merge;
> struct device *rdma_l;
> struct device *rdma_r;
> - struct device *merge;
> - struct device *ethdr;
> const struct drm_format_info *fmt_info =
> drm_format_info(pending->format);
> bool use_dual_pipe = false;
> unsigned int align_width;
> @@ -105,16 +105,16 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> &pending->addr, (pending->pitch / fmt_info->cpp[0]),
> pending->x, pending->y, pending->width, pending-
> >height);
>
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> idx];
> rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx];
> rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx + 1];
> - merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> idx];
> - ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
>
> if (!pending->enable) {
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> mtk_merge_stop_cmdq(merge, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> - mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> return;
> }
>
> @@ -313,6 +313,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct
> device *dev)
>
> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex
> *mutex)
> {
> + mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -325,11 +326,11 @@ void mtk_ovl_adaptor_add_comp(struct device
> *dev, struct mtk_mutex *mutex)
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct
> mtk_mutex *mutex)
> {
> + mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> @@ -342,11 +343,11 @@ void mtk_ovl_adaptor_remove_comp(struct device
> *dev, struct mtk_mutex *mutex)
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> }
>
> void mtk_ovl_adaptor_connect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2,
> DDP_COMPONENT_MERGE2);
> @@ -354,11 +355,11 @@ void mtk_ovl_adaptor_connect(struct device
> *dev, struct device *mmsys_dev, unsig
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4,
> DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> }
>
> void mtk_ovl_adaptor_disconnect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> {
> + mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1,
> DDP_COMPONENT_MERGE1);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2,
> DDP_COMPONENT_MERGE2);
> @@ -366,7 +367,6 @@ void mtk_ovl_adaptor_disconnect(struct device
> *dev, struct device *mmsys_dev, un
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3,
> DDP_COMPONENT_ETHDR_MIXER);
> mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4,
> DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER,
> next);
> }
>
> static int ovl_adaptor_comp_get_id(struct device *dev, struct
> device_node *node,
> @@ -385,17 +385,10 @@ static int ovl_adaptor_comp_get_id(struct
> device *dev, struct device_node *node,
> }
>
> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> - {
> - .compatible = "mediatek,mt8195-vdo1-rdma",
> - .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> - }, {
> - .compatible = "mediatek,mt8195-disp-merge",
> - .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> - }, {
> - .compatible = "mediatek,mt8195-disp-ethdr",
> - .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> - },
> - {},
> + { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void
> *)OVL_ADAPTOR_TYPE_ETHDR },
> + { .compatible = "mediatek,mt8195-disp-merge", .data = (void
> *)OVL_ADAPTOR_TYPE_MERGE },
> + { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void
> *)OVL_ADAPTOR_TYPE_MDP_RDMA },
> + { /* sentinel */ }
> };
>
> static int compare_of(struct device *dev, void *data)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-07-31 9:01 ` CK Hu (胡俊光)
-1 siblings, 0 replies; 45+ messages in thread
From: CK Hu (胡俊光) @ 2023-07-31 9:01 UTC (permalink / raw)
To: p.zabel, Shawn Sung (宋孝謙),
matthias.bgg, robh+dt, angelogioacchino.delregno, chunkuang.hu,
krzysztof.kozlowski+dt
Cc: linux-kernel, linux-mediatek,
Singo Chang (張興國),
Jason-JH Lin (林睿祥),
devicetree, Nancy Lin (林欣螢),
Project_Global_Chrome_Upstream_Group, linux-arm-kernel
Hi, Hsiao-chien:
On Tue, 2023-06-27 at 14:39 +0800, Hsiao Chien Sung wrote:
> - Register functions to enable/disable clock and reuse them
> to simplify the code
> - Check if the component is defined before using it since
> some modules are MT8188 only (ex. PADDING)
> - Control components according to its type rather than ID
> - Use a for-loop to add/remove components in an arrays,
> so we only has to maintain the array to make sure every
> component will be initialized properly
Separate each modification into one patch.
Regards,
CK
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 154 +++++++---------
> --
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++-
> 2 files changed, 79 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index 38f389471f66..f73a558dcf93 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,7 +51,9 @@ enum mtk_ovl_adaptor_comp_id {
>
> struct ovl_adaptor_comp_match {
> enum mtk_ovl_adaptor_comp_type type;
> + enum mtk_ddp_comp_id comp_id;
> int alias_id;
> + const struct mtk_ddp_comp_funcs *funcs;
> };
>
> struct mtk_disp_ovl_adaptor {
> @@ -66,20 +68,35 @@ static const char * const
> private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> };
>
> +static const struct mtk_ddp_comp_funcs _ethdr = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> +};
> +
> +static const struct mtk_ddp_comp_funcs _merge = {
> + .clk_enable = mtk_merge_clk_enable,
> + .clk_disable = mtk_merge_clk_disable,
> +};
> +
> +static const struct mtk_ddp_comp_funcs _rdma = {
> + .clk_enable = mtk_mdp_rdma_clk_enable,
> + .clk_disable = mtk_mdp_rdma_clk_disable,
> +};
> +
> static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR,
> DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE1, 1, &_merge },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE2, 2, &_merge },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE3, 3, &_merge },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE4, 4, &_merge },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -185,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
>
> int mtk_ovl_adaptor_clk_enable(struct device *dev)
> {
> - struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> - struct device *comp;
> - int ret;
> int i;
> -
> - for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> - ret = pm_runtime_get_sync(comp);
> - if (ret < 0) {
> - dev_err(dev, "Failed to enable power domain %d,
> err %d\n", i, ret);
> - goto pwr_err;
> - }
> - }
> + int ret;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> - if (i < OVL_ADAPTOR_MERGE0)
> - ret = mtk_mdp_rdma_clk_enable(comp);
> - else if (i < OVL_ADAPTOR_ETHDR0)
> - ret = mtk_merge_clk_enable(comp);
> - else
> - ret = mtk_ethdr_clk_enable(comp);
> + dev = ovl_adaptor->ovl_adaptor_comp[i];
> + if (!dev)
> + continue;
> + ret = comp_matches[i].funcs->clk_enable(dev);
> if (ret) {
> - dev_err(dev, "Failed to enable clock %d, err
> %d\n", i, ret);
> - goto clk_err;
> + while (--i >= 0)
> + comp_matches[i].funcs-
> >clk_disable(dev);
> + return ret;
> }
> }
> -
> - return ret;
> -
> -clk_err:
> - while (--i >= 0) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> - if (i < OVL_ADAPTOR_MERGE0)
> - mtk_mdp_rdma_clk_disable(comp);
> - else if (i < OVL_ADAPTOR_ETHDR0)
> - mtk_merge_clk_disable(comp);
> - else
> - mtk_ethdr_clk_disable(comp);
> - }
> - i = OVL_ADAPTOR_MERGE0;
> -
> -pwr_err:
> - while (--i >= 0)
> - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
> -
> - return ret;
> + return 0;
> }
>
> void mtk_ovl_adaptor_clk_disable(struct device *dev)
> {
> - struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> - struct device *comp;
> int i;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> - if (i < OVL_ADAPTOR_MERGE0) {
> - mtk_mdp_rdma_clk_disable(comp);
> - pm_runtime_put(comp);
> - } else if (i < OVL_ADAPTOR_ETHDR0) {
> - mtk_merge_clk_disable(comp);
> - } else {
> - mtk_ethdr_clk_disable(comp);
> - }
> + dev = ovl_adaptor->ovl_adaptor_comp[i];
> + if (!dev)
> + continue;
> + comp_matches[i].funcs->clk_disable(dev);
> }
> }
>
> @@ -313,36 +291,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct
> device *dev)
>
> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex
> *mutex)
> {
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> + int i;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> +
> + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + if (!ovl_adaptor->ovl_adaptor_comp[i])
> + continue;
> + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
> + }
> }
>
> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct
> mtk_mutex *mutex)
> {
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> + int i;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> +
> + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + if (!ovl_adaptor->ovl_adaptor_comp[i])
> + continue;
> + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
> + }
> }
>
> void mtk_ovl_adaptor_connect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> index e06db6e56b5f..a37146544e30 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -245,10 +245,23 @@ size_t mtk_mdp_rdma_get_num_formats(struct
> device *dev)
>
> int mtk_mdp_rdma_clk_enable(struct device *dev)
> {
> + int ret;
> struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
>
> - clk_prepare_enable(rdma->clk);
> - return 0;
> + /*
> + * Since LARBs (Local ARBiter) have to be powered on before its
> users,
> + * to ensure the power-on sequence, we created device link
> between
> + * RDMA and its LARB, and when pm_runtime_get_sync is called in
> RDMA,
> + * system will make sure the LARB is powered on, then the RDMA
> + */
> + ret = pm_runtime_get_sync(dev);
> +
> + if (ret < 0)
> + dev_err(dev, "pm_runtime_get_sync failed: %d\n", ret);
> + else
> + ret = clk_prepare_enable(rdma->clk);
> +
> + return ret;
> }
>
> void mtk_mdp_rdma_clk_disable(struct device *dev)
> @@ -256,6 +269,9 @@ void mtk_mdp_rdma_clk_disable(struct device *dev)
> struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
>
> clk_disable_unprepare(rdma->clk);
> +
> + /* Same reason as when enabling clock, turn the LARB off */
> + pm_runtime_put(dev);
> }
>
> static int mtk_mdp_rdma_bind(struct device *dev, struct device
> *master,
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver
@ 2023-07-31 9:01 ` CK Hu (胡俊光)
0 siblings, 0 replies; 45+ messages in thread
From: CK Hu (胡俊光) @ 2023-07-31 9:01 UTC (permalink / raw)
To: p.zabel, Shawn Sung (宋孝謙),
matthias.bgg, robh+dt, angelogioacchino.delregno, chunkuang.hu,
krzysztof.kozlowski+dt
Cc: linux-kernel, linux-mediatek,
Singo Chang (張興國),
Jason-JH Lin (林睿祥),
devicetree, Nancy Lin (林欣螢),
Project_Global_Chrome_Upstream_Group, linux-arm-kernel
Hi, Hsiao-chien:
On Tue, 2023-06-27 at 14:39 +0800, Hsiao Chien Sung wrote:
> - Register functions to enable/disable clock and reuse them
> to simplify the code
> - Check if the component is defined before using it since
> some modules are MT8188 only (ex. PADDING)
> - Control components according to its type rather than ID
> - Use a for-loop to add/remove components in an arrays,
> so we only has to maintain the array to make sure every
> component will be initialized properly
Separate each modification into one patch.
Regards,
CK
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 154 +++++++---------
> --
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++-
> 2 files changed, 79 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index 38f389471f66..f73a558dcf93 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -51,7 +51,9 @@ enum mtk_ovl_adaptor_comp_id {
>
> struct ovl_adaptor_comp_match {
> enum mtk_ovl_adaptor_comp_type type;
> + enum mtk_ddp_comp_id comp_id;
> int alias_id;
> + const struct mtk_ddp_comp_funcs *funcs;
> };
>
> struct mtk_disp_ovl_adaptor {
> @@ -66,20 +68,35 @@ static const char * const
> private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> };
>
> +static const struct mtk_ddp_comp_funcs _ethdr = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> +};
> +
> +static const struct mtk_ddp_comp_funcs _merge = {
> + .clk_enable = mtk_merge_clk_enable,
> + .clk_disable = mtk_merge_clk_disable,
> +};
> +
> +static const struct mtk_ddp_comp_funcs _rdma = {
> + .clk_enable = mtk_mdp_rdma_clk_enable,
> + .clk_disable = mtk_mdp_rdma_clk_disable,
> +};
> +
> static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 },
> - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 },
> - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 },
> - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 },
> - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 },
> - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 },
> - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 },
> - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 },
> - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR,
> DDP_COMPONENT_ETHDR_MIXER, 0, &_ethdr },
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA0, 0, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA1, 1, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA2, 2, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA3, 3, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA4, 4, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA5, 5, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA6, 6, &_rdma },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA,
> DDP_COMPONENT_MDP_RDMA7, 7, &_rdma },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE1, 1, &_merge },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE2, 2, &_merge },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE3, 3, &_merge },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE4, 4, &_merge },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -185,73 +202,34 @@ void mtk_ovl_adaptor_stop(struct device *dev)
>
> int mtk_ovl_adaptor_clk_enable(struct device *dev)
> {
> - struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> - struct device *comp;
> - int ret;
> int i;
> -
> - for (i = 0; i < OVL_ADAPTOR_MERGE0; i++) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> - ret = pm_runtime_get_sync(comp);
> - if (ret < 0) {
> - dev_err(dev, "Failed to enable power domain %d,
> err %d\n", i, ret);
> - goto pwr_err;
> - }
> - }
> + int ret;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> - if (i < OVL_ADAPTOR_MERGE0)
> - ret = mtk_mdp_rdma_clk_enable(comp);
> - else if (i < OVL_ADAPTOR_ETHDR0)
> - ret = mtk_merge_clk_enable(comp);
> - else
> - ret = mtk_ethdr_clk_enable(comp);
> + dev = ovl_adaptor->ovl_adaptor_comp[i];
> + if (!dev)
> + continue;
> + ret = comp_matches[i].funcs->clk_enable(dev);
> if (ret) {
> - dev_err(dev, "Failed to enable clock %d, err
> %d\n", i, ret);
> - goto clk_err;
> + while (--i >= 0)
> + comp_matches[i].funcs-
> >clk_disable(dev);
> + return ret;
> }
> }
> -
> - return ret;
> -
> -clk_err:
> - while (--i >= 0) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> - if (i < OVL_ADAPTOR_MERGE0)
> - mtk_mdp_rdma_clk_disable(comp);
> - else if (i < OVL_ADAPTOR_ETHDR0)
> - mtk_merge_clk_disable(comp);
> - else
> - mtk_ethdr_clk_disable(comp);
> - }
> - i = OVL_ADAPTOR_MERGE0;
> -
> -pwr_err:
> - while (--i >= 0)
> - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]);
> -
> - return ret;
> + return 0;
> }
>
> void mtk_ovl_adaptor_clk_disable(struct device *dev)
> {
> - struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> - struct device *comp;
> int i;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> - comp = ovl_adaptor->ovl_adaptor_comp[i];
> -
> - if (i < OVL_ADAPTOR_MERGE0) {
> - mtk_mdp_rdma_clk_disable(comp);
> - pm_runtime_put(comp);
> - } else if (i < OVL_ADAPTOR_ETHDR0) {
> - mtk_merge_clk_disable(comp);
> - } else {
> - mtk_ethdr_clk_disable(comp);
> - }
> + dev = ovl_adaptor->ovl_adaptor_comp[i];
> + if (!dev)
> + continue;
> + comp_matches[i].funcs->clk_disable(dev);
> }
> }
>
> @@ -313,36 +291,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct
> device *dev)
>
> void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex
> *mutex)
> {
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3);
> - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4);
> + int i;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> +
> + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + if (!ovl_adaptor->ovl_adaptor_comp[i])
> + continue;
> + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
> + }
> }
>
> void mtk_ovl_adaptor_remove_comp(struct device *dev, struct
> mtk_mutex *mutex)
> {
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3);
> - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4);
> + int i;
> + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> dev_get_drvdata(dev);
> +
> + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + if (!ovl_adaptor->ovl_adaptor_comp[i])
> + continue;
> + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
> + }
> }
>
> void mtk_ovl_adaptor_connect(struct device *dev, struct device
> *mmsys_dev, unsigned int next)
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> index e06db6e56b5f..a37146544e30 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -245,10 +245,23 @@ size_t mtk_mdp_rdma_get_num_formats(struct
> device *dev)
>
> int mtk_mdp_rdma_clk_enable(struct device *dev)
> {
> + int ret;
> struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
>
> - clk_prepare_enable(rdma->clk);
> - return 0;
> + /*
> + * Since LARBs (Local ARBiter) have to be powered on before its
> users,
> + * to ensure the power-on sequence, we created device link
> between
> + * RDMA and its LARB, and when pm_runtime_get_sync is called in
> RDMA,
> + * system will make sure the LARB is powered on, then the RDMA
> + */
> + ret = pm_runtime_get_sync(dev);
> +
> + if (ret < 0)
> + dev_err(dev, "pm_runtime_get_sync failed: %d\n", ret);
> + else
> + ret = clk_prepare_enable(rdma->clk);
> +
> + return ret;
> }
>
> void mtk_mdp_rdma_clk_disable(struct device *dev)
> @@ -256,6 +269,9 @@ void mtk_mdp_rdma_clk_disable(struct device *dev)
> struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
>
> clk_disable_unprepare(rdma->clk);
> +
> + /* Same reason as when enabling clock, turn the LARB off */
> + pm_runtime_put(dev);
> }
>
> static int mtk_mdp_rdma_bind(struct device *dev, struct device
> *master,
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^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 14/14] drm/mediatek: Support MT8188 Padding in display driver
2023-06-27 6:39 ` Hsiao Chien Sung
@ 2023-07-31 10:08 ` CK Hu (胡俊光)
-1 siblings, 0 replies; 45+ messages in thread
From: CK Hu (胡俊光) @ 2023-07-31 10:08 UTC (permalink / raw)
To: p.zabel, Shawn Sung (宋孝謙),
matthias.bgg, robh+dt, angelogioacchino.delregno, chunkuang.hu,
krzysztof.kozlowski+dt
Cc: linux-kernel, linux-mediatek,
Singo Chang (張興國),
Jason-JH Lin (林睿祥),
devicetree, Nancy Lin (林欣螢),
Project_Global_Chrome_Upstream_Group, linux-arm-kernel
Hi, Hsiao-chien:
On Tue, 2023-06-27 at 14:39 +0800, Hsiao Chien Sung wrote:
> Padding is a new display module on MT8188, it provides ability
> to add pixels to width and height of a layer with specified colors.
>
> Due to hardware design, Mixer in VDOSYS1 requires width of a layer
> to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
> we need Padding to deal with odd width.
>
> Please notice that even if the Padding is in bypass mode,
> settings in register must be cleared to 0,
> or undefined behaviors could happen.
Separate this patch to two patches. One for padding driver and another
one for ovl adapator.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 33 +++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
> drivers/gpu/drm/mediatek/mtk_padding.c | 136
> ++++++++++++++++++
> 6 files changed, 176 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index d4d193f60271..5e4436403b8d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_dsi.o \
> mtk_dpi.o \
> mtk_ethdr.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_padding.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2254038519e1..f9fdb1268aa5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev,
> struct mtk_mdp_rdma_cfg *cfg,
> const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
> size_t mtk_mdp_rdma_get_num_formats(struct device *dev);
>
> +int mtk_padding_clk_enable(struct device *dev);
> +void mtk_padding_clk_disable(struct device *dev);
> +void mtk_padding_config(struct device *dev, struct cmdq_pkt
> *cmdq_pkt);
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index f73a558dcf93..ca8f3febbf11 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -29,6 +29,7 @@ enum mtk_ovl_adaptor_comp_type {
> OVL_ADAPTOR_TYPE_ETHDR,
> OVL_ADAPTOR_TYPE_MDP_RDMA,
> OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_PADDING,
> OVL_ADAPTOR_TYPE_NUM,
> };
>
> @@ -46,6 +47,14 @@ enum mtk_ovl_adaptor_comp_id {
> OVL_ADAPTOR_MERGE1,
> OVL_ADAPTOR_MERGE2,
> OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_PADDING0,
> + OVL_ADAPTOR_PADDING1,
> + OVL_ADAPTOR_PADDING2,
> + OVL_ADAPTOR_PADDING3,
> + OVL_ADAPTOR_PADDING4,
> + OVL_ADAPTOR_PADDING5,
> + OVL_ADAPTOR_PADDING6,
> + OVL_ADAPTOR_PADDING7,
> OVL_ADAPTOR_ID_MAX
> };
>
> @@ -66,6 +75,7 @@ static const char * const
> private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
> [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_PADDING] = "padding",
> };
>
> static const struct mtk_ddp_comp_funcs _ethdr = {
> @@ -78,6 +88,11 @@ static const struct mtk_ddp_comp_funcs _merge = {
> .clk_disable = mtk_merge_clk_disable,
> };
>
> +static const struct mtk_ddp_comp_funcs _padding = {
> + .clk_enable = mtk_padding_clk_enable,
> + .clk_disable = mtk_padding_clk_disable,
> +};
> +
> static const struct mtk_ddp_comp_funcs _rdma = {
> .clk_enable = mtk_mdp_rdma_clk_enable,
> .clk_disable = mtk_mdp_rdma_clk_disable,
> @@ -97,6 +112,14 @@ static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE2, 2, &_merge },
> [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE3, 3, &_merge },
> [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE4, 4, &_merge },
> + [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING0, 0, &_padding },
> + [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING1, 1, &_padding },
> + [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING2, 2, &_padding },
> + [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING3, 3, &_padding },
> + [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING4, 4, &_padding },
> + [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING5, 5, &_padding },
> + [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING6, 6, &_padding },
> + [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING7, 7, &_padding },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -108,6 +131,8 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> struct mtk_mdp_rdma_cfg rdma_config = {0};
> struct device *ethdr;
> struct device *merge;
> + struct device *padding_l;
> + struct device *padding_r;
> struct device *rdma_l;
> struct device *rdma_r;
> const struct drm_format_info *fmt_info =
> drm_format_info(pending->format);
> @@ -124,6 +149,8 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
>
> ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> idx];
> + padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0
> + 2 * idx];
> + padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0
> + 2 * idx + 1];
> rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx];
> rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx + 1];
>
> @@ -159,10 +186,15 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> rdma_config.color_encoding = pending->color_encoding;
> mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
>
> + if (padding_l)
> + mtk_padding_config(padding_l, cmdq_pkt);
> +
> if (use_dual_pipe) {
> rdma_config.x_left = l_w;
> rdma_config.width = r_w;
> mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + if (padding_r)
> + mtk_padding_config(padding_r, cmdq_pkt);
> }
>
> mtk_merge_start_cmdq(merge, cmdq_pkt);
> @@ -353,6 +385,7 @@ static int ovl_adaptor_comp_get_id(struct device
> *dev, struct device_node *node,
> }
>
> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + { .compatible = "mediatek,mt8188-padding", .data = (void
> *)OVL_ADAPTOR_TYPE_PADDING },
> { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void
> *)OVL_ADAPTOR_TYPE_ETHDR },
> { .compatible = "mediatek,mt8195-disp-merge", .data = (void
> *)OVL_ADAPTOR_TYPE_MERGE },
> { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void
> *)OVL_ADAPTOR_TYPE_MDP_RDMA },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 613093068bb4..ed5b5b8d6c2e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -977,6 +977,7 @@ static struct platform_driver * const
> mtk_drm_drivers[] = {
> &mtk_dsi_driver,
> &mtk_ethdr_driver,
> &mtk_mdp_rdma_driver,
> + &mtk_padding_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index eb2fd45941f0..562f2db47add 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> extern struct platform_driver mtk_ethdr_driver;
> extern struct platform_driver mtk_mdp_rdma_driver;
> -
Why remove this blanking line?
> +extern struct platform_driver mtk_padding_driver;
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c
> b/drivers/gpu/drm/mediatek/mtk_padding.c
> new file mode 100644
> index 000000000000..bbb9c5e286ce
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_padding.c
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +/**
> + * struct mtk_padding - basic information of Padding
> + * @clk: Clock of the module
> + * @regs: Virtual address of the Padding for CPU to access
hardware control register.
> + * @cmdq_reg: CMDQ setting of the Padding
CMDQ client register setting.
> + *
> + * Every Padding should have different clock source, register base,
> and
> + * CMDQ settings, we stored these differences all together.
This comment is redundant.
Regards,
CK
> + */
> +struct mtk_padding {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> +};
> +
> +int mtk_padding_clk_enable(struct device *dev)
> +{
> + struct mtk_padding *padding = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(padding->clk);
> +}
> +
> +void mtk_padding_clk_disable(struct device *dev)
> +{
> + struct mtk_padding *padding = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(padding->clk);
> +}
> +
> +void mtk_padding_config(struct device *dev, struct cmdq_pkt
> *cmdq_pkt)
> +{
> + struct mtk_padding *padding = dev_get_drvdata(dev);
> +
> + /* bypass padding */
> + mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg,
> padding->regs, 0,
> + GENMASK(1, 0));
> +}
> +
> +static int mtk_padding_bind(struct device *dev, struct device
> *master, void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_padding_unbind(struct device *dev, struct device
> *master, void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_padding_component_ops = {
> + .bind = mtk_padding_bind,
> + .unbind = mtk_padding_unbind,
> +};
> +
> +static int mtk_padding_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_padding *priv;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0,
> &res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to do ioremap\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret) {
> + dev_err(dev, "failed to get gce client reg\n");
> + return ret;
> + }
> +#endif
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + return ret;
> +
> + ret = component_add(dev, &mtk_padding_component_ops);
> + if (ret) {
> + pm_runtime_disable(dev);
> + return dev_err_probe(dev, ret, "failed to add
> component\n");
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_padding_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_padding_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_padding_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8188-padding" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);
> +
> +struct platform_driver mtk_padding_driver = {
> + .probe = mtk_padding_probe,
> + .remove = mtk_padding_remove,
> + .driver = {
> + .name = "mediatek-padding",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_padding_driver_dt_match,
> + },
> +};
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v5 14/14] drm/mediatek: Support MT8188 Padding in display driver
@ 2023-07-31 10:08 ` CK Hu (胡俊光)
0 siblings, 0 replies; 45+ messages in thread
From: CK Hu (胡俊光) @ 2023-07-31 10:08 UTC (permalink / raw)
To: p.zabel, Shawn Sung (宋孝謙),
matthias.bgg, robh+dt, angelogioacchino.delregno, chunkuang.hu,
krzysztof.kozlowski+dt
Cc: linux-kernel, linux-mediatek,
Singo Chang (張興國),
Jason-JH Lin (林睿祥),
devicetree, Nancy Lin (林欣螢),
Project_Global_Chrome_Upstream_Group, linux-arm-kernel
Hi, Hsiao-chien:
On Tue, 2023-06-27 at 14:39 +0800, Hsiao Chien Sung wrote:
> Padding is a new display module on MT8188, it provides ability
> to add pixels to width and height of a layer with specified colors.
>
> Due to hardware design, Mixer in VDOSYS1 requires width of a layer
> to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
> we need Padding to deal with odd width.
>
> Please notice that even if the Padding is in bypass mode,
> settings in register must be cleared to 0,
> or undefined behaviors could happen.
Separate this patch to two patches. One for padding driver and another
one for ovl adapator.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 33 +++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
> drivers/gpu/drm/mediatek/mtk_padding.c | 136
> ++++++++++++++++++
> 6 files changed, 176 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index d4d193f60271..5e4436403b8d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -16,7 +16,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_dsi.o \
> mtk_dpi.o \
> mtk_ethdr.o \
> - mtk_mdp_rdma.o
> + mtk_mdp_rdma.o \
> + mtk_padding.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2254038519e1..f9fdb1268aa5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev,
> struct mtk_mdp_rdma_cfg *cfg,
> const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
> size_t mtk_mdp_rdma_get_num_formats(struct device *dev);
>
> +int mtk_padding_clk_enable(struct device *dev);
> +void mtk_padding_clk_disable(struct device *dev);
> +void mtk_padding_config(struct device *dev, struct cmdq_pkt
> *cmdq_pkt);
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> index f73a558dcf93..ca8f3febbf11 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -29,6 +29,7 @@ enum mtk_ovl_adaptor_comp_type {
> OVL_ADAPTOR_TYPE_ETHDR,
> OVL_ADAPTOR_TYPE_MDP_RDMA,
> OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_PADDING,
> OVL_ADAPTOR_TYPE_NUM,
> };
>
> @@ -46,6 +47,14 @@ enum mtk_ovl_adaptor_comp_id {
> OVL_ADAPTOR_MERGE1,
> OVL_ADAPTOR_MERGE2,
> OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_PADDING0,
> + OVL_ADAPTOR_PADDING1,
> + OVL_ADAPTOR_PADDING2,
> + OVL_ADAPTOR_PADDING3,
> + OVL_ADAPTOR_PADDING4,
> + OVL_ADAPTOR_PADDING5,
> + OVL_ADAPTOR_PADDING6,
> + OVL_ADAPTOR_PADDING7,
> OVL_ADAPTOR_ID_MAX
> };
>
> @@ -66,6 +75,7 @@ static const char * const
> private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> [OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
> [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_PADDING] = "padding",
> };
>
> static const struct mtk_ddp_comp_funcs _ethdr = {
> @@ -78,6 +88,11 @@ static const struct mtk_ddp_comp_funcs _merge = {
> .clk_disable = mtk_merge_clk_disable,
> };
>
> +static const struct mtk_ddp_comp_funcs _padding = {
> + .clk_enable = mtk_padding_clk_enable,
> + .clk_disable = mtk_padding_clk_disable,
> +};
> +
> static const struct mtk_ddp_comp_funcs _rdma = {
> .clk_enable = mtk_mdp_rdma_clk_enable,
> .clk_disable = mtk_mdp_rdma_clk_disable,
> @@ -97,6 +112,14 @@ static const struct ovl_adaptor_comp_match
> comp_matches[OVL_ADAPTOR_ID_MAX] = {
> [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE2, 2, &_merge },
> [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE3, 3, &_merge },
> [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE,
> DDP_COMPONENT_MERGE4, 4, &_merge },
> + [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING0, 0, &_padding },
> + [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING1, 1, &_padding },
> + [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING2, 2, &_padding },
> + [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING3, 3, &_padding },
> + [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING4, 4, &_padding },
> + [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING5, 5, &_padding },
> + [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING6, 6, &_padding },
> + [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING,
> DDP_COMPONENT_PADDING7, 7, &_padding },
> };
>
> void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> idx,
> @@ -108,6 +131,8 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> struct mtk_mdp_rdma_cfg rdma_config = {0};
> struct device *ethdr;
> struct device *merge;
> + struct device *padding_l;
> + struct device *padding_r;
> struct device *rdma_l;
> struct device *rdma_r;
> const struct drm_format_info *fmt_info =
> drm_format_info(pending->format);
> @@ -124,6 +149,8 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
>
> ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> idx];
> + padding_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0
> + 2 * idx];
> + padding_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0
> + 2 * idx + 1];
> rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx];
> rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> 2 * idx + 1];
>
> @@ -159,10 +186,15 @@ void mtk_ovl_adaptor_layer_config(struct device
> *dev, unsigned int idx,
> rdma_config.color_encoding = pending->color_encoding;
> mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
>
> + if (padding_l)
> + mtk_padding_config(padding_l, cmdq_pkt);
> +
> if (use_dual_pipe) {
> rdma_config.x_left = l_w;
> rdma_config.width = r_w;
> mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + if (padding_r)
> + mtk_padding_config(padding_r, cmdq_pkt);
> }
>
> mtk_merge_start_cmdq(merge, cmdq_pkt);
> @@ -353,6 +385,7 @@ static int ovl_adaptor_comp_get_id(struct device
> *dev, struct device_node *node,
> }
>
> static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + { .compatible = "mediatek,mt8188-padding", .data = (void
> *)OVL_ADAPTOR_TYPE_PADDING },
> { .compatible = "mediatek,mt8195-disp-ethdr", .data = (void
> *)OVL_ADAPTOR_TYPE_ETHDR },
> { .compatible = "mediatek,mt8195-disp-merge", .data = (void
> *)OVL_ADAPTOR_TYPE_MERGE },
> { .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void
> *)OVL_ADAPTOR_TYPE_MDP_RDMA },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 613093068bb4..ed5b5b8d6c2e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -977,6 +977,7 @@ static struct platform_driver * const
> mtk_drm_drivers[] = {
> &mtk_dsi_driver,
> &mtk_ethdr_driver,
> &mtk_mdp_rdma_driver,
> + &mtk_padding_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index eb2fd45941f0..562f2db47add 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> extern struct platform_driver mtk_ethdr_driver;
> extern struct platform_driver mtk_mdp_rdma_driver;
> -
Why remove this blanking line?
> +extern struct platform_driver mtk_padding_driver;
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c
> b/drivers/gpu/drm/mediatek/mtk_padding.c
> new file mode 100644
> index 000000000000..bbb9c5e286ce
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_padding.c
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +/**
> + * struct mtk_padding - basic information of Padding
> + * @clk: Clock of the module
> + * @regs: Virtual address of the Padding for CPU to access
hardware control register.
> + * @cmdq_reg: CMDQ setting of the Padding
CMDQ client register setting.
> + *
> + * Every Padding should have different clock source, register base,
> and
> + * CMDQ settings, we stored these differences all together.
This comment is redundant.
Regards,
CK
> + */
> +struct mtk_padding {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> +};
> +
> +int mtk_padding_clk_enable(struct device *dev)
> +{
> + struct mtk_padding *padding = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(padding->clk);
> +}
> +
> +void mtk_padding_clk_disable(struct device *dev)
> +{
> + struct mtk_padding *padding = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(padding->clk);
> +}
> +
> +void mtk_padding_config(struct device *dev, struct cmdq_pkt
> *cmdq_pkt)
> +{
> + struct mtk_padding *padding = dev_get_drvdata(dev);
> +
> + /* bypass padding */
> + mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg,
> padding->regs, 0,
> + GENMASK(1, 0));
> +}
> +
> +static int mtk_padding_bind(struct device *dev, struct device
> *master, void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_padding_unbind(struct device *dev, struct device
> *master, void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_padding_component_ops = {
> + .bind = mtk_padding_bind,
> + .unbind = mtk_padding_unbind,
> +};
> +
> +static int mtk_padding_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_padding *priv;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + priv->regs = devm_platform_get_and_ioremap_resource(pdev, 0,
> &res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to do ioremap\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret) {
> + dev_err(dev, "failed to get gce client reg\n");
> + return ret;
> + }
> +#endif
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + return ret;
> +
> + ret = component_add(dev, &mtk_padding_component_ops);
> + if (ret) {
> + pm_runtime_disable(dev);
> + return dev_err_probe(dev, ret, "failed to add
> component\n");
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_padding_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_padding_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_padding_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8188-padding" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match);
> +
> +struct platform_driver mtk_padding_driver = {
> + .probe = mtk_padding_probe,
> + .remove = mtk_padding_remove,
> + .driver = {
> + .name = "mediatek-padding",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_padding_driver_dt_match,
> + },
> +};
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^ permalink raw reply [flat|nested] 45+ messages in thread
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2023-06-27 6:39 [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1 Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 01/14] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 02/14] dt-bindings: display: mediatek: mdp-rdma: " Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 03/14] dt-bindings: display: mediatek: merge: " Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 04/14] dt-bindings: display: mediatek: padding: Add MT8188 Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 05/14] dt-bindings: arm: mediatek: Add compatible for MT8188 Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 06/14] dt-bindings: reset: mt8188: Add VDOSYS reset control bits Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 07/14] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 08/14] soc: mediatek: Support MT8188 VDOSYS1 Padding " Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 09/14] soc: mediatek: Support reset bit mapping in mmsys driver Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 10/14] soc: mediatek: Add MT8188 VDOSYS reset bit map Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 11/14] drm/mediatek: Support MT8188 VDOSYS1 in display driver Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 6:39 ` [PATCH v5 12/14] drm/mediatek: Sort OVL adaptor components in alphabetical order Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 10:52 ` Alexandre Mergnat
2023-06-27 10:52 ` Alexandre Mergnat
2023-07-31 8:45 ` CK Hu (胡俊光)
2023-07-31 8:45 ` CK Hu (胡俊光)
2023-06-27 6:39 ` [PATCH v5 13/14] drm/mediatek: Improve compatibility of display driver Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-06-27 13:48 ` Alexandre Mergnat
2023-06-27 13:48 ` Alexandre Mergnat
2023-06-28 4:24 ` Fei Shao
2023-06-28 4:24 ` Fei Shao
2023-07-31 9:01 ` CK Hu (胡俊光)
2023-07-31 9:01 ` CK Hu (胡俊光)
2023-06-27 6:39 ` [PATCH v5 14/14] drm/mediatek: Support MT8188 Padding in " Hsiao Chien Sung
2023-06-27 6:39 ` Hsiao Chien Sung
2023-07-31 10:08 ` CK Hu (胡俊光)
2023-07-31 10:08 ` CK Hu (胡俊光)
2023-07-18 8:08 ` [PATCH v5 00/14] Add display driver for MT8188 VDOSYS1 Fei Shao
2023-07-18 8:08 ` Fei Shao
2023-07-18 11:24 ` Shawn Sung (宋孝謙)
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