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From: Sudeep Holla <sudeep.holla@arm.com>
To: Simon Horman <horms+renesas@verge.net.au>,
	linux-renesas-soc@vger.kernel.org
Cc: Sudeep Holla <sudeep.holla@arm.com>,
	Magnus Damm <magnus.damm@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/2] arm64: dts: r8a7796: Add OPPs table for cpu devices
Date: Thu, 5 Oct 2017 16:04:47 +0100	[thread overview]
Message-ID: <e2e31fd8-b5f8-40a8-df3d-e7726bb8a8e1@arm.com> (raw)
In-Reply-To: <1507209984-17123-3-git-send-email-horms+renesas@verge.net.au>



On 05/10/17 14:26, Simon Horman wrote:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
> 
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
> 

I assume these OPPs will continue to work in future but just not optimal.

> Based in part on work by Hien Dang.
> 
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> v2 [Simon Horman]
> - Only provide one operating points node for each operating-points-v2 node
>   as per the binding; other nodes were unused and have been removed
> 
> v1 [Simon Horman]
> - consolidated several patches into one
> 
> v0 [Dien Pham]
> ---
>  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 58 ++++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> index 57ac5ca6ed98..2d9edc61437c 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -46,6 +46,8 @@
>  			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
> +			operating-points-v2 = <&cluster0_opp>;
>  		};
>  
>  		a57_1: cpu@1 {
> @@ -55,6 +57,7 @@
>  			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";

Just curious why clocks are not specified in secondaries ?
Does this continue work if I hotplug out CPUs in ascending order and
then hotplug back in descending order ? Also the current driver or OS
may deal with that but not a good assumption when write DT

-- 
Regards,
Sudeep

WARNING: multiple messages have this Message-ID (diff)
From: sudeep.holla@arm.com (Sudeep Holla)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/2] arm64: dts: r8a7796: Add OPPs table for cpu devices
Date: Thu, 5 Oct 2017 16:04:47 +0100	[thread overview]
Message-ID: <e2e31fd8-b5f8-40a8-df3d-e7726bb8a8e1@arm.com> (raw)
In-Reply-To: <1507209984-17123-3-git-send-email-horms+renesas@verge.net.au>



On 05/10/17 14:26, Simon Horman wrote:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
> 
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
> 

I assume these OPPs will continue to work in future but just not optimal.

> Based in part on work by Hien Dang.
> 
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> v2 [Simon Horman]
> - Only provide one operating points node for each operating-points-v2 node
>   as per the binding; other nodes were unused and have been removed
> 
> v1 [Simon Horman]
> - consolidated several patches into one
> 
> v0 [Dien Pham]
> ---
>  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 58 ++++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> index 57ac5ca6ed98..2d9edc61437c 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -46,6 +46,8 @@
>  			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
> +			operating-points-v2 = <&cluster0_opp>;
>  		};
>  
>  		a57_1: cpu at 1 {
> @@ -55,6 +57,7 @@
>  			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";

Just curious why clocks are not specified in secondaries ?
Does this continue work if I hotplug out CPUs in ascending order and
then hotplug back in descending order ? Also the current driver or OS
may deal with that but not a good assumption when write DT

-- 
Regards,
Sudeep

  reply	other threads:[~2017-10-05 15:04 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-05 13:26 [PATCH v2 0/2] arm64: dts: r8a779[56]: Add OPPs table for cpu devices Simon Horman
2017-10-05 13:26 ` Simon Horman
2017-10-05 13:26 ` [PATCH v2 1/2] arm64: dts: r8a7795: " Simon Horman
2017-10-05 13:26   ` Simon Horman
2017-10-09 11:58   ` Geert Uytterhoeven
2017-10-09 11:58     ` Geert Uytterhoeven
2017-10-05 13:26 ` [PATCH v2 2/2] arm64: dts: r8a7796: " Simon Horman
2017-10-05 13:26   ` Simon Horman
2017-10-05 15:04   ` Sudeep Holla [this message]
2017-10-05 15:04     ` Sudeep Holla
2017-10-09 11:57     ` Geert Uytterhoeven
2017-10-09 11:57       ` Geert Uytterhoeven
2017-10-10 14:33       ` Sudeep Holla
2017-10-10 14:33         ` Sudeep Holla
2017-10-10 14:44         ` Geert Uytterhoeven
2017-10-10 14:44           ` Geert Uytterhoeven
2017-10-10  7:25     ` Simon Horman
2017-10-10  7:25       ` Simon Horman
2017-10-09 11:56   ` Geert Uytterhoeven
2017-10-09 11:56     ` Geert Uytterhoeven
2017-10-10  7:25     ` Simon Horman
2017-10-10  7:25       ` Simon Horman

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