[PATCH 0/9] Broxton DSI dual-link and sequence fixes

[PATCH 0/9] Broxton DSI dual-link and sequence fixes

[Vidya Srinivas]

This patch series enables Broxton DSI dual-link support.
This also fixes sequence issues and resolves split screen
and suspend/resume issues.

Uma Shankar (9):
  drm/i915: Check for platform specific GPIO config
  drm/i915: Fix PLL 8x/3 divider for MIPI video mode
  drm: Add DSI panel power on/off sequence programming
  drm/i915: Add DSI panel power on/off sequence callbacks
  drm/i915/bxt: Fix BXT DSI ULPS sequence
  drm/i915/bxt: Fix BXT DSI disable sequence
  drm/i915/bxt: Disable device ready before shutdown command
  drm/i915/bxt: Enable BXT DSI dual link
  drm/i915/bxt: Fix the DSI enable sequence

 drivers/gpu/drm/i915/i915_reg.h            |   5 ++
 drivers/gpu/drm/i915/intel_dsi.c           | 105 ++++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  18 ++++-
 drivers/gpu/drm/i915/intel_dsi_pll.c       |   6 +-
 include/drm/drm_panel.h                    |  18 +++++
 5 files changed, 112 insertions(+), 40 deletions(-)

-- 
1.9.1

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[PATCH 1/9] drm/i915: Check for platform specific GPIO config

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Panel GPIO control should be done based on platform. Add a check
to restrict VLV and CHT specific GPIO confirguration, so that
they dont apply to other platforms.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c98234e..c297ea9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1584,7 +1584,8 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
 	 * In case of BYT with CRC PMIC, we need to use GPIO for
 	 * Panel control.
 	 */
-	if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+		(dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
 		intel_dsi->gpio_panel =
 			gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
 
-- 
1.9.1

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[PATCH 2/9] drm/i915: Fix PLL 8x/3 divider for MIPI video mode

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

MIPI Video Mode for high res panels (requiring dual link), need a
8X/3 divider to be programmed as 0x2. Modifying the same
in this patch.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 61440e5..3a73086 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -416,11 +416,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
 	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
 
-	/* As per bpsec program the 8/3X clock divider to the below value */
-	if (dev_priv->vbt.dsi.config->is_cmd_mode)
-		mipi_8by3_divider = 0x2;
-	else
-		mipi_8by3_divider = 0x3;
+	mipi_8by3_divider = 0x2;
 
 	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
 	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
-- 
1.9.1

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[PATCH 3/9] drm: Add DSI panel power on/off sequence programming

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Panel Power On/Off sequences are part of Panel spec.
Enabling the support of same in DRM layer for fine grained
panel control. Some DSI controller/panels require making
SOC specific device ready changes in between the panel
power ON and sending the OTP sequences.

This patch introduces drm_panel_power_on which can be used
to decouple panel power ON and OTP. Earlier both operations
were being done as part of drm_panel_prepare.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 include/drm/drm_panel.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 220d1e2b..515595b 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -69,6 +69,8 @@ struct drm_panel_funcs {
 	int (*disable)(struct drm_panel *panel);
 	int (*unprepare)(struct drm_panel *panel);
 	int (*prepare)(struct drm_panel *panel);
+	int (*power_on)(struct drm_panel *panel);
+	int (*power_off)(struct drm_panel *panel);
 	int (*enable)(struct drm_panel *panel);
 	int (*get_modes)(struct drm_panel *panel);
 	int (*get_timings)(struct drm_panel *panel, unsigned int num_timings,
@@ -166,6 +168,22 @@ static inline int drm_panel_enable(struct drm_panel *panel)
 	return panel ? -ENOSYS : -EINVAL;
 }
 
+static inline int drm_panel_power_on(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->power_on)
+		return panel->funcs->power_on(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
+static inline int drm_panel_power_off(struct drm_panel *panel)
+{
+	if (panel && panel->funcs && panel->funcs->power_off)
+		return panel->funcs->power_off(panel);
+
+	return panel ? -ENOSYS : -EINVAL;
+}
+
 /**
  * drm_panel_get_modes - probe the available display modes of a panel
  * @panel: DRM panel
-- 
1.9.1

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[PATCH 4/9] drm/i915: Add DSI panel power on/off sequence callbacks

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Panel Power On/Off sequences are part of Panel spec.
These are present in VBT v3 of the Intel VBT spec.
Some DSI controller/panels require making SOC specific
device ready changes in between the panel power ON and
sending the OTP sequences.

This patch introduces panel power on callbacks to decouple
panel power ON and OTP.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8f683b8..4279279 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -547,10 +547,24 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
 	return 1;
 }
 
+static int vbt_panel_power_on(struct drm_panel *panel)
+{
+	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
+	return 0;
+}
+
+static int vbt_panel_power_off(struct drm_panel *panel)
+{
+	generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
+	return 0;
+}
+
 static const struct drm_panel_funcs vbt_panel_funcs = {
 	.disable = vbt_panel_disable,
 	.unprepare = vbt_panel_unprepare,
 	.prepare = vbt_panel_prepare,
+	.power_on = vbt_panel_power_on,
+	.power_off = vbt_panel_power_off,
 	.enable = vbt_panel_enable,
 	.get_modes = vbt_panel_get_modes,
 };
-- 
1.9.1

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[PATCH 5/9] drm/i915/bxt: Fix BXT DSI ULPS sequence

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Fix the Sequence to program BXT DSI Latch and ULPS.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 23 +++++------------------
 1 file changed, 5 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c297ea9..538755b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 
 	DRM_DEBUG_KMS("\n");
 
-	/* Exit Low power state in 4 steps*/
+	/* Enable MIPI PHY transparent latch */
 	for_each_dsi_port(port, intel_dsi->ports) {
-
-		/* 1. Enable MIPI PHY transparent latch */
 		val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 		I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 		usleep_range(2000, 2500);
+	}
 
-		/* 2. Enter ULPS */
-		val = I915_READ(MIPI_DEVICE_READY(port));
-		val &= ~ULPS_STATE_MASK;
-		val |= (ULPS_STATE_ENTER | DEVICE_READY);
-		I915_WRITE(MIPI_DEVICE_READY(port), val);
-		/* at least 2us - relaxed for hrtimer subsystem optimization */
-		usleep_range(10, 50);
-
-		/* 3. Exit ULPS */
+	/* Clear ULPS and set device ready */
+	for_each_dsi_port(port, intel_dsi->ports) {
 		val = I915_READ(MIPI_DEVICE_READY(port));
 		val &= ~ULPS_STATE_MASK;
-		val |= (ULPS_STATE_EXIT | DEVICE_READY);
 		I915_WRITE(MIPI_DEVICE_READY(port), val);
-		usleep_range(1000, 1500);
-
-		/* Clear ULPS and set device ready */
-		val = I915_READ(MIPI_DEVICE_READY(port));
-		val &= ~ULPS_STATE_MASK;
+		usleep_range(2000, 2500);
 		val |= DEVICE_READY;
 		I915_WRITE(MIPI_DEVICE_READY(port), val);
 	}
-- 
1.9.1

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[PATCH 6/9] drm/i915/bxt: Fix BXT DSI disable sequence

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Fix BXT DSI disable sequence as per latest updates in BSpec.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 538755b..808158f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -632,8 +632,10 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		for_each_dsi_port(port, intel_dsi->ports)
 			wait_for_dsi_fifo_empty(intel_dsi, port);
 
-		intel_dsi_port_disable(encoder);
-		msleep(2);
+		if (!IS_BROXTON(dev_priv)) {
+			intel_dsi_port_disable(encoder);
+			usleep_range(2000, 2500);
+		}
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
@@ -641,7 +643,11 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
 		intel_dsi_reset_clocks(encoder, port);
-		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+		temp = 0;
+		if (intel_dsi->clock_stop) {
+			temp |= CLOCKSTOP;
+			I915_WRITE(MIPI_EOT_DISABLE(port), temp);
+		}
 
 		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 		temp &= ~VID_MODE_FORMAT_MASK;
@@ -707,12 +713,25 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 val;
+	enum port port;
 
 	DRM_DEBUG_KMS("\n");
 
 	intel_dsi_disable(encoder);
 
-	intel_dsi_clear_device_ready(encoder);
+	if (IS_BROXTON(dev_priv)) {
+		/*
+		 * Reset the DSI Device ready first for both ports
+		 * and then port control registers for both ports
+		 */
+		for_each_dsi_port(port, intel_dsi->ports)
+			I915_WRITE(MIPI_DEVICE_READY(port), 0);
+
+		for_each_dsi_port(port, intel_dsi->ports)
+			I915_WRITE(BXT_MIPI_PORT_CTRL(port), 0);
+	} else {
+		intel_dsi_clear_device_ready(encoder);
+	}
 
 	if (IS_BROXTON(dev_priv)) {
 		/* Power down DSI regulator to save power */
@@ -737,6 +756,8 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
 
 	drm_panel_unprepare(intel_dsi->panel);
 
+	/* Disable Panel */
+	drm_panel_power_off(intel_dsi->panel);
 	msleep(intel_dsi->panel_off_delay);
 
 	/* Panel Disable over CRC PMIC */
-- 
1.9.1

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[PATCH 7/9] drm/i915/bxt: Disable device ready before shutdown command

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Disable device ready before MIPI port shutdown command.
This helps to avoid mipi split screen issues.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 808158f..12aeee1 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -603,6 +603,8 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
 				  struct intel_crtc_state *old_crtc_state,
 				  struct drm_connector_state *old_conn_state)
 {
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 
@@ -610,6 +612,15 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
 
 	intel_panel_disable_backlight(intel_dsi->attached_connector);
 
+	/*
+	 * Disable Device ready before the port shutdown in order
+	 * to avoid split screen
+	 */
+	if (IS_BROXTON(dev_priv)) {
+		for_each_dsi_port(port, intel_dsi->ports)
+			I915_WRITE(MIPI_DEVICE_READY(port), 0);
+	}
+
 	if (is_vid_mode(intel_dsi)) {
 		/* Send Shutdown command to the panel in LP mode */
 		for_each_dsi_port(port, intel_dsi->ports)
-- 
1.9.1

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[PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Enable support for BXT DSI dual link mode.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  5 +++++
 drivers/gpu/drm/i915/intel_dsi.c | 27 ++++++++++++++++++---------
 2 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07b1a2d..3b2925c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8425,6 +8425,7 @@ enum {
 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
+#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 << 0)
 
 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
@@ -8758,6 +8759,10 @@ enum {
 #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
 #define  RGB_FLIP_TO_BGR				(1 << 2)
 
+/* BXT has dual link Z inversion overlap field */
+#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
+#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
+
 #define  BXT_PIPE_SELECT_SHIFT				7
 #define  BXT_PIPE_SELECT_MASK				(7 << 7)
 #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 12aeee1..60ca0b9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -440,15 +440,24 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
+	u32 temp;
 
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
-		u32 temp;
-
-		temp = I915_READ(VLV_CHICKEN_3);
-		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+		if (IS_BROXTON(dev_priv)) {
+			for_each_dsi_port(port, intel_dsi->ports) {
+				temp = I915_READ(MIPI_CTRL(port));
+				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 					intel_dsi->pixel_overlap <<
-					PIXEL_OVERLAP_CNT_SHIFT;
-		I915_WRITE(VLV_CHICKEN_3, temp);
+					BXT_PIXEL_OVERLAP_CNT_SHIFT;
+				I915_WRITE(MIPI_CTRL(port), temp);
+			}
+		} else {
+			temp = I915_READ(VLV_CHICKEN_3);
+			temp &= ~PIXEL_OVERLAP_CNT_MASK |
+				intel_dsi->pixel_overlap <<
+				PIXEL_OVERLAP_CNT_SHIFT;
+			I915_WRITE(VLV_CHICKEN_3, temp);
+		}
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
@@ -464,12 +473,12 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 			temp |= (intel_dsi->dual_link - 1)
 						<< DUAL_LINK_MODE_SHIFT;
-			if (IS_BROXTON(dev_priv))
-				temp |= LANE_CONFIGURATION_DUAL_LINK_A;
-			else
+			if (IS_VALLEYVIEW(dev_priv))
 				temp |= intel_crtc->pipe ?
 					LANE_CONFIGURATION_DUAL_LINK_B :
 					LANE_CONFIGURATION_DUAL_LINK_A;
+			else if (IS_BROXTON(dev_priv))
+				temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
 		}
 		/* assert ip_tg_enable signal */
 		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
-- 
1.9.1

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[PATCH 9/9] drm/i915/bxt: Fix the DSI enable sequence

[Vidya Srinivas]

From: Uma Shankar <uma.shankar@intel.com>

Device ready to be done after panel power on and before
sending the OTP commands. Patch fixes the enable sequence
as per this.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c           | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  4 +---
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 60ca0b9..ac02fd8 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -568,6 +568,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 
 	intel_dsi_prepare(encoder, pipe_config);
 
+	if (IS_BROXTON(dev_priv)) {
+		/* Panel Enable */
+		drm_panel_power_on(intel_dsi->panel);
+		msleep(intel_dsi->panel_on_delay);
+	}
+
 	/* Panel Enable over CRC PMIC */
 	if (intel_dsi->gpio_panel)
 		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
@@ -586,6 +592,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
 
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+		/* Panel Enable */
+		drm_panel_power_on(intel_dsi->panel);
+		msleep(intel_dsi->panel_on_delay);
+	}
+
 	drm_panel_prepare(intel_dsi->panel);
 
 	for_each_dsi_port(port, intel_dsi->ports)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 4279279..aa73d22 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -493,9 +493,6 @@ static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
 
 static int vbt_panel_prepare(struct drm_panel *panel)
 {
-	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
-	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
-	generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
 	generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
 
 	return 0;
@@ -550,6 +547,7 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
 static int vbt_panel_power_on(struct drm_panel *panel)
 {
 	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
+	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
 	return 0;
 }
 
-- 
1.9.1

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✓ Fi.CI.BAT: success for Broxton DSI dual-link and sequence fixes

[Patchwork]

== Series Details ==

Series: Broxton DSI dual-link and sequence fixes
URL   : https://patchwork.freedesktop.org/series/19296/
State : success

== Summary ==

Series 19296v1 Broxton DSI dual-link and sequence fixes
https://patchwork.freedesktop.org/api/1.0/series/19296/revisions/1/mbox/

Test kms_force_connector_basic:
        Subgroup force-connector-state:
                dmesg-warn -> PASS       (fi-snb-2520m)
Test kms_pipe_crc_basic:
        Subgroup nonblocking-crc-pipe-c-frame-sequence:
                fail       -> PASS       (fi-skl-6770hq)
        Subgroup read-crc-pipe-a-frame-sequence:
                fail       -> PASS       (fi-skl-6770hq)

fi-bdw-5557u     total:252  pass:238  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:252  pass:230  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-ilk-650       total:252  pass:199  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:252  pass:231  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:252  pass:231  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:252  pass:229  dwarn:0   dfail:0   fail:2   skip:21 
fi-skl-6260u     total:252  pass:239  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:252  pass:232  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:252  pass:227  dwarn:4   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:252  pass:239  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:252  pass:220  dwarn:0   dfail:0   fail:0   skip:32 

80b02983d80ad38722a8bb6c86ca001ed57b9755 drm-tip: 2017y-02m-08d-09h-27m-34s UTC integration manifest
b97fb97 drm/i915/bxt: Fix the DSI enable sequence
4d707c7 drm/i915/bxt: Enable BXT DSI dual link
23c7423 drm/i915/bxt: Disable device ready before shutdown command
5833cc7 drm/i915/bxt: Fix BXT DSI disable sequence
a588169 drm/i915/bxt: Fix BXT DSI ULPS sequence
225ab01 drm/i915: Add DSI panel power on/off sequence callbacks
d2e83b3 drm: Add DSI panel power on/off sequence programming
00c0935 drm/i915: Fix PLL 8x/3 divider for MIPI video mode
82b4e12 drm/i915: Check for platform specific GPIO config

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3733/
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Re: [PATCH 2/9] drm/i915: Fix PLL 8x/3 divider for MIPI video mode

[Jani Nikula]

On Wed, 08 Feb 2017, Vidya Srinivas <vidya.srinivas@intel.com> wrote:
> From: Uma Shankar <uma.shankar@intel.com>
>
> MIPI Video Mode for high res panels (requiring dual link), need a
> 8X/3 divider to be programmed as 0x2. Modifying the same
> in this patch.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

Pushed the first two patches to drm-intel-next-queued, thanks for the
patches.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 61440e5..3a73086 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -416,11 +416,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
>  	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>  	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>  
> -	/* As per bpsec program the 8/3X clock divider to the below value */
> -	if (dev_priv->vbt.dsi.config->is_cmd_mode)
> -		mipi_8by3_divider = 0x2;
> -	else
> -		mipi_8by3_divider = 0x3;
> +	mipi_8by3_divider = 0x2;
>  
>  	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
>  	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 1/9] drm/i915: Check for platform specific GPIO config

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:50 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Panel GPIO control should be done based on platform. Add a check
> to restrict VLV and CHT specific GPIO confirguration, so that
> they dont apply to other platforms.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index c98234e..c297ea9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1584,7 +1584,8 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
>  	 * In case of BYT with CRC PMIC, we need to use GPIO for
>  	 * Panel control.
>  	 */
> -	if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
> +	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> +		(dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
>  		intel_dsi->gpio_panel =
>  			gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
>  

It makes sense to restrict this as it isn't valid for other platforms
as written. But is there something similar for other platforms that we
should set up here?

Since it makes sense to limit this today..
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

-- 
--
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Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH 5/9] drm/i915/bxt: Fix BXT DSI ULPS sequence

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:54 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Fix the Sequence to program BXT DSI Latch and ULPS.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 23 +++++------------------
>  1 file changed, 5 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index c297ea9..538755b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>  
>  	DRM_DEBUG_KMS("\n");
>  
> -	/* Exit Low power state in 4 steps*/
> +	/* Enable MIPI PHY transparent latch */
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -
> -		/* 1. Enable MIPI PHY transparent latch */
>  		val = I915_READ(BXT_MIPI_PORT_CTRL(port));
>  		I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
>  		usleep_range(2000, 2500);
> +	}
>  
> -		/* 2. Enter ULPS */
> -		val = I915_READ(MIPI_DEVICE_READY(port));
> -		val &= ~ULPS_STATE_MASK;
> -		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> -		I915_WRITE(MIPI_DEVICE_READY(port), val);
> -		/* at least 2us - relaxed for hrtimer subsystem optimization */
> -		usleep_range(10, 50);
> -
> -		/* 3. Exit ULPS */
> +	/* Clear ULPS and set device ready */
> +	for_each_dsi_port(port, intel_dsi->ports) {
>  		val = I915_READ(MIPI_DEVICE_READY(port));
>  		val &= ~ULPS_STATE_MASK;
> -		val |= (ULPS_STATE_EXIT | DEVICE_READY);
>  		I915_WRITE(MIPI_DEVICE_READY(port), val);
> -		usleep_range(1000, 1500);
> -
> -		/* Clear ULPS and set device ready */
> -		val = I915_READ(MIPI_DEVICE_READY(port));
> -		val &= ~ULPS_STATE_MASK;
> +		usleep_range(2000, 2500);
>  		val |= DEVICE_READY;
>  		I915_WRITE(MIPI_DEVICE_READY(port), val);
>  	}



-- 
--
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Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH 6/9] drm/i915/bxt: Fix BXT DSI disable sequence

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:55 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Fix BXT DSI disable sequence as per latest updates in BSpec.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 29 +++++++++++++++++++++++++----
>  1 file changed, 25 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 538755b..808158f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -632,8 +632,10 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  		for_each_dsi_port(port, intel_dsi->ports)
>  			wait_for_dsi_fifo_empty(intel_dsi, port);
>  
> -		intel_dsi_port_disable(encoder);
> -		msleep(2);
> +		if (!IS_BROXTON(dev_priv)) {
> +			intel_dsi_port_disable(encoder);
> +			usleep_range(2000, 2500);
> +		}
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> @@ -641,7 +643,11 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>  		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>  
>  		intel_dsi_reset_clocks(encoder, port);
> -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> +		temp = 0;
> +		if (intel_dsi->clock_stop) {
> +			temp |= CLOCKSTOP;
> +			I915_WRITE(MIPI_EOT_DISABLE(port), temp);
> +		}

This could be simplified to just
		if (intel_dsi->clock_stop)
			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);


>  
>  		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
>  		temp &= ~VID_MODE_FORMAT_MASK;
> @@ -707,12 +713,25 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 val;
> +	enum port port;
>  
>  	DRM_DEBUG_KMS("\n");
>  
>  	intel_dsi_disable(encoder);
>  
> -	intel_dsi_clear_device_ready(encoder);
> +	if (IS_BROXTON(dev_priv)) {
> +		/*
> +		 * Reset the DSI Device ready first for both ports
> +		 * and then port control registers for both ports
> +		 */
> +		for_each_dsi_port(port, intel_dsi->ports)
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0);
> +
> +		for_each_dsi_port(port, intel_dsi->ports)
> +			I915_WRITE(BXT_MIPI_PORT_CTRL(port), 0);
> +	} else {
> +		intel_dsi_clear_device_ready(encoder);
> +	}
>  
>  	if (IS_BROXTON(dev_priv)) {
>  		/* Power down DSI regulator to save power */
> @@ -737,6 +756,8 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
>  
>  	drm_panel_unprepare(intel_dsi->panel);
>  
> +	/* Disable Panel */
> +	drm_panel_power_off(intel_dsi->panel);

This depends on the previous patch, which I don't think is the
direction we want to go.  If the code is reworked to not use the
drm_panel interface, then this would need to change also.

>  	msleep(intel_dsi->panel_off_delay);
>  

Do we need to call intel_disable_dsi_pll(encoder) here as part of the
power off?

>  	/* Panel Disable over CRC PMIC */



-- 
--
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Re: [PATCH 7/9] drm/i915/bxt: Disable device ready before shutdown command

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:56 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Disable device ready before MIPI port shutdown command.
> This helps to avoid mipi split screen issues.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 808158f..12aeee1 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -603,6 +603,8 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>  				  struct intel_crtc_state *old_crtc_state,
>  				  struct drm_connector_state *old_conn_state)
>  {
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port;
>  
> @@ -610,6 +612,15 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>  
>  	intel_panel_disable_backlight(intel_dsi->attached_connector);
>  
> +	/*
> +	 * Disable Device ready before the port shutdown in order
> +	 * to avoid split screen
> +	 */
> +	if (IS_BROXTON(dev_priv)) {
> +		for_each_dsi_port(port, intel_dsi->ports)
> +			I915_WRITE(MIPI_DEVICE_READY(port), 0);
> +	}
> +
>  	if (is_vid_mode(intel_dsi)) {
>  		/* Send Shutdown command to the panel in LP mode */
>  		for_each_dsi_port(port, intel_dsi->ports)



-- 
--
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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:57 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Enable support for BXT DSI dual link mode.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  5 +++++
>  drivers/gpu/drm/i915/intel_dsi.c | 27 ++++++++++++++++++---------
>  2 files changed, 23 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 07b1a2d..3b2925c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8425,6 +8425,7 @@ enum {
>  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
>  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
>  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
> +#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 << 0)
>  
>  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
>  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
> @@ -8758,6 +8759,10 @@ enum {
>  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
>  #define  RGB_FLIP_TO_BGR				(1 << 2)
>  
> +/* BXT has dual link Z inversion overlap field */
> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
> +
>  #define  BXT_PIPE_SELECT_SHIFT				7
>  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
>  #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 12aeee1..60ca0b9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -440,15 +440,24 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port;
> +	u32 temp;
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> -		u32 temp;
> -
> -		temp = I915_READ(VLV_CHICKEN_3);
> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +		if (IS_BROXTON(dev_priv)) {
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				temp = I915_READ(MIPI_CTRL(port));
> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
>  					intel_dsi->pixel_overlap <<
> -					PIXEL_OVERLAP_CNT_SHIFT;
> -		I915_WRITE(VLV_CHICKEN_3, temp);
> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> +				I915_WRITE(MIPI_CTRL(port), temp);
> +			}
> +		} else {
> +			temp = I915_READ(VLV_CHICKEN_3);
> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +				intel_dsi->pixel_overlap <<
> +				PIXEL_OVERLAP_CNT_SHIFT;
> +			I915_WRITE(VLV_CHICKEN_3, temp);
> +		}
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> @@ -464,12 +473,12 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
>  			temp |= (intel_dsi->dual_link - 1)
>  						<< DUAL_LINK_MODE_SHIFT;
> -			if (IS_BROXTON(dev_priv))
> -				temp |= LANE_CONFIGURATION_DUAL_LINK_A;
> -			else
> +			if (IS_VALLEYVIEW(dev_priv))
>  				temp |= intel_crtc->pipe ?
>  					LANE_CONFIGURATION_DUAL_LINK_B :
>  					LANE_CONFIGURATION_DUAL_LINK_A;
> +			else if (IS_BROXTON(dev_priv))
> +				temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
>  		}
>  		/* assert ip_tg_enable signal */
>  		I915_WRITE(port_ctrl, temp | DPI_ENABLE);



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH 4/9] drm/i915: Add DSI panel power on/off sequence callbacks

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:53 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Panel Power On/Off sequences are part of Panel spec.
> These are present in VBT v3 of the Intel VBT spec.
> Some DSI controller/panels require making SOC specific
> device ready changes in between the panel power ON and
> sending the OTP sequences.
> 
> This patch introduces panel power on callbacks to decouple
> panel power ON and OTP.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

Based on some conversation with Jani, we probably don't want to expand
the use of the drm_panel interfaces but instead move to an i915 only
panel interface.  This would allow us to have more granular control
over the sequences.

But since this is actually adding new drm_panel interfaces,

Acknowledged-by: Bob Paauwe <bob.j.paauwe@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 8f683b8..4279279 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -547,10 +547,24 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
>  	return 1;
>  }
>  
> +static int vbt_panel_power_on(struct drm_panel *panel)
> +{
> +	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> +	return 0;
> +}
> +
> +static int vbt_panel_power_off(struct drm_panel *panel)
> +{
> +	generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
> +	return 0;
> +}
> +
>  static const struct drm_panel_funcs vbt_panel_funcs = {
>  	.disable = vbt_panel_disable,
>  	.unprepare = vbt_panel_unprepare,
>  	.prepare = vbt_panel_prepare,
> +	.power_on = vbt_panel_power_on,
> +	.power_off = vbt_panel_power_off,
>  	.enable = vbt_panel_enable,
>  	.get_modes = vbt_panel_get_modes,
>  };



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
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Re: [PATCH 9/9] drm/i915/bxt: Fix the DSI enable sequence

[Bob Paauwe]

On Wed, 8 Feb 2017 16:20:58 +0530
Vidya Srinivas <vidya.srinivas@intel.com> wrote:

> From: Uma Shankar <uma.shankar@intel.com>
> 
> Device ready to be done after panel power on and before
> sending the OTP commands. Patch fixes the enable sequence
> as per this.
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

I think this will need to be rebased now.

The sequence looks like it will be slightly different from what I'm
currently using for Broxton.  But in general it seems correct.

Bob

> ---
>  drivers/gpu/drm/i915/intel_dsi.c           | 12 ++++++++++++
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  4 +---
>  2 files changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 60ca0b9..ac02fd8 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -568,6 +568,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  
>  	intel_dsi_prepare(encoder, pipe_config);
>  
> +	if (IS_BROXTON(dev_priv)) {
> +		/* Panel Enable */
> +		drm_panel_power_on(intel_dsi->panel);
> +		msleep(intel_dsi->panel_on_delay);
> +	}
> +
>  	/* Panel Enable over CRC PMIC */
>  	if (intel_dsi->gpio_panel)
>  		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
> @@ -586,6 +592,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>  	/* put device in ready state */
>  	intel_dsi_device_ready(encoder);
>  
> +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> +		/* Panel Enable */
> +		drm_panel_power_on(intel_dsi->panel);
> +		msleep(intel_dsi->panel_on_delay);
> +	}
> +
>  	drm_panel_prepare(intel_dsi->panel);
>  
>  	for_each_dsi_port(port, intel_dsi->ports)
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 4279279..aa73d22 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -493,9 +493,6 @@ static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id)
>  
>  static int vbt_panel_prepare(struct drm_panel *panel)
>  {
> -	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
> -	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> -	generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
>  	generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
>  
>  	return 0;
> @@ -550,6 +547,7 @@ static int vbt_panel_get_modes(struct drm_panel *panel)
>  static int vbt_panel_power_on(struct drm_panel *panel)
>  {
>  	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> +	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
>  	return 0;
>  }
>  



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH 5/9] drm/i915/bxt: Fix BXT DSI ULPS sequence

[Jani Nikula]

On Wed, 15 Feb 2017, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> On Wed, 8 Feb 2017 16:20:54 +0530
> Vidya Srinivas <vidya.srinivas@intel.com> wrote:
>
>> From: Uma Shankar <uma.shankar@intel.com>
>> 
>> Fix the Sequence to program BXT DSI Latch and ULPS.
>> 
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>
> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

Pushed this one patch to dinq, thanks for the patch and review.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi.c | 23 +++++------------------
>>  1 file changed, 5 insertions(+), 18 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index c297ea9..538755b 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
>>  
>>  	DRM_DEBUG_KMS("\n");
>>  
>> -	/* Exit Low power state in 4 steps*/
>> +	/* Enable MIPI PHY transparent latch */
>>  	for_each_dsi_port(port, intel_dsi->ports) {
>> -
>> -		/* 1. Enable MIPI PHY transparent latch */
>>  		val = I915_READ(BXT_MIPI_PORT_CTRL(port));
>>  		I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
>>  		usleep_range(2000, 2500);
>> +	}
>>  
>> -		/* 2. Enter ULPS */
>> -		val = I915_READ(MIPI_DEVICE_READY(port));
>> -		val &= ~ULPS_STATE_MASK;
>> -		val |= (ULPS_STATE_ENTER | DEVICE_READY);
>> -		I915_WRITE(MIPI_DEVICE_READY(port), val);
>> -		/* at least 2us - relaxed for hrtimer subsystem optimization */
>> -		usleep_range(10, 50);
>> -
>> -		/* 3. Exit ULPS */
>> +	/* Clear ULPS and set device ready */
>> +	for_each_dsi_port(port, intel_dsi->ports) {
>>  		val = I915_READ(MIPI_DEVICE_READY(port));
>>  		val &= ~ULPS_STATE_MASK;
>> -		val |= (ULPS_STATE_EXIT | DEVICE_READY);
>>  		I915_WRITE(MIPI_DEVICE_READY(port), val);
>> -		usleep_range(1000, 1500);
>> -
>> -		/* Clear ULPS and set device ready */
>> -		val = I915_READ(MIPI_DEVICE_READY(port));
>> -		val &= ~ULPS_STATE_MASK;
>> +		usleep_range(2000, 2500);
>>  		val |= DEVICE_READY;
>>  		I915_WRITE(MIPI_DEVICE_READY(port), val);
>>  	}

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 7/9] drm/i915/bxt: Disable device ready before shutdown command

[Jani Nikula]

On Wed, 15 Feb 2017, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> On Wed, 8 Feb 2017 16:20:56 +0530
> Vidya Srinivas <vidya.srinivas@intel.com> wrote:
>
>> From: Uma Shankar <uma.shankar@intel.com>
>> 
>> Disable device ready before MIPI port shutdown command.
>> This helps to avoid mipi split screen issues.
>> 
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>
> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

Pushed this one patch to dinq, thanks for the patch and review.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi.c | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 808158f..12aeee1 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -603,6 +603,8 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>>  				  struct intel_crtc_state *old_crtc_state,
>>  				  struct drm_connector_state *old_conn_state)
>>  {
>> +	struct drm_device *dev = encoder->base.dev;
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>  	enum port port;
>>  
>> @@ -610,6 +612,15 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>>  
>>  	intel_panel_disable_backlight(intel_dsi->attached_connector);
>>  
>> +	/*
>> +	 * Disable Device ready before the port shutdown in order
>> +	 * to avoid split screen
>> +	 */
>> +	if (IS_BROXTON(dev_priv)) {
>> +		for_each_dsi_port(port, intel_dsi->ports)
>> +			I915_WRITE(MIPI_DEVICE_READY(port), 0);
>> +	}
>> +
>>  	if (is_vid_mode(intel_dsi)) {
>>  		/* Send Shutdown command to the panel in LP mode */
>>  		for_each_dsi_port(port, intel_dsi->ports)

-- 
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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Jani Nikula]

On Wed, 15 Feb 2017, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> On Wed, 8 Feb 2017 16:20:57 +0530
> Vidya Srinivas <vidya.srinivas@intel.com> wrote:
>
>> From: Uma Shankar <uma.shankar@intel.com>
>> 
>> Enable support for BXT DSI dual link mode.
>> 
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>
> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>

This doesn't apply because I've pushed

commit 6043801f937ada9c9ed9dfa3c6ce542a79643401
Author: Deepak M <m.deepak@intel.com>
Date:   Tue Feb 14 18:46:16 2017 +0530

    drm/i915: Set the Z inversion overlap field

Please update the patch, and in general, please send a new series of
patches that do *not* depend on the drm_panel changes. We can get all of
those merged first. We should try to make progress.

BR,
Jani.


>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  |  5 +++++
>>  drivers/gpu/drm/i915/intel_dsi.c | 27 ++++++++++++++++++---------
>>  2 files changed, 23 insertions(+), 9 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 07b1a2d..3b2925c 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8425,6 +8425,7 @@ enum {
>>  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
>>  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
>>  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
>> +#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 << 0)
>>  
>>  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
>>  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
>> @@ -8758,6 +8759,10 @@ enum {
>>  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
>>  #define  RGB_FLIP_TO_BGR				(1 << 2)
>>  
>> +/* BXT has dual link Z inversion overlap field */
>> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
>> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
>> +
>>  #define  BXT_PIPE_SELECT_SHIFT				7
>>  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
>>  #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 12aeee1..60ca0b9 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -440,15 +440,24 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>  	enum port port;
>> +	u32 temp;
>>  
>>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>> -		u32 temp;
>> -
>> -		temp = I915_READ(VLV_CHICKEN_3);
>> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
>> +		if (IS_BROXTON(dev_priv)) {
>> +			for_each_dsi_port(port, intel_dsi->ports) {
>> +				temp = I915_READ(MIPI_CTRL(port));
>> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
>>  					intel_dsi->pixel_overlap <<
>> -					PIXEL_OVERLAP_CNT_SHIFT;
>> -		I915_WRITE(VLV_CHICKEN_3, temp);
>> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
>> +				I915_WRITE(MIPI_CTRL(port), temp);
>> +			}
>> +		} else {
>> +			temp = I915_READ(VLV_CHICKEN_3);
>> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
>> +				intel_dsi->pixel_overlap <<
>> +				PIXEL_OVERLAP_CNT_SHIFT;
>> +			I915_WRITE(VLV_CHICKEN_3, temp);
>> +		}
>>  	}
>>  
>>  	for_each_dsi_port(port, intel_dsi->ports) {
>> @@ -464,12 +473,12 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>>  		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
>>  			temp |= (intel_dsi->dual_link - 1)
>>  						<< DUAL_LINK_MODE_SHIFT;
>> -			if (IS_BROXTON(dev_priv))
>> -				temp |= LANE_CONFIGURATION_DUAL_LINK_A;
>> -			else
>> +			if (IS_VALLEYVIEW(dev_priv))
>>  				temp |= intel_crtc->pipe ?
>>  					LANE_CONFIGURATION_DUAL_LINK_B :
>>  					LANE_CONFIGURATION_DUAL_LINK_A;
>> +			else if (IS_BROXTON(dev_priv))
>> +				temp |= LANE_CONFIGURATION_DUAL_LINK_ENABLE;
>>  		}
>>  		/* assert ip_tg_enable signal */
>>  		I915_WRITE(port_ctrl, temp | DPI_ENABLE);

-- 
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Re: [PATCH 6/9] drm/i915/bxt: Fix BXT DSI disable sequence

[Srinivas, Vidya]

> -----Original Message-----
> From: Paauwe, Bob J
> Sent: Wednesday, February 15, 2017 11:55 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 6/9] drm/i915/bxt: Fix BXT DSI disable
> sequence
> 
> On Wed, 8 Feb 2017 16:20:55 +0530
> Vidya Srinivas <vidya.srinivas@intel.com> wrote:
> 
> > From: Uma Shankar <uma.shankar@intel.com>
> >
> > Fix BXT DSI disable sequence as per latest updates in BSpec.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 29 +++++++++++++++++++++++++----
> >  1 file changed, 25 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 538755b..808158f 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -632,8 +632,10 @@ static void intel_dsi_disable(struct intel_encoder
> *encoder)
> >  		for_each_dsi_port(port, intel_dsi->ports)
> >  			wait_for_dsi_fifo_empty(intel_dsi, port);
> >
> > -		intel_dsi_port_disable(encoder);
> > -		msleep(2);
> > +		if (!IS_BROXTON(dev_priv)) {
> > +			intel_dsi_port_disable(encoder);
> > +			usleep_range(2000, 2500);
> > +		}
> >  	}
> >
> >  	for_each_dsi_port(port, intel_dsi->ports) { @@ -641,7 +643,11 @@
> > static void intel_dsi_disable(struct intel_encoder *encoder)
> >  		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> >
> >  		intel_dsi_reset_clocks(encoder, port);
> > -		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> > +		temp = 0;
> > +		if (intel_dsi->clock_stop) {
> > +			temp |= CLOCKSTOP;
> > +			I915_WRITE(MIPI_EOT_DISABLE(port), temp);
> > +		}
> 
> This could be simplified to just
> 		if (intel_dsi->clock_stop)
> 			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> 
Yes, thanks Bob. I will fix this and resend.

> >
> >  		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> >  		temp &= ~VID_MODE_FORMAT_MASK;
> > @@ -707,12 +713,25 @@ static void intel_dsi_post_disable(struct
> intel_encoder *encoder,
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> >  	u32 val;
> > +	enum port port;
> >
> >  	DRM_DEBUG_KMS("\n");
> >
> >  	intel_dsi_disable(encoder);
> >
> > -	intel_dsi_clear_device_ready(encoder);
> > +	if (IS_BROXTON(dev_priv)) {
> > +		/*
> > +		 * Reset the DSI Device ready first for both ports
> > +		 * and then port control registers for both ports
> > +		 */
> > +		for_each_dsi_port(port, intel_dsi->ports)
> > +			I915_WRITE(MIPI_DEVICE_READY(port), 0);
> > +
> > +		for_each_dsi_port(port, intel_dsi->ports)
> > +			I915_WRITE(BXT_MIPI_PORT_CTRL(port), 0);
> > +	} else {
> > +		intel_dsi_clear_device_ready(encoder);
> > +	}
> >
> >  	if (IS_BROXTON(dev_priv)) {
> >  		/* Power down DSI regulator to save power */ @@ -737,6
> +756,8 @@
> > static void intel_dsi_post_disable(struct intel_encoder *encoder,
> >
> >  	drm_panel_unprepare(intel_dsi->panel);
> >
> > +	/* Disable Panel */
> > +	drm_panel_power_off(intel_dsi->panel);
> 
> This depends on the previous patch, which I don't think is the direction we
> want to go.  If the code is reworked to not use the drm_panel interface, then
> this would need to change also.
> 
Yes, I am planning a different approach to remove the drm_panel interface
Dependency. Will re-submit an updated series.

Thanks Bob for the review and useful comments.

Regards
Vidya

> >  	msleep(intel_dsi->panel_off_delay);
> >
> 
> Do we need to call intel_disable_dsi_pll(encoder) here as part of the power
> off?
> 
> >  	/* Panel Disable over CRC PMIC */
> 
> 
> 
> --
> --
> Bob Paauwe
> Bob.J.Paauwe@intel.com
> IOTG / PED Software Organization
> Intel Corp.  Folsom, CA
> (916) 356-6193

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Re: [PATCH 9/9] drm/i915/bxt: Fix the DSI enable sequence

[Srinivas, Vidya]

> -----Original Message-----
> From: Paauwe, Bob J
> Sent: Thursday, February 16, 2017 12:31 AM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 9/9] drm/i915/bxt: Fix the DSI enable
> sequence
> 
> On Wed, 8 Feb 2017 16:20:58 +0530
> Vidya Srinivas <vidya.srinivas@intel.com> wrote:
> 
> > From: Uma Shankar <uma.shankar@intel.com>
> >
> > Device ready to be done after panel power on and before sending the
> > OTP commands. Patch fixes the enable sequence as per this.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> 
> I think this will need to be rebased now.
> The sequence looks like it will be slightly different from what I'm currently
> using for Broxton.  But in general it seems correct.
> 
> Bob

Thanks Bob. I will rebase the rest of the changes and re-submit.

Regards
Vidya
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c           | 12 ++++++++++++
> >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  4 +---
> >  2 files changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 60ca0b9..ac02fd8 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -568,6 +568,12 @@ static void intel_dsi_pre_enable(struct
> > intel_encoder *encoder,
> >
> >  	intel_dsi_prepare(encoder, pipe_config);
> >
> > +	if (IS_BROXTON(dev_priv)) {
> > +		/* Panel Enable */
> > +		drm_panel_power_on(intel_dsi->panel);
> > +		msleep(intel_dsi->panel_on_delay);
> > +	}
> > +
> >  	/* Panel Enable over CRC PMIC */
> >  	if (intel_dsi->gpio_panel)
> >  		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); @@ -
> 586,6
> > +592,12 @@ static void intel_dsi_pre_enable(struct intel_encoder
> *encoder,
> >  	/* put device in ready state */
> >  	intel_dsi_device_ready(encoder);
> >
> > +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > +		/* Panel Enable */
> > +		drm_panel_power_on(intel_dsi->panel);
> > +		msleep(intel_dsi->panel_on_delay);
> > +	}
> > +
> >  	drm_panel_prepare(intel_dsi->panel);
> >
> >  	for_each_dsi_port(port, intel_dsi->ports) diff --git
> > a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 4279279..aa73d22 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -493,9 +493,6 @@ static void generic_exec_sequence(struct
> drm_panel
> > *panel, enum mipi_seq seq_id)
> >
> >  static int vbt_panel_prepare(struct drm_panel *panel)  {
> > -	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
> > -	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> > -	generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
> >  	generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
> >
> >  	return 0;
> > @@ -550,6 +547,7 @@ static int vbt_panel_get_modes(struct drm_panel
> > *panel)  static int vbt_panel_power_on(struct drm_panel *panel)  {
> >  	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> > +	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
> >  	return 0;
> >  }
> >
> 
> 
> 
> --
> --
> Bob Paauwe
> Bob.J.Paauwe@intel.com
> IOTG / PED Software Organization
> Intel Corp.  Folsom, CA
> (916) 356-6193

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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Srinivas, Vidya]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Thursday, February 16, 2017 8:56 PM
> To: Paauwe, Bob J <bob.j.paauwe@intel.com>; Srinivas, Vidya
> <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link
> 
> On Wed, 15 Feb 2017, Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> > On Wed, 8 Feb 2017 16:20:57 +0530
> > Vidya Srinivas <vidya.srinivas@intel.com> wrote:
> >
> >> From: Uma Shankar <uma.shankar@intel.com>
> >>
> >> Enable support for BXT DSI dual link mode.
> >>
> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> >
> > Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
> 
> This doesn't apply because I've pushed
> 
> commit 6043801f937ada9c9ed9dfa3c6ce542a79643401
> Author: Deepak M <m.deepak@intel.com>
> Date:   Tue Feb 14 18:46:16 2017 +0530
> 
>     drm/i915: Set the Z inversion overlap field
> 
> Please update the patch, and in general, please send a new series of patches
> that do *not* depend on the drm_panel changes. We can get all of those
> merged first. We should try to make progress.
> 
> BR,
> Jani.

Thanks Jani. I will rebase and re-submit and also  to remove drm_panel
interface dependency, I am planning to create panel sequence callbacks
in intel_dsi structure itself. Is this approach okay?

Regards
Vidya

> 
> 
> >
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h  |  5 +++++
> >> drivers/gpu/drm/i915/intel_dsi.c | 27 ++++++++++++++++++---------
> >>  2 files changed, 23 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h index 07b1a2d..3b2925c 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -8425,6 +8425,7 @@ enum {
> >>  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
> >>  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 <<
> 0)
> >>  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 <<
> 0)
> >> +#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 <<
> 0)
> >>
> >>  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE
> + 0x61194)
> >>  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE
> + 0x61704)
> >> @@ -8758,6 +8759,10 @@ enum {
> >>  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
> >>  #define  RGB_FLIP_TO_BGR				(1 << 2)
> >>
> >> +/* BXT has dual link Z inversion overlap field */
> >> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> >> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
> >> +
> >>  #define  BXT_PIPE_SELECT_SHIFT				7
> >>  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
> >>  #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> >> b/drivers/gpu/drm/i915/intel_dsi.c
> >> index 12aeee1..60ca0b9 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> >> @@ -440,15 +440,24 @@ static void intel_dsi_port_enable(struct
> intel_encoder *encoder)
> >>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> >>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> >>  	enum port port;
> >> +	u32 temp;
> >>
> >>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> >> -		u32 temp;
> >> -
> >> -		temp = I915_READ(VLV_CHICKEN_3);
> >> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> >> +		if (IS_BROXTON(dev_priv)) {
> >> +			for_each_dsi_port(port, intel_dsi->ports) {
> >> +				temp = I915_READ(MIPI_CTRL(port));
> >> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK
> |
> >>  					intel_dsi->pixel_overlap <<
> >> -					PIXEL_OVERLAP_CNT_SHIFT;
> >> -		I915_WRITE(VLV_CHICKEN_3, temp);
> >> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> >> +				I915_WRITE(MIPI_CTRL(port), temp);
> >> +			}
> >> +		} else {
> >> +			temp = I915_READ(VLV_CHICKEN_3);
> >> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> >> +				intel_dsi->pixel_overlap <<
> >> +				PIXEL_OVERLAP_CNT_SHIFT;
> >> +			I915_WRITE(VLV_CHICKEN_3, temp);
> >> +		}
> >>  	}
> >>
> >>  	for_each_dsi_port(port, intel_dsi->ports) { @@ -464,12 +473,12
> @@
> >> static void intel_dsi_port_enable(struct intel_encoder *encoder)
> >>  		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
> >>  			temp |= (intel_dsi->dual_link - 1)
> >>  						<<
> DUAL_LINK_MODE_SHIFT;
> >> -			if (IS_BROXTON(dev_priv))
> >> -				temp |=
> LANE_CONFIGURATION_DUAL_LINK_A;
> >> -			else
> >> +			if (IS_VALLEYVIEW(dev_priv))
> >>  				temp |= intel_crtc->pipe ?
> >>
> 	LANE_CONFIGURATION_DUAL_LINK_B :
> >>
> 	LANE_CONFIGURATION_DUAL_LINK_A;
> >> +			else if (IS_BROXTON(dev_priv))
> >> +				temp |=
> LANE_CONFIGURATION_DUAL_LINK_ENABLE;
> >>  		}
> >>  		/* assert ip_tg_enable signal */
> >>  		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Jani Nikula]

On Mon, 20 Feb 2017, "Srinivas, Vidya" <vidya.srinivas@intel.com> wrote:
> Thanks Jani. I will rebase and re-submit and also  to remove drm_panel
> interface dependency, I am planning to create panel sequence callbacks
> in intel_dsi structure itself. Is this approach okay?

I think that's unnecessary overhead. I've come to think we should just
do what Hans suggested in his patch [1]. It's easiest, and we don't
really benefit anything from the drm_panel interface or function pointer
chasing.

Hans, do you think you'll have the time or motivation to refresh your
series, or should we just let Vidya do this?

As an added difficulty, there's Madhav doing the Geminilake enabling at
the same time, and these two/three series [2][3][4] are bound to
conflict to some extent.

BR,
Jani.


[1] http://patchwork.freedesktop.org/patch/msgid/20161201202925.12220-10-hdegoede@redhat.com
[2] http://mid.mail-archive.com/20161201202925.12220-1-hdegoede@redhat.com
[3] http://mid.mail-archive.com/1486551058-22596-1-git-send-email-vidya.srinivas@intel.com
[4] http://mid.mail-archive.com/1487335415-14766-1-git-send-email-madhav.chauhan@intel.com
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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Hans de Goede]

Hi,

On 20-02-17 12:00, Jani Nikula wrote:
> On Mon, 20 Feb 2017, "Srinivas, Vidya" <vidya.srinivas@intel.com> wrote:
>> Thanks Jani. I will rebase and re-submit and also  to remove drm_panel
>> interface dependency, I am planning to create panel sequence callbacks
>> in intel_dsi structure itself. Is this approach okay?
>
> I think that's unnecessary overhead. I've come to think we should just
> do what Hans suggested in his patch [1]. It's easiest, and we don't
> really benefit anything from the drm_panel interface or function pointer
> chasing.
>
> Hans, do you think you'll have the time or motivation to refresh your
> series, or should we just let Vidya do this?
>
> As an added difficulty, there's Madhav doing the Geminilake enabling at
> the same time, and these two/three series [2][3][4] are bound to
> conflict to some extent.

I've my series rebased in a personal repo. As I was planning on resubmitting
it at some point in the future. I can send out a new version right now if
you want ...

Regards,

Hans
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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Jani Nikula]

On Mon, 20 Feb 2017, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 20-02-17 12:00, Jani Nikula wrote:
>> On Mon, 20 Feb 2017, "Srinivas, Vidya" <vidya.srinivas@intel.com> wrote:
>>> Thanks Jani. I will rebase and re-submit and also  to remove drm_panel
>>> interface dependency, I am planning to create panel sequence callbacks
>>> in intel_dsi structure itself. Is this approach okay?
>>
>> I think that's unnecessary overhead. I've come to think we should just
>> do what Hans suggested in his patch [1]. It's easiest, and we don't
>> really benefit anything from the drm_panel interface or function pointer
>> chasing.
>>
>> Hans, do you think you'll have the time or motivation to refresh your
>> series, or should we just let Vidya do this?
>>
>> As an added difficulty, there's Madhav doing the Geminilake enabling at
>> the same time, and these two/three series [2][3][4] are bound to
>> conflict to some extent.
>
> I've my series rebased in a personal repo. As I was planning on resubmitting
> it at some point in the future. I can send out a new version right now if
> you want ...

Please do!

BR,
Jani.


>
> Regards,
>
> Hans

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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Jani Nikula]

On Mon, 20 Feb 2017, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 20-02-17 12:00, Jani Nikula wrote:
>> On Mon, 20 Feb 2017, "Srinivas, Vidya" <vidya.srinivas@intel.com> wrote:
>>> Thanks Jani. I will rebase and re-submit and also  to remove drm_panel
>>> interface dependency, I am planning to create panel sequence callbacks
>>> in intel_dsi structure itself. Is this approach okay?
>>
>> I think that's unnecessary overhead. I've come to think we should just
>> do what Hans suggested in his patch [1]. It's easiest, and we don't
>> really benefit anything from the drm_panel interface or function pointer
>> chasing.
>>
>> Hans, do you think you'll have the time or motivation to refresh your
>> series, or should we just let Vidya do this?
>>
>> As an added difficulty, there's Madhav doing the Geminilake enabling at
>> the same time, and these two/three series [2][3][4] are bound to
>> conflict to some extent.
>
> I've my series rebased in a personal repo. As I was planning on resubmitting
> it at some point in the future. I can send out a new version right now if
> you want ...

Vidya, see [1] for Hans' series. I'm inclined to pick (most of) that,
and continue from there. Thoughts?

BR,
Jani.


[1] http://mid.mail-archive.com/20170220140845.1714-1-hdegoede@redhat.com


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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Srinivas, Vidya]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Tuesday, February 21, 2017 12:49 AM
> To: Hans de Goede <hdegoede@redhat.com>; Srinivas, Vidya
> <vidya.srinivas@intel.com>; Paauwe, Bob J <bob.j.paauwe@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link
> 
> On Mon, 20 Feb 2017, Hans de Goede <hdegoede@redhat.com> wrote:
> > Hi,
> >
> > On 20-02-17 12:00, Jani Nikula wrote:
> >> On Mon, 20 Feb 2017, "Srinivas, Vidya" <vidya.srinivas@intel.com>
> wrote:
> >>> Thanks Jani. I will rebase and re-submit and also  to remove
> >>> drm_panel interface dependency, I am planning to create panel
> >>> sequence callbacks in intel_dsi structure itself. Is this approach okay?
> >>
> >> I think that's unnecessary overhead. I've come to think we should
> >> just do what Hans suggested in his patch [1]. It's easiest, and we
> >> don't really benefit anything from the drm_panel interface or
> >> function pointer chasing.
> >>
> >> Hans, do you think you'll have the time or motivation to refresh your
> >> series, or should we just let Vidya do this?
> >>
> >> As an added difficulty, there's Madhav doing the Geminilake enabling
> >> at the same time, and these two/three series [2][3][4] are bound to
> >> conflict to some extent.
> >
> > I've my series rebased in a personal repo. As I was planning on
> > resubmitting it at some point in the future. I can send out a new
> > version right now if you want ...
> 
> Vidya, see [1] for Hans' series. I'm inclined to pick (most of) that, and
> continue from there. Thoughts?
> 
> BR,
> Jani.

We went through Hans' series. 
http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg113101.html
We feel its okay to call the panel sequences directly instead of introducing
new call backs. We can use this approach. But, Hans' series has other changes
as well. For now, can we have only the generic sequence changes merged and
we will rebase our changes on top of that.

Regards
Vidya
> 
> 
> [1] http://mid.mail-archive.com/20170220140845.1714-1-
> hdegoede@redhat.com
> 
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Hans de Goede]

Hi,

On 21-02-17 07:21, Srinivas, Vidya wrote:
>
>
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Tuesday, February 21, 2017 12:49 AM
>> To: Hans de Goede <hdegoede@redhat.com>; Srinivas, Vidya
>> <vidya.srinivas@intel.com>; Paauwe, Bob J <bob.j.paauwe@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org; Chauhan, Madhav
>> <madhav.chauhan@intel.com>
>> Subject: Re: [Intel-gfx] [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link
>>
>> On Mon, 20 Feb 2017, Hans de Goede <hdegoede@redhat.com> wrote:
>>> Hi,
>>>
>>> On 20-02-17 12:00, Jani Nikula wrote:
>>>> On Mon, 20 Feb 2017, "Srinivas, Vidya" <vidya.srinivas@intel.com>
>> wrote:
>>>>> Thanks Jani. I will rebase and re-submit and also  to remove
>>>>> drm_panel interface dependency, I am planning to create panel
>>>>> sequence callbacks in intel_dsi structure itself. Is this approach okay?
>>>>
>>>> I think that's unnecessary overhead. I've come to think we should
>>>> just do what Hans suggested in his patch [1]. It's easiest, and we
>>>> don't really benefit anything from the drm_panel interface or
>>>> function pointer chasing.
>>>>
>>>> Hans, do you think you'll have the time or motivation to refresh your
>>>> series, or should we just let Vidya do this?
>>>>
>>>> As an added difficulty, there's Madhav doing the Geminilake enabling
>>>> at the same time, and these two/three series [2][3][4] are bound to
>>>> conflict to some extent.
>>>
>>> I've my series rebased in a personal repo. As I was planning on
>>> resubmitting it at some point in the future. I can send out a new
>>> version right now if you want ...
>>
>> Vidya, see [1] for Hans' series. I'm inclined to pick (most of) that, and
>> continue from there. Thoughts?
>>
>> BR,
>> Jani.
>
> We went through Hans' series.
> http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg113101.html
> We feel its okay to call the panel sequences directly instead of introducing
> new call backs. We can use this approach. But, Hans' series has other changes
> as well.

Right, changes to actually make the driver follow the spec, instead of calling
a number of sequences at the wrong time, these seem like worthwhile changes
to have and it would be good to land them sooner rather then later so that
most bxt qa will be done with the sequences called at the proper times.

Regards,

Hans


  For now, can we have only the generic sequence changes merged and
> we will rebase our changes on top of that.
>
> Regards
> Vidya
>>
>>
>> [1] http://mid.mail-archive.com/20170220140845.1714-1-
>> hdegoede@redhat.com
>>
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
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