[PATCH v2 0/4] Use build registers for getting numbers of interrupts

[PATCH v2 0/4] Use build registers for getting numbers of interrupts

[Yuriy Kolerov]

A summary:

  * Use build registers for getting numbers of interrupts both for
    core interrupt controller and for IDU interrupt controller.
  * Set a default priority for all core interrupt to prevent
    unexpected switching of banks of registers.
  * Remove option for setting number of interrupts since it does
    not affect a number of interrupts in IRQ domains and breaks
    portability since it is impossible to change size of table of
    interrupts after linkage.

Change in v2:

  * Squash some commits.
  * Do not move a structure for control register of core intc to
    the header since it is used only once.

Yuriy Kolerov (4):
  ARCv2: IRQ: Move structure for build register of core intc to the
    header
  ARCv2: IRQ: Remove option for setting number of interrupts
  ARCv2: IRQ: Use build registers for getting numbers of interrupts
  ARCv2: IRQ: Set a default priority for all core interrupts

 arch/arc/Kconfig               | 11 -----------
 arch/arc/include/asm/arcregs.h | 11 +++++++++++
 arch/arc/include/asm/irq.h     | 32 +++++++++++++++++++++++++++++---
 arch/arc/kernel/entry-arcv2.S  |  3 ++-
 arch/arc/kernel/intc-arcv2.c   | 31 ++++++++++++++++++++-----------
 arch/arc/kernel/mcip.c         | 31 +++++++++++++++++++------------
 include/soc/arc/mcip.h         | 17 +++++++++++++++++
 7 files changed, 98 insertions(+), 38 deletions(-)

-- 
2.7.4

[PATCH v2 0/4] Use build registers for getting numbers of interrupts

[Yuriy Kolerov]

A summary:

  * Use build registers for getting numbers of interrupts both for
    core interrupt controller and for IDU interrupt controller.
  * Set a default priority for all core interrupt to prevent
    unexpected switching of banks of registers.
  * Remove option for setting number of interrupts since it does
    not affect a number of interrupts in IRQ domains and breaks
    portability since it is impossible to change size of table of
    interrupts after linkage.

Change in v2:

  * Squash some commits.
  * Do not move a structure for control register of core intc to
    the header since it is used only once.

Yuriy Kolerov (4):
  ARCv2: IRQ: Move structure for build register of core intc to the
    header
  ARCv2: IRQ: Remove option for setting number of interrupts
  ARCv2: IRQ: Use build registers for getting numbers of interrupts
  ARCv2: IRQ: Set a default priority for all core interrupts

 arch/arc/Kconfig               | 11 -----------
 arch/arc/include/asm/arcregs.h | 11 +++++++++++
 arch/arc/include/asm/irq.h     | 32 +++++++++++++++++++++++++++++---
 arch/arc/kernel/entry-arcv2.S  |  3 ++-
 arch/arc/kernel/intc-arcv2.c   | 31 ++++++++++++++++++++-----------
 arch/arc/kernel/mcip.c         | 31 +++++++++++++++++++------------
 include/soc/arc/mcip.h         | 17 +++++++++++++++++
 7 files changed, 98 insertions(+), 38 deletions(-)

-- 
2.7.4

[PATCH v2 1/4] ARCv2: IRQ: Move structure for build register of core intc to the header

[Yuriy Kolerov]

Also add new macro ARC_REG_STATUS32 for the address of STATUS32
auxiliary register. It is better to use it instead of magic numbers.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
---
 arch/arc/include/asm/arcregs.h | 11 +++++++++++
 arch/arc/kernel/intc-arcv2.c   | 10 ++--------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index f659942..2328244 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -38,6 +38,9 @@
 #define ARC_REG_CLUSTER_BCR	0xcf
 #define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */
 
+/* Common for ARCompact and ARCv2 status register */
+#define ARC_REG_STATUS32	0x0A
+
 /* status32 Bits Positions */
 #define STATUS_AE_BIT		5	/* Exception active */
 #define STATUS_DE_BIT		6	/* PC is in delay slot */
@@ -233,6 +236,14 @@ struct bcr_generic {
 #endif
 };
 
+struct bcr_irq_arcv2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
+#else
+	unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
+#endif
+};
+
 /*
  *******************************************************************
  * Generic structures to hold build configuration used at runtime
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index ecef0fb..9de0665 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -24,13 +24,7 @@ void arc_init_IRQ(void)
 {
 	unsigned int tmp, irq_prio;
 
-	struct irq_build {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-		unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
-#else
-		unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
-#endif
-	} irq_bcr;
+	struct bcr_irq_arcv2 irq_bcr;
 
 	struct aux_irq_ctrl {
 #ifdef CONFIG_CPU_BIG_ENDIAN
@@ -69,7 +63,7 @@ void arc_init_IRQ(void)
 		irq_bcr.firq ? " FIRQ (not used)":"");
 
 	/* setup status32, don't enable intr yet as kernel doesn't want */
-	tmp = read_aux_reg(0xa);
+	tmp = read_aux_reg(ARC_REG_STATUS32);
 	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
 	tmp &= ~STATUS_IE_MASK;
 	asm volatile("kflag %0	\n"::"r"(tmp));
-- 
2.7.4

[PATCH v2 1/4] ARCv2: IRQ: Move structure for build register of core intc to the header

[Yuriy Kolerov]

Also add new macro ARC_REG_STATUS32 for the address of STATUS32
auxiliary register. It is better to use it instead of magic numbers.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
---
 arch/arc/include/asm/arcregs.h | 11 +++++++++++
 arch/arc/kernel/intc-arcv2.c   | 10 ++--------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index f659942..2328244 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -38,6 +38,9 @@
 #define ARC_REG_CLUSTER_BCR	0xcf
 #define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */
 
+/* Common for ARCompact and ARCv2 status register */
+#define ARC_REG_STATUS32	0x0A
+
 /* status32 Bits Positions */
 #define STATUS_AE_BIT		5	/* Exception active */
 #define STATUS_DE_BIT		6	/* PC is in delay slot */
@@ -233,6 +236,14 @@ struct bcr_generic {
 #endif
 };
 
+struct bcr_irq_arcv2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
+#else
+	unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
+#endif
+};
+
 /*
  *******************************************************************
  * Generic structures to hold build configuration used at runtime
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index ecef0fb..9de0665 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -24,13 +24,7 @@ void arc_init_IRQ(void)
 {
 	unsigned int tmp, irq_prio;
 
-	struct irq_build {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-		unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
-#else
-		unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
-#endif
-	} irq_bcr;
+	struct bcr_irq_arcv2 irq_bcr;
 
 	struct aux_irq_ctrl {
 #ifdef CONFIG_CPU_BIG_ENDIAN
@@ -69,7 +63,7 @@ void arc_init_IRQ(void)
 		irq_bcr.firq ? " FIRQ (not used)":"");
 
 	/* setup status32, don't enable intr yet as kernel doesn't want */
-	tmp = read_aux_reg(0xa);
+	tmp = read_aux_reg(ARC_REG_STATUS32);
 	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
 	tmp &= ~STATUS_IE_MASK;
 	asm volatile("kflag %0	\n"::"r"(tmp));
-- 
2.7.4

[PATCH v2 2/4] ARCv2: IRQ: Remove option for setting number of interrupts

[Yuriy Kolerov]

When you set a value of ARC_NUMBER_OF_INTERRUPTS option
it affects only a size of the interrupts table but macros
for number of virtual interrupts (NR_IRQS) and for number
of hardware interrupts (NR_CPU_IRQS) remain unchanged.
Moreover usage of ARC_NUMBER_OF_INTERRUPTS is bad for
portability since it is not possible to change size
of the interrupts table after linkage.

This patch makes these changes in IRQ subsystem:

  * NR_CPU_IRQS defines a maximum number of hardware interrupts.
  * Remove ARC_NUMBER_OF_INTERRUPTS option and create interrupts
    table for all possible hardware interrupts.
  * Increase a maximum number of virtual IRQs to 512. ARCv2 can
    support 240 interrupts in the core interrupts controllers
    and 128 interrupts in IDU. Thus 512 virtual IRQs must be
    enough for most configurations of boards.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
---
 arch/arc/Kconfig              | 11 -----------
 arch/arc/include/asm/irq.h    | 28 +++++++++++++++++++++++++---
 arch/arc/kernel/entry-arcv2.S |  3 ++-
 3 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 283099c..ba15cb8 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -412,17 +412,6 @@ config ARC_HAS_DIV_REM
 	bool "Insn: div, divu, rem, remu"
 	default y
 
-config ARC_NUMBER_OF_INTERRUPTS
-	int "Number of interrupts"
-	range 8 240
-	default 32
-	help
-	  This defines the number of interrupts on the ARCv2HS core.
-	  It affects the size of vector table.
-	  The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
-	  in hardware, it keep things simple for Linux to assume they are always
-	  present.
-
 endif	# ISA_ARCV2
 
 endmenu   # "ARC CPU Configuration"
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index c0fa0d2..d28499a 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -9,18 +9,40 @@
 #ifndef __ASM_ARC_IRQ_H
 #define __ASM_ARC_IRQ_H
 
-#define NR_CPU_IRQS	32  /* number of interrupt lines of ARC770 CPU */
-#define NR_IRQS		128 /* allow some CPU external IRQ handling */
+#ifdef CONFIG_ISA_ARCV2
+
+/*
+ * A maximum number of supported interrupts in the core interrupt controller.
+ * This number is not equal to the maximum interrupt number (256) because
+ * first 16 lines are reserved for exceptions and are not configurable.
+ */
+#define NR_CPU_IRQS	240
+
+/*
+ * ARCv2 can support 240 interrupts in the core interrupts controllers and
+ * 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
+ * configurations of boards.
+ */
+#define NR_IRQS		512
 
 /* Platform Independent IRQs */
-#ifdef CONFIG_ISA_ARCV2
 #define IPI_IRQ		19
 #define SOFTIRQ_IRQ	21
+
+#else
+
+#define NR_CPU_IRQS	32  /* number of interrupt lines of ARC770 CPU */
+#define NR_IRQS		128 /* allow some CPU external IRQ handling */
+
 #endif
 
+#ifndef __ASSEMBLY__
+
 #include <linux/interrupt.h>
 #include <asm-generic/irq.h>
 
 extern void arc_init_IRQ(void);
 
 #endif
+
+#endif
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index 0b6388a..f22101e 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -13,6 +13,7 @@
 #include <asm/errno.h>
 #include <asm/arcregs.h>
 #include <asm/irqflags.h>
+#include <asm/irq.h>
 
 	.cpu HS
 
@@ -52,7 +53,7 @@ VECTOR	handle_interrupt	; unused
 VECTOR	handle_interrupt	; (23) unused
 # End of fixed IRQs
 
-.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8
+.rept NR_CPU_IRQS - 8
 	VECTOR	handle_interrupt
 .endr
 
-- 
2.7.4

[PATCH v2 2/4] ARCv2: IRQ: Remove option for setting number of interrupts

[Yuriy Kolerov]

When you set a value of ARC_NUMBER_OF_INTERRUPTS option
it affects only a size of the interrupts table but macros
for number of virtual interrupts (NR_IRQS) and for number
of hardware interrupts (NR_CPU_IRQS) remain unchanged.
Moreover usage of ARC_NUMBER_OF_INTERRUPTS is bad for
portability since it is not possible to change size
of the interrupts table after linkage.

This patch makes these changes in IRQ subsystem:

  * NR_CPU_IRQS defines a maximum number of hardware interrupts.
  * Remove ARC_NUMBER_OF_INTERRUPTS option and create interrupts
    table for all possible hardware interrupts.
  * Increase a maximum number of virtual IRQs to 512. ARCv2 can
    support 240 interrupts in the core interrupts controllers
    and 128 interrupts in IDU. Thus 512 virtual IRQs must be
    enough for most configurations of boards.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
---
 arch/arc/Kconfig              | 11 -----------
 arch/arc/include/asm/irq.h    | 28 +++++++++++++++++++++++++---
 arch/arc/kernel/entry-arcv2.S |  3 ++-
 3 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 283099c..ba15cb8 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -412,17 +412,6 @@ config ARC_HAS_DIV_REM
 	bool "Insn: div, divu, rem, remu"
 	default y
 
-config ARC_NUMBER_OF_INTERRUPTS
-	int "Number of interrupts"
-	range 8 240
-	default 32
-	help
-	  This defines the number of interrupts on the ARCv2HS core.
-	  It affects the size of vector table.
-	  The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
-	  in hardware, it keep things simple for Linux to assume they are always
-	  present.
-
 endif	# ISA_ARCV2
 
 endmenu   # "ARC CPU Configuration"
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index c0fa0d2..d28499a 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -9,18 +9,40 @@
 #ifndef __ASM_ARC_IRQ_H
 #define __ASM_ARC_IRQ_H
 
-#define NR_CPU_IRQS	32  /* number of interrupt lines of ARC770 CPU */
-#define NR_IRQS		128 /* allow some CPU external IRQ handling */
+#ifdef CONFIG_ISA_ARCV2
+
+/*
+ * A maximum number of supported interrupts in the core interrupt controller.
+ * This number is not equal to the maximum interrupt number (256) because
+ * first 16 lines are reserved for exceptions and are not configurable.
+ */
+#define NR_CPU_IRQS	240
+
+/*
+ * ARCv2 can support 240 interrupts in the core interrupts controllers and
+ * 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
+ * configurations of boards.
+ */
+#define NR_IRQS		512
 
 /* Platform Independent IRQs */
-#ifdef CONFIG_ISA_ARCV2
 #define IPI_IRQ		19
 #define SOFTIRQ_IRQ	21
+
+#else
+
+#define NR_CPU_IRQS	32  /* number of interrupt lines of ARC770 CPU */
+#define NR_IRQS		128 /* allow some CPU external IRQ handling */
+
 #endif
 
+#ifndef __ASSEMBLY__
+
 #include <linux/interrupt.h>
 #include <asm-generic/irq.h>
 
 extern void arc_init_IRQ(void);
 
 #endif
+
+#endif
diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
index 0b6388a..f22101e 100644
--- a/arch/arc/kernel/entry-arcv2.S
+++ b/arch/arc/kernel/entry-arcv2.S
@@ -13,6 +13,7 @@
 #include <asm/errno.h>
 #include <asm/arcregs.h>
 #include <asm/irqflags.h>
+#include <asm/irq.h>
 
 	.cpu HS
 
@@ -52,7 +53,7 @@ VECTOR	handle_interrupt	; unused
 VECTOR	handle_interrupt	; (23) unused
 # End of fixed IRQs
 
-.rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8
+.rept NR_CPU_IRQS - 8
 	VECTOR	handle_interrupt
 .endr
 
-- 
2.7.4

[PATCH v2 3/4] ARCv2: IRQ: Use build registers for getting numbers of interrupts

[Yuriy Kolerov]

This enhancement allows to mask all available common interrupts
in IDU interrupt controller in boot time since the kernel can
discover a number of them from the build register. Also now there
is no need to specify in device tree a list of used core interrupts
by IDU. E.g. before:

    idu_intc: idu-interrupt-controller {
        compatible = "snps,archs-idu-intc";
        interrupt-controller;
        interrupt-parent = <&core_intc>;
        #interrupt-cells = <2>;
        interrupts = <24 25 26 27 28 29 30 31>;
    };

and after:

    idu_intc: idu-interrupt-controller {
        compatible = "snps,archs-idu-intc";
        interrupt-controller;
        interrupt-parent = <&core_intc>;
        #interrupt-cells = <2>;
    };

Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
---
 arch/arc/include/asm/irq.h   |  4 ++++
 arch/arc/kernel/intc-arcv2.c |  9 +++++++--
 arch/arc/kernel/mcip.c       | 31 +++++++++++++++++++------------
 include/soc/arc/mcip.h       | 17 +++++++++++++++++
 4 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index d28499a..1970d78c 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -18,6 +18,9 @@
  */
 #define NR_CPU_IRQS	240
 
+/* A fixed number of exceptions which occupy first interrupt lines */
+#define NR_EXCEPTIONS	16
+
 /*
  * ARCv2 can support 240 interrupts in the core interrupts controllers and
  * 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
@@ -28,6 +31,7 @@
 /* Platform Independent IRQs */
 #define IPI_IRQ		19
 #define SOFTIRQ_IRQ	21
+#define FIRST_EXT_IRQ	24
 
 #else
 
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 9de0665..31246cc 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -109,7 +109,7 @@ static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
 	 * core intc IRQs [16, 23]:
 	 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
 	 */
-	if (hw < 24) {
+	if (hw < FIRST_EXT_IRQ) {
 		/*
 		 * A subsequent request_percpu_irq() fails if percpu_devid is
 		 * not set. That in turns sets NOAUTOEN, meaning each core needs
@@ -134,11 +134,16 @@ static int __init
 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
 {
 	struct irq_domain *root_domain;
+	struct bcr_irq_arcv2 irq_bcr;
+	unsigned int nr_cpu_irqs;
+
+	READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
+	nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
 
 	if (parent)
 		panic("DeviceTree incore intc not a root irq controller\n");
 
-	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL);
+	root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
 	if (!root_domain)
 		panic("root irq domain not avail\n");
 
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index 9988b42..45d45fc 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -157,15 +157,20 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
 	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
 }
 
-static void idu_irq_mask(struct irq_data *data)
+static void idu_irq_mask_raw(irq_hw_number_t hwirq)
 {
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&mcip_lock, flags);
-	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
+	__mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
 	raw_spin_unlock_irqrestore(&mcip_lock, flags);
 }
 
+static void idu_irq_mask(struct irq_data *data)
+{
+	idu_irq_mask_raw(data->hwirq);
+}
+
 static void idu_irq_unmask(struct irq_data *data)
 {
 	unsigned long flags;
@@ -231,14 +236,12 @@ static struct irq_chip idu_irq_chip = {
 
 };
 
-static irq_hw_number_t idu_first_hwirq;
-
 static void idu_cascade_isr(struct irq_desc *desc)
 {
 	struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
 	struct irq_chip *core_chip = irq_desc_get_chip(desc);
 	irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
-	irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
+	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
 
 	chained_irq_enter(core_chip, desc);
 	generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
@@ -284,33 +287,37 @@ static int __init
 idu_of_init(struct device_node *intc, struct device_node *parent)
 {
 	struct irq_domain *domain;
-	/* Read IDU BCR to confirm nr_irqs */
-	int nr_irqs = of_irq_count(intc);
+	int nr_irqs;
 	int i, virq;
 	struct mcip_bcr mp;
+	struct mcip_idu_bcr idu_bcr;
 
 	READ_BCR(ARC_REG_MCIP_BCR, mp);
 
 	if (!mp.idu)
 		panic("IDU not detected, but DeviceTree using it");
 
-	pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
+	READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
+	nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
+
+	pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
 
 	domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
 
 	/* Parent interrupts (core-intc) are already mapped */
 
 	for (i = 0; i < nr_irqs; i++) {
+		/* Mask all common interrupts by default */
+		idu_irq_mask_raw(i);
+
 		/*
 		 * Return parent uplink IRQs (towards core intc) 24,25,.....
 		 * this step has been done before already
 		 * however we need it to get the parent virq and set IDU handler
 		 * as first level isr
 		 */
-		virq = irq_of_parse_and_map(intc, i);
-		if (!i)
-			idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
-
+		virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
+		BUG_ON(!virq);
 		irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
 	}
 
diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h
index 6902c2a..798c01b 100644
--- a/include/soc/arc/mcip.h
+++ b/include/soc/arc/mcip.h
@@ -14,6 +14,7 @@
 #include <soc/arc/aux.h>
 
 #define ARC_REG_MCIP_BCR	0x0d0
+#define ARC_REG_MCIP_IDU_BCR	0x0D5
 #define ARC_REG_MCIP_CMD	0x600
 #define ARC_REG_MCIP_WDATA	0x601
 #define ARC_REG_MCIP_READBACK	0x602
@@ -69,6 +70,22 @@ struct mcip_bcr {
 #endif
 };
 
+struct mcip_idu_bcr {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	unsigned int pad:21, cirqnum:3, ver:8;
+#else
+	unsigned int ver:8, cirqnum:3, pad:21;
+#endif
+};
+
+
+/*
+ * Build register for IDU contains not an actual number of supported common
+ * interrupts but an exponent of 2 which must be multiplied by 4 to
+ * get a number of supported common interrupts.
+ */
+#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
+
 /*
  * MCIP programming model
  *
-- 
2.7.4

[PATCH v2 3/4] ARCv2: IRQ: Use build registers for getting numbers of interrupts

[Yuriy Kolerov]

This enhancement allows to mask all available common interrupts
in IDU interrupt controller in boot time since the kernel can
discover a number of them from the build register. Also now there
is no need to specify in device tree a list of used core interrupts
by IDU. E.g. before:

    idu_intc: idu-interrupt-controller {
        compatible = "snps,archs-idu-intc";
        interrupt-controller;
        interrupt-parent = <&core_intc>;
        #interrupt-cells = <2>;
        interrupts = <24 25 26 27 28 29 30 31>;
    };

and after:

    idu_intc: idu-interrupt-controller {
        compatible = "snps,archs-idu-intc";
        interrupt-controller;
        interrupt-parent = <&core_intc>;
        #interrupt-cells = <2>;
    };

Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
---
 arch/arc/include/asm/irq.h   |  4 ++++
 arch/arc/kernel/intc-arcv2.c |  9 +++++++--
 arch/arc/kernel/mcip.c       | 31 +++++++++++++++++++------------
 include/soc/arc/mcip.h       | 17 +++++++++++++++++
 4 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index d28499a..1970d78c 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -18,6 +18,9 @@
  */
 #define NR_CPU_IRQS	240
 
+/* A fixed number of exceptions which occupy first interrupt lines */
+#define NR_EXCEPTIONS	16
+
 /*
  * ARCv2 can support 240 interrupts in the core interrupts controllers and
  * 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
@@ -28,6 +31,7 @@
 /* Platform Independent IRQs */
 #define IPI_IRQ		19
 #define SOFTIRQ_IRQ	21
+#define FIRST_EXT_IRQ	24
 
 #else
 
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 9de0665..31246cc 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -109,7 +109,7 @@ static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
 	 * core intc IRQs [16, 23]:
 	 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
 	 */
-	if (hw < 24) {
+	if (hw < FIRST_EXT_IRQ) {
 		/*
 		 * A subsequent request_percpu_irq() fails if percpu_devid is
 		 * not set. That in turns sets NOAUTOEN, meaning each core needs
@@ -134,11 +134,16 @@ static int __init
 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
 {
 	struct irq_domain *root_domain;
+	struct bcr_irq_arcv2 irq_bcr;
+	unsigned int nr_cpu_irqs;
+
+	READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
+	nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
 
 	if (parent)
 		panic("DeviceTree incore intc not a root irq controller\n");
 
-	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL);
+	root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
 	if (!root_domain)
 		panic("root irq domain not avail\n");
 
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index 9988b42..45d45fc 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -157,15 +157,20 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
 	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
 }
 
-static void idu_irq_mask(struct irq_data *data)
+static void idu_irq_mask_raw(irq_hw_number_t hwirq)
 {
 	unsigned long flags;
 
 	raw_spin_lock_irqsave(&mcip_lock, flags);
-	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
+	__mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
 	raw_spin_unlock_irqrestore(&mcip_lock, flags);
 }
 
+static void idu_irq_mask(struct irq_data *data)
+{
+	idu_irq_mask_raw(data->hwirq);
+}
+
 static void idu_irq_unmask(struct irq_data *data)
 {
 	unsigned long flags;
@@ -231,14 +236,12 @@ static struct irq_chip idu_irq_chip = {
 
 };
 
-static irq_hw_number_t idu_first_hwirq;
-
 static void idu_cascade_isr(struct irq_desc *desc)
 {
 	struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
 	struct irq_chip *core_chip = irq_desc_get_chip(desc);
 	irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
-	irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
+	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
 
 	chained_irq_enter(core_chip, desc);
 	generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
@@ -284,33 +287,37 @@ static int __init
 idu_of_init(struct device_node *intc, struct device_node *parent)
 {
 	struct irq_domain *domain;
-	/* Read IDU BCR to confirm nr_irqs */
-	int nr_irqs = of_irq_count(intc);
+	int nr_irqs;
 	int i, virq;
 	struct mcip_bcr mp;
+	struct mcip_idu_bcr idu_bcr;
 
 	READ_BCR(ARC_REG_MCIP_BCR, mp);
 
 	if (!mp.idu)
 		panic("IDU not detected, but DeviceTree using it");
 
-	pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
+	READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
+	nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
+
+	pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
 
 	domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
 
 	/* Parent interrupts (core-intc) are already mapped */
 
 	for (i = 0; i < nr_irqs; i++) {
+		/* Mask all common interrupts by default */
+		idu_irq_mask_raw(i);
+
 		/*
 		 * Return parent uplink IRQs (towards core intc) 24,25,.....
 		 * this step has been done before already
 		 * however we need it to get the parent virq and set IDU handler
 		 * as first level isr
 		 */
-		virq = irq_of_parse_and_map(intc, i);
-		if (!i)
-			idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
-
+		virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
+		BUG_ON(!virq);
 		irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
 	}
 
diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h
index 6902c2a..798c01b 100644
--- a/include/soc/arc/mcip.h
+++ b/include/soc/arc/mcip.h
@@ -14,6 +14,7 @@
 #include <soc/arc/aux.h>
 
 #define ARC_REG_MCIP_BCR	0x0d0
+#define ARC_REG_MCIP_IDU_BCR	0x0D5
 #define ARC_REG_MCIP_CMD	0x600
 #define ARC_REG_MCIP_WDATA	0x601
 #define ARC_REG_MCIP_READBACK	0x602
@@ -69,6 +70,22 @@ struct mcip_bcr {
 #endif
 };
 
+struct mcip_idu_bcr {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	unsigned int pad:21, cirqnum:3, ver:8;
+#else
+	unsigned int ver:8, cirqnum:3, pad:21;
+#endif
+};
+
+
+/*
+ * Build register for IDU contains not an actual number of supported common
+ * interrupts but an exponent of 2 which must be multiplied by 4 to
+ * get a number of supported common interrupts.
+ */
+#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
+
 /*
  * MCIP programming model
  *
-- 
2.7.4

[PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts

[Yuriy Kolerov]

After reset all interrupts in the core interrupt controller has
the highest priority P0. If the platform supports Fast IRQs and
has more than 1 banks of registers then CPU automatically switch
banks of registers when P0 interrupt comes.

The problem is that the kernel expects that by default switching
of banks is not used by all interrupts. It is necessary to set a
default nonzero priority for all available interrupts to avoid
undefined behaviour.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
---
 arch/arc/kernel/intc-arcv2.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 31246cc..d4fa4a5 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -22,7 +22,7 @@
  */
 void arc_init_IRQ(void)
 {
-	unsigned int tmp, irq_prio;
+	unsigned int tmp, irq_prio, i;
 
 	struct bcr_irq_arcv2 irq_bcr;
 
@@ -62,6 +62,16 @@ void arc_init_IRQ(void)
 		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
 		irq_bcr.firq ? " FIRQ (not used)":"");
 
+	/*
+	 * Set a default priority for all available interrupts to prevent
+	 * switching of register banks if Fast IRQ and multiple register banks
+	 * are supported by CPU.
+	 */
+	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
+		write_aux_reg(AUX_IRQ_SELECT, i);
+		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
+	}
+
 	/* setup status32, don't enable intr yet as kernel doesn't want */
 	tmp = read_aux_reg(ARC_REG_STATUS32);
 	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
-- 
2.7.4

[PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts

[Yuriy Kolerov]

After reset all interrupts in the core interrupt controller has
the highest priority P0. If the platform supports Fast IRQs and
has more than 1 banks of registers then CPU automatically switch
banks of registers when P0 interrupt comes.

The problem is that the kernel expects that by default switching
of banks is not used by all interrupts. It is necessary to set a
default nonzero priority for all available interrupts to avoid
undefined behaviour.

Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
---
 arch/arc/kernel/intc-arcv2.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 31246cc..d4fa4a5 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -22,7 +22,7 @@
  */
 void arc_init_IRQ(void)
 {
-	unsigned int tmp, irq_prio;
+	unsigned int tmp, irq_prio, i;
 
 	struct bcr_irq_arcv2 irq_bcr;
 
@@ -62,6 +62,16 @@ void arc_init_IRQ(void)
 		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
 		irq_bcr.firq ? " FIRQ (not used)":"");
 
+	/*
+	 * Set a default priority for all available interrupts to prevent
+	 * switching of register banks if Fast IRQ and multiple register banks
+	 * are supported by CPU.
+	 */
+	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
+		write_aux_reg(AUX_IRQ_SELECT, i);
+		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
+	}
+
 	/* setup status32, don't enable intr yet as kernel doesn't want */
 	tmp = read_aux_reg(ARC_REG_STATUS32);
 	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
-- 
2.7.4

Re: [PATCH v2 1/4] ARCv2: IRQ: Move structure for build register of core intc to the header

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> Also add new macro ARC_REG_STATUS32 for the address of STATUS32
> auxiliary register. It is better to use it instead of magic numbers.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>

Applied to for-next.

Thx,
-Vineet

[PATCH v2 1/4] ARCv2: IRQ: Move structure for build register of core intc to the header

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> Also add new macro ARC_REG_STATUS32 for the address of STATUS32
> auxiliary register. It is better to use it instead of magic numbers.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>

Applied to for-next.

Thx,
-Vineet

Re: [PATCH v2 2/4] ARCv2: IRQ: Remove option for setting number of interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> When you set a value of ARC_NUMBER_OF_INTERRUPTS option
> it affects only a size of the interrupts table but macros
> for number of virtual interrupts (NR_IRQS) and for number
> of hardware interrupts (NR_CPU_IRQS) remain unchanged.
> Moreover usage of ARC_NUMBER_OF_INTERRUPTS is bad for
> portability since it is not possible to change size
> of the interrupts table after linkage.
> 
> This patch makes these changes in IRQ subsystem:
> 
>   * NR_CPU_IRQS defines a maximum number of hardware interrupts.
>   * Remove ARC_NUMBER_OF_INTERRUPTS option and create interrupts
>     table for all possible hardware interrupts.
>   * Increase a maximum number of virtual IRQs to 512. ARCv2 can
>     support 240 interrupts in the core interrupts controllers
>     and 128 interrupts in IDU. Thus 512 virtual IRQs must be
>     enough for most configurations of boards.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>

Applied to for-next.

Thx,
-Vineet

[PATCH v2 2/4] ARCv2: IRQ: Remove option for setting number of interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> When you set a value of ARC_NUMBER_OF_INTERRUPTS option
> it affects only a size of the interrupts table but macros
> for number of virtual interrupts (NR_IRQS) and for number
> of hardware interrupts (NR_CPU_IRQS) remain unchanged.
> Moreover usage of ARC_NUMBER_OF_INTERRUPTS is bad for
> portability since it is not possible to change size
> of the interrupts table after linkage.
> 
> This patch makes these changes in IRQ subsystem:
> 
>   * NR_CPU_IRQS defines a maximum number of hardware interrupts.
>   * Remove ARC_NUMBER_OF_INTERRUPTS option and create interrupts
>     table for all possible hardware interrupts.
>   * Increase a maximum number of virtual IRQs to 512. ARCv2 can
>     support 240 interrupts in the core interrupts controllers
>     and 128 interrupts in IDU. Thus 512 virtual IRQs must be
>     enough for most configurations of boards.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>

Applied to for-next.

Thx,
-Vineet

Re: [PATCH v2 3/4] ARCv2: IRQ: Use build registers for getting numbers of interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> This enhancement allows to mask all available common interrupts
> in IDU interrupt controller in boot time since the kernel can
> discover a number of them from the build register. Also now there
> is no need to specify in device tree a list of used core interrupts
> by IDU. E.g. before:
> 
>     idu_intc: idu-interrupt-controller {
>         compatible = "snps,archs-idu-intc";
>         interrupt-controller;
>         interrupt-parent = <&core_intc>;
>         #interrupt-cells = <2>;
>         interrupts = <24 25 26 27 28 29 30 31>;
>     };
> 
> and after:
> 
>     idu_intc: idu-interrupt-controller {
>         compatible = "snps,archs-idu-intc";
>         interrupt-controller;
>         interrupt-parent = <&core_intc>;
>         #interrupt-cells = <2>;
>     };
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
> ---
>  arch/arc/include/asm/irq.h   |  4 ++++
>  arch/arc/kernel/intc-arcv2.c |  9 +++++++--
>  arch/arc/kernel/mcip.c       | 31 +++++++++++++++++++------------
>  include/soc/arc/mcip.h       | 17 +++++++++++++++++
>  4 files changed, 47 insertions(+), 14 deletions(-)

We need to update existing DTs and
Documentation/devicetree/bindings/arc/archs-idu-intc.txt too - addon patch is fine !

> 
> diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
> index d28499a..1970d78c 100644
> --- a/arch/arc/include/asm/irq.h
> +++ b/arch/arc/include/asm/irq.h
> @@ -18,6 +18,9 @@
>   */
>  #define NR_CPU_IRQS	240
>  
> +/* A fixed number of exceptions which occupy first interrupt lines */
> +#define NR_EXCEPTIONS	16
> +
>  /*
>   * ARCv2 can support 240 interrupts in the core interrupts controllers and
>   * 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
> @@ -28,6 +31,7 @@
>  /* Platform Independent IRQs */
>  #define IPI_IRQ		19
>  #define SOFTIRQ_IRQ	21
> +#define FIRST_EXT_IRQ	24
>  
>  #else
>  
> diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
> index 9de0665..31246cc 100644
> --- a/arch/arc/kernel/intc-arcv2.c
> +++ b/arch/arc/kernel/intc-arcv2.c
> @@ -109,7 +109,7 @@ static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
>  	 * core intc IRQs [16, 23]:
>  	 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
>  	 */
> -	if (hw < 24) {
> +	if (hw < FIRST_EXT_IRQ) {
>  		/*
>  		 * A subsequent request_percpu_irq() fails if percpu_devid is
>  		 * not set. That in turns sets NOAUTOEN, meaning each core needs
> @@ -134,11 +134,16 @@ static int __init
>  init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
>  {
>  	struct irq_domain *root_domain;
> +	struct bcr_irq_arcv2 irq_bcr;
> +	unsigned int nr_cpu_irqs;
> +
> +	READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
> +	nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
>  
>  	if (parent)
>  		panic("DeviceTree incore intc not a root irq controller\n");
>  
> -	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL);
> +	root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
>  	if (!root_domain)
>  		panic("root irq domain not avail\n");
>  
> diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
> index 9988b42..45d45fc 100644
> --- a/arch/arc/kernel/mcip.c
> +++ b/arch/arc/kernel/mcip.c
> @@ -157,15 +157,20 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
>  	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
>  }
>  
> -static void idu_irq_mask(struct irq_data *data)
> +static void idu_irq_mask_raw(irq_hw_number_t hwirq)
>  {
>  	unsigned long flags;
>  
>  	raw_spin_lock_irqsave(&mcip_lock, flags);
> -	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
> +	__mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
>  	raw_spin_unlock_irqrestore(&mcip_lock, flags);
>  }
>  
> +static void idu_irq_mask(struct irq_data *data)
> +{
> +	idu_irq_mask_raw(data->hwirq);
> +}
> +
>  static void idu_irq_unmask(struct irq_data *data)
>  {
>  	unsigned long flags;
> @@ -231,14 +236,12 @@ static struct irq_chip idu_irq_chip = {
>  
>  };
>  
> -static irq_hw_number_t idu_first_hwirq;
> -
>  static void idu_cascade_isr(struct irq_desc *desc)
>  {
>  	struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
>  	struct irq_chip *core_chip = irq_desc_get_chip(desc);
>  	irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
> -	irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
> +	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
>  
>  	chained_irq_enter(core_chip, desc);
>  	generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
> @@ -284,33 +287,37 @@ static int __init
>  idu_of_init(struct device_node *intc, struct device_node *parent)
>  {
>  	struct irq_domain *domain;
> -	/* Read IDU BCR to confirm nr_irqs */
> -	int nr_irqs = of_irq_count(intc);
> +	int nr_irqs;
>  	int i, virq;
>  	struct mcip_bcr mp;
> +	struct mcip_idu_bcr idu_bcr;
>  
>  	READ_BCR(ARC_REG_MCIP_BCR, mp);
>  
>  	if (!mp.idu)
>  		panic("IDU not detected, but DeviceTree using it");
>  
> -	pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
> +	READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
> +	nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
> +
> +	pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
>  
>  	domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
>  
>  	/* Parent interrupts (core-intc) are already mapped */
>  
>  	for (i = 0; i < nr_irqs; i++) {
> +		/* Mask all common interrupts by default */
> +		idu_irq_mask_raw(i);
> +

This deserves to be seperate patch - this is a semantical change and needs to
called out seperately - in case it we want to quickly revert it etc.

>  		/*
>  		 * Return parent uplink IRQs (towards core intc) 24,25,.....
>  		 * this step has been done before already
>  		 * however we need it to get the parent virq and set IDU handler
>  		 * as first level isr
>  		 */
> -		virq = irq_of_parse_and_map(intc, i);
> -		if (!i)
> -			idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
> -
> +		virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
> +		BUG_ON(!virq);
>  		irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
>  	}
>  
> diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h
> index 6902c2a..798c01b 100644
> --- a/include/soc/arc/mcip.h
> +++ b/include/soc/arc/mcip.h
> @@ -14,6 +14,7 @@
>  #include <soc/arc/aux.h>
>  
>  #define ARC_REG_MCIP_BCR	0x0d0
> +#define ARC_REG_MCIP_IDU_BCR	0x0D5
>  #define ARC_REG_MCIP_CMD	0x600
>  #define ARC_REG_MCIP_WDATA	0x601
>  #define ARC_REG_MCIP_READBACK	0x602
> @@ -69,6 +70,22 @@ struct mcip_bcr {
>  #endif
>  };
>  
> +struct mcip_idu_bcr {
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +	unsigned int pad:21, cirqnum:3, ver:8;
> +#else
> +	unsigned int ver:8, cirqnum:3, pad:21;
> +#endif
> +};
> +
> +
> +/*
> + * Build register for IDU contains not an actual number of supported common
> + * interrupts but an exponent of 2 which must be multiplied by 4 to
> + * get a number of supported common interrupts.
> + */
> +#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
> +
>  /*
>   * MCIP programming model
>   *
> 

[PATCH v2 3/4] ARCv2: IRQ: Use build registers for getting numbers of interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> This enhancement allows to mask all available common interrupts
> in IDU interrupt controller in boot time since the kernel can
> discover a number of them from the build register. Also now there
> is no need to specify in device tree a list of used core interrupts
> by IDU. E.g. before:
> 
>     idu_intc: idu-interrupt-controller {
>         compatible = "snps,archs-idu-intc";
>         interrupt-controller;
>         interrupt-parent = <&core_intc>;
>         #interrupt-cells = <2>;
>         interrupts = <24 25 26 27 28 29 30 31>;
>     };
> 
> and after:
> 
>     idu_intc: idu-interrupt-controller {
>         compatible = "snps,archs-idu-intc";
>         interrupt-controller;
>         interrupt-parent = <&core_intc>;
>         #interrupt-cells = <2>;
>     };
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
> ---
>  arch/arc/include/asm/irq.h   |  4 ++++
>  arch/arc/kernel/intc-arcv2.c |  9 +++++++--
>  arch/arc/kernel/mcip.c       | 31 +++++++++++++++++++------------
>  include/soc/arc/mcip.h       | 17 +++++++++++++++++
>  4 files changed, 47 insertions(+), 14 deletions(-)

We need to update existing DTs and
Documentation/devicetree/bindings/arc/archs-idu-intc.txt too - addon patch is fine !

> 
> diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
> index d28499a..1970d78c 100644
> --- a/arch/arc/include/asm/irq.h
> +++ b/arch/arc/include/asm/irq.h
> @@ -18,6 +18,9 @@
>   */
>  #define NR_CPU_IRQS	240
>  
> +/* A fixed number of exceptions which occupy first interrupt lines */
> +#define NR_EXCEPTIONS	16
> +
>  /*
>   * ARCv2 can support 240 interrupts in the core interrupts controllers and
>   * 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
> @@ -28,6 +31,7 @@
>  /* Platform Independent IRQs */
>  #define IPI_IRQ		19
>  #define SOFTIRQ_IRQ	21
> +#define FIRST_EXT_IRQ	24
>  
>  #else
>  
> diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
> index 9de0665..31246cc 100644
> --- a/arch/arc/kernel/intc-arcv2.c
> +++ b/arch/arc/kernel/intc-arcv2.c
> @@ -109,7 +109,7 @@ static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
>  	 * core intc IRQs [16, 23]:
>  	 * Statically assigned always private-per-core (Timers, WDT, IPI, PCT)
>  	 */
> -	if (hw < 24) {
> +	if (hw < FIRST_EXT_IRQ) {
>  		/*
>  		 * A subsequent request_percpu_irq() fails if percpu_devid is
>  		 * not set. That in turns sets NOAUTOEN, meaning each core needs
> @@ -134,11 +134,16 @@ static int __init
>  init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
>  {
>  	struct irq_domain *root_domain;
> +	struct bcr_irq_arcv2 irq_bcr;
> +	unsigned int nr_cpu_irqs;
> +
> +	READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
> +	nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS;
>  
>  	if (parent)
>  		panic("DeviceTree incore intc not a root irq controller\n");
>  
> -	root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS, &arcv2_irq_ops, NULL);
> +	root_domain = irq_domain_add_linear(intc, nr_cpu_irqs, &arcv2_irq_ops, NULL);
>  	if (!root_domain)
>  		panic("root irq domain not avail\n");
>  
> diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
> index 9988b42..45d45fc 100644
> --- a/arch/arc/kernel/mcip.c
> +++ b/arch/arc/kernel/mcip.c
> @@ -157,15 +157,20 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
>  	__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
>  }
>  
> -static void idu_irq_mask(struct irq_data *data)
> +static void idu_irq_mask_raw(irq_hw_number_t hwirq)
>  {
>  	unsigned long flags;
>  
>  	raw_spin_lock_irqsave(&mcip_lock, flags);
> -	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
> +	__mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
>  	raw_spin_unlock_irqrestore(&mcip_lock, flags);
>  }
>  
> +static void idu_irq_mask(struct irq_data *data)
> +{
> +	idu_irq_mask_raw(data->hwirq);
> +}
> +
>  static void idu_irq_unmask(struct irq_data *data)
>  {
>  	unsigned long flags;
> @@ -231,14 +236,12 @@ static struct irq_chip idu_irq_chip = {
>  
>  };
>  
> -static irq_hw_number_t idu_first_hwirq;
> -
>  static void idu_cascade_isr(struct irq_desc *desc)
>  {
>  	struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
>  	struct irq_chip *core_chip = irq_desc_get_chip(desc);
>  	irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
> -	irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
> +	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
>  
>  	chained_irq_enter(core_chip, desc);
>  	generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
> @@ -284,33 +287,37 @@ static int __init
>  idu_of_init(struct device_node *intc, struct device_node *parent)
>  {
>  	struct irq_domain *domain;
> -	/* Read IDU BCR to confirm nr_irqs */
> -	int nr_irqs = of_irq_count(intc);
> +	int nr_irqs;
>  	int i, virq;
>  	struct mcip_bcr mp;
> +	struct mcip_idu_bcr idu_bcr;
>  
>  	READ_BCR(ARC_REG_MCIP_BCR, mp);
>  
>  	if (!mp.idu)
>  		panic("IDU not detected, but DeviceTree using it");
>  
> -	pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
> +	READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
> +	nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
> +
> +	pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
>  
>  	domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
>  
>  	/* Parent interrupts (core-intc) are already mapped */
>  
>  	for (i = 0; i < nr_irqs; i++) {
> +		/* Mask all common interrupts by default */
> +		idu_irq_mask_raw(i);
> +

This deserves to be seperate patch - this is a semantical change and needs to
called out seperately - in case it we want to quickly revert it etc.

>  		/*
>  		 * Return parent uplink IRQs (towards core intc) 24,25,.....
>  		 * this step has been done before already
>  		 * however we need it to get the parent virq and set IDU handler
>  		 * as first level isr
>  		 */
> -		virq = irq_of_parse_and_map(intc, i);
> -		if (!i)
> -			idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
> -
> +		virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
> +		BUG_ON(!virq);
>  		irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
>  	}
>  
> diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h
> index 6902c2a..798c01b 100644
> --- a/include/soc/arc/mcip.h
> +++ b/include/soc/arc/mcip.h
> @@ -14,6 +14,7 @@
>  #include <soc/arc/aux.h>
>  
>  #define ARC_REG_MCIP_BCR	0x0d0
> +#define ARC_REG_MCIP_IDU_BCR	0x0D5
>  #define ARC_REG_MCIP_CMD	0x600
>  #define ARC_REG_MCIP_WDATA	0x601
>  #define ARC_REG_MCIP_READBACK	0x602
> @@ -69,6 +70,22 @@ struct mcip_bcr {
>  #endif
>  };
>  
> +struct mcip_idu_bcr {
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +	unsigned int pad:21, cirqnum:3, ver:8;
> +#else
> +	unsigned int ver:8, cirqnum:3, pad:21;
> +#endif
> +};
> +
> +
> +/*
> + * Build register for IDU contains not an actual number of supported common
> + * interrupts but an exponent of 2 which must be multiplied by 4 to
> + * get a number of supported common interrupts.
> + */
> +#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
> +
>  /*
>   * MCIP programming model
>   *
> 

Re: [PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> After reset all interrupts in the core interrupt controller has
> the highest priority P0. If the platform supports Fast IRQs and
> has more than 1 banks of registers then CPU automatically switch
> banks of registers when P0 interrupt comes.
> 
> The problem is that the kernel expects that by default switching
> of banks is not used by all interrupts. It is necessary to set a
> default nonzero priority for all available interrupts to avoid
> undefined behaviour.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
> ---
>  arch/arc/kernel/intc-arcv2.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
> index 31246cc..d4fa4a5 100644
> --- a/arch/arc/kernel/intc-arcv2.c
> +++ b/arch/arc/kernel/intc-arcv2.c
> @@ -22,7 +22,7 @@
>   */
>  void arc_init_IRQ(void)
>  {
> -	unsigned int tmp, irq_prio;
> +	unsigned int tmp, irq_prio, i;
>  
>  	struct bcr_irq_arcv2 irq_bcr;
>  
> @@ -62,6 +62,16 @@ void arc_init_IRQ(void)
>  		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
>  		irq_bcr.firq ? " FIRQ (not used)":"");
>  
> +	/*
> +	 * Set a default priority for all available interrupts to prevent
> +	 * switching of register banks if Fast IRQ and multiple register banks
> +	 * are supported by CPU.
> +	 */
> +	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
> +		write_aux_reg(AUX_IRQ_SELECT, i);
> +		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
> +	}
> +

This itself is fine. However going forward can we move to the genirq
irq_cpu_online() etc instead of doing this in our platform per cpu hook ?

https://www.linux-mips.org/archives/linux-mips/2011-03/msg00115.html


>  	/* setup status32, don't enable intr yet as kernel doesn't want */
>  	tmp = read_aux_reg(ARC_REG_STATUS32);
>  	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
> 

[PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> After reset all interrupts in the core interrupt controller has
> the highest priority P0. If the platform supports Fast IRQs and
> has more than 1 banks of registers then CPU automatically switch
> banks of registers when P0 interrupt comes.
> 
> The problem is that the kernel expects that by default switching
> of banks is not used by all interrupts. It is necessary to set a
> default nonzero priority for all available interrupts to avoid
> undefined behaviour.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
> ---
>  arch/arc/kernel/intc-arcv2.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
> index 31246cc..d4fa4a5 100644
> --- a/arch/arc/kernel/intc-arcv2.c
> +++ b/arch/arc/kernel/intc-arcv2.c
> @@ -22,7 +22,7 @@
>   */
>  void arc_init_IRQ(void)
>  {
> -	unsigned int tmp, irq_prio;
> +	unsigned int tmp, irq_prio, i;
>  
>  	struct bcr_irq_arcv2 irq_bcr;
>  
> @@ -62,6 +62,16 @@ void arc_init_IRQ(void)
>  		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
>  		irq_bcr.firq ? " FIRQ (not used)":"");
>  
> +	/*
> +	 * Set a default priority for all available interrupts to prevent
> +	 * switching of register banks if Fast IRQ and multiple register banks
> +	 * are supported by CPU.
> +	 */
> +	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
> +		write_aux_reg(AUX_IRQ_SELECT, i);
> +		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
> +	}
> +

This itself is fine. However going forward can we move to the genirq
irq_cpu_online() etc instead of doing this in our platform per cpu hook ?

https://www.linux-mips.org/archives/linux-mips/2011-03/msg00115.html


>  	/* setup status32, don't enable intr yet as kernel doesn't want */
>  	tmp = read_aux_reg(ARC_REG_STATUS32);
>  	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
> 

Re: [PATCH v2 1/4] ARCv2: IRQ: Move structure for build register of core intc to the header

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> Also add new macro ARC_REG_STATUS32 for the address of STATUS32
> auxiliary register. It is better to use it instead of magic numbers.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
> ---
>  arch/arc/include/asm/arcregs.h | 11 +++++++++++
>  arch/arc/kernel/intc-arcv2.c   | 10 ++--------
>  2 files changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
> index f659942..2328244 100644
> --- a/arch/arc/include/asm/arcregs.h
> +++ b/arch/arc/include/asm/arcregs.h
> @@ -38,6 +38,9 @@
>  #define ARC_REG_CLUSTER_BCR	0xcf
>  #define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */
>  
> +/* Common for ARCompact and ARCv2 status register */
> +#define ARC_REG_STATUS32	0x0A
> +
>  /* status32 Bits Positions */
>  #define STATUS_AE_BIT		5	/* Exception active */
>  #define STATUS_DE_BIT		6	/* PC is in delay slot */
> @@ -233,6 +236,14 @@ struct bcr_generic {
>  #endif
>  };
>  
> +struct bcr_irq_arcv2 {
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +	unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
> +#else
> +	unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
> +#endif
> +};

Looks like I was too eager to apply.
This doesn't need to be exported to outside intc code. I will fix it up locally !

> +
>  /*
>   *******************************************************************
>   * Generic structures to hold build configuration used at runtime
> diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
> index ecef0fb..9de0665 100644
> --- a/arch/arc/kernel/intc-arcv2.c
> +++ b/arch/arc/kernel/intc-arcv2.c
> @@ -24,13 +24,7 @@ void arc_init_IRQ(void)
>  {
>  	unsigned int tmp, irq_prio;
>  
> -	struct irq_build {
> -#ifdef CONFIG_CPU_BIG_ENDIAN
> -		unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
> -#else
> -		unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
> -#endif
> -	} irq_bcr;
> +	struct bcr_irq_arcv2 irq_bcr;
>  
>  	struct aux_irq_ctrl {
>  #ifdef CONFIG_CPU_BIG_ENDIAN
> @@ -69,7 +63,7 @@ void arc_init_IRQ(void)
>  		irq_bcr.firq ? " FIRQ (not used)":"");
>  
>  	/* setup status32, don't enable intr yet as kernel doesn't want */
> -	tmp = read_aux_reg(0xa);
> +	tmp = read_aux_reg(ARC_REG_STATUS32);
>  	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
>  	tmp &= ~STATUS_IE_MASK;
>  	asm volatile("kflag %0	\n"::"r"(tmp));
> 

[PATCH v2 1/4] ARCv2: IRQ: Move structure for build register of core intc to the header

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> Also add new macro ARC_REG_STATUS32 for the address of STATUS32
> auxiliary register. It is better to use it instead of magic numbers.
> 
> Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
> ---
>  arch/arc/include/asm/arcregs.h | 11 +++++++++++
>  arch/arc/kernel/intc-arcv2.c   | 10 ++--------
>  2 files changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
> index f659942..2328244 100644
> --- a/arch/arc/include/asm/arcregs.h
> +++ b/arch/arc/include/asm/arcregs.h
> @@ -38,6 +38,9 @@
>  #define ARC_REG_CLUSTER_BCR	0xcf
>  #define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */
>  
> +/* Common for ARCompact and ARCv2 status register */
> +#define ARC_REG_STATUS32	0x0A
> +
>  /* status32 Bits Positions */
>  #define STATUS_AE_BIT		5	/* Exception active */
>  #define STATUS_DE_BIT		6	/* PC is in delay slot */
> @@ -233,6 +236,14 @@ struct bcr_generic {
>  #endif
>  };
>  
> +struct bcr_irq_arcv2 {
> +#ifdef CONFIG_CPU_BIG_ENDIAN
> +	unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
> +#else
> +	unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
> +#endif
> +};

Looks like I was too eager to apply.
This doesn't need to be exported to outside intc code. I will fix it up locally !

> +
>  /*
>   *******************************************************************
>   * Generic structures to hold build configuration used at runtime
> diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
> index ecef0fb..9de0665 100644
> --- a/arch/arc/kernel/intc-arcv2.c
> +++ b/arch/arc/kernel/intc-arcv2.c
> @@ -24,13 +24,7 @@ void arc_init_IRQ(void)
>  {
>  	unsigned int tmp, irq_prio;
>  
> -	struct irq_build {
> -#ifdef CONFIG_CPU_BIG_ENDIAN
> -		unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
> -#else
> -		unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
> -#endif
> -	} irq_bcr;
> +	struct bcr_irq_arcv2 irq_bcr;
>  
>  	struct aux_irq_ctrl {
>  #ifdef CONFIG_CPU_BIG_ENDIAN
> @@ -69,7 +63,7 @@ void arc_init_IRQ(void)
>  		irq_bcr.firq ? " FIRQ (not used)":"");
>  
>  	/* setup status32, don't enable intr yet as kernel doesn't want */
> -	tmp = read_aux_reg(0xa);
> +	tmp = read_aux_reg(ARC_REG_STATUS32);
>  	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
>  	tmp &= ~STATUS_IE_MASK;
>  	asm volatile("kflag %0	\n"::"r"(tmp));
> 

RE: [PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts

[Yuriy Kolerov]

Hi Vineet,

> -----Original Message-----
> From: Vineet Gupta [mailto:vgupta@synopsys.com]
> Sent: Tuesday, January 31, 2017 8:54 PM
> To: Yuriy Kolerov <yuriy.kolerov@synopsys.com>; linux-snps-
> arc@lists.infradead.org
> Cc: marc.zyngier@arm.com; Alexey.Brodkin@synopsys.com; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core
> interrupts
> 
> On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> > After reset all interrupts in the core interrupt controller has the
> > highest priority P0. If the platform supports Fast IRQs and has more
> > than 1 banks of registers then CPU automatically switch banks of
> > registers when P0 interrupt comes.
> >
> > The problem is that the kernel expects that by default switching of
> > banks is not used by all interrupts. It is necessary to set a default
> > nonzero priority for all available interrupts to avoid undefined
> > behaviour.
> >
> > Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
> > ---
> >  arch/arc/kernel/intc-arcv2.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arc/kernel/intc-arcv2.c
> > b/arch/arc/kernel/intc-arcv2.c index 31246cc..d4fa4a5 100644
> > --- a/arch/arc/kernel/intc-arcv2.c
> > +++ b/arch/arc/kernel/intc-arcv2.c
> > @@ -22,7 +22,7 @@
> >   */
> >  void arc_init_IRQ(void)
> >  {
> > -	unsigned int tmp, irq_prio;
> > +	unsigned int tmp, irq_prio, i;
> >
> >  	struct bcr_irq_arcv2 irq_bcr;
> >
> > @@ -62,6 +62,16 @@ void arc_init_IRQ(void)
> >  		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
> >  		irq_bcr.firq ? " FIRQ (not used)":"");
> >
> > +	/*
> > +	 * Set a default priority for all available interrupts to prevent
> > +	 * switching of register banks if Fast IRQ and multiple register banks
> > +	 * are supported by CPU.
> > +	 */
> > +	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
> > +		write_aux_reg(AUX_IRQ_SELECT, i);
> > +		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
> > +	}
> > +
> 
> This itself is fine. However going forward can we move to the genirq
> irq_cpu_online() etc instead of doing this in our platform per cpu hook ?
> 
> https://www.linux-mips.org/archives/linux-mips/2011-03/msg00115.html

We need to set a default priority for all interrupts for each CPU before interrupt controller is configured. In other words it this necessary to guaranty a default state of all interrupts before doing something else with interrupts. Moreover as I understand irq_cpu_online() is intended to be used with virtual IRQs (already allocated interrupts) but the configuration of priorities must be done for all hardware interrupts to bring CPU to the default state.

> >  	/* setup status32, don't enable intr yet as kernel doesn't want */
> >  	tmp = read_aux_reg(ARC_REG_STATUS32);
> >  	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
> >

[PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts

[Yuriy Kolerov]

Hi Vineet,

> -----Original Message-----
> From: Vineet Gupta [mailto:vgupta at synopsys.com]
> Sent: Tuesday, January 31, 2017 8:54 PM
> To: Yuriy Kolerov <yuriy.kolerov at synopsys.com>; linux-snps-
> arc at lists.infradead.org
> Cc: marc.zyngier at arm.com; Alexey.Brodkin at synopsys.com; linux-
> kernel at vger.kernel.org
> Subject: Re: [PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core
> interrupts
> 
> On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> > After reset all interrupts in the core interrupt controller has the
> > highest priority P0. If the platform supports Fast IRQs and has more
> > than 1 banks of registers then CPU automatically switch banks of
> > registers when P0 interrupt comes.
> >
> > The problem is that the kernel expects that by default switching of
> > banks is not used by all interrupts. It is necessary to set a default
> > nonzero priority for all available interrupts to avoid undefined
> > behaviour.
> >
> > Signed-off-by: Yuriy Kolerov <yuriy.kolerov at synopsys.com>
> > ---
> >  arch/arc/kernel/intc-arcv2.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arc/kernel/intc-arcv2.c
> > b/arch/arc/kernel/intc-arcv2.c index 31246cc..d4fa4a5 100644
> > --- a/arch/arc/kernel/intc-arcv2.c
> > +++ b/arch/arc/kernel/intc-arcv2.c
> > @@ -22,7 +22,7 @@
> >   */
> >  void arc_init_IRQ(void)
> >  {
> > -	unsigned int tmp, irq_prio;
> > +	unsigned int tmp, irq_prio, i;
> >
> >  	struct bcr_irq_arcv2 irq_bcr;
> >
> > @@ -62,6 +62,16 @@ void arc_init_IRQ(void)
> >  		irq_prio + 1, ARCV2_IRQ_DEF_PRIO,
> >  		irq_bcr.firq ? " FIRQ (not used)":"");
> >
> > +	/*
> > +	 * Set a default priority for all available interrupts to prevent
> > +	 * switching of register banks if Fast IRQ and multiple register banks
> > +	 * are supported by CPU.
> > +	 */
> > +	for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
> > +		write_aux_reg(AUX_IRQ_SELECT, i);
> > +		write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
> > +	}
> > +
> 
> This itself is fine. However going forward can we move to the genirq
> irq_cpu_online() etc instead of doing this in our platform per cpu hook ?
> 
> https://www.linux-mips.org/archives/linux-mips/2011-03/msg00115.html

We need to set a default priority for all interrupts for each CPU before interrupt controller is configured. In other words it this necessary to guaranty a default state of all interrupts before doing something else with interrupts. Moreover as I understand irq_cpu_online() is intended to be used with virtual IRQs (already allocated interrupts) but the configuration of priorities must be done for all hardware interrupts to bring CPU to the default state.

> >  	/* setup status32, don't enable intr yet as kernel doesn't want */
> >  	tmp = read_aux_reg(ARC_REG_STATUS32);
> >  	tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1);
> >

Re: [PATCH v2 0/4] Use build registers for getting numbers of interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> A summary:
> 
>   * Use build registers for getting numbers of interrupts both for
>     core interrupt controller and for IDU interrupt controller.
>   * Set a default priority for all core interrupt to prevent
>     unexpected switching of banks of registers.
>   * Remove option for setting number of interrupts since it does
>     not affect a number of interrupts in IRQ domains and breaks
>     portability since it is impossible to change size of table of
>     interrupts after linkage.
> 
> Change in v2:
> 
>   * Squash some commits.
>   * Do not move a structure for control register of core intc to
>     the header since it is used only once.
> 
> Yuriy Kolerov (4):
>   ARCv2: IRQ: Move structure for build register of core intc to the
>     header
>   ARCv2: IRQ: Remove option for setting number of interrupts
>   ARCv2: IRQ: Use build registers for getting numbers of interrupts
>   ARCv2: IRQ: Set a default priority for all core interrupts
> 
>  arch/arc/Kconfig               | 11 -----------
>  arch/arc/include/asm/arcregs.h | 11 +++++++++++
>  arch/arc/include/asm/irq.h     | 32 +++++++++++++++++++++++++++++---
>  arch/arc/kernel/entry-arcv2.S  |  3 ++-
>  arch/arc/kernel/intc-arcv2.c   | 31 ++++++++++++++++++++-----------
>  arch/arc/kernel/mcip.c         | 31 +++++++++++++++++++------------
>  include/soc/arc/mcip.h         | 17 +++++++++++++++++
>  7 files changed, 98 insertions(+), 38 deletions(-)
> 

Hi Yuriy,

I've reworked your series a bit and pushed to my for-next.

Care to take a look please.

Thx,
-Vineet

[PATCH v2 0/4] Use build registers for getting numbers of interrupts

[Vineet Gupta]

On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> A summary:
> 
>   * Use build registers for getting numbers of interrupts both for
>     core interrupt controller and for IDU interrupt controller.
>   * Set a default priority for all core interrupt to prevent
>     unexpected switching of banks of registers.
>   * Remove option for setting number of interrupts since it does
>     not affect a number of interrupts in IRQ domains and breaks
>     portability since it is impossible to change size of table of
>     interrupts after linkage.
> 
> Change in v2:
> 
>   * Squash some commits.
>   * Do not move a structure for control register of core intc to
>     the header since it is used only once.
> 
> Yuriy Kolerov (4):
>   ARCv2: IRQ: Move structure for build register of core intc to the
>     header
>   ARCv2: IRQ: Remove option for setting number of interrupts
>   ARCv2: IRQ: Use build registers for getting numbers of interrupts
>   ARCv2: IRQ: Set a default priority for all core interrupts
> 
>  arch/arc/Kconfig               | 11 -----------
>  arch/arc/include/asm/arcregs.h | 11 +++++++++++
>  arch/arc/include/asm/irq.h     | 32 +++++++++++++++++++++++++++++---
>  arch/arc/kernel/entry-arcv2.S  |  3 ++-
>  arch/arc/kernel/intc-arcv2.c   | 31 ++++++++++++++++++++-----------
>  arch/arc/kernel/mcip.c         | 31 +++++++++++++++++++------------
>  include/soc/arc/mcip.h         | 17 +++++++++++++++++
>  7 files changed, 98 insertions(+), 38 deletions(-)
> 

Hi Yuriy,

I've reworked your series a bit and pushed to my for-next.

Care to take a look please.

Thx,
-Vineet

RE: [PATCH v2 0/4] Use build registers for getting numbers of interrupts

[Yuriy Kolerov]

Hi Vineet,

I have checked reworked patches. I think it is fine.

> -----Original Message-----
> From: Vineet Gupta [mailto:vgupta@synopsys.com]
> Sent: Wednesday, February 01, 2017 11:58 PM
> To: Yuriy Kolerov <yuriy.kolerov@synopsys.com>; linux-snps-
> arc@lists.infradead.org
> Cc: Alexey.Brodkin@synopsys.com; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 0/4] Use build registers for getting numbers of
> interrupts
> 
> On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> > A summary:
> >
> >   * Use build registers for getting numbers of interrupts both for
> >     core interrupt controller and for IDU interrupt controller.
> >   * Set a default priority for all core interrupt to prevent
> >     unexpected switching of banks of registers.
> >   * Remove option for setting number of interrupts since it does
> >     not affect a number of interrupts in IRQ domains and breaks
> >     portability since it is impossible to change size of table of
> >     interrupts after linkage.
> >
> > Change in v2:
> >
> >   * Squash some commits.
> >   * Do not move a structure for control register of core intc to
> >     the header since it is used only once.
> >
> > Yuriy Kolerov (4):
> >   ARCv2: IRQ: Move structure for build register of core intc to the
> >     header
> >   ARCv2: IRQ: Remove option for setting number of interrupts
> >   ARCv2: IRQ: Use build registers for getting numbers of interrupts
> >   ARCv2: IRQ: Set a default priority for all core interrupts
> >
> >  arch/arc/Kconfig               | 11 -----------
> >  arch/arc/include/asm/arcregs.h | 11 +++++++++++
> >  arch/arc/include/asm/irq.h     | 32 +++++++++++++++++++++++++++++---
> >  arch/arc/kernel/entry-arcv2.S  |  3 ++-
> >  arch/arc/kernel/intc-arcv2.c   | 31 ++++++++++++++++++++-----------
> >  arch/arc/kernel/mcip.c         | 31 +++++++++++++++++++------------
> >  include/soc/arc/mcip.h         | 17 +++++++++++++++++
> >  7 files changed, 98 insertions(+), 38 deletions(-)
> >
> 
> Hi Yuriy,
> 
> I've reworked your series a bit and pushed to my for-next.
> 
> Care to take a look please.
> 
> Thx,
> -Vineet

[PATCH v2 0/4] Use build registers for getting numbers of interrupts

[Yuriy Kolerov]

Hi Vineet,

I have checked reworked patches. I think it is fine.

> -----Original Message-----
> From: Vineet Gupta [mailto:vgupta at synopsys.com]
> Sent: Wednesday, February 01, 2017 11:58 PM
> To: Yuriy Kolerov <yuriy.kolerov at synopsys.com>; linux-snps-
> arc at lists.infradead.org
> Cc: Alexey.Brodkin at synopsys.com; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH v2 0/4] Use build registers for getting numbers of
> interrupts
> 
> On 01/31/2017 03:45 AM, Yuriy Kolerov wrote:
> > A summary:
> >
> >   * Use build registers for getting numbers of interrupts both for
> >     core interrupt controller and for IDU interrupt controller.
> >   * Set a default priority for all core interrupt to prevent
> >     unexpected switching of banks of registers.
> >   * Remove option for setting number of interrupts since it does
> >     not affect a number of interrupts in IRQ domains and breaks
> >     portability since it is impossible to change size of table of
> >     interrupts after linkage.
> >
> > Change in v2:
> >
> >   * Squash some commits.
> >   * Do not move a structure for control register of core intc to
> >     the header since it is used only once.
> >
> > Yuriy Kolerov (4):
> >   ARCv2: IRQ: Move structure for build register of core intc to the
> >     header
> >   ARCv2: IRQ: Remove option for setting number of interrupts
> >   ARCv2: IRQ: Use build registers for getting numbers of interrupts
> >   ARCv2: IRQ: Set a default priority for all core interrupts
> >
> >  arch/arc/Kconfig               | 11 -----------
> >  arch/arc/include/asm/arcregs.h | 11 +++++++++++
> >  arch/arc/include/asm/irq.h     | 32 +++++++++++++++++++++++++++++---
> >  arch/arc/kernel/entry-arcv2.S  |  3 ++-
> >  arch/arc/kernel/intc-arcv2.c   | 31 ++++++++++++++++++++-----------
> >  arch/arc/kernel/mcip.c         | 31 +++++++++++++++++++------------
> >  include/soc/arc/mcip.h         | 17 +++++++++++++++++
> >  7 files changed, 98 insertions(+), 38 deletions(-)
> >
> 
> Hi Yuriy,
> 
> I've reworked your series a bit and pushed to my for-next.
> 
> Care to take a look please.
> 
> Thx,
> -Vineet