* [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header
@ 2020-03-05 13:33 Monk Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV Monk Liu
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Monk Liu @ 2020-03-05 13:33 UTC (permalink / raw)
To: amd-gfx; +Cc: Monk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h | 338 ++++++++++++++++++++++++++++++++
1 file changed, 338 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h
new file mode 100644
index 0000000..1b5086c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MMSCH_V2_0_H__
+#define __MMSCH_V2_0_H__
+
+// addressBlock: uvd0_mmsch_dec
+// base address: 0x1e000
+#define mmMMSCH_UCODE_ADDR 0x0000
+#define mmMMSCH_UCODE_ADDR_BASE_IDX 0
+#define mmMMSCH_UCODE_DATA 0x0001
+#define mmMMSCH_UCODE_DATA_BASE_IDX 0
+#define mmMMSCH_SRAM_ADDR 0x0002
+#define mmMMSCH_SRAM_ADDR_BASE_IDX 0
+#define mmMMSCH_SRAM_DATA 0x0003
+#define mmMMSCH_SRAM_DATA_BASE_IDX 0
+#define mmMMSCH_VF_SRAM_OFFSET 0x0004
+#define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX 0
+#define mmMMSCH_DB_SRAM_OFFSET 0x0005
+#define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX 0
+#define mmMMSCH_CTX_SRAM_OFFSET 0x0006
+#define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0
+#define mmMMSCH_CTL 0x0007
+#define mmMMSCH_CTL_BASE_IDX 0
+#define mmMMSCH_INTR 0x0008
+#define mmMMSCH_INTR_BASE_IDX 0
+#define mmMMSCH_INTR_ACK 0x0009
+#define mmMMSCH_INTR_ACK_BASE_IDX 0
+#define mmMMSCH_INTR_STATUS 0x000a
+#define mmMMSCH_INTR_STATUS_BASE_IDX 0
+#define mmMMSCH_VF_VMID 0x000b
+#define mmMMSCH_VF_VMID_BASE_IDX 0
+#define mmMMSCH_VF_CTX_ADDR_LO 0x000c
+#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
+#define mmMMSCH_VF_CTX_ADDR_HI 0x000d
+#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
+#define mmMMSCH_VF_CTX_SIZE 0x000e
+#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0
+#define mmMMSCH_VF_GPCOM_ADDR_LO 0x000f
+#define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
+#define mmMMSCH_VF_GPCOM_ADDR_HI 0x0010
+#define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
+#define mmMMSCH_VF_GPCOM_SIZE 0x0011
+#define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_HOST 0x0012
+#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_RESP 0x0013
+#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_0 0x0014
+#define mmMMSCH_VF_MAILBOX_0_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_0_RESP 0x0015
+#define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_1 0x0016
+#define mmMMSCH_VF_MAILBOX_1_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_1_RESP 0x0017
+#define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0
+#define mmMMSCH_CNTL 0x001c
+#define mmMMSCH_CNTL_BASE_IDX 0
+#define mmMMSCH_NONCACHE_OFFSET0 0x001d
+#define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX 0
+#define mmMMSCH_NONCACHE_SIZE0 0x001e
+#define mmMMSCH_NONCACHE_SIZE0_BASE_IDX 0
+#define mmMMSCH_NONCACHE_OFFSET1 0x001f
+#define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX 0
+#define mmMMSCH_NONCACHE_SIZE1 0x0020
+#define mmMMSCH_NONCACHE_SIZE1_BASE_IDX 0
+#define mmMMSCH_PDEBUG_STATUS 0x0021
+#define mmMMSCH_PDEBUG_STATUS_BASE_IDX 0
+#define mmMMSCH_PDEBUG_DATA_32UPPERBITS 0x0022
+#define mmMMSCH_PDEBUG_DATA_32UPPERBITS_BASE_IDX 0
+#define mmMMSCH_PDEBUG_DATA_32LOWERBITS 0x0023
+#define mmMMSCH_PDEBUG_DATA_32LOWERBITS_BASE_IDX 0
+#define mmMMSCH_PDEBUG_EPC 0x0024
+#define mmMMSCH_PDEBUG_EPC_BASE_IDX 0
+#define mmMMSCH_PDEBUG_EXCCAUSE 0x0025
+#define mmMMSCH_PDEBUG_EXCCAUSE_BASE_IDX 0
+#define mmMMSCH_PROC_STATE1 0x0026
+#define mmMMSCH_PROC_STATE1_BASE_IDX 0
+#define mmMMSCH_LAST_MC_ADDR 0x0027
+#define mmMMSCH_LAST_MC_ADDR_BASE_IDX 0
+#define mmMMSCH_LAST_MEM_ACCESS_HI 0x0028
+#define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0
+#define mmMMSCH_LAST_MEM_ACCESS_LO 0x0029
+#define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0
+#define mmMMSCH_IOV_ACTIVE_FCN_ID 0x002a
+#define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 0
+#define mmMMSCH_SCRATCH_0 0x002b
+#define mmMMSCH_SCRATCH_0_BASE_IDX 0
+#define mmMMSCH_SCRATCH_1 0x002c
+#define mmMMSCH_SCRATCH_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_SCH_BLOCK_0 0x002d
+#define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_CONTROL_0 0x002e
+#define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_STATUS_0 0x002f
+#define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030
+#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031
+#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW6_0 0x0033
+#define mmMMSCH_GPUIOV_DW6_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW7_0 0x0034
+#define mmMMSCH_GPUIOV_DW7_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW8_0 0x0035
+#define mmMMSCH_GPUIOV_DW8_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_SCH_BLOCK_1 0x0036
+#define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_CONTROL_1 0x0037
+#define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_STATUS_1 0x0038
+#define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039
+#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a
+#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW6_1 0x003c
+#define mmMMSCH_GPUIOV_DW6_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW7_1 0x003d
+#define mmMMSCH_GPUIOV_DW7_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW8_1 0x003e
+#define mmMMSCH_GPUIOV_DW8_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CNTXT 0x003f
+#define mmMMSCH_GPUIOV_CNTXT_BASE_IDX 0
+#define mmMMSCH_SCRATCH_2 0x0040
+#define mmMMSCH_SCRATCH_2_BASE_IDX 0
+#define mmMMSCH_SCRATCH_3 0x0041
+#define mmMMSCH_SCRATCH_3_BASE_IDX 0
+#define mmMMSCH_SCRATCH_4 0x0042
+#define mmMMSCH_SCRATCH_4_BASE_IDX 0
+#define mmMMSCH_SCRATCH_5 0x0043
+#define mmMMSCH_SCRATCH_5_BASE_IDX 0
+#define mmMMSCH_SCRATCH_6 0x0044
+#define mmMMSCH_SCRATCH_6_BASE_IDX 0
+#define mmMMSCH_SCRATCH_7 0x0045
+#define mmMMSCH_SCRATCH_7_BASE_IDX 0
+#define mmMMSCH_VFID_FIFO_HEAD_0 0x0046
+#define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0
+#define mmMMSCH_VFID_FIFO_TAIL_0 0x0047
+#define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0
+#define mmMMSCH_VFID_FIFO_HEAD_1 0x0048
+#define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0
+#define mmMMSCH_VFID_FIFO_TAIL_1 0x0049
+#define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0
+#define mmMMSCH_NACK_STATUS 0x004a
+#define mmMMSCH_NACK_STATUS_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX0_DATA 0x004b
+#define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX1_DATA 0x004c
+#define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0
+#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d
+#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e
+#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0
+#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050
+#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051
+#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CNTXT_IP 0x0053
+#define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0
+#define mmMMSCH_GPUIOV_SCH_BLOCK_2 0x0054
+#define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_CONTROL_2 0x0055
+#define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_STATUS_2 0x0056
+#define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057
+#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058
+#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW6_2 0x005a
+#define mmMMSCH_GPUIOV_DW6_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW7_2 0x005b
+#define mmMMSCH_GPUIOV_DW7_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_DW8_2 0x005c
+#define mmMMSCH_GPUIOV_DW8_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d
+#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e
+#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f
+#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0
+#define mmMMSCH_VFID_FIFO_HEAD_2 0x0060
+#define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0
+#define mmMMSCH_VFID_FIFO_TAIL_2 0x0061
+#define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0
+#define mmMMSCH_VM_BUSY_STATUS_0 0x0062
+#define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0
+#define mmMMSCH_VM_BUSY_STATUS_1 0x0063
+#define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0
+#define mmMMSCH_VM_BUSY_STATUS_2 0x0064
+#define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0
+
+#define MMSCH_VERSION_MAJOR 2
+#define MMSCH_VERSION_MINOR 0
+#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
+
+enum mmsch_v2_0_command_type {
+ MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
+ MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
+ MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
+ MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
+ MMSCH_COMMAND__END = 0xf
+};
+
+struct mmsch_v2_0_init_header {
+ uint32_t version;
+ uint32_t header_size;
+ uint32_t vcn_init_status;
+ uint32_t vcn_table_offset;
+ uint32_t vcn_table_size;
+};
+
+struct mmsch_v2_0_cmd_direct_reg_header {
+ uint32_t reg_offset : 28;
+ uint32_t command_type : 4;
+};
+
+struct mmsch_v2_0_cmd_indirect_reg_header {
+ uint32_t reg_offset : 20;
+ uint32_t reg_idx_space : 8;
+ uint32_t command_type : 4;
+};
+
+struct mmsch_v2_0_cmd_direct_write {
+ struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
+ uint32_t reg_value;
+};
+
+struct mmsch_v2_0_cmd_direct_read_modify_write {
+ struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
+ uint32_t write_data;
+ uint32_t mask_value;
+};
+
+struct mmsch_v2_0_cmd_direct_polling {
+ struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
+ uint32_t mask_value;
+ uint32_t wait_value;
+};
+
+struct mmsch_v2_0_cmd_end {
+ struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
+};
+
+struct mmsch_v2_0_cmd_indirect_write {
+ struct mmsch_v2_0_cmd_indirect_reg_header cmd_header;
+ uint32_t reg_value;
+};
+
+static inline void mmsch_v2_0_insert_direct_wt(struct mmsch_v2_0_cmd_direct_write *direct_wt,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t value)
+{
+ direct_wt->cmd_header.reg_offset = reg_offset;
+ direct_wt->reg_value = value;
+ memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v2_0_cmd_direct_write));
+}
+
+static inline void mmsch_v2_0_insert_direct_rd_mod_wt(struct mmsch_v2_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t mask, uint32_t data)
+{
+ direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
+ direct_rd_mod_wt->mask_value = mask;
+ direct_rd_mod_wt->write_data = data;
+ memcpy((void *)init_table, direct_rd_mod_wt,
+ sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write));
+}
+
+static inline void mmsch_v2_0_insert_direct_poll(struct mmsch_v2_0_cmd_direct_polling *direct_poll,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t mask, uint32_t wait)
+{
+ direct_poll->cmd_header.reg_offset = reg_offset;
+ direct_poll->mask_value = mask;
+ direct_poll->wait_value = wait;
+ memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v2_0_cmd_direct_polling));
+}
+
+#define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
+ mmsch_v2_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
+ init_table, (reg), \
+ (mask), (data)); \
+ init_table += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \
+ table_size += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \
+}
+
+#define MMSCH_V2_0_INSERT_DIRECT_WT(reg, value) { \
+ mmsch_v2_0_insert_direct_wt(&direct_wt, \
+ init_table, (reg), \
+ (value)); \
+ init_table += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \
+ table_size += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \
+}
+
+#define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
+ mmsch_v2_0_insert_direct_poll(&direct_poll, \
+ init_table, (reg), \
+ (mask), (wait)); \
+ init_table += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \
+ table_size += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \
+}
+
+#endif
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
@ 2020-03-05 13:33 ` Monk Liu
2020-03-05 13:37 ` Christian König
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 " Monk Liu
` (4 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Monk Liu @ 2020-03-05 13:33 UTC (permalink / raw)
To: amd-gfx; +Cc: Monk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2d1bebd..033cbbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -516,7 +516,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ if (!amdgpu_sriov_vf(adev))
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
break;
default:
return -EINVAL;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 for SRIOV
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV Monk Liu
@ 2020-03-05 13:33 ` Monk Liu
2020-03-05 16:07 ` Leo Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 4/6] drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0 Monk Liu
` (3 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Monk Liu @ 2020-03-05 13:33 UTC (permalink / raw)
To: amd-gfx; +Cc: Monk Liu
one dec ring and one enc ring
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 231 +++++++++++++++++++++++++++++++++-
1 file changed, 228 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index c387c81..421e5bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -29,6 +29,7 @@
#include "soc15d.h"
#include "amdgpu_pm.h"
#include "amdgpu_psp.h"
+#include "mmsch_v2_0.h"
#include "vcn/vcn_2_0_0_offset.h"
#include "vcn/vcn_2_0_0_sh_mask.h"
@@ -54,7 +55,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
enum amd_powergating_state state);
static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
-
+static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
/**
* vcn_v2_0_early_init - set function pointers
*
@@ -67,7 +68,10 @@ static int vcn_v2_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
adev->vcn.num_vcn_inst = 1;
- adev->vcn.num_enc_rings = 2;
+ if (amdgpu_sriov_vf(adev))
+ adev->vcn.num_enc_rings = 1;
+ else
+ adev->vcn.num_enc_rings = 2;
vcn_v2_0_set_dec_ring_funcs(adev);
vcn_v2_0_set_enc_ring_funcs(adev);
@@ -154,7 +158,10 @@ static int vcn_v2_0_sw_init(void *handle)
for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
ring = &adev->vcn.inst->ring_enc[i];
ring->use_doorbell = true;
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
+ if (!amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
+ else
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
sprintf(ring->name, "vcn_enc%d", i);
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
if (r)
@@ -163,6 +170,10 @@ static int vcn_v2_0_sw_init(void *handle)
adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
+ r = amdgpu_virt_alloc_mm_table(adev);
+ if (r)
+ return r;
+
return 0;
}
@@ -178,6 +189,8 @@ static int vcn_v2_0_sw_fini(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ amdgpu_virt_free_mm_table(adev);
+
r = amdgpu_vcn_suspend(adev);
if (r)
return r;
@@ -203,6 +216,9 @@ static int vcn_v2_0_hw_init(void *handle)
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
ring->doorbell_index, 0);
+ if (amdgpu_sriov_vf(adev))
+ vcn_v2_0_start_sriov(adev);
+
r = amdgpu_ring_test_helper(ring);
if (r)
goto done;
@@ -1680,6 +1696,215 @@ static int vcn_v2_0_set_powergating_state(void *handle,
return ret;
}
+static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
+ struct amdgpu_mm_table *table)
+{
+ uint32_t data = 0, loop;
+ uint64_t addr = table->gpu_addr;
+ struct mmsch_v2_0_init_header *header;
+ uint32_t size;
+ int i;
+
+ header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
+ size = header->header_size + header->vcn_table_size;
+
+ /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
+ * of memory descriptor location
+ */
+ WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
+ WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
+
+ /* 2, update vmid of descriptor */
+ data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
+ data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
+ /* use domain0 for MM scheduler */
+ data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
+ WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
+
+ /* 3, notify mmsch about the size of this descriptor */
+ WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
+
+ /* 4, set resp to zero */
+ WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
+
+ adev->vcn.inst->ring_dec.wptr = 0;
+ adev->vcn.inst->ring_dec.wptr_old = 0;
+ vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ adev->vcn.inst->ring_enc[i].wptr = 0;
+ adev->vcn.inst->ring_enc[i].wptr_old = 0;
+ vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
+ }
+
+ /* 5, kick off the initialization and wait until
+ * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
+ */
+ WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
+
+ data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
+ loop = 1000;
+ while ((data & 0x10000002) != 0x10000002) {
+ udelay(10);
+ data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
+ loop--;
+ if (!loop)
+ break;
+ }
+
+ if (!loop) {
+ DRM_ERROR("failed to init MMSCH, " \
+ "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
+{
+ int r;
+ uint32_t tmp;
+ struct amdgpu_ring *ring;
+ uint32_t offset, size;
+ uint32_t table_size = 0;
+ struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
+ struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
+ struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
+ struct mmsch_v2_0_cmd_end end = { {0} };
+ struct mmsch_v2_0_init_header *header;
+ uint32_t *init_table = adev->virt.mm_table.cpu_addr;
+ uint8_t i = 0;
+
+ header = (struct mmsch_v2_0_init_header *)init_table;
+ direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
+ direct_rd_mod_wt.cmd_header.command_type =
+ MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
+ direct_poll.cmd_header.command_type =
+ MMSCH_COMMAND__DIRECT_REG_POLLING;
+ end.cmd_header.command_type = MMSCH_COMMAND__END;
+
+ if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
+ header->version = MMSCH_VERSION;
+ header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
+
+ header->vcn_table_offset = header->header_size;
+
+ init_table += header->vcn_table_offset;
+
+ size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
+
+ MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
+ 0xFFFFFFFF, 0x00000004);
+
+ /* mc resume*/
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ tmp = AMDGPU_UCODE_ID_VCN;
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ adev->firmware.ucode[tmp].tmr_mc_addr_lo);
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ adev->firmware.ucode[tmp].tmr_mc_addr_hi);
+ offset = 0;
+ } else {
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.inst->gpu_addr));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.inst->gpu_addr));
+ offset = size;
+ }
+
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
+ 0);
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
+ size);
+
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.inst->gpu_addr + offset));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.inst->gpu_addr + offset));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
+ 0);
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
+ AMDGPU_VCN_STACK_SIZE);
+
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.inst->gpu_addr + offset +
+ AMDGPU_VCN_STACK_SIZE));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.inst->gpu_addr + offset +
+ AMDGPU_VCN_STACK_SIZE));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
+ 0);
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
+ AMDGPU_VCN_CONTEXT_SIZE);
+
+ for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
+ ring = &adev->vcn.inst->ring_enc[r];
+ ring->wptr = 0;
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
+ lower_32_bits(ring->gpu_addr));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
+ upper_32_bits(ring->gpu_addr));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
+ ring->ring_size / 4);
+ }
+
+ ring = &adev->vcn.inst->ring_dec;
+ ring->wptr = 0;
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
+ lower_32_bits(ring->gpu_addr));
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i,
+ mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
+ upper_32_bits(ring->gpu_addr));
+ /* force RBC into idle state */
+ tmp = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ MMSCH_V2_0_INSERT_DIRECT_WT(
+ SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
+
+ /* add end packet */
+ tmp = sizeof(struct mmsch_v2_0_cmd_end);
+ memcpy((void *)init_table, &end, tmp);
+ table_size += (tmp / 4);
+ header->vcn_table_size = table_size;
+
+ }
+ return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
+}
+
static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
.name = "vcn_v2_0",
.early_init = vcn_v2_0_early_init,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [enable VCN2.0 for NV12 SRIOV 4/6] drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV Monk Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 " Monk Liu
@ 2020-03-05 13:33 ` Monk Liu
2020-03-05 16:10 ` Leo Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 5/6] drm/amdgpu: disable clock/power gating for SRIOV Monk Liu
` (2 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Monk Liu @ 2020-03-05 13:33 UTC (permalink / raw)
To: amd-gfx; +Cc: Monk Liu
support IB test on dec/enc ring
disable ring test on dec/enc ring (MMSCH limitation)
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 11 +++--------
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 +++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index f96464e..ae9754f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -497,10 +497,6 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
struct dma_fence *fence;
long r;
- /* temporarily disable ib test for sriov */
- if (amdgpu_sriov_vf(adev))
- return 0;
-
r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
if (r)
goto error;
@@ -527,6 +523,9 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
r = amdgpu_ring_alloc(ring, 16);
if (r)
return r;
@@ -661,10 +660,6 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
struct amdgpu_bo *bo = NULL;
long r;
- /* temporarily disable ib test for sriov */
- if (amdgpu_sriov_vf(adev))
- return 0;
-
r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
&bo, NULL, NULL);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 421e5bf..dd500d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -1647,6 +1647,9 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 4);
if (r)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [enable VCN2.0 for NV12 SRIOV 5/6] drm/amdgpu: disable clock/power gating for SRIOV
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
` (2 preceding siblings ...)
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 4/6] drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0 Monk Liu
@ 2020-03-05 13:33 ` Monk Liu
2020-03-05 16:11 ` Leo Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var Monk Liu
2020-03-05 15:59 ` [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Leo Liu
5 siblings, 1 reply; 18+ messages in thread
From: Monk Liu @ 2020-03-05 13:33 UTC (permalink / raw)
To: amd-gfx; +Cc: Monk Liu
and disable MC resum in VCN2.0 as well
those are not concerned by VF driver
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index dd500d1..f2745fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -320,6 +320,9 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
uint32_t offset;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
@@ -464,6 +467,9 @@ static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
{
uint32_t data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* UVD disable CGC */
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
@@ -622,6 +628,9 @@ static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
{
uint32_t data = 0;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* enable UVD CGC */
data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
@@ -674,6 +683,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
uint32_t data = 0;
int ret;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
@@ -721,6 +733,9 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
uint32_t data = 0;
int ret;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
/* Before power off, this indicator has to be turned on */
data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
@@ -1231,6 +1246,9 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_CG_STATE_GATE);
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
if (enable) {
/* wait for STATUS to clear */
if (vcn_v2_0_is_idle(handle))
@@ -1686,6 +1704,11 @@ static int vcn_v2_0_set_powergating_state(void *handle,
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
+
if (state == adev->vcn.cur_state)
return 0;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
` (3 preceding siblings ...)
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 5/6] drm/amdgpu: disable clock/power gating for SRIOV Monk Liu
@ 2020-03-05 13:33 ` Monk Liu
2020-03-05 13:37 ` Christian König
2020-03-05 16:16 ` Leo Liu
2020-03-05 15:59 ` [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Leo Liu
5 siblings, 2 replies; 18+ messages in thread
From: Monk Liu @ 2020-03-05 13:33 UTC (permalink / raw)
To: amd-gfx; +Cc: Monk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index ae9754f..a41272f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -493,7 +493,6 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
- struct amdgpu_device *adev = ring->adev;
struct dma_fence *fence;
long r;
@@ -655,7 +654,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
- struct amdgpu_device *adev = ring->adev;
struct dma_fence *fence = NULL;
struct amdgpu_bo *bo = NULL;
long r;
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var Monk Liu
@ 2020-03-05 13:37 ` Christian König
2020-03-06 3:31 ` Deng, Emily
2020-03-05 16:16 ` Leo Liu
1 sibling, 1 reply; 18+ messages in thread
From: Christian König @ 2020-03-05 13:37 UTC (permalink / raw)
To: Monk Liu, amd-gfx
Am 05.03.20 um 14:33 schrieb Monk Liu:
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index ae9754f..a41272f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -493,7 +493,6 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> - struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence;
> long r;
>
> @@ -655,7 +654,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> - struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence = NULL;
> struct amdgpu_bo *bo = NULL;
> long r;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV Monk Liu
@ 2020-03-05 13:37 ` Christian König
2020-03-05 13:39 ` Liu, Monk
0 siblings, 1 reply; 18+ messages in thread
From: Christian König @ 2020-03-05 13:37 UTC (permalink / raw)
To: Monk Liu, amd-gfx
A commit message explaining why we disable it and if it could be enabled
again or if this is permanent would be nice to have.
Christian.
Am 05.03.20 um 14:33 schrieb Monk Liu:
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 2d1bebd..033cbbc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -516,7 +516,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> !amdgpu_sriov_vf(adev))
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> + if (!amdgpu_sriov_vf(adev))
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> break;
> default:
> return -EINVAL;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV
2020-03-05 13:37 ` Christian König
@ 2020-03-05 13:39 ` Liu, Monk
2020-03-05 16:01 ` Leo Liu
0 siblings, 1 reply; 18+ messages in thread
From: Liu, Monk @ 2020-03-05 13:39 UTC (permalink / raw)
To: Koenig, Christian, amd-gfx
This is not supported by MMSCH FW...
_____________________________________
Monk Liu|GPU Virtualization Team |AMD
-----Original Message-----
From: Christian König <ckoenig.leichtzumerken@gmail.com>
Sent: Thursday, March 5, 2020 9:38 PM
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV
A commit message explaining why we disable it and if it could be enabled again or if this is permanent would be nice to have.
Christian.
Am 05.03.20 um 14:33 schrieb Monk Liu:
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> b/drivers/gpu/drm/amd/amdgpu/nv.c index 2d1bebd..033cbbc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -516,7 +516,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> !amdgpu_sriov_vf(adev))
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> + if (!amdgpu_sriov_vf(adev))
> + amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
> break;
> default:
> return -EINVAL;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
` (4 preceding siblings ...)
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var Monk Liu
@ 2020-03-05 15:59 ` Leo Liu
5 siblings, 0 replies; 18+ messages in thread
From: Leo Liu @ 2020-03-05 15:59 UTC (permalink / raw)
To: Monk Liu, amd-gfx
This patch is:
Acked-by: Leo Liu <leo.liu@amd.com>
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h | 338 ++++++++++++++++++++++++++++++++
> 1 file changed, 338 insertions(+)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h
> new file mode 100644
> index 0000000..1b5086c
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v2_0.h
> @@ -0,0 +1,338 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __MMSCH_V2_0_H__
> +#define __MMSCH_V2_0_H__
> +
> +// addressBlock: uvd0_mmsch_dec
> +// base address: 0x1e000
> +#define mmMMSCH_UCODE_ADDR 0x0000
> +#define mmMMSCH_UCODE_ADDR_BASE_IDX 0
> +#define mmMMSCH_UCODE_DATA 0x0001
> +#define mmMMSCH_UCODE_DATA_BASE_IDX 0
> +#define mmMMSCH_SRAM_ADDR 0x0002
> +#define mmMMSCH_SRAM_ADDR_BASE_IDX 0
> +#define mmMMSCH_SRAM_DATA 0x0003
> +#define mmMMSCH_SRAM_DATA_BASE_IDX 0
> +#define mmMMSCH_VF_SRAM_OFFSET 0x0004
> +#define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX 0
> +#define mmMMSCH_DB_SRAM_OFFSET 0x0005
> +#define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX 0
> +#define mmMMSCH_CTX_SRAM_OFFSET 0x0006
> +#define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX 0
> +#define mmMMSCH_CTL 0x0007
> +#define mmMMSCH_CTL_BASE_IDX 0
> +#define mmMMSCH_INTR 0x0008
> +#define mmMMSCH_INTR_BASE_IDX 0
> +#define mmMMSCH_INTR_ACK 0x0009
> +#define mmMMSCH_INTR_ACK_BASE_IDX 0
> +#define mmMMSCH_INTR_STATUS 0x000a
> +#define mmMMSCH_INTR_STATUS_BASE_IDX 0
> +#define mmMMSCH_VF_VMID 0x000b
> +#define mmMMSCH_VF_VMID_BASE_IDX 0
> +#define mmMMSCH_VF_CTX_ADDR_LO 0x000c
> +#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
> +#define mmMMSCH_VF_CTX_ADDR_HI 0x000d
> +#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
> +#define mmMMSCH_VF_CTX_SIZE 0x000e
> +#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0
> +#define mmMMSCH_VF_GPCOM_ADDR_LO 0x000f
> +#define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
> +#define mmMMSCH_VF_GPCOM_ADDR_HI 0x0010
> +#define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
> +#define mmMMSCH_VF_GPCOM_SIZE 0x0011
> +#define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX_HOST 0x0012
> +#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX_RESP 0x0013
> +#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX_0 0x0014
> +#define mmMMSCH_VF_MAILBOX_0_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX_0_RESP 0x0015
> +#define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX_1 0x0016
> +#define mmMMSCH_VF_MAILBOX_1_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX_1_RESP 0x0017
> +#define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX 0
> +#define mmMMSCH_CNTL 0x001c
> +#define mmMMSCH_CNTL_BASE_IDX 0
> +#define mmMMSCH_NONCACHE_OFFSET0 0x001d
> +#define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX 0
> +#define mmMMSCH_NONCACHE_SIZE0 0x001e
> +#define mmMMSCH_NONCACHE_SIZE0_BASE_IDX 0
> +#define mmMMSCH_NONCACHE_OFFSET1 0x001f
> +#define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX 0
> +#define mmMMSCH_NONCACHE_SIZE1 0x0020
> +#define mmMMSCH_NONCACHE_SIZE1_BASE_IDX 0
> +#define mmMMSCH_PDEBUG_STATUS 0x0021
> +#define mmMMSCH_PDEBUG_STATUS_BASE_IDX 0
> +#define mmMMSCH_PDEBUG_DATA_32UPPERBITS 0x0022
> +#define mmMMSCH_PDEBUG_DATA_32UPPERBITS_BASE_IDX 0
> +#define mmMMSCH_PDEBUG_DATA_32LOWERBITS 0x0023
> +#define mmMMSCH_PDEBUG_DATA_32LOWERBITS_BASE_IDX 0
> +#define mmMMSCH_PDEBUG_EPC 0x0024
> +#define mmMMSCH_PDEBUG_EPC_BASE_IDX 0
> +#define mmMMSCH_PDEBUG_EXCCAUSE 0x0025
> +#define mmMMSCH_PDEBUG_EXCCAUSE_BASE_IDX 0
> +#define mmMMSCH_PROC_STATE1 0x0026
> +#define mmMMSCH_PROC_STATE1_BASE_IDX 0
> +#define mmMMSCH_LAST_MC_ADDR 0x0027
> +#define mmMMSCH_LAST_MC_ADDR_BASE_IDX 0
> +#define mmMMSCH_LAST_MEM_ACCESS_HI 0x0028
> +#define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX 0
> +#define mmMMSCH_LAST_MEM_ACCESS_LO 0x0029
> +#define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX 0
> +#define mmMMSCH_IOV_ACTIVE_FCN_ID 0x002a
> +#define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_0 0x002b
> +#define mmMMSCH_SCRATCH_0_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_1 0x002c
> +#define mmMMSCH_SCRATCH_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_0 0x002d
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_CONTROL_0 0x002e
> +#define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_STATUS_0 0x002f
> +#define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0 0x0030
> +#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0 0x0031
> +#define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0x0032
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW6_0 0x0033
> +#define mmMMSCH_GPUIOV_DW6_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW7_0 0x0034
> +#define mmMMSCH_GPUIOV_DW7_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW8_0 0x0035
> +#define mmMMSCH_GPUIOV_DW8_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_1 0x0036
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_CONTROL_1 0x0037
> +#define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_STATUS_1 0x0038
> +#define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1 0x0039
> +#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1 0x003a
> +#define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0x003b
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW6_1 0x003c
> +#define mmMMSCH_GPUIOV_DW6_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW7_1 0x003d
> +#define mmMMSCH_GPUIOV_DW7_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW8_1 0x003e
> +#define mmMMSCH_GPUIOV_DW8_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CNTXT 0x003f
> +#define mmMMSCH_GPUIOV_CNTXT_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_2 0x0040
> +#define mmMMSCH_SCRATCH_2_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_3 0x0041
> +#define mmMMSCH_SCRATCH_3_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_4 0x0042
> +#define mmMMSCH_SCRATCH_4_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_5 0x0043
> +#define mmMMSCH_SCRATCH_5_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_6 0x0044
> +#define mmMMSCH_SCRATCH_6_BASE_IDX 0
> +#define mmMMSCH_SCRATCH_7 0x0045
> +#define mmMMSCH_SCRATCH_7_BASE_IDX 0
> +#define mmMMSCH_VFID_FIFO_HEAD_0 0x0046
> +#define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX 0
> +#define mmMMSCH_VFID_FIFO_TAIL_0 0x0047
> +#define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX 0
> +#define mmMMSCH_VFID_FIFO_HEAD_1 0x0048
> +#define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX 0
> +#define mmMMSCH_VFID_FIFO_TAIL_1 0x0049
> +#define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX 0
> +#define mmMMSCH_NACK_STATUS 0x004a
> +#define mmMMSCH_NACK_STATUS_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX0_DATA 0x004b
> +#define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX 0
> +#define mmMMSCH_VF_MAILBOX1_DATA 0x004c
> +#define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0 0x004d
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0 0x004e
> +#define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0x004f
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1 0x0050
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1 0x0051
> +#define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0x0052
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CNTXT_IP 0x0053
> +#define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_2 0x0054
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_CONTROL_2 0x0055
> +#define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_STATUS_2 0x0056
> +#define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2 0x0057
> +#define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2 0x0058
> +#define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0x0059
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW6_2 0x005a
> +#define mmMMSCH_GPUIOV_DW6_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW7_2 0x005b
> +#define mmMMSCH_GPUIOV_DW7_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_DW8_2 0x005c
> +#define mmMMSCH_GPUIOV_DW8_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2 0x005d
> +#define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2 0x005e
> +#define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX 0
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0x005f
> +#define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX 0
> +#define mmMMSCH_VFID_FIFO_HEAD_2 0x0060
> +#define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX 0
> +#define mmMMSCH_VFID_FIFO_TAIL_2 0x0061
> +#define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX 0
> +#define mmMMSCH_VM_BUSY_STATUS_0 0x0062
> +#define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX 0
> +#define mmMMSCH_VM_BUSY_STATUS_1 0x0063
> +#define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX 0
> +#define mmMMSCH_VM_BUSY_STATUS_2 0x0064
> +#define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX 0
> +
> +#define MMSCH_VERSION_MAJOR 2
> +#define MMSCH_VERSION_MINOR 0
> +#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
> +
> +enum mmsch_v2_0_command_type {
> + MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
> + MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
> + MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
> + MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
> + MMSCH_COMMAND__END = 0xf
> +};
> +
> +struct mmsch_v2_0_init_header {
> + uint32_t version;
> + uint32_t header_size;
> + uint32_t vcn_init_status;
> + uint32_t vcn_table_offset;
> + uint32_t vcn_table_size;
> +};
> +
> +struct mmsch_v2_0_cmd_direct_reg_header {
> + uint32_t reg_offset : 28;
> + uint32_t command_type : 4;
> +};
> +
> +struct mmsch_v2_0_cmd_indirect_reg_header {
> + uint32_t reg_offset : 20;
> + uint32_t reg_idx_space : 8;
> + uint32_t command_type : 4;
> +};
> +
> +struct mmsch_v2_0_cmd_direct_write {
> + struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
> + uint32_t reg_value;
> +};
> +
> +struct mmsch_v2_0_cmd_direct_read_modify_write {
> + struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
> + uint32_t write_data;
> + uint32_t mask_value;
> +};
> +
> +struct mmsch_v2_0_cmd_direct_polling {
> + struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
> + uint32_t mask_value;
> + uint32_t wait_value;
> +};
> +
> +struct mmsch_v2_0_cmd_end {
> + struct mmsch_v2_0_cmd_direct_reg_header cmd_header;
> +};
> +
> +struct mmsch_v2_0_cmd_indirect_write {
> + struct mmsch_v2_0_cmd_indirect_reg_header cmd_header;
> + uint32_t reg_value;
> +};
> +
> +static inline void mmsch_v2_0_insert_direct_wt(struct mmsch_v2_0_cmd_direct_write *direct_wt,
> + uint32_t *init_table,
> + uint32_t reg_offset,
> + uint32_t value)
> +{
> + direct_wt->cmd_header.reg_offset = reg_offset;
> + direct_wt->reg_value = value;
> + memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v2_0_cmd_direct_write));
> +}
> +
> +static inline void mmsch_v2_0_insert_direct_rd_mod_wt(struct mmsch_v2_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
> + uint32_t *init_table,
> + uint32_t reg_offset,
> + uint32_t mask, uint32_t data)
> +{
> + direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
> + direct_rd_mod_wt->mask_value = mask;
> + direct_rd_mod_wt->write_data = data;
> + memcpy((void *)init_table, direct_rd_mod_wt,
> + sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write));
> +}
> +
> +static inline void mmsch_v2_0_insert_direct_poll(struct mmsch_v2_0_cmd_direct_polling *direct_poll,
> + uint32_t *init_table,
> + uint32_t reg_offset,
> + uint32_t mask, uint32_t wait)
> +{
> + direct_poll->cmd_header.reg_offset = reg_offset;
> + direct_poll->mask_value = mask;
> + direct_poll->wait_value = wait;
> + memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v2_0_cmd_direct_polling));
> +}
> +
> +#define MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
> + mmsch_v2_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
> + init_table, (reg), \
> + (mask), (data)); \
> + init_table += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \
> + table_size += sizeof(struct mmsch_v2_0_cmd_direct_read_modify_write)/4; \
> +}
> +
> +#define MMSCH_V2_0_INSERT_DIRECT_WT(reg, value) { \
> + mmsch_v2_0_insert_direct_wt(&direct_wt, \
> + init_table, (reg), \
> + (value)); \
> + init_table += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \
> + table_size += sizeof(struct mmsch_v2_0_cmd_direct_write)/4; \
> +}
> +
> +#define MMSCH_V2_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
> + mmsch_v2_0_insert_direct_poll(&direct_poll, \
> + init_table, (reg), \
> + (mask), (wait)); \
> + init_table += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \
> + table_size += sizeof(struct mmsch_v2_0_cmd_direct_polling)/4; \
> +}
> +
> +#endif
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV
2020-03-05 13:39 ` Liu, Monk
@ 2020-03-05 16:01 ` Leo Liu
0 siblings, 0 replies; 18+ messages in thread
From: Leo Liu @ 2020-03-05 16:01 UTC (permalink / raw)
To: Liu, Monk, Koenig, Christian, amd-gfx
On 2020-03-05 8:39 a.m., Liu, Monk wrote:
> This is not supported by MMSCH FW...
With this added to commit message, this patch is:
Reviewed-by: Leo Liu <leo.liu@amd.com>
>
> _____________________________________
> Monk Liu|GPU Virtualization Team |AMD
>
>
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumerken@gmail.com>
> Sent: Thursday, March 5, 2020 9:38 PM
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Subject: Re: [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV
>
> A commit message explaining why we disable it and if it could be enabled again or if this is permanent would be nice to have.
>
> Christian.
>
> Am 05.03.20 um 14:33 schrieb Monk Liu:
>> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> b/drivers/gpu/drm/amd/amdgpu/nv.c index 2d1bebd..033cbbc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -516,7 +516,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>> !amdgpu_sriov_vf(adev))
>> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>> amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
>> - amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
>> + if (!amdgpu_sriov_vf(adev))
>> + amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
>> break;
>> default:
>> return -EINVAL;
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cleo.liu%40amd.com%7C73f28c93e88241bc4c5908d7c10a96e3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637190123555130366&sdata=CVcac9dEWc3mR0oNkcrkOTtxXqvdtjzEN78c%2FBYty8E%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 for SRIOV
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 " Monk Liu
@ 2020-03-05 16:07 ` Leo Liu
2020-03-06 2:43 ` Liu, Monk
0 siblings, 1 reply; 18+ messages in thread
From: Leo Liu @ 2020-03-05 16:07 UTC (permalink / raw)
To: Monk Liu, amd-gfx
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> one dec ring and one enc ring
It seems more than that, you might add more messages.
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 231 +++++++++++++++++++++++++++++++++-
> 1 file changed, 228 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index c387c81..421e5bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -29,6 +29,7 @@
> #include "soc15d.h"
> #include "amdgpu_pm.h"
> #include "amdgpu_psp.h"
> +#include "mmsch_v2_0.h"
>
> #include "vcn/vcn_2_0_0_offset.h"
> #include "vcn/vcn_2_0_0_sh_mask.h"
> @@ -54,7 +55,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> enum amd_powergating_state state);
> static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> -
> +static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
Please keep the empty line here.
> /**
> * vcn_v2_0_early_init - set function pointers
> *
> @@ -67,7 +68,10 @@ static int vcn_v2_0_early_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> adev->vcn.num_vcn_inst = 1;
> - adev->vcn.num_enc_rings = 2;
> + if (amdgpu_sriov_vf(adev))
> + adev->vcn.num_enc_rings = 1;
> + else
> + adev->vcn.num_enc_rings = 2;
>
> vcn_v2_0_set_dec_ring_funcs(adev);
> vcn_v2_0_set_enc_ring_funcs(adev);
> @@ -154,7 +158,10 @@ static int vcn_v2_0_sw_init(void *handle)
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> ring = &adev->vcn.inst->ring_enc[i];
> ring->use_doorbell = true;
> - ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
> + if (!amdgpu_sriov_vf(adev))
> + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
> + else
> + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
> sprintf(ring->name, "vcn_enc%d", i);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> if (r)
> @@ -163,6 +170,10 @@ static int vcn_v2_0_sw_init(void *handle)
>
> adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
>
> + r = amdgpu_virt_alloc_mm_table(adev);
> + if (r)
> + return r;
> +
This is not needed for bare metal.
> return 0;
> }
>
> @@ -178,6 +189,8 @@ static int vcn_v2_0_sw_fini(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + amdgpu_virt_free_mm_table(adev);
> +
same as above here.
Regards,
Leo
> r = amdgpu_vcn_suspend(adev);
> if (r)
> return r;
> @@ -203,6 +216,9 @@ static int vcn_v2_0_hw_init(void *handle)
> adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
> ring->doorbell_index, 0);
>
> + if (amdgpu_sriov_vf(adev))
> + vcn_v2_0_start_sriov(adev);
> +
> r = amdgpu_ring_test_helper(ring);
> if (r)
> goto done;
> @@ -1680,6 +1696,215 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> return ret;
> }
>
> +static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
> + struct amdgpu_mm_table *table)
> +{
> + uint32_t data = 0, loop;
> + uint64_t addr = table->gpu_addr;
> + struct mmsch_v2_0_init_header *header;
> + uint32_t size;
> + int i;
> +
> + header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
> + size = header->header_size + header->vcn_table_size;
> +
> + /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
> + * of memory descriptor location
> + */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
> +
> + /* 2, update vmid of descriptor */
> + data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
> + data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
> + /* use domain0 for MM scheduler */
> + data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
> +
> + /* 3, notify mmsch about the size of this descriptor */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
> +
> + /* 4, set resp to zero */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
> +
> + adev->vcn.inst->ring_dec.wptr = 0;
> + adev->vcn.inst->ring_dec.wptr_old = 0;
> + vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
> +
> + for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> + adev->vcn.inst->ring_enc[i].wptr = 0;
> + adev->vcn.inst->ring_enc[i].wptr_old = 0;
> + vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
> + }
> +
> + /* 5, kick off the initialization and wait until
> + * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
> + */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
> +
> + data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
> + loop = 1000;
> + while ((data & 0x10000002) != 0x10000002) {
> + udelay(10);
> + data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
> + loop--;
> + if (!loop)
> + break;
> + }
> +
> + if (!loop) {
> + DRM_ERROR("failed to init MMSCH, " \
> + "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
> + return -EBUSY;
> + }
> +
> + return 0;
> +}
> +
> +static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
> +{
> + int r;
> + uint32_t tmp;
> + struct amdgpu_ring *ring;
> + uint32_t offset, size;
> + uint32_t table_size = 0;
> + struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
> + struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
> + struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
> + struct mmsch_v2_0_cmd_end end = { {0} };
> + struct mmsch_v2_0_init_header *header;
> + uint32_t *init_table = adev->virt.mm_table.cpu_addr;
> + uint8_t i = 0;
> +
> + header = (struct mmsch_v2_0_init_header *)init_table;
> + direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
> + direct_rd_mod_wt.cmd_header.command_type =
> + MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
> + direct_poll.cmd_header.command_type =
> + MMSCH_COMMAND__DIRECT_REG_POLLING;
> + end.cmd_header.command_type = MMSCH_COMMAND__END;
> +
> + if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
> + header->version = MMSCH_VERSION;
> + header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
> +
> + header->vcn_table_offset = header->header_size;
> +
> + init_table += header->vcn_table_offset;
> +
> + size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> +
> + MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
> + 0xFFFFFFFF, 0x00000004);
> +
> + /* mc resume*/
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> + tmp = AMDGPU_UCODE_ID_VCN;
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + adev->firmware.ucode[tmp].tmr_mc_addr_lo);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + adev->firmware.ucode[tmp].tmr_mc_addr_hi);
> + offset = 0;
> + } else {
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + lower_32_bits(adev->vcn.inst->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + upper_32_bits(adev->vcn.inst->gpu_addr));
> + offset = size;
> + }
> +
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
> + 0);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
> + size);
> +
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> + lower_32_bits(adev->vcn.inst->gpu_addr + offset));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> + upper_32_bits(adev->vcn.inst->gpu_addr + offset));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
> + 0);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
> + AMDGPU_VCN_STACK_SIZE);
> +
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> + lower_32_bits(adev->vcn.inst->gpu_addr + offset +
> + AMDGPU_VCN_STACK_SIZE));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> + upper_32_bits(adev->vcn.inst->gpu_addr + offset +
> + AMDGPU_VCN_STACK_SIZE));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
> + 0);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
> + AMDGPU_VCN_CONTEXT_SIZE);
> +
> + for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
> + ring = &adev->vcn.inst->ring_enc[r];
> + ring->wptr = 0;
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
> + lower_32_bits(ring->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
> + upper_32_bits(ring->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
> + ring->ring_size / 4);
> + }
> +
> + ring = &adev->vcn.inst->ring_dec;
> + ring->wptr = 0;
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
> + lower_32_bits(ring->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
> + upper_32_bits(ring->gpu_addr));
> + /* force RBC into idle state */
> + tmp = order_base_2(ring->ring_size);
> + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
> +
> + /* add end packet */
> + tmp = sizeof(struct mmsch_v2_0_cmd_end);
> + memcpy((void *)init_table, &end, tmp);
> + table_size += (tmp / 4);
> + header->vcn_table_size = table_size;
> +
> + }
> + return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
> +}
> +
> static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
> .name = "vcn_v2_0",
> .early_init = vcn_v2_0_early_init,
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 4/6] drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 4/6] drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0 Monk Liu
@ 2020-03-05 16:10 ` Leo Liu
0 siblings, 0 replies; 18+ messages in thread
From: Leo Liu @ 2020-03-05 16:10 UTC (permalink / raw)
To: Monk Liu, amd-gfx
This patch is:
Reviewed-by: Leo Liu <leo.liu@amd.com>
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> support IB test on dec/enc ring
> disable ring test on dec/enc ring (MMSCH limitation)
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 11 +++--------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 +++
> 2 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index f96464e..ae9754f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -497,10 +497,6 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> struct dma_fence *fence;
> long r;
>
> - /* temporarily disable ib test for sriov */
> - if (amdgpu_sriov_vf(adev))
> - return 0;
> -
> r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
> if (r)
> goto error;
> @@ -527,6 +523,9 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
> unsigned i;
> int r;
>
> + if (amdgpu_sriov_vf(adev))
> + return 0;
> +
> r = amdgpu_ring_alloc(ring, 16);
> if (r)
> return r;
> @@ -661,10 +660,6 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> struct amdgpu_bo *bo = NULL;
> long r;
>
> - /* temporarily disable ib test for sriov */
> - if (amdgpu_sriov_vf(adev))
> - return 0;
> -
> r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM,
> &bo, NULL, NULL);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 421e5bf..dd500d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -1647,6 +1647,9 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
> unsigned i;
> int r;
>
> + if (amdgpu_sriov_vf(adev))
> + return 0;
> +
> WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 4);
> if (r)
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 5/6] drm/amdgpu: disable clock/power gating for SRIOV
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 5/6] drm/amdgpu: disable clock/power gating for SRIOV Monk Liu
@ 2020-03-05 16:11 ` Leo Liu
0 siblings, 0 replies; 18+ messages in thread
From: Leo Liu @ 2020-03-05 16:11 UTC (permalink / raw)
To: Monk Liu, amd-gfx
This patch is:
Acked-by: Leo Liu <leo.liu@amd.com>
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> and disable MC resum in VCN2.0 as well
>
> those are not concerned by VF driver
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index dd500d1..f2745fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -320,6 +320,9 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
> uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> uint32_t offset;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* cache window 0: fw */
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> @@ -464,6 +467,9 @@ static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
> {
> uint32_t data;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* UVD disable CGC */
> data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -622,6 +628,9 @@ static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
> {
> uint32_t data = 0;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> /* enable UVD CGC */
> data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
> if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
> @@ -674,6 +683,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
> uint32_t data = 0;
> int ret;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
> | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
> @@ -721,6 +733,9 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
> uint32_t data = 0;
> int ret;
>
> + if (amdgpu_sriov_vf(adev))
> + return;
> +
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> /* Before power off, this indicator has to be turned on */
> data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
> @@ -1231,6 +1246,9 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> bool enable = (state == AMD_CG_STATE_GATE);
>
> + if (amdgpu_sriov_vf(adev))
> + return 0;
> +
> if (enable) {
> /* wait for STATUS to clear */
> if (vcn_v2_0_is_idle(handle))
> @@ -1686,6 +1704,11 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + if (amdgpu_sriov_vf(adev)) {
> + adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
> + return 0;
> + }
> +
> if (state == adev->vcn.cur_state)
> return 0;
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var Monk Liu
2020-03-05 13:37 ` Christian König
@ 2020-03-05 16:16 ` Leo Liu
2020-03-06 2:43 ` Liu, Monk
1 sibling, 1 reply; 18+ messages in thread
From: Leo Liu @ 2020-03-05 16:16 UTC (permalink / raw)
To: Monk Liu, amd-gfx
Is this warning introduced by your patch 4?
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index ae9754f..a41272f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -493,7 +493,6 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> - struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence;
> long r;
>
> @@ -655,7 +654,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> - struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence = NULL;
> struct amdgpu_bo *bo = NULL;
> long r;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var
2020-03-05 16:16 ` Leo Liu
@ 2020-03-06 2:43 ` Liu, Monk
0 siblings, 0 replies; 18+ messages in thread
From: Liu, Monk @ 2020-03-06 2:43 UTC (permalink / raw)
To: Liu, Leo, amd-gfx
No, this is an existed warning
_____________________________________
Monk Liu|GPU Virtualization Team |AMD
-----Original Message-----
From: Liu, Leo <Leo.Liu@amd.com>
Sent: Friday, March 6, 2020 12:17 AM
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var
Is this warning introduced by your patch 4?
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index ae9754f..a41272f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -493,7 +493,6 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> - struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence;
> long r;
>
> @@ -655,7 +654,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> - struct amdgpu_device *adev = ring->adev;
> struct dma_fence *fence = NULL;
> struct amdgpu_bo *bo = NULL;
> long r;
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 for SRIOV
2020-03-05 16:07 ` Leo Liu
@ 2020-03-06 2:43 ` Liu, Monk
0 siblings, 0 replies; 18+ messages in thread
From: Liu, Monk @ 2020-03-06 2:43 UTC (permalink / raw)
To: Liu, Leo, amd-gfx
Okay, no problem
_____________________________________
Monk Liu|GPU Virtualization Team |AMD
-----Original Message-----
From: Liu, Leo <Leo.Liu@amd.com>
Sent: Friday, March 6, 2020 12:08 AM
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 for SRIOV
On 2020-03-05 8:33 a.m., Monk Liu wrote:
> one dec ring and one enc ring
It seems more than that, you might add more messages.
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 231 +++++++++++++++++++++++++++++++++-
> 1 file changed, 228 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index c387c81..421e5bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -29,6 +29,7 @@
> #include "soc15d.h"
> #include "amdgpu_pm.h"
> #include "amdgpu_psp.h"
> +#include "mmsch_v2_0.h"
>
> #include "vcn/vcn_2_0_0_offset.h"
> #include "vcn/vcn_2_0_0_sh_mask.h"
> @@ -54,7 +55,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> enum amd_powergating_state state);
> static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> -
> +static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
Please keep the empty line here.
> /**
> * vcn_v2_0_early_init - set function pointers
> *
> @@ -67,7 +68,10 @@ static int vcn_v2_0_early_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> adev->vcn.num_vcn_inst = 1;
> - adev->vcn.num_enc_rings = 2;
> + if (amdgpu_sriov_vf(adev))
> + adev->vcn.num_enc_rings = 1;
> + else
> + adev->vcn.num_enc_rings = 2;
>
> vcn_v2_0_set_dec_ring_funcs(adev);
> vcn_v2_0_set_enc_ring_funcs(adev);
> @@ -154,7 +158,10 @@ static int vcn_v2_0_sw_init(void *handle)
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> ring = &adev->vcn.inst->ring_enc[i];
> ring->use_doorbell = true;
> - ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
> + if (!amdgpu_sriov_vf(adev))
> + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
> + else
> + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1)
> ++ 1 + i;
> sprintf(ring->name, "vcn_enc%d", i);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> if (r)
> @@ -163,6 +170,10 @@ static int vcn_v2_0_sw_init(void *handle)
>
> adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
>
> + r = amdgpu_virt_alloc_mm_table(adev);
> + if (r)
> + return r;
> +
This is not needed for bare metal.
> return 0;
> }
>
> @@ -178,6 +189,8 @@ static int vcn_v2_0_sw_fini(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> + amdgpu_virt_free_mm_table(adev);
> +
same as above here.
Regards,
Leo
> r = amdgpu_vcn_suspend(adev);
> if (r)
> return r;
> @@ -203,6 +216,9 @@ static int vcn_v2_0_hw_init(void *handle)
> adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
> ring->doorbell_index, 0);
>
> + if (amdgpu_sriov_vf(adev))
> + vcn_v2_0_start_sriov(adev);
> +
> r = amdgpu_ring_test_helper(ring);
> if (r)
> goto done;
> @@ -1680,6 +1696,215 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> return ret;
> }
>
> +static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
> + struct amdgpu_mm_table *table)
> +{
> + uint32_t data = 0, loop;
> + uint64_t addr = table->gpu_addr;
> + struct mmsch_v2_0_init_header *header;
> + uint32_t size;
> + int i;
> +
> + header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
> + size = header->header_size + header->vcn_table_size;
> +
> + /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
> + * of memory descriptor location
> + */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
> +
> + /* 2, update vmid of descriptor */
> + data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
> + data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
> + /* use domain0 for MM scheduler */
> + data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
> +
> + /* 3, notify mmsch about the size of this descriptor */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
> +
> + /* 4, set resp to zero */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
> +
> + adev->vcn.inst->ring_dec.wptr = 0;
> + adev->vcn.inst->ring_dec.wptr_old = 0;
> + vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
> +
> + for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> + adev->vcn.inst->ring_enc[i].wptr = 0;
> + adev->vcn.inst->ring_enc[i].wptr_old = 0;
> + vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
> + }
> +
> + /* 5, kick off the initialization and wait until
> + * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
> + */
> + WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
> +
> + data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
> + loop = 1000;
> + while ((data & 0x10000002) != 0x10000002) {
> + udelay(10);
> + data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
> + loop--;
> + if (!loop)
> + break;
> + }
> +
> + if (!loop) {
> + DRM_ERROR("failed to init MMSCH, " \
> + "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
> + return -EBUSY;
> + }
> +
> + return 0;
> +}
> +
> +static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) {
> + int r;
> + uint32_t tmp;
> + struct amdgpu_ring *ring;
> + uint32_t offset, size;
> + uint32_t table_size = 0;
> + struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
> + struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
> + struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
> + struct mmsch_v2_0_cmd_end end = { {0} };
> + struct mmsch_v2_0_init_header *header;
> + uint32_t *init_table = adev->virt.mm_table.cpu_addr;
> + uint8_t i = 0;
> +
> + header = (struct mmsch_v2_0_init_header *)init_table;
> + direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
> + direct_rd_mod_wt.cmd_header.command_type =
> + MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
> + direct_poll.cmd_header.command_type =
> + MMSCH_COMMAND__DIRECT_REG_POLLING;
> + end.cmd_header.command_type = MMSCH_COMMAND__END;
> +
> + if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
> + header->version = MMSCH_VERSION;
> + header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
> +
> + header->vcn_table_offset = header->header_size;
> +
> + init_table += header->vcn_table_offset;
> +
> + size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> +
> + MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
> + 0xFFFFFFFF, 0x00000004);
> +
> + /* mc resume*/
> + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> + tmp = AMDGPU_UCODE_ID_VCN;
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + adev->firmware.ucode[tmp].tmr_mc_addr_lo);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + adev->firmware.ucode[tmp].tmr_mc_addr_hi);
> + offset = 0;
> + } else {
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + lower_32_bits(adev->vcn.inst->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + upper_32_bits(adev->vcn.inst->gpu_addr));
> + offset = size;
> + }
> +
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
> + 0);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
> + size);
> +
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> + lower_32_bits(adev->vcn.inst->gpu_addr + offset));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> + upper_32_bits(adev->vcn.inst->gpu_addr + offset));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
> + 0);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
> + AMDGPU_VCN_STACK_SIZE);
> +
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> + lower_32_bits(adev->vcn.inst->gpu_addr + offset +
> + AMDGPU_VCN_STACK_SIZE));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> + upper_32_bits(adev->vcn.inst->gpu_addr + offset +
> + AMDGPU_VCN_STACK_SIZE));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
> + 0);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
> + AMDGPU_VCN_CONTEXT_SIZE);
> +
> + for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
> + ring = &adev->vcn.inst->ring_enc[r];
> + ring->wptr = 0;
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
> + lower_32_bits(ring->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
> + upper_32_bits(ring->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
> + ring->ring_size / 4);
> + }
> +
> + ring = &adev->vcn.inst->ring_dec;
> + ring->wptr = 0;
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
> + lower_32_bits(ring->gpu_addr));
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i,
> + mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
> + upper_32_bits(ring->gpu_addr));
> + /* force RBC into idle state */
> + tmp = order_base_2(ring->ring_size);
> + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
> + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
> + MMSCH_V2_0_INSERT_DIRECT_WT(
> + SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
> +
> + /* add end packet */
> + tmp = sizeof(struct mmsch_v2_0_cmd_end);
> + memcpy((void *)init_table, &end, tmp);
> + table_size += (tmp / 4);
> + header->vcn_table_size = table_size;
> +
> + }
> + return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); }
> +
> static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
> .name = "vcn_v2_0",
> .early_init = vcn_v2_0_early_init,
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var
2020-03-05 13:37 ` Christian König
@ 2020-03-06 3:31 ` Deng, Emily
0 siblings, 0 replies; 18+ messages in thread
From: Deng, Emily @ 2020-03-06 3:31 UTC (permalink / raw)
To: Koenig, Christian, Liu, Monk, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Series reviewed-by: Emily Deng <Emily.Deng@amd.com>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>Christian König
>Sent: Thursday, March 5, 2020 9:37 PM
>To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
>Subject: Re: [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning
>on unused var
>
>Am 05.03.20 um 14:33 schrieb Monk Liu:
>> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
>
>Acked-by: Christian König <christian.koenig@amd.com>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
>> 1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>> index ae9754f..a41272f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>> @@ -493,7 +493,6 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct
>amdgpu_ring *ring, uint32_t han
>>
>> int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>> {
>> - struct amdgpu_device *adev = ring->adev;
>> struct dma_fence *fence;
>> long r;
>>
>> @@ -655,7 +654,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct
>amdgpu_ring *ring, uint32_t han
>>
>> int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>> {
>> - struct amdgpu_device *adev = ring->adev;
>> struct dma_fence *fence = NULL;
>> struct amdgpu_bo *bo = NULL;
>> long r;
>
>_______________________________________________
>amd-gfx mailing list
>amd-gfx@lists.freedesktop.org
>https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.fr
>eedesktop.org%2Fmailman%2Flistinfo%2Famd-
>gfx&data=02%7C01%7CEmily.Deng%40amd.com%7C65554a78d47c44316
>3ee08d7c10a4c0d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63
>7190122293430826&sdata=DeaDmgrUF9yqz1dTnjovIHU6UcjGX4rEy6lcyC
>hHxeA%3D&reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2020-03-06 3:31 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-05 13:33 [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Monk Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 2/6] drm/amdgpu: disable jpeg block for SRIOV Monk Liu
2020-03-05 13:37 ` Christian König
2020-03-05 13:39 ` Liu, Monk
2020-03-05 16:01 ` Leo Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 3/6] drm/amdgpu: implement initialization part on VCN2.0 " Monk Liu
2020-03-05 16:07 ` Leo Liu
2020-03-06 2:43 ` Liu, Monk
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 4/6] drm/amdgpu: cleanup ring/ib test for SRIOV vcn2.0 Monk Liu
2020-03-05 16:10 ` Leo Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 5/6] drm/amdgpu: disable clock/power gating for SRIOV Monk Liu
2020-03-05 16:11 ` Leo Liu
2020-03-05 13:33 ` [enable VCN2.0 for NV12 SRIOV 6/6] drm/amdgpu: clear warning on unused var Monk Liu
2020-03-05 13:37 ` Christian König
2020-03-06 3:31 ` Deng, Emily
2020-03-05 16:16 ` Leo Liu
2020-03-06 2:43 ` Liu, Monk
2020-03-05 15:59 ` [enable VCN2.0 for NV12 SRIOV 1/6] drm/amdgpu: introduce mmsch v2.0 header Leo Liu
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.