[PATCH v2 1/5] drm/amdgpu:add tmr mac address into amdgpu_firmware_info

[PATCH v2 1/5] drm/amdgpu:add tmr mac address into amdgpu_firmware_info

[James Zhu]

amdgpu IP blocks booting need Trust Memory Region(tmr) mac address
of its firmware which is loaded by PSP

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 11e81a3..e9d64e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -232,6 +232,9 @@ struct amdgpu_firmware_info {
 	void *kaddr;
 	/* ucode_size_bytes */
 	uint32_t ucode_size;
+	/* starting tmr mc address */
+	uint32_t tmr_mc_addr_lo;
+	uint32_t tmr_mc_addr_hi;
 };
 
 struct amdgpu_firmware {
-- 
2.7.4

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[PATCH v2 2/5] drm/amdgpu: update tmr mac address

[James Zhu]

Update tmr mac address with firmware loading address
which is returned from PSP firmware

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 9f1a5bd..5b39d13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -131,6 +131,11 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		msleep(1);
 	}
 
+	if (ucode) {
+		ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
+		ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
+	}
+
 	return ret;
 }
 
-- 
2.7.4

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[PATCH v2 3/5] drm/amdgpu:add new firmware id for VCN

[James Zhu]

From: Likun Gao <Likun.Gao@amd.com>

Add the new firmware id for VCN into the enum

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index e9d64e7..a1edc70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -194,6 +194,7 @@ enum AMDGPU_UCODE_ID {
 	AMDGPU_UCODE_ID_SMC,
 	AMDGPU_UCODE_ID_UVD,
 	AMDGPU_UCODE_ID_VCE,
+	AMDGPU_UCODE_ID_VCN,
 	AMDGPU_UCODE_ID_MAXIMUM,
 };
 
-- 
2.7.4

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[PATCH v2 4/5] drm/amdgpu:add VCN support in PSP driver

[James Zhu]

From: Likun Gao <Likun.Gao@amd.com>

Add VCN support in PSP driver

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 0ff136d..02be34e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -88,6 +88,9 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *
 	case AMDGPU_UCODE_ID_VCE:
 		*type = GFX_FW_TYPE_VCE;
 		break;
+	case AMDGPU_UCODE_ID_VCN:
+		*type = GFX_FW_TYPE_VCN;
+		break;
 	case AMDGPU_UCODE_ID_MAXIMUM:
 	default:
 		return -EINVAL;
-- 
2.7.4

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[PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

[James Zhu]

From: Likun Gao <Likun.Gao@amd.com>

Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++++++++++++++++++++++++++-------
 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 878f62c..77c192a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 			version_major, version_minor, family_id);
 	}
 
-	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
-		  +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
 		  +  AMDGPU_VCN_SESSION_SIZE * 40;
+	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
 				    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
@@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 		unsigned offset;
 
 		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-		offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-		memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
-			    le32_to_cpu(hdr->ucode_size_bytes));
-		size -= le32_to_cpu(hdr->ucode_size_bytes);
-		ptr += le32_to_cpu(hdr->ucode_size_bytes);
+		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+			offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+			memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
+				    le32_to_cpu(hdr->ucode_size_bytes));
+			size -= le32_to_cpu(hdr->ucode_size_bytes);
+			ptr += le32_to_cpu(hdr->ucode_size_bytes);
+		}
 		memset_io(ptr, 0, size);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2ce91a7..74c4ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
 	if (r)
 		return r;
 
+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+		const struct common_firmware_header *hdr;
+		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
+		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+		adev->firmware.fw_size +=
+			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+		DRM_INFO("PSP loading VCN firmware\n");
+	}
+
 	r = amdgpu_vcn_resume(adev);
 	if (r)
 		return r;
@@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
 {
 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
-
-	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+	uint32_t offset;
+
+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+		offset = 0;
+	} else {
+		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 			lower_32_bits(adev->vcn.gpu_addr));
-	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 			upper_32_bits(adev->vcn.gpu_addr));
-	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+		offset = size;
+		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 				AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+	}
+
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 
 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
-			lower_32_bits(adev->vcn.gpu_addr + size));
+			lower_32_bits(adev->vcn.gpu_addr + offset));
 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
-			upper_32_bits(adev->vcn.gpu_addr + size));
+			upper_32_bits(adev->vcn.gpu_addr + offset));
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);
 
 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
-			lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
+			lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
-			upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
+			upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
 			AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));
-- 
2.7.4

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Re: [PATCH v2 1/5] drm/amdgpu:add tmr mac address into amdgpu_firmware_info

[Huang Rui]

On Fri, Aug 10, 2018 at 12:31:38AM +0800, James Zhu wrote:
> amdgpu IP blocks booting need Trust Memory Region(tmr) mac address
> of its firmware which is loaded by PSP
> 
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

For series:
Acked-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> index 11e81a3..e9d64e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
> @@ -232,6 +232,9 @@ struct amdgpu_firmware_info {
>  	void *kaddr;
>  	/* ucode_size_bytes */
>  	uint32_t ucode_size;
> +	/* starting tmr mc address */
> +	uint32_t tmr_mc_addr_lo;
> +	uint32_t tmr_mc_addr_hi;
>  };
>  
>  struct amdgpu_firmware {
> -- 
> 2.7.4
> 
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RE: [PATCH v2 1/5] drm/amdgpu:add tmr mac address into amdgpu_firmware_info

[Gao, Likun]

For series:
Review-by: Likun Gao <likun.gao@amd.com>

Thanks for all your efforts and will apply those patch to pco topic branch

Regards,
Likun

-----Original Message-----
From: James Zhu <jzhums@gmail.com> 
Sent: Friday, August 10, 2018 12:32 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Gao, Likun <Likun.Gao@amd.com>; Huang, Ray <Ray.Huang@amd.com>
Subject: [PATCH v2 1/5] drm/amdgpu:add tmr mac address into amdgpu_firmware_info

amdgpu IP blocks booting need Trust Memory Region(tmr) mac address of its firmware which is loaded by PSP

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 11e81a3..e9d64e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -232,6 +232,9 @@ struct amdgpu_firmware_info {
 	void *kaddr;
 	/* ucode_size_bytes */
 	uint32_t ucode_size;
+	/* starting tmr mc address */
+	uint32_t tmr_mc_addr_lo;
+	uint32_t tmr_mc_addr_hi;
 };
 
 struct amdgpu_firmware {
--
2.7.4

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Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 7106 bytes --]

Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new tmr_mc_addr? And the mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH and mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH still use the old adev->vcn.gpu_addr?


Regards,

Evan

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of James Zhu <jzhums-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Friday, August 10, 2018 12:31:42 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
Subject: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

From: Likun Gao <Likun.Gao-5C7GfCeVMHo@public.gmane.org>

Setup psp firmware loading for VCN, and make VCN block
booting from tmr mac address.

Signed-off-by: James Zhu <James.Zhu-5C7GfCeVMHo@public.gmane.org>
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++++++++++++++++++++++++++-------
 2 files changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 878f62c..77c192a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
                         version_major, version_minor, family_id);
         }

-       bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
-                 +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+       bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
                   +  AMDGPU_VCN_SESSION_SIZE * 40;
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+               bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
                                     &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
@@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
                 unsigned offset;

                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-               offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-               memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
-                           le32_to_cpu(hdr->ucode_size_bytes));
-               size -= le32_to_cpu(hdr->ucode_size_bytes);
-               ptr += le32_to_cpu(hdr->ucode_size_bytes);
+               if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+                       offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+                       memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
+                                   le32_to_cpu(hdr->ucode_size_bytes));
+                       size -= le32_to_cpu(hdr->ucode_size_bytes);
+                       ptr += le32_to_cpu(hdr->ucode_size_bytes);
+               }
                 memset_io(ptr, 0, size);
         }

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2ce91a7..74c4ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
         if (r)
                 return r;

+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+               const struct common_firmware_header *hdr;
+               hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+               adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
+               adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
+               adev->firmware.fw_size +=
+                       ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+               DRM_INFO("PSP loading VCN firmware\n");
+       }
+
         r = amdgpu_vcn_resume(adev);
         if (r)
                 return r;
@@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
 static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
 {
         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
-
-       WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+       uint32_t offset;
+
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+                       (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
+               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+                       (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
+               WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
+               offset = 0;
+       } else {
+               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
                         lower_32_bits(adev->vcn.gpu_addr));
-       WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
                         upper_32_bits(adev->vcn.gpu_addr));
-       WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
+               offset = size;
+               WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+       }
+
         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
-                       lower_32_bits(adev->vcn.gpu_addr + size));
+                       lower_32_bits(adev->vcn.gpu_addr + offset));
         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
-                       upper_32_bits(adev->vcn.gpu_addr + size));
+                       upper_32_bits(adev->vcn.gpu_addr + offset));
         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);

         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
-                       lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
+                       lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
-                       upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
+                       upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
                         AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));
--
2.7.4

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Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

[James Zhu]

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PSP engine only allocate space for firmware. 
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH is for firmware TMR address.

The other two address are for HEAP/Session.


Regards!

James Zhu


On 2018-08-13 12:16 AM, Quan, Evan wrote:
>
> Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new 
> tmr_mc_addr? And the mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH and 
> mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH still use the old 
> adev->vcn.gpu_addr?
>
>
> Regards,
>
> Evan
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of 
> James Zhu <jzhums-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> *Sent:* Friday, August 10, 2018 12:31:42 AM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Cc:* Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
> *Subject:* [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware 
> loaded by PSP
> From: Likun Gao <Likun.Gao-5C7GfCeVMHo@public.gmane.org>
>
> Setup psp firmware loading for VCN, and make VCN block
> booting from tmr mac address.
>
> Signed-off-by: James Zhu <James.Zhu-5C7GfCeVMHo@public.gmane.org>
> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 
> ++++++++++++++++++++++++++-------
>  2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 878f62c..77c192a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>                          version_major, version_minor, family_id);
>          }
>
> -       bo_size = 
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -                 +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> +       bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
>                    +  AMDGPU_VCN_SESSION_SIZE * 40;
> +       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> +               bo_size += 
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>          r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
> &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
>                  unsigned offset;
>
>                  hdr = (const struct common_firmware_header 
> *)adev->vcn.fw->data;
> -               offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> -               memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + 
> offset,
> - le32_to_cpu(hdr->ucode_size_bytes));
> -               size -= le32_to_cpu(hdr->ucode_size_bytes);
> -               ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +               if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> +                       offset = 
> le32_to_cpu(hdr->ucode_array_offset_bytes);
> +                       memcpy_toio(adev->vcn.cpu_addr, 
> adev->vcn.fw->data + offset,
> + le32_to_cpu(hdr->ucode_size_bytes));
> +                       size -= le32_to_cpu(hdr->ucode_size_bytes);
> +                       ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +               }
>                  memset_io(ptr, 0, size);
>          }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 2ce91a7..74c4ef4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
>          if (r)
>                  return r;
>
> +       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +               const struct common_firmware_header *hdr;
> +               hdr = (const struct common_firmware_header 
> *)adev->vcn.fw->data;
> + adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = 
> AMDGPU_UCODE_ID_VCN;
> + adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> +               adev->firmware.fw_size +=
> + ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> +               DRM_INFO("PSP loading VCN firmware\n");
> +       }
> +
>          r = amdgpu_vcn_resume(adev);
>          if (r)
>                  return r;
> @@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
>  static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
>  {
>          uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> -
> -       WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +       uint32_t offset;
> +
> +       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
> +               WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
> +               offset = 0;
> +       } else {
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> lower_32_bits(adev->vcn.gpu_addr));
> -       WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +               WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> upper_32_bits(adev->vcn.gpu_addr));
> -       WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> +               offset = size;
> +               WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> +       }
> +
>          WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
>
>          WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
> - lower_32_bits(adev->vcn.gpu_addr + size));
> + lower_32_bits(adev->vcn.gpu_addr + offset));
>          WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
> - upper_32_bits(adev->vcn.gpu_addr + size));
> + upper_32_bits(adev->vcn.gpu_addr + offset));
>          WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
>          WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, 
> AMDGPU_VCN_HEAP_SIZE);
>
>          WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
> - lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> + lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>          WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
> - upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> + upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>          WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
>          WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
>                          AMDGPU_VCN_STACK_SIZE + 
> (AMDGPU_VCN_SESSION_SIZE * 40));
> -- 
> 2.7.4
>
> _______________________________________________
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> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
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Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

[Felix Kuehling]

ROCm CQE is seeing what looks like hangs during amdgpu initialization on
Raven and Vega20. Amdgpu basically stops printing messages while trying
to load VCN firmware. It never completes initialization, but there is no
obvious error message. These are the last messages from amdgpu in the log:

[    1.282661] [drm] Found VCN firmware Version: 1.24 Family ID: 18
[    1.282664] [drm] PSP loading VCN firmware
[    1.303164] [drm] reserve 0x400000 from 0xf400e00000 for PSP TMR SIZE

Any applications trying to use /dev/dri/* hang with a backtrace like below.

Was this change expected to affect Raven and Vega20? Has it been tested
before submitting? Do we need updated VCN firmware for it to work?

Thanks,
  Felix

[  363.352985] INFO: task gpu-manager:937 blocked for more than 120 seconds.
[  363.352995]       Not tainted 4.18.0-rc1-kfd-compute-roc-master-8912 #1
[  363.352999] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[  363.353004] gpu-manager     D    0   937      1 0x00000000
[  363.353008] Call Trace:
[  363.353018]  ? __schedule+0x3d9/0x8b0
[  363.353023]  schedule+0x32/0x80
[  363.353026]  schedule_preempt_disabled+0xa/0x10
[  363.353028]  __mutex_lock.isra.4+0x2ae/0x4e0
[  363.353031]  ? _cond_resched+0x16/0x40
[  363.353048]  ? drm_stub_open+0x2e/0x100 [drm]
[  363.353063]  drm_stub_open+0x2e/0x100 [drm]
[  363.353069]  chrdev_open+0xbe/0x1a0
[  363.353072]  ? cdev_put+0x20/0x20
[  363.353075]  do_dentry_open+0x1e2/0x300
[  363.353078]  path_openat+0x2b4/0x14b0
[  363.353082]  ? vsnprintf+0x230/0x4c0
[  363.353086]  ? __alloc_pages_nodemask+0x100/0x290
[  363.353088]  do_filp_open+0x99/0x110
[  363.353092]  ? generic_update_time+0x6a/0xc0
[  363.353094]  ? touch_atime+0xc1/0xd0
[  363.353096]  ? _cond_resched+0x16/0x40
[  363.353100]  ? do_sys_open+0x126/0x210
[  363.353102]  do_sys_open+0x126/0x210
[  363.353106]  do_syscall_64+0x4f/0x100
[  363.353110]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  363.353113] RIP: 0033:0x7f988f340040
[  363.353113] Code: Bad RIP value.
[  363.353120] RSP: 002b:00007ffecdefe618 EFLAGS: 00000246 ORIG_RAX: 0000000000000002
[  363.353123] RAX: ffffffffffffffda RBX: 0000000002337cd0 RCX: 00007f988f340040
[  363.353124] RDX: 00007ffecdefe67e RSI: 0000000000000002 RDI: 00007ffecdefe670
[  363.353125] RBP: 00007ffecdefe6a0 R08: 0000000000000000 R09: 000000000000000e
[  363.353126] R10: 000000000000069d R11: 0000000000000246 R12: 0000000000401b40
[  363.353127] R13: 00007ffecdefe910 R14: 0000000000000000 R15: 0000000000000000



On 2018-08-09 12:31 PM, James Zhu wrote:
> From: Likun Gao <Likun.Gao@amd.com>
>
> Setup psp firmware loading for VCN, and make VCN block
> booting from tmr mac address.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++++++++++++++++++++++++++-------
>  2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 878f62c..77c192a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>  			version_major, version_minor, family_id);
>  	}
>  
> -	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -		  +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> +	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
>  		  +  AMDGPU_VCN_SESSION_SIZE * 40;
> +	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> +		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>  	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>  				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
>  				    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
>  		unsigned offset;
>  
>  		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -		offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> -		memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> -			    le32_to_cpu(hdr->ucode_size_bytes));
> -		size -= le32_to_cpu(hdr->ucode_size_bytes);
> -		ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> +			offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> +			memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> +				    le32_to_cpu(hdr->ucode_size_bytes));
> +			size -= le32_to_cpu(hdr->ucode_size_bytes);
> +			ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +		}
>  		memset_io(ptr, 0, size);
>  	}
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 2ce91a7..74c4ef4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
>  	if (r)
>  		return r;
>  
> +	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +		const struct common_firmware_header *hdr;
> +		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> +		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
> +		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> +		adev->firmware.fw_size +=
> +			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> +		DRM_INFO("PSP loading VCN firmware\n");
> +	}
> +
>  	r = amdgpu_vcn_resume(adev);
>  	if (r)
>  		return r;
> @@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
>  static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
>  {
>  	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> -
> -	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +	uint32_t offset;
> +
> +	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> +		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
> +		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
> +		offset = 0;
> +	} else {
> +		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>  			lower_32_bits(adev->vcn.gpu_addr));
> -	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>  			upper_32_bits(adev->vcn.gpu_addr));
> -	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> +		offset = size;
> +		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
>  				AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> +	}
> +
>  	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
>  
>  	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
> -			lower_32_bits(adev->vcn.gpu_addr + size));
> +			lower_32_bits(adev->vcn.gpu_addr + offset));
>  	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
> -			upper_32_bits(adev->vcn.gpu_addr + size));
> +			upper_32_bits(adev->vcn.gpu_addr + offset));
>  	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
>  	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);
>  
>  	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
> -			lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> +			lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>  	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
> -			upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> +			upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>  	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
>  	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
>  			AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));

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Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

[Zhu, James]

[-- Attachment #1.1: Type: text/plain, Size: 9822 bytes --]

Hi Felix,


We did test on both China team and Makham team. Also Embedded team did the test also on release 18.20 for Raven.


Please let ROCm CQE team issue a JIRA ticket and the detail reproduce step.


Thanks & Best Regards!


James Zhu

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Felix Kuehling <felix.kuehling-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 17, 2018 7:25:53 PM
To: James Zhu; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
Subject: Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

ROCm CQE is seeing what looks like hangs during amdgpu initialization on
Raven and Vega20. Amdgpu basically stops printing messages while trying
to load VCN firmware. It never completes initialization, but there is no
obvious error message. These are the last messages from amdgpu in the log:

[    1.282661] [drm] Found VCN firmware Version: 1.24 Family ID: 18
[    1.282664] [drm] PSP loading VCN firmware
[    1.303164] [drm] reserve 0x400000 from 0xf400e00000 for PSP TMR SIZE

Any applications trying to use /dev/dri/* hang with a backtrace like below.

Was this change expected to affect Raven and Vega20? Has it been tested
before submitting? Do we need updated VCN firmware for it to work?

Thanks,
  Felix

[  363.352985] INFO: task gpu-manager:937 blocked for more than 120 seconds.
[  363.352995]       Not tainted 4.18.0-rc1-kfd-compute-roc-master-8912 #1
[  363.352999] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[  363.353004] gpu-manager     D    0   937      1 0x00000000
[  363.353008] Call Trace:
[  363.353018]  ? __schedule+0x3d9/0x8b0
[  363.353023]  schedule+0x32/0x80
[  363.353026]  schedule_preempt_disabled+0xa/0x10
[  363.353028]  __mutex_lock.isra.4+0x2ae/0x4e0
[  363.353031]  ? _cond_resched+0x16/0x40
[  363.353048]  ? drm_stub_open+0x2e/0x100 [drm]
[  363.353063]  drm_stub_open+0x2e/0x100 [drm]
[  363.353069]  chrdev_open+0xbe/0x1a0
[  363.353072]  ? cdev_put+0x20/0x20
[  363.353075]  do_dentry_open+0x1e2/0x300
[  363.353078]  path_openat+0x2b4/0x14b0
[  363.353082]  ? vsnprintf+0x230/0x4c0
[  363.353086]  ? __alloc_pages_nodemask+0x100/0x290
[  363.353088]  do_filp_open+0x99/0x110
[  363.353092]  ? generic_update_time+0x6a/0xc0
[  363.353094]  ? touch_atime+0xc1/0xd0
[  363.353096]  ? _cond_resched+0x16/0x40
[  363.353100]  ? do_sys_open+0x126/0x210
[  363.353102]  do_sys_open+0x126/0x210
[  363.353106]  do_syscall_64+0x4f/0x100
[  363.353110]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  363.353113] RIP: 0033:0x7f988f340040
[  363.353113] Code: Bad RIP value.
[  363.353120] RSP: 002b:00007ffecdefe618 EFLAGS: 00000246 ORIG_RAX: 0000000000000002
[  363.353123] RAX: ffffffffffffffda RBX: 0000000002337cd0 RCX: 00007f988f340040
[  363.353124] RDX: 00007ffecdefe67e RSI: 0000000000000002 RDI: 00007ffecdefe670
[  363.353125] RBP: 00007ffecdefe6a0 R08: 0000000000000000 R09: 000000000000000e
[  363.353126] R10: 000000000000069d R11: 0000000000000246 R12: 0000000000401b40
[  363.353127] R13: 00007ffecdefe910 R14: 0000000000000000 R15: 0000000000000000



On 2018-08-09 12:31 PM, James Zhu wrote:
> From: Likun Gao <Likun.Gao-5C7GfCeVMHo@public.gmane.org>
>
> Setup psp firmware loading for VCN, and make VCN block
> booting from tmr mac address.
>
> Signed-off-by: James Zhu <James.Zhu-5C7GfCeVMHo@public.gmane.org>
> Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 38 ++++++++++++++++++++++++++-------
>  2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 878f62c..77c192a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
>                        version_major, version_minor, family_id);
>        }
>
> -     bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -               +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> +     bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
>                  +  AMDGPU_VCN_SESSION_SIZE * 40;
> +     if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> +             bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>        r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>                                    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
>                                    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
>                unsigned offset;
>
>                hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -             offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> -             memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> -                         le32_to_cpu(hdr->ucode_size_bytes));
> -             size -= le32_to_cpu(hdr->ucode_size_bytes);
> -             ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +             if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> +                     offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> +                     memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
> +                                 le32_to_cpu(hdr->ucode_size_bytes));
> +                     size -= le32_to_cpu(hdr->ucode_size_bytes);
> +                     ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +             }
>                memset_io(ptr, 0, size);
>        }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 2ce91a7..74c4ef4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
>        if (r)
>                return r;
>
> +     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +             const struct common_firmware_header *hdr;
> +             hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> +             adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
> +             adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> +             adev->firmware.fw_size +=
> +                     ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> +             DRM_INFO("PSP loading VCN firmware\n");
> +     }
> +
>        r = amdgpu_vcn_resume(adev);
>        if (r)
>                return r;
> @@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
>  static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
>  {
>        uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> -
> -     WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +     uint32_t offset;
> +
> +     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +             WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +                     (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> +             WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +                     (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
> +             WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
> +             offset = 0;
> +     } else {
> +             WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>                        lower_32_bits(adev->vcn.gpu_addr));
> -     WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +             WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>                        upper_32_bits(adev->vcn.gpu_addr));
> -     WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> +             offset = size;
> +             WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
>                                AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> +     }
> +
>        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
>
>        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
> -                     lower_32_bits(adev->vcn.gpu_addr + size));
> +                     lower_32_bits(adev->vcn.gpu_addr + offset));
>        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
> -                     upper_32_bits(adev->vcn.gpu_addr + size));
> +                     upper_32_bits(adev->vcn.gpu_addr + offset));
>        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
>        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);
>
>        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
> -                     lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> +                     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
> -                     upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> +                     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
>        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
>        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
>                        AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));

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Re: [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware loaded by PSP

[Michel Dänzer]

On 2018-08-18 01:25 AM, Felix Kuehling wrote:
> ROCm CQE is seeing what looks like hangs during amdgpu initialization on
> Raven and Vega20. Amdgpu basically stops printing messages while trying
> to load VCN firmware. It never completes initialization, but there is no
> obvious error message.

What does "never" mean exactly? :) I.e. how long have you waited?

If it does continue after a few minutes, it sounds like the firmware
isn't available in the same place where the driver is loaded from, i.e.
either the driver is loaded from initrd but the firmware isn't available
there, or the driver is built into the kernel, but the firmware isn't
built into the kernel.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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