* [PATCH v4 0/5] dp8393x: fixes and improvements
@ 2021-07-11 10:36 Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 1/5] dp8393x: Replace address_space_rw(is_write=1) by address_space_write() Philippe Mathieu-Daudé
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 10:36 UTC (permalink / raw)
To: qemu-devel
Cc: Finn Thain, Jason Wang, Mark Cave-Ayland, Laurent Vivier,
Philippe Mathieu-Daudé,
Hervé Poussineau
Hi Mark,
This should be the last respin.
Since v3:
- dropped worrying patches
- squashed migration patch
- added tags
Patch #3 (dp8393x: Store CAM registers as 16-bit) still
misses your S-o-b tag.
Based-on mips-next.
Mark Cave-Ayland (1):
dp8393x: don't force 32-bit register access
Philippe Mathieu-Daudé (4):
dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition
dp8393x: Store CAM registers as 16-bit
dp8393x: Rewrite dp8393x_get() / dp8393x_put()
hw/net/dp8393x.c | 206 ++++++++++++++++++++---------------------------
1 file changed, 87 insertions(+), 119 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/5] dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
@ 2021-07-11 10:36 ` Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 2/5] dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition Philippe Mathieu-Daudé
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 10:36 UTC (permalink / raw)
To: qemu-devel
Cc: Finn Thain, Jason Wang, Mark Cave-Ayland, Laurent Vivier,
Philippe Mathieu-Daudé,
Hervé Poussineau
Replace address_space_rw(is_write=1) by address_space_write()
and remove pointless cast.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-2-f4bug@amsat.org>
---
hw/net/dp8393x.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 11810c9b600..9118364aa33 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -816,8 +816,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * width;
address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
dp8393x_put(s, width, 0, 0);
- address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)s->data, size, 1);
+ address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
+ s->data, size);
/* Move to next descriptor */
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
@@ -846,8 +846,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Pad short packets to keep pointers aligned */
if (rx_len < padded_len) {
size = padded_len - rx_len;
- address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- (uint8_t *)"\xFF\xFF\xFF", size, 1);
+ address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
+ "\xFF\xFF\xFF", size);
address += size;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/5] dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 1/5] dp8393x: Replace address_space_rw(is_write=1) by address_space_write() Philippe Mathieu-Daudé
@ 2021-07-11 10:36 ` Philippe Mathieu-Daudé
2021-07-11 19:50 ` Mark Cave-Ayland
2021-07-11 10:36 ` [PATCH v4 3/5] dp8393x: Store CAM registers as 16-bit Philippe Mathieu-Daudé
` (4 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 10:36 UTC (permalink / raw)
To: qemu-devel
Cc: Finn Thain, Jason Wang, Mark Cave-Ayland, Laurent Vivier,
Philippe Mathieu-Daudé,
Hervé Poussineau
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-3-f4bug@amsat.org>
---
hw/net/dp8393x.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 9118364aa33..d1e147a82a6 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -85,6 +85,7 @@ static const char *reg_names[] = {
#define SONIC_MPT 0x2e
#define SONIC_MDT 0x2f
#define SONIC_DCR2 0x3f
+#define SONIC_REG_COUNT 0x40
#define SONIC_CR_HTX 0x0001
#define SONIC_CR_TXP 0x0002
@@ -158,7 +159,7 @@ struct dp8393xState {
/* Registers */
uint8_t cam[16][6];
- uint16_t regs[0x40];
+ uint16_t regs[SONIC_REG_COUNT];
/* Temporaries */
uint8_t tx_buffer[0x10000];
@@ -972,7 +973,7 @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
address_space_init(&s->as, s->dma_mr, "dp8393x");
memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
- "dp8393x-regs", 0x40 << s->it_shift);
+ "dp8393x-regs", SONIC_REG_COUNT << s->it_shift);
s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id, s);
@@ -987,7 +988,7 @@ static const VMStateDescription vmstate_dp8393x = {
.minimum_version_id = 0,
.fields = (VMStateField []) {
VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
- VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
+ VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT),
VMSTATE_END_OF_LIST()
}
};
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 3/5] dp8393x: Store CAM registers as 16-bit
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 1/5] dp8393x: Replace address_space_rw(is_write=1) by address_space_write() Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 2/5] dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition Philippe Mathieu-Daudé
@ 2021-07-11 10:36 ` Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 4/5] dp8393x: Rewrite dp8393x_get() / dp8393x_put() Philippe Mathieu-Daudé
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 10:36 UTC (permalink / raw)
To: qemu-devel
Cc: Finn Thain, Jason Wang, Mark Cave-Ayland, Laurent Vivier,
Philippe Mathieu-Daudé,
Hervé Poussineau
Per the DP83932C datasheet from July 1995:
4.0 SONIC Registers
4.1 THE CAM UNIT
The Content Addressable Memory (CAM) consists of sixteen
48-bit entries for complete address filtering of network
packets. Each entry corresponds to a 48-bit destination
address that is user programmable and can contain any
combination of Multicast or Physical addresses. Each entry
is partitioned into three 16-bit CAM cells accessible
through CAM Address Ports (CAP 2, CAP 1 and CAP 0) with
CAP0 corresponding to the least significant 16 bits of
the Destination Address and CAP2 corresponding to the
most significant bits.
Store the CAM registers as 16-bit as it simplifies the code.
Having now the CAM registers as arrays of 3 uint16_t, we can avoid
using the VMSTATE_BUFFER_UNSAFE macro by using VMSTATE_UINT16_2DARRAY
which is more appropriate. This breaks the migration stream however.
Co-developed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-5-f4bug@amsat.org>
---
Missing:
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/net/dp8393x.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index d1e147a82a6..283de9db0bf 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -158,7 +158,7 @@ struct dp8393xState {
MemoryRegion mmio;
/* Registers */
- uint8_t cam[16][6];
+ uint16_t cam[16][3];
uint16_t regs[SONIC_REG_COUNT];
/* Temporaries */
@@ -281,15 +281,13 @@ static void dp8393x_do_load_cam(dp8393xState *s)
address_space_read(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, s->data, size);
index = dp8393x_get(s, width, 0) & 0xf;
- s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
- s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
- s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
- s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
- s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
- s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
- trace_dp8393x_load_cam(index, s->cam[index][0], s->cam[index][1],
- s->cam[index][2], s->cam[index][3],
- s->cam[index][4], s->cam[index][5]);
+ s->cam[index][0] = dp8393x_get(s, width, 1);
+ s->cam[index][1] = dp8393x_get(s, width, 2);
+ s->cam[index][2] = dp8393x_get(s, width, 3);
+ trace_dp8393x_load_cam(index,
+ s->cam[index][0] >> 8, s->cam[index][0] & 0xff,
+ s->cam[index][1] >> 8, s->cam[index][1] & 0xff,
+ s->cam[index][2] >> 8, s->cam[index][2] & 0xff);
/* Move to next entry */
s->regs[SONIC_CDC]--;
s->regs[SONIC_CDP] += size;
@@ -592,8 +590,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
case SONIC_CAP1:
case SONIC_CAP0:
if (s->regs[SONIC_CR] & SONIC_CR_RST) {
- val = s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg) + 1] << 8;
- val |= s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg)];
+ val = s->cam[s->regs[SONIC_CEP] & 0xf][SONIC_CAP0 - reg];
}
break;
/* All other registers have no special contraints */
@@ -984,10 +981,10 @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
static const VMStateDescription vmstate_dp8393x = {
.name = "dp8393x",
- .version_id = 0,
- .minimum_version_id = 0,
+ .version_id = 1,
+ .minimum_version_id = 1,
.fields = (VMStateField []) {
- VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
+ VMSTATE_UINT16_2DARRAY(cam, dp8393xState, 16, 3),
VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT),
VMSTATE_END_OF_LIST()
}
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 4/5] dp8393x: Rewrite dp8393x_get() / dp8393x_put()
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-07-11 10:36 ` [PATCH v4 3/5] dp8393x: Store CAM registers as 16-bit Philippe Mathieu-Daudé
@ 2021-07-11 10:36 ` Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 5/5] dp8393x: don't force 32-bit register access Philippe Mathieu-Daudé
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 10:36 UTC (permalink / raw)
To: qemu-devel
Cc: Finn Thain, Jason Wang, Mark Cave-Ayland, Laurent Vivier,
Philippe Mathieu-Daudé,
Hervé Poussineau
Instead of accessing N registers via a single address_space API
call using a temporary buffer (stored in the device state) and
updating each register, move the address_space call in the
register put/get. The load/store and word size checks are moved
to put/get too. This simplifies a bit, making the code easier
to read.
Co-developed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-8-f4bug@amsat.org>
---
hw/net/dp8393x.c | 160 +++++++++++++++++++----------------------------
1 file changed, 63 insertions(+), 97 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 283de9db0bf..4057a263de3 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -163,7 +163,6 @@ struct dp8393xState {
/* Temporaries */
uint8_t tx_buffer[0x10000];
- uint16_t data[12];
int loopback_packet;
/* Memory access */
@@ -220,34 +219,48 @@ static uint32_t dp8393x_wt(dp8393xState *s)
return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
}
-static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
+static uint16_t dp8393x_get(dp8393xState *s, hwaddr addr, int offset)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint16_t val;
- if (s->big_endian) {
- val = be16_to_cpu(s->data[offset * width + width - 1]);
+ if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
+ addr += offset << 2;
+ if (s->big_endian) {
+ val = address_space_ldl_be(&s->as, addr, attrs, NULL);
+ } else {
+ val = address_space_ldl_le(&s->as, addr, attrs, NULL);
+ }
} else {
- val = le16_to_cpu(s->data[offset * width]);
+ addr += offset << 1;
+ if (s->big_endian) {
+ val = address_space_lduw_be(&s->as, addr, attrs, NULL);
+ } else {
+ val = address_space_lduw_le(&s->as, addr, attrs, NULL);
+ }
}
+
return val;
}
-static void dp8393x_put(dp8393xState *s, int width, int offset,
- uint16_t val)
+static void dp8393x_put(dp8393xState *s,
+ hwaddr addr, int offset, uint16_t val)
{
- if (s->big_endian) {
- if (width == 2) {
- s->data[offset * 2] = 0;
- s->data[offset * 2 + 1] = cpu_to_be16(val);
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
+
+ if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
+ addr += offset << 2;
+ if (s->big_endian) {
+ address_space_stl_be(&s->as, addr, val, attrs, NULL);
} else {
- s->data[offset] = cpu_to_be16(val);
+ address_space_stl_le(&s->as, addr, val, attrs, NULL);
}
} else {
- if (width == 2) {
- s->data[offset * 2] = cpu_to_le16(val);
- s->data[offset * 2 + 1] = 0;
+ addr += offset << 1;
+ if (s->big_endian) {
+ address_space_stw_be(&s->as, addr, val, attrs, NULL);
} else {
- s->data[offset] = cpu_to_le16(val);
+ address_space_stw_le(&s->as, addr, val, attrs, NULL);
}
}
}
@@ -278,12 +291,10 @@ static void dp8393x_do_load_cam(dp8393xState *s)
while (s->regs[SONIC_CDC] & 0x1f) {
/* Fill current entry */
- address_space_read(&s->as, dp8393x_cdp(s),
- MEMTXATTRS_UNSPECIFIED, s->data, size);
- index = dp8393x_get(s, width, 0) & 0xf;
- s->cam[index][0] = dp8393x_get(s, width, 1);
- s->cam[index][1] = dp8393x_get(s, width, 2);
- s->cam[index][2] = dp8393x_get(s, width, 3);
+ index = dp8393x_get(s, dp8393x_cdp(s), 0) & 0xf;
+ s->cam[index][0] = dp8393x_get(s, dp8393x_cdp(s), 1);
+ s->cam[index][1] = dp8393x_get(s, dp8393x_cdp(s), 2);
+ s->cam[index][2] = dp8393x_get(s, dp8393x_cdp(s), 3);
trace_dp8393x_load_cam(index,
s->cam[index][0] >> 8, s->cam[index][0] & 0xff,
s->cam[index][1] >> 8, s->cam[index][1] & 0xff,
@@ -294,9 +305,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
}
/* Read CAM enable */
- address_space_read(&s->as, dp8393x_cdp(s),
- MEMTXATTRS_UNSPECIFIED, s->data, size);
- s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
+ s->regs[SONIC_CE] = dp8393x_get(s, dp8393x_cdp(s), 0);
trace_dp8393x_load_cam_done(s->regs[SONIC_CE]);
/* Done */
@@ -312,14 +321,12 @@ static void dp8393x_do_read_rra(dp8393xState *s)
/* Read memory */
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
size = sizeof(uint16_t) * 4 * width;
- address_space_read(&s->as, dp8393x_rrp(s),
- MEMTXATTRS_UNSPECIFIED, s->data, size);
/* Update SONIC registers */
- s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
- s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
- s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
- s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
+ s->regs[SONIC_CRBA0] = dp8393x_get(s, dp8393x_rrp(s), 0);
+ s->regs[SONIC_CRBA1] = dp8393x_get(s, dp8393x_rrp(s), 1);
+ s->regs[SONIC_RBWC0] = dp8393x_get(s, dp8393x_rrp(s), 2);
+ s->regs[SONIC_RBWC1] = dp8393x_get(s, dp8393x_rrp(s), 3);
trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
@@ -415,28 +422,22 @@ static void dp8393x_do_receiver_disable(dp8393xState *s)
static void dp8393x_do_transmit_packets(dp8393xState *s)
{
NetClientState *nc = qemu_get_queue(s->nic);
- int width, size;
int tx_len, len;
uint16_t i;
- width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
-
while (1) {
/* Read memory */
- size = sizeof(uint16_t) * 6 * width;
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
trace_dp8393x_transmit_packet(dp8393x_ttda(s));
- address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
- MEMTXATTRS_UNSPECIFIED, s->data, size);
tx_len = 0;
/* Update registers */
- s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
- s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
- s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
- s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
- s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
- s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
+ s->regs[SONIC_TCR] = dp8393x_get(s, dp8393x_ttda(s), 1) & 0xf000;
+ s->regs[SONIC_TPS] = dp8393x_get(s, dp8393x_ttda(s), 2);
+ s->regs[SONIC_TFC] = dp8393x_get(s, dp8393x_ttda(s), 3);
+ s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s), 4);
+ s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s), 5);
+ s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s), 6);
/* Handle programmable interrupt */
if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
@@ -458,15 +459,12 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
i++;
if (i != s->regs[SONIC_TFC]) {
/* Read next fragment details */
- size = sizeof(uint16_t) * 3 * width;
- address_space_read(&s->as,
- dp8393x_ttda(s)
- + sizeof(uint16_t) * width * (4 + 3 * i),
- MEMTXATTRS_UNSPECIFIED, s->data,
- size);
- s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
- s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
- s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
+ s->regs[SONIC_TSA0] = dp8393x_get(s, dp8393x_ttda(s),
+ 4 + 3 * i);
+ s->regs[SONIC_TSA1] = dp8393x_get(s, dp8393x_ttda(s),
+ 5 + 3 * i);
+ s->regs[SONIC_TFS] = dp8393x_get(s, dp8393x_ttda(s),
+ 6 + 3 * i);
}
}
@@ -499,22 +497,12 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
/* Write status */
- dp8393x_put(s, width, 0,
- s->regs[SONIC_TCR] & 0x0fff); /* status */
- size = sizeof(uint16_t) * width;
- address_space_write(&s->as, dp8393x_ttda(s),
- MEMTXATTRS_UNSPECIFIED, s->data, size);
+ dp8393x_put(s, dp8393x_ttda(s), 0, s->regs[SONIC_TCR] & 0x0fff);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
- size = sizeof(uint16_t) * width;
- address_space_read(&s->as,
- dp8393x_ttda(s)
- + sizeof(uint16_t) * width
- * (4 + 3 * s->regs[SONIC_TFC]),
- MEMTXATTRS_UNSPECIFIED, s->data,
- size);
- s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
+ s->regs[SONIC_CTDA] = dp8393x_get(s, dp8393x_ttda(s),
+ 4 + 3 * s->regs[SONIC_TFC]);
if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
/* EOL detected */
break;
@@ -762,7 +750,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
dp8393xState *s = qemu_get_nic_opaque(nc);
int packet_type;
uint32_t available, address;
- int width, rx_len, padded_len;
+ int rx_len, padded_len;
uint32_t checksum;
int size;
@@ -775,10 +763,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
rx_len = pkt_size + sizeof(checksum);
if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
- width = 2;
padded_len = ((rx_len - 1) | 3) + 1;
} else {
- width = 1;
padded_len = ((rx_len - 1) | 1) + 1;
}
@@ -799,11 +785,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Check for EOL */
if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* Are we still in resource exhaustion? */
- size = sizeof(uint16_t) * 1 * width;
- address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
- address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- s->data, size);
- s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
+ s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* Still EOL ; stop reception */
return -1;
@@ -811,11 +793,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Link has been updated by host */
/* Clear in_use */
- size = sizeof(uint16_t) * width;
- address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
- dp8393x_put(s, width, 0, 0);
- address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- s->data, size);
+ dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
/* Move to next descriptor */
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
@@ -869,32 +847,20 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Write status to memory */
trace_dp8393x_receive_write_status(dp8393x_crda(s));
- dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */
- dp8393x_put(s, width, 1, rx_len); /* byte count */
- dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
- dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
- dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
- size = sizeof(uint16_t) * 5 * width;
- address_space_write(&s->as, dp8393x_crda(s),
- MEMTXATTRS_UNSPECIFIED,
- s->data, size);
+ dp8393x_put(s, dp8393x_crda(s), 0, s->regs[SONIC_RCR]); /* status */
+ dp8393x_put(s, dp8393x_crda(s), 1, rx_len); /* byte count */
+ dp8393x_put(s, dp8393x_crda(s), 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
+ dp8393x_put(s, dp8393x_crda(s), 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
+ dp8393x_put(s, dp8393x_crda(s), 4, s->regs[SONIC_RSC]); /* seq_no */
/* Check link field */
- size = sizeof(uint16_t) * width;
- address_space_read(&s->as,
- dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
- MEMTXATTRS_UNSPECIFIED, s->data, size);
- s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
+ s->regs[SONIC_LLFA] = dp8393x_get(s, dp8393x_crda(s), 5);
if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
/* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else {
/* Clear in_use */
- size = sizeof(uint16_t) * width;
- address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
- dp8393x_put(s, width, 0, 0);
- address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
- s->data, size);
+ dp8393x_put(s, dp8393x_crda(s), 6, 0x0000);
/* Move to next descriptor */
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 5/5] dp8393x: don't force 32-bit register access
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-07-11 10:36 ` [PATCH v4 4/5] dp8393x: Rewrite dp8393x_get() / dp8393x_put() Philippe Mathieu-Daudé
@ 2021-07-11 10:36 ` Philippe Mathieu-Daudé
2021-07-11 19:58 ` [PATCH v4 0/5] dp8393x: fixes and improvements Mark Cave-Ayland
2021-07-11 20:28 ` Philippe Mathieu-Daudé
6 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 10:36 UTC (permalink / raw)
To: qemu-devel
Cc: Finn Thain, Jason Wang, Mark Cave-Ayland, Laurent Vivier,
Philippe Mathieu-Daudé,
Hervé Poussineau
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" set .impl.min_access_size
and .impl.max_access_size to 4 to try and fix the Linux jazzsonic driver which uses
32-bit accesses.
The problem with forcing the register access to 32-bit in this way is that since the
dp8393x uses 16-bit registers, a manual endian swap is required for devices on big
endian machines with 32-bit accesses.
For both access sizes and machine endians the QEMU memory API can do the right thing
automatically: all that is needed is to set .impl.min_access_size to 2 to declare that
the dp8393x implements 16-bit registers.
Normally .impl.max_access_size should also be set to 2, however that doesn't quite
work in this case since the register stride is specified using a (dynamic) it_shift
property which is applied during the MMIO access itself. The effect of this is that
for a 32-bit access the memory API performs 2 x 16-bit accesses, but the use of
it_shift within the MMIO access itself causes the register value to be repeated in both
the top 16-bits and bottom 16-bits. The Linux jazzsonic driver expects the stride to be
zero-extended up to access size and therefore fails to correctly detect the dp8393x
device due to the extra data in the top 16-bits.
The solution here is to remove .impl.max_access_size so that the memory API will
correctly zero-extend the 16-bit registers to the access size up to and including
it_shift. Since it_shift is never greater than 2 than this will always do the right
thing for both 16-bit and 32-bit accesses regardless of the machine endian, allowing
the manual endian swap code to be removed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Fixes: 3fe9a838ec ("dp8393x: Always use 32-bit accesses")
Message-Id: <20210705214929.17222-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Finn Thain <fthain@linux-m68k.org>
---
hw/net/dp8393x.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 4057a263de3..45b954e46c2 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -588,15 +588,14 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
trace_dp8393x_read(reg, reg_names[reg], val, size);
- return s->big_endian ? val << 16 : val;
+ return val;
}
-static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
+static void dp8393x_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int size)
{
dp8393xState *s = opaque;
int reg = addr >> s->it_shift;
- uint32_t val = s->big_endian ? data >> 16 : data;
trace_dp8393x_write(reg, reg_names[reg], val, size);
@@ -677,11 +676,16 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
}
}
+/*
+ * Since .impl.max_access_size is effectively controlled by the it_shift
+ * property, leave it unspecified for now to allow the memory API to
+ * correctly zero extend the 16-bit register values to the access size up to and
+ * including it_shift.
+ */
static const MemoryRegionOps dp8393x_ops = {
.read = dp8393x_read,
.write = dp8393x_write,
- .impl.min_access_size = 4,
- .impl.max_access_size = 4,
+ .impl.min_access_size = 2,
.endianness = DEVICE_NATIVE_ENDIAN,
};
--
2.31.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 2/5] dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition
2021-07-11 10:36 ` [PATCH v4 2/5] dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition Philippe Mathieu-Daudé
@ 2021-07-11 19:50 ` Mark Cave-Ayland
0 siblings, 0 replies; 9+ messages in thread
From: Mark Cave-Ayland @ 2021-07-11 19:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Jason Wang, Hervé Poussineau, Laurent Vivier, Finn Thain
On 11/07/2021 11:36, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Tested-by: Finn Thain <fthain@linux-m68k.org>
> Message-Id: <20210710174954.2577195-3-f4bug@amsat.org>
> ---
> hw/net/dp8393x.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
> index 9118364aa33..d1e147a82a6 100644
> --- a/hw/net/dp8393x.c
> +++ b/hw/net/dp8393x.c
> @@ -85,6 +85,7 @@ static const char *reg_names[] = {
> #define SONIC_MPT 0x2e
> #define SONIC_MDT 0x2f
> #define SONIC_DCR2 0x3f
> +#define SONIC_REG_COUNT 0x40
>
> #define SONIC_CR_HTX 0x0001
> #define SONIC_CR_TXP 0x0002
> @@ -158,7 +159,7 @@ struct dp8393xState {
>
> /* Registers */
> uint8_t cam[16][6];
> - uint16_t regs[0x40];
> + uint16_t regs[SONIC_REG_COUNT];
>
> /* Temporaries */
> uint8_t tx_buffer[0x10000];
> @@ -972,7 +973,7 @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
>
> address_space_init(&s->as, s->dma_mr, "dp8393x");
> memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
> - "dp8393x-regs", 0x40 << s->it_shift);
> + "dp8393x-regs", SONIC_REG_COUNT << s->it_shift);
>
> s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
> object_get_typename(OBJECT(dev)), dev->id, s);
> @@ -987,7 +988,7 @@ static const VMStateDescription vmstate_dp8393x = {
> .minimum_version_id = 0,
> .fields = (VMStateField []) {
> VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
> - VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
> + VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT),
> VMSTATE_END_OF_LIST()
> }
> };
I just noticed that the subject line is wrong here: the subject line mentions
SONIC_REG16_COUNT whereas the variable name in the patch is SONIC_REG_COUNT. This is
trivial enough to fix without resending the series though.
ATB,
Mark.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 0/5] dp8393x: fixes and improvements
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-07-11 10:36 ` [PATCH v4 5/5] dp8393x: don't force 32-bit register access Philippe Mathieu-Daudé
@ 2021-07-11 19:58 ` Mark Cave-Ayland
2021-07-11 20:28 ` Philippe Mathieu-Daudé
6 siblings, 0 replies; 9+ messages in thread
From: Mark Cave-Ayland @ 2021-07-11 19:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Jason Wang, Hervé Poussineau, Laurent Vivier, Finn Thain
On 11/07/2021 11:36, Philippe Mathieu-Daudé wrote:
> Hi Mark,
>
> This should be the last respin.
>
> Since v3:
> - dropped worrying patches
> - squashed migration patch
> - added tags
>
> Patch #3 (dp8393x: Store CAM registers as 16-bit) still
> misses your S-o-b tag.
>
> Based-on mips-next.
>
> Mark Cave-Ayland (1):
> dp8393x: don't force 32-bit register access
>
> Philippe Mathieu-Daudé (4):
> dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
> dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition
> dp8393x: Store CAM registers as 16-bit
> dp8393x: Rewrite dp8393x_get() / dp8393x_put()
>
> hw/net/dp8393x.c | 206 ++++++++++++++++++++---------------------------
> 1 file changed, 87 insertions(+), 119 deletions(-)
Thanks Phil. A small typo in the subject line of patch 2, but otherwise this series
passes my local tests (assuming "dp8393x: fix CAM descriptor entry index" is already
applied to mips-next).
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
ATB,
Mark.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 0/5] dp8393x: fixes and improvements
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2021-07-11 19:58 ` [PATCH v4 0/5] dp8393x: fixes and improvements Mark Cave-Ayland
@ 2021-07-11 20:28 ` Philippe Mathieu-Daudé
6 siblings, 0 replies; 9+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-11 20:28 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Jason Wang, Mark Cave-Ayland,
Laurent Vivier, Finn Thain
On 7/11/21 12:36 PM, Philippe Mathieu-Daudé wrote:
> Hi Mark,
>
> This should be the last respin.
>
> Since v3:
> - dropped worrying patches
> - squashed migration patch
> - added tags
>
> Patch #3 (dp8393x: Store CAM registers as 16-bit) still
> misses your S-o-b tag.
>
> Based-on mips-next.
>
> Mark Cave-Ayland (1):
> dp8393x: don't force 32-bit register access
>
> Philippe Mathieu-Daudé (4):
> dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
> dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition
> dp8393x: Store CAM registers as 16-bit
> dp8393x: Rewrite dp8393x_get() / dp8393x_put()
Series applied to mips-next.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-07-11 20:31 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-11 10:36 [PATCH v4 0/5] dp8393x: fixes and improvements Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 1/5] dp8393x: Replace address_space_rw(is_write=1) by address_space_write() Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 2/5] dp8393x: Replace 0x40 magic value by SONIC_REG16_COUNT definition Philippe Mathieu-Daudé
2021-07-11 19:50 ` Mark Cave-Ayland
2021-07-11 10:36 ` [PATCH v4 3/5] dp8393x: Store CAM registers as 16-bit Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 4/5] dp8393x: Rewrite dp8393x_get() / dp8393x_put() Philippe Mathieu-Daudé
2021-07-11 10:36 ` [PATCH v4 5/5] dp8393x: don't force 32-bit register access Philippe Mathieu-Daudé
2021-07-11 19:58 ` [PATCH v4 0/5] dp8393x: fixes and improvements Mark Cave-Ayland
2021-07-11 20:28 ` Philippe Mathieu-Daudé
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