* [PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency Richard Henderson
` (46 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, David Hildenbrand, Philippe Mathieu-Daudé,
Richard W . M . Jones, Miroslav Rezanina
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The code is currently comparing c2 to the type promotion of
uint32_t and int32_t. That is, the conversion rules are as:
(common_type) c2 == (common_type) (uint32_t)
(is_unsigned
? (uint32_t)c2
: (uint32_t)(int32_t)c2)
In the signed case we lose the desired sign extensions because
of the argument promotion rules of the ternary operator.
Solve the problem by doing the round-trip parsing through the
intermediate type and back to the desired common type (all at
one expression).
Fixes: a534bb15f30 ("tcg/s390: Use constant pool for cmpi")
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
Reported-by: Richard W.M. Jones <rjones@redhat.com>
Suggested-by: David Hildenbrand <david@redhat.com>
Suggested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210204182902.1742826-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index b67470137c..695d7ee652 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -1067,7 +1067,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
op = (is_unsigned ? RIL_CLFI : RIL_CFI);
tcg_out_insn_RIL(s, op, r1, c2);
goto exit;
- } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) {
+ } else if (c2 == (is_unsigned ? (TCGArg)(uint32_t)c2 : (TCGArg)(int32_t)c2)) {
op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);
tcg_out_insn_RIL(s, op, r1, c2);
goto exit;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
2021-02-05 22:56 ` [PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps Richard Henderson
` (45 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
"exec/cpu-defs.h" contains generic CPU definitions for the
TCG frontends (mostly related to TLB). TCG backends definitions
aren't relevant here.
See tcg/README description:
4) Backend
tcg-target.h contains the target specific definitions. tcg-target.c.inc
contains the target specific code; it is #included by tcg/tcg.c, rather
than being a standalone C file.
So far only "tcg/tcg.h" requires these headers.
Remove the "target-tcg.h" header dependency on TCG frontends, so we
don't have to rebuild all frontends when hacking a single backend.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210204191423.1754158-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d1f5e3fc3d..ba3cd32a1e 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -25,9 +25,6 @@
#include "qemu/host-utils.h"
#include "qemu/thread.h"
-#ifdef CONFIG_TCG
-#include "tcg-target.h"
-#endif
#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
2021-02-05 22:56 ` [PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility Richard Henderson
2021-02-05 22:56 ` [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 04/46] configure: Fix --enable-tcg-interpreter Richard Henderson
` (44 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd
argument is an integer, not a temporary, which now tickles
an assert added in e89b28a6350.
Previously, the value computed into v2 would be garbage for
rotli_vec, but as the value was unused it caused no harm.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 3c1ee39fd4..1376cdc404 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2488,7 +2488,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
v0 = temp_tcgv_vec(arg_temp(a0));
v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
a2 = va_arg(va, TCGArg);
- v2 = temp_tcgv_vec(arg_temp(a2));
+ va_end(va);
switch (opc) {
case INDEX_op_rotli_vec:
@@ -2502,6 +2502,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
/* Right shifts are negative left shifts for AArch64. */
+ v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
tcg_gen_neg_vec(vece, t1, v2);
opc = (opc == INDEX_op_shrv_vec
@@ -2512,6 +2513,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
break;
case INDEX_op_rotlv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
tcg_gen_sub_vec(vece, t1, v2, c1);
@@ -2525,6 +2527,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
break;
case INDEX_op_rotrv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
t2 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
@@ -2543,8 +2546,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
default:
g_assert_not_reached();
}
-
- va_end(va);
}
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 04/46] configure: Fix --enable-tcg-interpreter
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2021-02-05 22:56 ` [PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local Richard Henderson
` (43 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Daniel P . Berrangé,
Alex Bennée, Philippe Mathieu-Daudé,
Stefan Weil, Philippe Mathieu-Daudé
The configure option was backward, and we failed to
pass the value on to meson.
Fixes: 23a77b2d18b ("build-system: clean up TCG/TCI configury")
Tested-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configure | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index e85d6baf8f..a34f91171d 100755
--- a/configure
+++ b/configure
@@ -1110,9 +1110,9 @@ for opt do
;;
--enable-whpx) whpx="enabled"
;;
- --disable-tcg-interpreter) tcg_interpreter="true"
+ --disable-tcg-interpreter) tcg_interpreter="false"
;;
- --enable-tcg-interpreter) tcg_interpreter="false"
+ --enable-tcg-interpreter) tcg_interpreter="true"
;;
--disable-cap-ng) cap_ng="disabled"
;;
@@ -6417,6 +6417,7 @@ NINJA=$ninja $meson setup \
-Dvhost_user_blk_server=$vhost_user_blk_server \
-Dfuse=$fuse -Dfuse_lseek=$fuse_lseek -Dguest_agent_msi=$guest_agent_msi \
$(if test "$default_features" = no; then echo "-Dauto_features=disabled"; fi) \
+ -Dtcg_interpreter=$tcg_interpreter \
$cross_arg \
"$PWD" "$source_path"
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2021-02-05 22:56 ` [PULL 04/46] configure: Fix --enable-tcg-interpreter Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32 Richard Henderson
` (42 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Each thread must have its own pc, even under TCI.
Remove the GETPC ifdef, because GETPC is always available for
helpers, and thus is always required. Move the assignment
under INDEX_op_call, because the value is only visible when
we make a call to a helper function.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204014509.882821-6-richard.henderson@linaro.org>
---
include/exec/exec-all.h | 2 +-
tcg/tcg-common.c | 4 ----
tcg/tci.c | 7 +++----
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 125000bcf7..f933c74c44 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -544,7 +544,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
/* GETPC is the true target of the return instruction that we'll execute. */
#if defined(CONFIG_TCG_INTERPRETER)
-extern uintptr_t tci_tb_ptr;
+extern __thread uintptr_t tci_tb_ptr;
# define GETPC() tci_tb_ptr
#else
# define GETPC() \
diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c
index 7e1992e79e..aa0c4f60c9 100644
--- a/tcg/tcg-common.c
+++ b/tcg/tcg-common.c
@@ -25,10 +25,6 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
-#if defined(CONFIG_TCG_INTERPRETER)
-uintptr_t tci_tb_ptr;
-#endif
-
TCGOpDef tcg_op_defs[] = {
#define DEF(s, oargs, iargs, cargs, flags) \
{ #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
diff --git a/tcg/tci.c b/tcg/tci.c
index 3fc82d3c79..b3f9531a73 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,6 +57,8 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
tcg_target_ulong, tcg_target_ulong);
#endif
+__thread uintptr_t tci_tb_ptr;
+
static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
{
tci_assert(index < TCG_TARGET_NB_REGS);
@@ -526,16 +528,13 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
TCGMemOpIdx oi;
-#if defined(GETPC)
- tci_tb_ptr = (uintptr_t)tb_ptr;
-#endif
-
/* Skip opcode and size entry. */
tb_ptr += 2;
switch (opc) {
case INDEX_op_call:
t0 = tci_read_ri(regs, &tb_ptr);
+ tci_tb_ptr = (uintptr_t)tb_ptr;
#if TCG_TARGET_REG_BITS == 32
tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
tci_read_reg(regs, TCG_REG_R1),
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2021-02-05 22:56 ` [PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64 Richard Henderson
` (41 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Stefan Weil
From: Stefan Weil <sw@weilnetz.de>
That TCG opcode is used by debian-buster (arm64) running ffmpeg:
qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20210128024814.2056958-1-sw@weilnetz.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index b3f9531a73..2ba97da189 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -615,7 +615,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
TODO();
break;
case INDEX_op_ld16s_i32:
- TODO();
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
break;
case INDEX_op_ld_i32:
t0 = *tb_ptr++;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2021-02-05 22:56 ` [PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32 Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller Richard Henderson
` (40 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Stefan Weil
From: Stefan Weil <sw@weilnetz.de>
That TCG opcode is used by debian-buster (arm64) running ffmpeg:
qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20210128020425.2055454-1-sw@weilnetz.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 2ba97da189..c3a8511dfe 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -883,7 +883,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
- TODO();
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
break;
case INDEX_op_ld16u_i64:
t0 = *tb_ptr++;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (6 preceding siblings ...)
2021-02-05 22:56 ` [PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64 Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers Richard Henderson
` (39 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index c3a8511dfe..e8023b5384 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value)
-{
- tci_write_reg(regs, index, value);
-}
-#endif
-
static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
{
tci_write_reg(regs, index, value);
@@ -907,7 +899,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (7 preceding siblings ...)
2021-02-05 22:56 ` [PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller Richard Henderson
` (38 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e8023b5384..740244cc54 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,11 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
-{
- tci_write_reg(regs, index, value);
-}
-
#if TCG_TARGET_REG_BITS == 64
static void
tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
@@ -598,7 +593,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i32:
TODO();
@@ -872,7 +867,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
t0 = *tb_ptr++;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (8 preceding siblings ...)
2021-02-05 22:56 ` [PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers Richard Henderson
` (37 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 740244cc54..005d2946c4 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
-{
- tci_write_reg(regs, index, value);
-}
-#endif
-
static void
tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
{
@@ -879,7 +871,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break;
case INDEX_op_ld16s_i64:
TODO();
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (9 preceding siblings ...)
2021-02-05 22:56 ` [PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers Richard Henderson
` (36 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
For a 64-bit TCI, the upper bits of a 32-bit operation are
undefined (much like a native ppc64 32-bit operation). It
simplifies everything if we don't force-extend the result.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 66 +++++++++++++++++++++++++------------------------------
1 file changed, 30 insertions(+), 36 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 005d2946c4..39ad00663f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,12 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-static void
-tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
-{
- tci_write_reg(regs, index, value);
-}
-
#if TCG_TARGET_REG_BITS == 32
static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
uint32_t low_index, uint64_t value)
@@ -549,7 +543,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t1 = tci_read_r32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
condition = *tb_ptr++;
- tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition));
+ tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
@@ -557,7 +551,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tmp64 = tci_read_r64(regs, &tb_ptr);
v64 = tci_read_ri64(regs, &tb_ptr);
condition = *tb_ptr++;
- tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition));
+ tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
@@ -571,12 +565,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mov_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i32:
t0 = *tb_ptr++;
t1 = tci_read_i32(&tb_ptr);
- tci_write_reg32(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
/* Load/store operations (32 bit). */
@@ -603,7 +597,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_st8_i32:
t0 = tci_read_r8(regs, &tb_ptr);
@@ -631,44 +625,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 + t2);
+ tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 - t2);
+ tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 * t2);
+ tci_write_reg(regs, t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i32
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2);
+ tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 / t2);
+ tci_write_reg(regs, t0, t1 / t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2);
+ tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 % t2);
+ tci_write_reg(regs, t0, t1 % t2);
break;
#elif TCG_TARGET_HAS_div2_i32
case INDEX_op_div2_i32:
@@ -680,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 & t2);
+ tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 | t2);
+ tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 ^ t2);
+ tci_write_reg(regs, t0, t1 ^ t2);
break;
/* Shift/rotate operations (32 bit). */
@@ -701,32 +695,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 << (t2 & 31));
+ tci_write_reg(regs, t0, t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1 >> (t2 & 31));
+ tci_write_reg(regs, t0, t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31)));
+ tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, rol32(t1, t2 & 31));
+ tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
t2 = tci_read_ri32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, ror32(t1, t2 & 31));
+ tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
@@ -737,7 +731,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16);
- tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
+ tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
break;
#endif
case INDEX_op_brcond_i32:
@@ -789,56 +783,56 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext8s_i32:
t0 = *tb_ptr++;
t1 = tci_read_r8s(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32
case INDEX_op_ext16s_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16s(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32
case INDEX_op_ext8u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r8(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32
case INDEX_op_ext16u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg32(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32
case INDEX_op_bswap16_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg32(regs, t0, bswap16(t1));
+ tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32
case INDEX_op_bswap32_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, bswap32(t1));
+ tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i32
case INDEX_op_not_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, ~t1);
+ tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i32
case INDEX_op_neg_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg32(regs, t0, -t1);
+ tci_write_reg(regs, t0, -t1);
break;
#endif
#if TCG_TARGET_REG_BITS == 64
@@ -880,7 +874,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (10 preceding siblings ...)
2021-02-05 22:56 ` [PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} Richard Henderson
` (35 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Note that we had two functions of the same name: a 32-bit version
which took two register numbers and a 64-bit version which was a
no-op wrapper for tcg_write_reg. After this, we are left with
only the 32-bit version.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 60 +++++++++++++++++++++++++------------------------------
1 file changed, 27 insertions(+), 33 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 39ad00663f..0f56702b93 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -124,12 +124,6 @@ static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
tci_write_reg(regs, low_index, value);
tci_write_reg(regs, high_index, value >> 32);
}
-#elif TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value)
-{
- tci_write_reg(regs, index, value);
-}
#endif
#if TCG_TARGET_REG_BITS == 32
@@ -559,7 +553,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t1 = tci_read_r64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
condition = *tb_ptr++;
- tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition));
+ tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
#endif
case INDEX_op_mov_i32:
@@ -839,12 +833,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(&tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
/* Load/store operations (64 bit). */
@@ -886,7 +880,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st8_i64:
t0 = tci_read_r8(regs, &tb_ptr);
@@ -920,19 +914,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 + t2);
+ tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 - t2);
+ tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 * t2);
+ tci_write_reg(regs, t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
@@ -951,19 +945,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 & t2);
+ tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 | t2);
+ tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 ^ t2);
+ tci_write_reg(regs, t0, t1 ^ t2);
break;
/* Shift/rotate operations (64 bit). */
@@ -972,32 +966,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 << (t2 & 63));
+ tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1 >> (t2 & 63));
+ tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63)));
+ tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, rol64(t1, t2 & 63));
+ tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
t2 = tci_read_ri64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, ror64(t1, t2 & 63));
+ tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
@@ -1008,7 +1002,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
- tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
+ tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
break;
#endif
case INDEX_op_brcond_i64:
@@ -1026,28 +1020,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8s(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16s(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext32s_i64
@@ -1056,7 +1050,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32s(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#if TCG_TARGET_HAS_ext32u_i64
case INDEX_op_ext32u_i64:
@@ -1064,41 +1058,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg64(regs, t0, t1);
+ tci_write_reg(regs, t0, t1);
break;
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(regs, &tb_ptr);
- tci_write_reg64(regs, t0, bswap16(t1));
+ tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i64
case INDEX_op_bswap32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- tci_write_reg64(regs, t0, bswap32(t1));
+ tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, bswap64(t1));
+ tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i64
case INDEX_op_not_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, ~t1);
+ tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i64
case INDEX_op_neg_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- tci_write_reg64(regs, t0, -t1);
+ tci_write_reg(regs, t0, -t1);
break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (11 preceding siblings ...)
2021-02-05 22:56 ` [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Richard Henderson
` (34 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 0f56702b93..7e108bcbb3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -455,6 +455,18 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
# define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
#endif
+#if TCG_TARGET_REG_BITS == 64
+# define CASE_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i64): \
+ case glue(glue(INDEX_op_, x), _i32):
+# define CASE_64(x) \
+ case glue(glue(INDEX_op_, x), _i64):
+#else
+# define CASE_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i32):
+# define CASE_64(x)
+#endif
+
/* Interpret pseudo code in tb. */
/*
* Disable CFI checks.
@@ -569,7 +581,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (32 bit). */
- case INDEX_op_ld8u_i32:
+ CASE_32_64(ld8u)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
@@ -843,12 +855,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (64 bit). */
- case INDEX_op_ld8u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
- break;
case INDEX_op_ld8s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (12 preceding siblings ...)
2021-02-05 22:56 ` [PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Richard Henderson
` (33 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Eliminating a TODO for ld8s_i32.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 7e108bcbb3..c31be1a1f4 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -587,8 +587,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
- case INDEX_op_ld8s_i32:
- TODO();
+ CASE_32_64(ld8s)
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
break;
case INDEX_op_ld16u_i32:
TODO();
@@ -855,12 +858,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (64 bit). */
- case INDEX_op_ld8s_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
- break;
case INDEX_op_ld16u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (13 preceding siblings ...)
2021-02-05 22:56 ` [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Richard Henderson
` (32 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Eliminating a TODO for ld16u_i32.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index c31be1a1f4..b64d611ec9 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -593,8 +593,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
break;
- case INDEX_op_ld16u_i32:
- TODO();
+ CASE_32_64(ld16u)
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break;
case INDEX_op_ld16s_i32:
t0 = *tb_ptr++;
@@ -858,12 +861,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (64 bit). */
- case INDEX_op_ld16u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
- break;
case INDEX_op_ld16s_i64:
TODO();
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (14 preceding siblings ...)
2021-02-05 22:56 ` [PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} Richard Henderson
` (31 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Eliminating a TODO for ld16s_i64.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index b64d611ec9..259a8538bf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -599,7 +599,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break;
- case INDEX_op_ld16s_i32:
+ CASE_32_64(ld16s)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
@@ -861,9 +861,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (64 bit). */
- case INDEX_op_ld16s_i64:
- TODO();
- break;
case INDEX_op_ld32u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (15 preceding siblings ...)
2021-02-05 22:56 ` [PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64} Richard Henderson
` (30 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 259a8538bf..55863f76a7 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -606,6 +606,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
break;
case INDEX_op_ld_i32:
+ CASE_64(ld32u)
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
@@ -861,12 +862,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Load/store operations (64 bit). */
- case INDEX_op_ld32u_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
- break;
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (16 preceding siblings ...)
2021-02-05 22:56 ` [PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64} Richard Henderson
` (29 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 55863f76a7..6819c97792 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -612,7 +612,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
- case INDEX_op_st8_i32:
+ CASE_32_64(st8)
t0 = tci_read_r8(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
@@ -874,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
- case INDEX_op_st8_i64:
- t0 = tci_read_r8(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint8_t *)(t1 + t2) = t0;
- break;
case INDEX_op_st16_i64:
t0 = tci_read_r16(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (17 preceding siblings ...)
2021-02-05 22:56 ` [PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 20/46] tcg/tci: Move stack bounds check to compile-time Richard Henderson
` (28 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 6819c97792..fe935e71a3 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -618,7 +618,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
- case INDEX_op_st16_i32:
+ CASE_32_64(st16)
t0 = tci_read_r16(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
@@ -874,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
- case INDEX_op_st16_i64:
- t0 = tci_read_r16(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint16_t *)(t1 + t2) = t0;
- break;
case INDEX_op_st32_i64:
t0 = tci_read_r32(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 20/46] tcg/tci: Move stack bounds check to compile-time
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (18 preceding siblings ...)
2021-02-05 22:56 ` [PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} Richard Henderson
` (27 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
The existing check was incomplete:
(1) Only applied to two of the 7 stores, and not to the loads at all.
(2) Only checked the upper, but not the lower bound of the stack.
Doing this at compile time means that we don't need to do it
at runtime as well.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 2 --
tcg/tci/tcg-target.c.inc | 13 +++++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index fe935e71a3..ee2cd7dfa2 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -628,7 +628,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = tci_read_r32(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint32_t *)(t1 + t2) = t0;
break;
@@ -884,7 +883,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = tci_read_r64(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint64_t *)(t1 + t2) = t0;
break;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index f0f6b13112..82efb9af60 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -375,10 +375,20 @@ static void tci_out_label(TCGContext *s, TCGLabel *label)
}
}
+static void stack_bounds_check(TCGReg base, target_long offset)
+{
+ if (base == TCG_REG_CALL_STACK) {
+ tcg_debug_assert(offset < 0);
+ tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long)));
+ }
+}
+
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2)
{
uint8_t *old_code_ptr = s->code_ptr;
+
+ stack_bounds_check(arg1, arg2);
if (type == TCG_TYPE_I32) {
tcg_out_op_t(s, INDEX_op_ld_i32);
tcg_out_r(s, ret);
@@ -514,6 +524,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
+ stack_bounds_check(args[1], args[2]);
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_debug_assert(args[2] == (int32_t)args[2]);
@@ -716,6 +727,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
intptr_t arg2)
{
uint8_t *old_code_ptr = s->code_ptr;
+
+ stack_bounds_check(arg1, arg2);
if (type == TCG_TYPE_I32) {
tcg_out_op_t(s, INDEX_op_st_i32);
tcg_out_r(s, arg);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (19 preceding siblings ...)
2021-02-05 22:56 ` [PULL 20/46] tcg/tci: Move stack bounds check to compile-time Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 22/46] tcg/tci: Use g_assert_not_reached Richard Henderson
` (26 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index ee2cd7dfa2..eb70672efb 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -625,6 +625,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i32:
+ CASE_64(st32)
t0 = tci_read_r32(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
@@ -873,12 +874,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
- case INDEX_op_st32_i64:
- t0 = tci_read_r32(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_s32(&tb_ptr);
- *(uint32_t *)(t1 + t2) = t0;
- break;
case INDEX_op_st_i64:
t0 = tci_read_r64(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 22/46] tcg/tci: Use g_assert_not_reached
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (20 preceding siblings ...)
2021-02-05 22:56 ` [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Richard Henderson
` (25 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Stefan Weil
Three TODO instances are never happen cases.
Other uses of tcg_abort are also indicating unreachable cases.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index eb70672efb..36d594672f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -362,7 +362,7 @@ static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
result = (u0 > u1);
break;
default:
- TODO();
+ g_assert_not_reached();
}
return result;
}
@@ -404,7 +404,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
result = (u0 > u1);
break;
default:
- TODO();
+ g_assert_not_reached();
}
return result;
}
@@ -1114,7 +1114,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tmp32 = qemu_ld_beul;
break;
default:
- tcg_abort();
+ g_assert_not_reached();
}
tci_write_reg(regs, t0, tmp32);
break;
@@ -1163,7 +1163,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tmp64 = qemu_ld_beq;
break;
default:
- tcg_abort();
+ g_assert_not_reached();
}
tci_write_reg(regs, t0, tmp64);
if (TCG_TARGET_REG_BITS == 32) {
@@ -1191,7 +1191,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
qemu_st_bel(t0);
break;
default:
- tcg_abort();
+ g_assert_not_reached();
}
break;
case INDEX_op_qemu_st_i64:
@@ -1221,7 +1221,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
qemu_st_beq(tmp64);
break;
default:
- tcg_abort();
+ g_assert_not_reached();
}
break;
case INDEX_op_mb:
@@ -1229,8 +1229,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
smp_mb();
break;
default:
- TODO();
- break;
+ g_assert_not_reached();
}
tci_assert(tb_ptr == old_code_ptr + op_size);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (21 preceding siblings ...)
2021-02-05 22:56 ` [PULL 22/46] tcg/tci: Use g_assert_not_reached Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 24/46] tcg/tci: Implement 64-bit division Richard Henderson
` (24 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
We do not simultaneously support div and div2 -- it's one
or the other. TCI is already using div, so remove div2.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 12 ------------
tcg/tci/tcg-target.c.inc | 8 --------
2 files changed, 20 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 36d594672f..25329345cf 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -652,7 +652,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_ri32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
-#if TCG_TARGET_HAS_div_i32
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
@@ -677,12 +676,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_ri32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 % t2);
break;
-#elif TCG_TARGET_HAS_div2_i32
- case INDEX_op_div2_i32:
- case INDEX_op_divu2_i32:
- TODO();
- break;
-#endif
case INDEX_op_and_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
@@ -908,11 +901,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_remu_i64:
TODO();
break;
-#elif TCG_TARGET_HAS_div2_i64
- case INDEX_op_div2_i64:
- case INDEX_op_divu2_i64:
- TODO();
- break;
#endif
case INDEX_op_and_i64:
t0 = *tb_ptr++;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 82efb9af60..6dc5bac2f3 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -596,10 +596,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
TODO();
break;
- case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
- case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
- TODO();
- break;
case INDEX_op_brcond_i64:
tcg_out_r(s, args[0]);
tcg_out_ri64(s, const_args[1], args[1]);
@@ -639,10 +635,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_ri32(s, const_args[1], args[1]);
tcg_out_ri32(s, const_args[2], args[2]);
break;
- case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
- case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
- TODO();
- break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 24/46] tcg/tci: Implement 64-bit division
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (22 preceding siblings ...)
2021-02-05 22:56 ` [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 25/46] tcg/tci: Remove TODO as unused Richard Henderson
` (23 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Trivially implemented like other arithmetic.
Tested via check-tcg and the ppc64 target.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c | 28 ++++++++++++++++++++++------
tcg/tci/tcg-target.c.inc | 10 ++++------
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index bb784e018e..7fc349a3de 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -100,8 +100,8 @@
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 25329345cf..5c84a1c979 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -894,14 +894,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_ri64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
-#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
- case INDEX_op_divu_i64:
- case INDEX_op_rem_i64:
- case INDEX_op_remu_i64:
- TODO();
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
+ break;
+ case INDEX_op_divu_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
+ break;
+ case INDEX_op_rem_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
+ break;
+ case INDEX_op_remu_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
-#endif
case INDEX_op_and_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 6dc5bac2f3..3327ce3072 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -577,6 +577,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_sar_i64:
case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
+ case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
tcg_out_r(s, args[0]);
tcg_out_ri64(s, const_args[1], args[1]);
tcg_out_ri64(s, const_args[2], args[2]);
@@ -590,12 +594,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_debug_assert(args[4] <= UINT8_MAX);
tcg_out8(s, args[4]);
break;
- case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- TODO();
- break;
case INDEX_op_brcond_i64:
tcg_out_r(s, args[0]);
tcg_out_ri64(s, const_args[1], args[1]);
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 25/46] tcg/tci: Remove TODO as unused
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (23 preceding siblings ...)
2021-02-05 22:56 ` [PULL 24/46] tcg/tci: Implement 64-bit division Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Richard Henderson
` (22 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 5c84a1c979..e0d815e4b2 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -33,14 +33,6 @@
#include "tcg/tcg-op.h"
#include "qemu/compiler.h"
-/* Marker for missing code. */
-#define TODO() \
- do { \
- fprintf(stderr, "TODO %s:%u: %s()\n", \
- __FILE__, __LINE__, __func__); \
- tcg_abort(); \
- } while (0)
-
#if MAX_OPC_PARAM_IARGS != 6
# error Fix needed, number of supported input arguments changed!
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (24 preceding siblings ...)
2021-02-05 22:56 ` [PULL 25/46] tcg/tci: Remove TODO as unused Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage Richard Henderson
` (21 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented. Shortly, we will
rearrange the encoding which will make 32 regs impossible.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 32 +++++---------------------------
tcg/tci/tcg-target.c.inc | 26 --------------------------
2 files changed, 5 insertions(+), 53 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 7fc349a3de..8f7ed676fc 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -133,11 +133,8 @@
#define TCG_TARGET_HAS_mulu2_i32 1
#endif /* TCG_TARGET_REG_BITS == 64 */
-/* Number of registers available.
- For 32 bit hosts, we need more than 8 registers (call arguments). */
-/* #define TCG_TARGET_NB_REGS 8 */
+/* Number of registers available. */
#define TCG_TARGET_NB_REGS 16
-/* #define TCG_TARGET_NB_REGS 32 */
/* List of registers which are used by TCG. */
typedef enum {
@@ -149,7 +146,6 @@ typedef enum {
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
@@ -158,33 +154,15 @@ typedef enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
-#if TCG_TARGET_NB_REGS >= 32
- TCG_REG_R16,
- TCG_REG_R17,
- TCG_REG_R18,
- TCG_REG_R19,
- TCG_REG_R20,
- TCG_REG_R21,
- TCG_REG_R22,
- TCG_REG_R23,
- TCG_REG_R24,
- TCG_REG_R25,
- TCG_REG_R26,
- TCG_REG_R27,
- TCG_REG_R28,
- TCG_REG_R29,
- TCG_REG_R30,
- TCG_REG_R31,
-#endif
-#endif
+
+ TCG_AREG0 = TCG_REG_R14,
+ TCG_REG_CALL_STACK = TCG_REG_R15,
+
/* Special value UINT8_MAX is used by TCI to encode constant values. */
TCG_CONST = UINT8_MAX
} TCGReg;
-#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
-
/* Used for function call generation. */
-#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
#define TCG_TARGET_CALL_STACK_OFFSET 0
#define TCG_TARGET_STACK_ALIGN 16
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 3327ce3072..7e3bed811e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
@@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
-#endif
};
#if MAX_OPC_PARAM_IARGS != 6
@@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] = {
#if TCG_TARGET_REG_BITS == 32
/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
TCG_REG_R12,
-#else
-# error Too few input registers available
-#endif
#endif
};
@@ -245,7 +239,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r05",
"r06",
"r07",
-#if TCG_TARGET_NB_REGS >= 16
"r08",
"r09",
"r10",
@@ -254,25 +247,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r13",
"r14",
"r15",
-#if TCG_TARGET_NB_REGS >= 32
- "r16",
- "r17",
- "r18",
- "r19",
- "r20",
- "r21",
- "r22",
- "r23",
- "r24",
- "r25",
- "r26",
- "r27",
- "r28",
- "r29",
- "r30",
- "r31"
-#endif
-#endif
};
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (25 preceding siblings ...)
2021-02-05 22:56 ` [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 28/46] tcg/tci: Remove TCG_CONST Richard Henderson
` (20 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
This was removed from tcg_target_reg_alloc_order and
tcg_target_call_iarg_regs on the assumption that it
was the stack. This was incorrectly copied from i386.
For tci, the stack is R15.
By adding R4 back to tcg_target_call_iarg_regs, adjust the other
entries so that 6 (or 12) entries are still present in the array,
and adjust the numbers in the interpreter.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 8 ++++----
tcg/tci/tcg-target.c.inc | 7 +------
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e0d815e4b2..935eb87330 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -511,14 +511,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_read_reg(regs, TCG_REG_R1),
tci_read_reg(regs, TCG_REG_R2),
tci_read_reg(regs, TCG_REG_R3),
+ tci_read_reg(regs, TCG_REG_R4),
tci_read_reg(regs, TCG_REG_R5),
tci_read_reg(regs, TCG_REG_R6),
tci_read_reg(regs, TCG_REG_R7),
tci_read_reg(regs, TCG_REG_R8),
tci_read_reg(regs, TCG_REG_R9),
tci_read_reg(regs, TCG_REG_R10),
- tci_read_reg(regs, TCG_REG_R11),
- tci_read_reg(regs, TCG_REG_R12));
+ tci_read_reg(regs, TCG_REG_R11));
tci_write_reg(regs, TCG_REG_R0, tmp64);
tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32);
#else
@@ -526,8 +526,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_read_reg(regs, TCG_REG_R1),
tci_read_reg(regs, TCG_REG_R2),
tci_read_reg(regs, TCG_REG_R3),
- tci_read_reg(regs, TCG_REG_R5),
- tci_read_reg(regs, TCG_REG_R6));
+ tci_read_reg(regs, TCG_REG_R4),
+ tci_read_reg(regs, TCG_REG_R5));
tci_write_reg(regs, TCG_REG_R0, tmp64);
#endif
break;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 7e3bed811e..aba7f75ad1 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -181,9 +181,7 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
-#if 0 /* used for TCG_REG_CALL_STACK */
TCG_REG_R4,
-#endif
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
@@ -206,19 +204,16 @@ static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
-#if 0 /* used for TCG_REG_CALL_STACK */
TCG_REG_R4,
-#endif
TCG_REG_R5,
- TCG_REG_R6,
#if TCG_TARGET_REG_BITS == 32
/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
+ TCG_REG_R6,
TCG_REG_R7,
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
- TCG_REG_R12,
#endif
};
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 28/46] tcg/tci: Remove TCG_CONST
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (26 preceding siblings ...)
2021-02-05 22:56 ` [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 29/46] cpu: Introduce TCGCpuOperations struct Richard Henderson
` (19 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Restrict all operands to registers. All constants will be forced
into registers by the middle-end. Removing the difference in how
immediate integers were encoded will allow more code to be shared
between 32-bit and 64-bit operations.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-con-set.h | 6 +-
tcg/tci/tcg-target.h | 3 -
tcg/tci.c | 189 +++++++++++++----------------------
tcg/tci/tcg-target.c.inc | 85 ++++------------
4 files changed, 89 insertions(+), 194 deletions(-)
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
index 38e82f7535..f51b7bcb13 100644
--- a/tcg/tci/tcg-target-con-set.h
+++ b/tcg/tci/tcg-target-con-set.h
@@ -10,16 +10,12 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I2(r, r)
-C_O0_I2(r, ri)
C_O0_I3(r, r, r)
-C_O0_I4(r, r, ri, ri)
C_O0_I4(r, r, r, r)
C_O1_I1(r, r)
C_O1_I2(r, 0, r)
-C_O1_I2(r, ri, ri)
C_O1_I2(r, r, r)
-C_O1_I2(r, r, ri)
-C_O1_I4(r, r, r, ri, ri)
+C_O1_I4(r, r, r, r, r)
C_O2_I1(r, r, r)
C_O2_I2(r, r, r, r)
C_O2_I4(r, r, r, r, r, r)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 8f7ed676fc..9c0021a26f 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -157,9 +157,6 @@ typedef enum {
TCG_AREG0 = TCG_REG_R14,
TCG_REG_CALL_STACK = TCG_REG_R15,
-
- /* Special value UINT8_MAX is used by TCI to encode constant values. */
- TCG_CONST = UINT8_MAX
} TCGReg;
/* Used for function call generation. */
diff --git a/tcg/tci.c b/tcg/tci.c
index 935eb87330..fb3c97aaf1 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -255,61 +255,6 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return taddr;
}
-/* Read indexed register or constant (native size) from bytecode. */
-static tcg_target_ulong
-tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
-{
- tcg_target_ulong value;
- TCGReg r = **tb_ptr;
- *tb_ptr += 1;
- if (r == TCG_CONST) {
- value = tci_read_i(tb_ptr);
- } else {
- value = tci_read_reg(regs, r);
- }
- return value;
-}
-
-/* Read indexed register or constant (32 bit) from bytecode. */
-static uint32_t tci_read_ri32(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint32_t value;
- TCGReg r = **tb_ptr;
- *tb_ptr += 1;
- if (r == TCG_CONST) {
- value = tci_read_i32(tb_ptr);
- } else {
- value = tci_read_reg32(regs, r);
- }
- return value;
-}
-
-#if TCG_TARGET_REG_BITS == 32
-/* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
-static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint32_t low = tci_read_ri32(regs, tb_ptr);
- return tci_uint64(tci_read_ri32(regs, tb_ptr), low);
-}
-#elif TCG_TARGET_REG_BITS == 64
-/* Read indexed register or constant (64 bit) from bytecode. */
-static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
- const uint8_t **tb_ptr)
-{
- uint64_t value;
- TCGReg r = **tb_ptr;
- *tb_ptr += 1;
- if (r == TCG_CONST) {
- value = tci_read_i64(tb_ptr);
- } else {
- value = tci_read_reg64(regs, r);
- }
- return value;
-}
-#endif
-
static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
{
tcg_target_ulong label = tci_read_i(tb_ptr);
@@ -504,7 +449,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
switch (opc) {
case INDEX_op_call:
- t0 = tci_read_ri(regs, &tb_ptr);
+ t0 = tci_read_i(&tb_ptr);
tci_tb_ptr = (uintptr_t)tb_ptr;
#if TCG_TARGET_REG_BITS == 32
tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
@@ -539,7 +484,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
@@ -547,7 +492,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_setcond2_i32:
t0 = *tb_ptr++;
tmp64 = tci_read_r64(regs, &tb_ptr);
- v64 = tci_read_ri64(regs, &tb_ptr);
+ v64 = tci_read_r64(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
break;
@@ -555,7 +500,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
@@ -628,62 +573,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_add_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
case INDEX_op_div_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 / t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 % t2);
break;
case INDEX_op_and_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -691,33 +636,33 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_ri32(regs, &tb_ptr);
- t2 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
+ t2 = tci_read_r32(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break;
#endif
@@ -734,7 +679,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
case INDEX_op_brcond_i32:
t0 = tci_read_r32(regs, &tb_ptr);
- t1 = tci_read_ri32(regs, &tb_ptr);
+ t1 = tci_read_r32(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
@@ -760,7 +705,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
case INDEX_op_brcond2_i32:
tmp64 = tci_read_r64(regs, &tb_ptr);
- v64 = tci_read_ri64(regs, &tb_ptr);
+ v64 = tci_read_r64(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(tmp64, v64, condition)) {
@@ -870,62 +815,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_add_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
case INDEX_op_div_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
break;
case INDEX_op_divu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
break;
case INDEX_op_rem_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
break;
case INDEX_op_remu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
case INDEX_op_and_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -933,33 +878,33 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_ri64(regs, &tb_ptr);
- t2 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
+ t2 = tci_read_r64(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
@@ -976,7 +921,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif
case INDEX_op_brcond_i64:
t0 = tci_read_r64(regs, &tb_ptr);
- t1 = tci_read_ri64(regs, &tb_ptr);
+ t1 = tci_read_r64(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index aba7f75ad1..feac4659cc 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -92,8 +92,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rem_i64:
case INDEX_op_remu_i32:
case INDEX_op_remu_i64:
- return C_O1_I2(r, r, r);
-
case INDEX_op_add_i32:
case INDEX_op_add_i64:
case INDEX_op_sub_i32:
@@ -126,8 +124,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
- /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
- return C_O1_I2(r, ri, ri);
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, r);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
@@ -135,11 +134,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return C_O0_I2(r, ri);
-
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return C_O1_I2(r, r, ri);
+ return C_O0_I2(r, r);
#if TCG_TARGET_REG_BITS == 32
/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
@@ -147,11 +142,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub2_i32:
return C_O2_I4(r, r, r, r, r, r);
case INDEX_op_brcond2_i32:
- return C_O0_I4(r, r, ri, ri);
+ return C_O0_I4(r, r, r, r);
case INDEX_op_mulu2_i32:
return C_O2_I2(r, r, r, r);
case INDEX_op_setcond2_i32:
- return C_O1_I4(r, r, r, ri, ri);
+ return C_O1_I4(r, r, r, r, r);
#endif
case INDEX_op_qemu_ld_i32:
@@ -294,44 +289,6 @@ static void tcg_out_r(TCGContext *s, TCGArg t0)
tcg_out8(s, t0);
}
-/* Write register or constant (native size). */
-static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
-{
- if (const_arg) {
- tcg_debug_assert(const_arg == 1);
- tcg_out8(s, TCG_CONST);
- tcg_out_i(s, arg);
- } else {
- tcg_out_r(s, arg);
- }
-}
-
-/* Write register or constant (32 bit). */
-static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
-{
- if (const_arg) {
- tcg_debug_assert(const_arg == 1);
- tcg_out8(s, TCG_CONST);
- tcg_out32(s, arg);
- } else {
- tcg_out_r(s, arg);
- }
-}
-
-#if TCG_TARGET_REG_BITS == 64
-/* Write register or constant (64 bit). */
-static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
-{
- if (const_arg) {
- tcg_debug_assert(const_arg == 1);
- tcg_out8(s, TCG_CONST);
- tcg_out64(s, arg);
- } else {
- tcg_out_r(s, arg);
- }
-}
-#endif
-
/* Write label. */
static void tci_out_label(TCGContext *s, TCGLabel *label)
{
@@ -419,7 +376,7 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
{
uint8_t *old_code_ptr = s->code_ptr;
tcg_out_op_t(s, INDEX_op_call);
- tcg_out_ri(s, 1, (uintptr_t)arg);
+ tcg_out_i(s, (uintptr_t)arg);
old_code_ptr[1] = s->code_ptr - old_code_ptr;
}
@@ -453,7 +410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_setcond_i32:
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
+ tcg_out_r(s, args[2]);
tcg_out8(s, args[3]); /* condition */
break;
#if TCG_TARGET_REG_BITS == 32
@@ -462,15 +419,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
tcg_out_r(s, args[2]);
- tcg_out_ri32(s, const_args[3], args[3]);
- tcg_out_ri32(s, const_args[4], args[4]);
+ tcg_out_r(s, args[3]);
+ tcg_out_r(s, args[4]);
tcg_out8(s, args[5]); /* condition */
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
- tcg_out_ri64(s, const_args[2], args[2]);
+ tcg_out_r(s, args[2]);
tcg_out8(s, args[3]); /* condition */
break;
#endif
@@ -516,8 +473,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
tcg_out_r(s, args[0]);
- tcg_out_ri32(s, const_args[1], args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
break;
case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
tcg_out_r(s, args[0]);
@@ -551,8 +508,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
tcg_out_r(s, args[0]);
- tcg_out_ri64(s, const_args[1], args[1]);
- tcg_out_ri64(s, const_args[2], args[2]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
break;
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
tcg_out_r(s, args[0]);
@@ -565,7 +522,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_brcond_i64:
tcg_out_r(s, args[0]);
- tcg_out_ri64(s, const_args[1], args[1]);
+ tcg_out_r(s, args[1]);
tcg_out8(s, args[2]); /* condition */
tci_out_label(s, arg_label(args[3]));
break;
@@ -599,8 +556,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
tcg_out_r(s, args[0]);
- tcg_out_ri32(s, const_args[1], args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
+ tcg_out_r(s, args[1]);
+ tcg_out_r(s, args[2]);
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
@@ -615,8 +572,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_brcond2_i32:
tcg_out_r(s, args[0]);
tcg_out_r(s, args[1]);
- tcg_out_ri32(s, const_args[2], args[2]);
- tcg_out_ri32(s, const_args[3], args[3]);
+ tcg_out_r(s, args[2]);
+ tcg_out_r(s, args[3]);
tcg_out8(s, args[4]); /* condition */
tci_out_label(s, arg_label(args[5]));
break;
@@ -629,7 +586,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
#endif
case INDEX_op_brcond_i32:
tcg_out_r(s, args[0]);
- tcg_out_ri32(s, const_args[1], args[1]);
+ tcg_out_r(s, args[1]);
tcg_out8(s, args[2]); /* condition */
tci_out_label(s, arg_label(args[3]));
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 29/46] cpu: Introduce TCGCpuOperations struct
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (27 preceding siblings ...)
2021-02-05 22:56 ` [PULL 28/46] tcg/tci: Remove TCG_CONST Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG Richard Henderson
` (18 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Eduardo Habkost
From: Eduardo Habkost <ehabkost@redhat.com>
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: move TCGCpuOperations inside include/hw/core/cpu.h]
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-2-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 16 +++++++++++++++-
cpu.c | 6 +++++-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 12 ++++++------
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 48 insertions(+), 30 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 140fa32a5e..26b89fd7a4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,6 +76,19 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
+/**
+ * struct TcgCpuOperations: TCG operations specific to a CPU class
+ */
+typedef struct TcgCpuOperations {
+ /**
+ * @initialize: Initalize TCG state
+ *
+ * Called when the first CPU is realized.
+ */
+ void (*initialize)(void);
+
+} TcgCpuOperations;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -222,12 +235,13 @@ struct CPUClass {
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
- void (*tcg_initialize)(void);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+
+ TcgCpuOperations tcg_ops;
};
/*
diff --git a/cpu.c b/cpu.c
index 0b245cda2e..79a2bf12b3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -159,14 +159,18 @@ void cpu_exec_initfn(CPUState *cpu)
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+#ifdef CONFIG_TCG
static bool tcg_target_initialized;
+#endif /* CONFIG_TCG */
cpu_list_add(cpu);
+#ifdef CONFIG_TCG
if (tcg_enabled() && !tcg_target_initialized) {
tcg_target_initialized = true;
- cc->tcg_initialize();
+ cc->tcg_ops.initialize();
}
+#endif /* CONFIG_TCG */
tlb_init(cpu);
qemu_plugin_vcpu_init_hook(cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b3fd6643e8..d66f0351a9 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -231,7 +231,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
- cc->tcg_initialize = alpha_translate_init;
+ cc->tcg_ops.initialize = alpha_translate_init;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 40142ac141..fa4d4ba4eb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2276,7 +2276,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = arm_translate_init;
+ cc->tcg_ops.initialize = arm_translate_init;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 6f3d5a9e4a..fb66695fbb 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
- cc->tcg_initialize = avr_cpu_tcg_init;
+ cc->tcg_ops.initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index cff6b9eabf..4328f8e6c9 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -201,7 +201,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 8;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -212,7 +212,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 9;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -223,7 +223,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 10;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -234,7 +234,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 11;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
@@ -245,7 +245,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 17;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
@@ -284,7 +284,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
- cc->tcg_initialize = cris_initialize_tcg;
+ cc->tcg_ops.initialize = cris_initialize_tcg;
}
#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e28f047d10..80e3081631 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -154,7 +154,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
cc->disas_set_info = hppa_cpu_disas_set_info;
- cc->tcg_initialize = hppa_translate_init;
+ cc->tcg_ops.initialize = hppa_translate_init;
cc->gdb_num_core_regs = 128;
}
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 4fa013720e..d90502a0cc 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -64,7 +64,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
- cc->tcg_initialize = tcg_x86_init;
+ cc->tcg_ops.initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c50ad5fa15..ef795b81a4 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -237,7 +237,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
- cc->tcg_initialize = lm32_translate_init;
+ cc->tcg_ops.initialize = lm32_translate_init;
}
#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b811a0bdde..3604ece49b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -478,7 +478,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
dc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
- cc->tcg_initialize = m68k_tcg_init;
+ cc->tcg_ops.initialize = m68k_tcg_init;
cc->gdb_num_core_regs = 18;
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index d5e8bfe11f..f2978ca726 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -382,7 +382,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 32 + 27;
cc->disas_set_info = mb_disas_set_info;
- cc->tcg_initialize = mb_tcg_init;
+ cc->tcg_ops.initialize = mb_tcg_init;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4c4548233c..b96c3d5969 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -689,7 +689,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = mips_tcg_init;
+ cc->tcg_ops.initialize = mips_tcg_init;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 6e0443ccb7..224cfc8361 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -116,7 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
- cc->tcg_initialize = moxie_translate_init;
+ cc->tcg_ops.initialize = moxie_translate_init;
}
static void moxielite_initfn(Object *obj)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 58688e1623..c28eb05ef0 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -234,7 +234,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
cc->gdb_num_core_regs = 49;
- cc->tcg_initialize = nios2_tcg_init;
+ cc->tcg_ops.initialize = nios2_tcg_init;
}
static const TypeInfo nios2_cpu_type_info = {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b0bdfbe4fe..a957f59e2e 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -198,7 +198,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
- cc->tcg_initialize = openrisc_translate_init;
+ cc->tcg_ops.initialize = openrisc_translate_init;
cc->disas_set_info = openrisc_disas_set_info;
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 27788021eb..567f6790a9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,7 +618,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
#ifdef CONFIG_TCG
- cc->tcg_initialize = riscv_translate_init;
+ cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
#endif
device_class_set_props(dc, riscv_cpu_properties);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 2bb14144a7..cdcab49c8a 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -195,7 +195,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
- cc->tcg_initialize = rx_translate_init;
+ cc->tcg_ops.initialize = rx_translate_init;
cc->tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7da70afbf2..890781e74c 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -515,7 +515,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = s390x_translate_init;
+ cc->tcg_ops.initialize = s390x_translate_init;
cc->tlb_fill = s390_cpu_tlb_fill;
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 1e0f05a15b..b86753cda5 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -232,7 +232,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
- cc->tcg_initialize = sh4_translate_init;
+ cc->tcg_ops.initialize = sh4_translate_init;
cc->gdb_num_core_regs = 59;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 6f14e370ed..3ab71e9d00 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -881,7 +881,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
- cc->tcg_initialize = sparc_tcg_init;
+ cc->tcg_ops.initialize = sparc_tcg_init;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 1fee87c094..cd24d0eb9d 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -153,7 +153,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
- cc->tcg_initialize = tilegx_tcg_init;
+ cc->tcg_ops.initialize = tilegx_tcg_init;
}
static const TypeInfo tilegx_cpu_type_info = {
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 4bff1d4718..bf135af40f 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -164,7 +164,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
- cc->tcg_initialize = tricore_tcg_init;
+ cc->tcg_ops.initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index b27fb9689f..226bf4226e 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -137,7 +137,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->tcg_initialize = uc32_translate_init;
+ cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 88a32268a1..5a6f5bf88b 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -209,7 +209,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->tcg_initialize = xtensa_translate_init;
+ cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 3c05a17343..189f27cd1c 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10878,7 +10878,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
#ifdef CONFIG_TCG
- cc->tcg_initialize = ppc_translate_init;
+ cc->tcg_ops.initialize = ppc_translate_init;
cc->tlb_fill = ppc_cpu_tlb_fill;
#endif
#ifndef CONFIG_USER_ONLY
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (28 preceding siblings ...)
2021-02-05 22:56 ` [PULL 29/46] cpu: Introduce TCGCpuOperations struct Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn Richard Henderson
` (17 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, peter.maydell, Alistair Francis, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-3-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 567f6790a9..60d0b43153 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,10 +617,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
-#ifdef CONFIG_TCG
cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
-#endif
+
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (29 preceding siblings ...)
2021-02-05 22:56 ` [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops Richard Henderson
` (16 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
move away TCG-only code, make it compile only on TCG.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-4-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 11 +++++--
include/hw/core/cpu.h | 2 ++
accel/tcg/cpu-exec.c | 28 +++++++++++++++++
cpu.c | 70 ++++++++++++++++++++----------------------
hw/core/cpu.c | 6 +++-
5 files changed, 77 insertions(+), 40 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 4b5408c341..cfb1d79331 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -410,19 +410,26 @@ static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr)
}
#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
void dump_drift_info(void);
+/* accel/tcg/translate-all.c */
void dump_exec_info(void);
void dump_opcount_info(void);
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
+#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
+int cpu_exec(CPUState *cpu);
+void tcg_exec_realizefn(CPUState *cpu, Error **errp);
+void tcg_exec_unrealizefn(CPUState *cpu);
+#endif /* CONFIG_TCG */
+
/* Returns: 0 on success, -1 on error */
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
void *ptr, target_ulong len, bool is_write);
-int cpu_exec(CPUState *cpu);
-
/**
* cpu_set_cpustate_pointers(cpu)
* @cpu: The cpu object
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 26b89fd7a4..d0b17dcc4c 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1126,6 +1126,8 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
+
+/* $(top_srcdir)/cpu.c */
void cpu_exec_initfn(CPUState *cpu);
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 6d017e46dd..5628a156d1 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -828,6 +828,34 @@ int cpu_exec(CPUState *cpu)
return ret;
}
+void tcg_exec_realizefn(CPUState *cpu, Error **errp)
+{
+ static bool tcg_target_initialized;
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!tcg_target_initialized) {
+ cc->tcg_ops.initialize();
+ tcg_target_initialized = true;
+ }
+ tlb_init(cpu);
+ qemu_plugin_vcpu_init_hook(cpu);
+
+#ifndef CONFIG_USER_ONLY
+ tcg_iommu_init_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+}
+
+/* undo the initializations in reverse order */
+void tcg_exec_unrealizefn(CPUState *cpu)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_iommu_free_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+
+ qemu_plugin_vcpu_exit_hook(cpu);
+ tlb_destroy(cpu);
+}
+
#ifndef CONFIG_USER_ONLY
void dump_drift_info(void)
diff --git a/cpu.c b/cpu.c
index 79a2bf12b3..bfbe5a66f9 100644
--- a/cpu.c
+++ b/cpu.c
@@ -124,12 +124,34 @@ const VMStateDescription vmstate_cpu_common = {
};
#endif
-void cpu_exec_unrealizefn(CPUState *cpu)
+void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- tlb_destroy(cpu);
- cpu_list_remove(cpu);
+ cpu_list_add(cpu);
+
+#ifdef CONFIG_TCG
+ /* NB: errp parameter is unused currently */
+ if (tcg_enabled()) {
+ tcg_exec_realizefn(cpu, errp);
+ }
+#endif /* CONFIG_TCG */
+
+#ifdef CONFIG_USER_ONLY
+ assert(cc->vmsd == NULL);
+#else
+ if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+ vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
+ }
+ if (cc->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ }
+#endif /* CONFIG_USER_ONLY */
+}
+
+void cpu_exec_unrealizefn(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
#ifdef CONFIG_USER_ONLY
assert(cc->vmsd == NULL);
@@ -140,8 +162,15 @@ void cpu_exec_unrealizefn(CPUState *cpu)
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
}
- tcg_iommu_free_notifier_list(cpu);
#endif
+#ifdef CONFIG_TCG
+ /* NB: errp parameter is unused currently */
+ if (tcg_enabled()) {
+ tcg_exec_unrealizefn(cpu);
+ }
+#endif /* CONFIG_TCG */
+
+ cpu_list_remove(cpu);
}
void cpu_exec_initfn(CPUState *cpu)
@@ -156,39 +185,6 @@ void cpu_exec_initfn(CPUState *cpu)
#endif
}
-void cpu_exec_realizefn(CPUState *cpu, Error **errp)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_TCG
- static bool tcg_target_initialized;
-#endif /* CONFIG_TCG */
-
- cpu_list_add(cpu);
-
-#ifdef CONFIG_TCG
- if (tcg_enabled() && !tcg_target_initialized) {
- tcg_target_initialized = true;
- cc->tcg_ops.initialize();
- }
-#endif /* CONFIG_TCG */
- tlb_init(cpu);
-
- qemu_plugin_vcpu_init_hook(cpu);
-
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else /* !CONFIG_USER_ONLY */
- if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
- vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
- }
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
- }
-
- tcg_iommu_init_notifier_list(cpu);
-#endif
-}
-
const char *parse_cpu_option(const char *cpu_option)
{
ObjectClass *oc;
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7553411653..57542b6906 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -199,6 +199,10 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
return target_words_bigendian();
}
+/*
+ * XXX the following #if is always true because this is a common_ss
+ * module, so target CONFIG_* is never defined.
+ */
#if !defined(CONFIG_USER_ONLY)
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
@@ -340,9 +344,9 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
static void cpu_common_unrealizefn(DeviceState *dev)
{
CPUState *cpu = CPU(dev);
+
/* NOTE: latest generic point before the cpu is fully unrealized */
trace_fini_vcpu(cpu);
- qemu_plugin_vcpu_exit_hook(cpu);
cpu_exec_unrealizefn(cpu);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (30 preceding siblings ...)
2021-02-05 22:56 ` [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 33/46] cpu: Move cpu_exec_* " Richard Henderson
` (15 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Alex Bennée, Eduardo Habkost, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped target code in CONFIG_TCG, reworded comments]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-5-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 22 +++++++++++++---------
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 4 +++-
target/avr/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
13 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d0b17dcc4c..8cf5585db7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -86,6 +86,19 @@ typedef struct TcgCpuOperations {
* Called when the first CPU is realized.
*/
void (*initialize)(void);
+ /**
+ * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
+ *
+ * This is called when we abandon execution of a TB before starting it,
+ * and must set all parts of the CPU state which the previous TB in the
+ * chain may not have updated.
+ * By default, when this is NULL, a call is made to @set_pc(tb->pc).
+ *
+ * If more state needs to be restored, the target must implement a
+ * function to restore all the state, and register it here.
+ */
+ void (*synchronize_from_tb)(CPUState *cpu,
+ const struct TranslationBlock *tb);
} TcgCpuOperations;
@@ -119,13 +132,6 @@ typedef struct TcgCpuOperations {
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @synchronize_from_tb: Callback for synchronizing state from a TCG
- * #TranslationBlock. This is called when we abandon execution
- * of a TB before starting it, and must set all parts of the CPU
- * state which the previous TB in the chain may not have updated.
- * This always includes at least the program counter; some targets
- * will need to do more. If this hook is not implemented then the
- * default is to call @set_pc(tb->pc).
* @tlb_fill: Callback for handling a softmmu tlb miss or user-only
* address fault. For system mode, if the access is valid, call
* tlb_set_page and return true; if the access is invalid, and
@@ -202,8 +208,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- void (*synchronize_from_tb)(CPUState *cpu,
- const struct TranslationBlock *tb);
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5628a156d1..12b6a91d62 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -213,8 +213,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
TARGET_FMT_lx "] %s\n",
last_tb->tc.ptr, last_tb->pc,
lookup_symbol(last_tb->pc));
- if (cc->synchronize_from_tb) {
- cc->synchronize_from_tb(cpu, last_tb);
+ if (cc->tcg_ops.synchronize_from_tb) {
+ cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
} else {
assert(cc->set_pc);
cc->set_pc(cpu, last_tb->pc);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index fa4d4ba4eb..140cb33f07 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -70,6 +71,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs,
env->regs[15] = tb->pc;
}
}
+#endif /* CONFIG_TCG */
static bool arm_cpu_has_work(CPUState *cs)
{
@@ -2257,7 +2259,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
- cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -2277,6 +2278,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = arm_translate_init;
+ cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index fb66695fbb..a82fa9d7a8 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -208,7 +208,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_ops.initialize = avr_cpu_tcg_init;
- cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_num_core_regs = 35;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 80e3081631..94ea3014a3 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -144,7 +144,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
- cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
cc->tlb_fill = hppa_cpu_tlb_fill;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index d90502a0cc..874286de28 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -61,7 +61,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
- cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f2978ca726..e40d1db88d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -369,7 +369,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
- cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tlb_fill = mb_cpu_tlb_fill;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b96c3d5969..350f1c66c7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -257,6 +257,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void mips_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -267,6 +268,7 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs,
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
+#endif /* CONFIG_TCG */
static bool mips_cpu_has_work(CPUState *cs)
{
@@ -678,7 +680,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
- cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -690,6 +691,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 60d0b43153..1e9bd3c313 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -597,7 +597,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
- cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index cdcab49c8a..4e0de14eef 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -190,7 +190,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
- cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index b86753cda5..130debe074 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,7 +223,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
- cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
cc->tlb_fill = superh_cpu_tlb_fill;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 3ab71e9d00..0ae38eb496 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -870,7 +870,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
#endif
cc->set_pc = sparc_cpu_set_pc;
- cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tlb_fill = sparc_cpu_tlb_fill;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index bf135af40f..09cc6a0e62 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 33/46] cpu: Move cpu_exec_* to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (31 preceding siblings ...)
2021-02-05 22:56 ` [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 34/46] cpu: Move tlb_fill " Richard Henderson
` (14 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
Eduardo Habkost, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-6-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 12 ++++++------
accel/tcg/cpu-exec.c | 12 ++++++------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 5 ++++-
target/arm/cpu_tcg.c | 7 ++++++-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 6 +++---
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 16 ++++++++++------
25 files changed, 54 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8cf5585db7..532984e016 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -99,6 +99,12 @@ typedef struct TcgCpuOperations {
*/
void (*synchronize_from_tb)(CPUState *cpu,
const struct TranslationBlock *tb);
+ /** @cpu_exec_enter: Callback for cpu_exec preparation */
+ void (*cpu_exec_enter)(CPUState *cpu);
+ /** @cpu_exec_exit: Callback for cpu_exec cleanup */
+ void (*cpu_exec_exit)(CPUState *cpu);
+ /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
} TcgCpuOperations;
@@ -168,9 +174,6 @@ typedef struct TcgCpuOperations {
* @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
* gdb stub. Returns a pointer to the XML contents for the specified XML file
* or NULL if the CPU doesn't have a dynamically generated content for it.
- * @cpu_exec_enter: Callback for cpu_exec preparation.
- * @cpu_exec_exit: Callback for cpu_exec cleanup.
- * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
* @disas_set_info: Setup architecture specific components of disassembly info
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
@@ -233,9 +236,6 @@ struct CPUClass {
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
- void (*cpu_exec_enter)(CPUState *cpu);
- void (*cpu_exec_exit)(CPUState *cpu);
- bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 12b6a91d62..953f050698 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -262,8 +262,8 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->cpu_exec_enter) {
- cc->cpu_exec_enter(cpu);
+ if (cc->tcg_ops.cpu_exec_enter) {
+ cc->tcg_ops.cpu_exec_enter(cpu);
}
}
@@ -271,8 +271,8 @@ static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->cpu_exec_exit) {
- cc->cpu_exec_exit(cpu);
+ if (cc->tcg_ops.cpu_exec_exit) {
+ cc->tcg_ops.cpu_exec_exit(cpu);
}
}
@@ -655,8 +655,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- if (cc->cpu_exec_interrupt &&
- cc->cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (cc->tcg_ops.cpu_exec_interrupt &&
+ cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d66f0351a9..d9ced1635a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,7 +218,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
- cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 140cb33f07..98a5a0c648 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2256,7 +2256,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
@@ -2278,6 +2277,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = arm_translate_init;
+ cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5e851028c5..a9a1cdb871 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -805,7 +805,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
+#endif /* CONFIG_TCG */
+
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 98544db2df..f2e565166e 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifdef CONFIG_TCG
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
+#endif /* CONFIG_TCG */
static void arm926_initfn(Object *obj)
{
@@ -668,7 +670,10 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#endif /* CONFIG_TCG */
+
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a82fa9d7a8..499a98dcee 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -199,7 +199,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = avr_cpu_has_work;
cc->do_interrupt = avr_cpu_do_interrupt;
- cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 4328f8e6c9..7489fc20c8 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -269,7 +269,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
cc->do_interrupt = cris_cpu_do_interrupt;
- cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 94ea3014a3..34c598230e 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -141,7 +141,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
cc->do_interrupt = hppa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 874286de28..b7c485aa76 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -60,10 +60,10 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
- cc->cpu_exec_enter = x86_cpu_exec_enter;
- cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
+ cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index ef795b81a4..eea2d3e515 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -223,7 +223,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
cc->do_interrupt = lm32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 3604ece49b..0d5f8e0dd8 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -466,7 +466,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
- cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index e40d1db88d..35b4b2eb9d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -366,7 +366,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
cc->do_unaligned_access = mb_cpu_do_unaligned_access;
- cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 350f1c66c7..929f98a57a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -677,7 +677,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
- cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->gdb_read_register = mips_cpu_gdb_read_register;
@@ -691,6 +690,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index c28eb05ef0..b0d51f77f5 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -222,7 +222,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
cc->do_interrupt = nios2_cpu_do_interrupt;
- cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index a957f59e2e..48c416e138 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -187,7 +187,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e9bd3c313..81ec7e6c99 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -594,7 +594,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
- cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 4e0de14eef..9493e9031a 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -187,7 +187,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
cc->do_interrupt = rx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 890781e74c..53c2f6f89e 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -508,7 +508,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
- cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 130debe074..b2d4e3648c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -220,7 +220,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
cc->do_interrupt = superh_cpu_do_interrupt;
- cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0ae38eb496..139939494e 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -864,7 +864,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index cd24d0eb9d..4c6176d26e 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -148,7 +148,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 226bf4226e..84c3419989 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -132,7 +132,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
cc->do_interrupt = uc32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 5a6f5bf88b..42a5e4ebe8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -195,7 +195,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
cc->do_interrupt = xtensa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 189f27cd1c..2b0343686f 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10700,6 +10700,7 @@ static void ppc_cpu_reset(DeviceState *dev)
}
#ifndef CONFIG_USER_ONLY
+
static bool ppc_cpu_is_big_endian(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -10710,6 +10711,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
return !msr_le;
}
+#ifdef CONFIG_TCG
static void ppc_cpu_exec_enter(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -10731,7 +10733,9 @@ static void ppc_cpu_exec_exit(CPUState *cs)
vhc->cpu_exec_exit(cpu->vhyp, cpu);
}
}
-#endif
+#endif /* CONFIG_TCG */
+
+#endif /* !CONFIG_USER_ONLY */
static void ppc_cpu_instance_init(Object *obj)
{
@@ -10842,7 +10846,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = ppc_cpu_class_by_name;
cc->has_work = ppc_cpu_has_work;
cc->do_interrupt = ppc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -10879,12 +10882,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#endif
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
+ cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
cc->tlb_fill = ppc_cpu_tlb_fill;
-#endif
#ifndef CONFIG_USER_ONLY
- cc->cpu_exec_enter = ppc_cpu_exec_enter;
- cc->cpu_exec_exit = ppc_cpu_exec_exit;
-#endif
+ cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
+ cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
cc->disas_set_info = ppc_disas_set_info;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 34/46] cpu: Move tlb_fill to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (32 preceding siblings ...)
2021-02-05 22:56 ` [PULL 33/46] cpu: Move cpu_exec_* " Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 35/46] cpu: Move debug_excp_handler " Richard Henderson
` (13 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
Eduardo Habkost, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-7-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 21 ++++++++++++---------
accel/tcg/cputlb.c | 7 ++++---
accel/tcg/user-exec.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
26 files changed, 42 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 532984e016..94236b68d7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -105,6 +105,18 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
+ *
+ * For system mode, if the access is valid, call tlb_set_page
+ * and return true; if the access is invalid, and probe is
+ * true, return false; otherwise raise an exception and do
+ * not return. For user-only mode, always raise an exception
+ * and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
} TcgCpuOperations;
@@ -138,12 +150,6 @@ typedef struct TcgCpuOperations {
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
- * address fault. For system mode, if the access is valid, call
- * tlb_set_page and return true; if the access is invalid, and
- * probe is true, return false; otherwise raise an exception and
- * do not return. For user-only mode, always raise an exception
- * and do not return.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
* associated memory transaction attributes to use for the access.
@@ -211,9 +217,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 7a69726ba4..b7717803b8 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1305,7 +1305,8 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
- ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+ ok = cc->tcg_ops.tlb_fill(cpu, addr, size,
+ access_type, mmu_idx, false, retaddr);
assert(ok);
}
@@ -1576,8 +1577,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
CPUState *cs = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cs);
- if (!cc->tlb_fill(cs, addr, fault_size, access_type,
- mmu_idx, nonfault, retaddr)) {
+ if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
*phost = NULL;
return TLB_INVALID_MASK;
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 1215b55ca0..5509dd53e9 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -187,7 +187,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
+ cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
@@ -217,8 +217,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
} else {
CPUState *cpu = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tlb_fill(cpu, addr, fault_size, access_type,
- MMU_USER_IDX, false, ra);
+ cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
+ MMU_USER_IDX, false, ra);
g_assert_not_reached();
}
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d9ced1635a..9f36f824fd 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -223,7 +223,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
- cc->tlb_fill = alpha_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 98a5a0c648..27a16c1950 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2279,7 +2279,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.initialize = arm_translate_init;
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
- cc->tlb_fill = arm_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 499a98dcee..d6e93049b4 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -204,7 +204,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->tlb_fill = avr_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_ops.initialize = avr_cpu_tcg_init;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 7489fc20c8..9222717f3e 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -274,7 +274,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
- cc->tlb_fill = cris_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 34c598230e..d5a25014e8 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -147,7 +147,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
- cc->tlb_fill = hppa_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index b7c485aa76..85b69224a9 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -65,7 +65,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
- cc->tlb_fill = x86_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
#endif
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index eea2d3e515..76dc728858 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -228,7 +228,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
- cc->tlb_fill = lm32_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = lm32_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 0d5f8e0dd8..e38e4d5456 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -471,7 +471,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
- cc->tlb_fill = m68k_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
cc->do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 35b4b2eb9d..3c09507069 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -372,7 +372,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
- cc->tlb_fill = mb_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 929f98a57a..63c0f3b94c 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -692,7 +692,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.initialize = mips_tcg_init;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
- cc->tlb_fill = mips_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#endif
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 224cfc8361..1177d092c1 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -110,7 +110,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
- cc->tlb_fill = moxie_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index b0d51f77f5..1384836de0 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -226,7 +226,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
- cc->tlb_fill = nios2_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 48c416e138..9857bfde23 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -192,7 +192,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
- cc->tlb_fill = openrisc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 81ec7e6c99..9d813924ef 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,7 +618,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
cc->tcg_ops.initialize = riscv_translate_init;
- cc->tlb_fill = riscv_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill;
device_class_set_props(dc, riscv_cpu_properties);
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 9493e9031a..77609728b8 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -196,7 +196,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->tcg_ops.initialize = rx_translate_init;
- cc->tlb_fill = rx_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "rx-core.xml";
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 53c2f6f89e..ceee62ddca 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = s390_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = s390x_translate_init;
- cc->tlb_fill = s390_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = s390_cpu_tlb_fill;
#endif
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index b2d4e3648c..1f6c687c3c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -226,7 +226,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
- cc->tlb_fill = superh_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 139939494e..19e90a414d 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -873,7 +873,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
- cc->tlb_fill = sparc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 4c6176d26e..75b3a4bae3 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -151,7 +151,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
- cc->tlb_fill = tilegx_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
cc->tcg_ops.initialize = tilegx_tcg_init;
}
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 09cc6a0e62..9b21b640e2 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -165,7 +165,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = tricore_tcg_init;
- cc->tlb_fill = tricore_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = tricore_cpu_tlb_fill;
}
#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 84c3419989..a57d315d2f 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -135,7 +135,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->tlb_fill = uc32_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 42a5e4ebe8..e764dbeb73 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -201,7 +201,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
- cc->tlb_fill = xtensa_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 2b0343686f..1e0fc5ac3d 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10883,7 +10883,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
- cc->tlb_fill = ppc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 35/46] cpu: Move debug_excp_handler to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (33 preceding siblings ...)
2021-02-05 22:56 ` [PULL 34/46] cpu: Move tlb_fill " Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly Richard Henderson
` (12 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Alex Bennée, Eduardo Habkost, Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-8-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 94236b68d7..ff82eae939 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -117,6 +117,8 @@ typedef struct TcgCpuOperations {
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+ /** @debug_excp_handler: Callback for handling debug exceptions */
+ void (*debug_excp_handler)(CPUState *cpu);
} TcgCpuOperations;
@@ -161,7 +163,6 @@ typedef struct TcgCpuOperations {
* @gdb_write_register: Callback for letting GDB write a register.
* @debug_check_watchpoint: Callback: return true if the architectural
* watchpoint whose address has matched should really fire.
- * @debug_excp_handler: Callback for handling debug exceptions.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -224,7 +225,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
- void (*debug_excp_handler)(CPUState *cpu);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 953f050698..e7e54fd75d 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -512,8 +512,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- if (cc->debug_excp_handler) {
- cc->debug_excp_handler(cpu);
+ if (cc->tcg_ops.debug_excp_handler) {
+ cc->tcg_ops.debug_excp_handler(cpu);
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 27a16c1950..66ac210b0c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2280,7 +2280,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
- cc->debug_excp_handler = arm_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 85b69224a9..6c1ebbdcc6 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -67,6 +67,6 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.initialize = tcg_x86_init;
cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->debug_excp_handler = breakpoint_handler;
+ cc->tcg_ops.debug_excp_handler = breakpoint_handler;
#endif
}
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 76dc728858..bbe1405e32 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
- cc->debug_excp_handler = lm32_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
cc->tcg_ops.initialize = lm32_translate_init;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index ceee62ddca..8ade66178e 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -509,7 +509,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
- cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e764dbeb73..b6f13ceb32 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
- cc->debug_excp_handler = xtensa_breakpoint_handler;
+ cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (34 preceding siblings ...)
2021-02-05 22:56 ` [PULL 35/46] cpu: Move debug_excp_handler " Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 37/46] cpu: move cc->do_interrupt to tcg_ops Richard Henderson
` (11 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Alex Bennée, Claudio Fontana,
Philippe Mathieu-Daudé
From: Claudio Fontana <cfontana@suse.de>
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture state in a
similar way where userspace code has identified that it needs to
deliver an exception to the guest.
In the case of ARM, that includes:
1) the vcpu thread got a SIGBUS indicating a memory error,
and we need to deliver a Synchronous External Abort to the guest to
let it know about the error.
2) the kernel told us about a debug exception (breakpoint, watchpoint)
but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
so it must be a breakpoint the guest itself has set up, therefore
we need to deliver it to the guest.
So in order to reuse code, the same arm_do_interrupt function is used.
This is all fine, but we need to avoid calling it using the callback
registered in CPUClass, since that one is now TCG-only.
Fortunately this is easily solved by replacing calls to
CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210204163931.7358-9-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 4 ++++
target/arm/kvm64.c | 6 ++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 47e266d7e6..1a64bd748c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9969,6 +9969,10 @@ static void handle_semihosting(CPUState *cs)
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
+ *
+ * Note: this is used for both TCG (as the do_interrupt tcg op),
+ * and KVM to re-inject guest debug exceptions, and to
+ * inject a Synchronous-External-Abort.
*/
void arm_cpu_do_interrupt(CPUState *cs)
{
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 3c37fc4fb6..dff85f6db9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -946,7 +946,6 @@ static void kvm_inject_arm_sea(CPUState *c)
{
ARMCPU *cpu = ARM_CPU(c);
CPUARMState *env = &cpu->env;
- CPUClass *cc = CPU_GET_CLASS(c);
uint32_t esr;
bool same_el;
@@ -962,7 +961,7 @@ static void kvm_inject_arm_sea(CPUState *c)
env->exception.syndrome = esr;
- cc->do_interrupt(c);
+ arm_cpu_do_interrupt(c);
}
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
@@ -1493,7 +1492,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
{
int hsr_ec = syn_get_ec(debug_exit->hsr);
ARMCPU *cpu = ARM_CPU(cs);
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUARMState *env = &cpu->env;
/* Ensure PC is synchronised */
@@ -1547,7 +1545,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
env->exception.vaddress = debug_exit->far;
env->exception.target_el = 1;
qemu_mutex_lock_iothread();
- cc->do_interrupt(cs);
+ arm_cpu_do_interrupt(cs);
qemu_mutex_unlock_iothread();
return false;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 37/46] cpu: move cc->do_interrupt to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (35 preceding siblings ...)
2021-02-05 22:56 ` [PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 38/46] cpu: move cc->transaction_failed " Richard Henderson
` (10 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-10-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/arm/cpu_tcg.c | 9 ++++-----
target/avr/cpu.c | 2 +-
target/avr/helper.c | 4 ++--
target/cris/cpu.c | 12 ++++++------
target/cris/helper.c | 4 ++--
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 ++--
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
27 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index ff82eae939..60cf20bf05 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -105,6 +105,8 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /** @do_interrupt: Callback for interrupt handling. */
+ void (*do_interrupt)(CPUState *cpu);
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
@@ -129,7 +131,6 @@ typedef struct TcgCpuOperations {
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_interrupt: Callback for interrupt handling.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
* @do_transaction_failed: Callback for handling failed memory transactions
@@ -199,7 +200,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- void (*do_interrupt)(CPUState *cpu);
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index e7e54fd75d..633ee3ef9e 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -547,7 +547,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->do_interrupt(cpu);
+ cc->tcg_ops.do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;
@@ -556,7 +556,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (replay_exception()) {
CPUClass *cc = CPU_GET_CLASS(cpu);
qemu_mutex_lock_iothread();
- cc->do_interrupt(cpu);
+ cc->tcg_ops.do_interrupt(cpu);
qemu_mutex_unlock_iothread();
cpu->exception_index = -1;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 9f36f824fd..66f1166672 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
- cc->do_interrupt = alpha_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 66ac210b0c..dfb2398392 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -590,7 +590,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
return true;
}
@@ -2261,7 +2261,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_cpu_do_interrupt;
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->vmsd = &vmstate_arm_cpu;
@@ -2286,6 +2285,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+ cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif
}
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index f2e565166e..d9c160f1ac 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -34,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
return ret;
@@ -666,12 +666,11 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
-#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
-#endif
-
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#ifndef CONFIG_USER_ONLY
+ cc->tcg_ops.do_interrupt = arm_v7m_cpu_do_interrupt;
+#endif
#endif /* CONFIG_TCG */
cc->gdb_core_xml_file = "arm-m-profile.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index d6e93049b4..476e645b37 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
- cc->do_interrupt = avr_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = avr_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
diff --git a/target/avr/helper.c b/target/avr/helper.c
index d96d14372b..69d3b6181f 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -34,7 +34,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
@@ -45,7 +45,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
int index = ctz32(env->intsrc);
cs->exception_index = EXCP_INT(index);
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 9222717f3e..b65743e8ca 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -199,7 +199,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -210,7 +210,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -221,7 +221,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -232,7 +232,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -243,7 +243,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -268,7 +268,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
- cc->do_interrupt = cris_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = cris_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
diff --git a/target/cris/helper.c b/target/cris/helper.c
index ed45c3d9b7..1f4d6f7d45 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -299,7 +299,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
@@ -311,7 +311,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
cs->exception_index = EXCP_NMI;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d5a25014e8..68233acf53 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
- cc->do_interrupt = hppa_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 6c1ebbdcc6..4a53cd89e2 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -59,7 +59,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
void tcg_cpu_common_class_init(CPUClass *cc)
{
- cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = x86_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index bbe1405e32..fb3761b749 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -222,7 +222,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
- cc->do_interrupt = lm32_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = lm32_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index e38e4d5456..69093a621f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -465,7 +465,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
- cc->do_interrupt = m68k_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = m68k_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 3c09507069..c93e44b8e5 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -364,7 +364,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
- cc->do_interrupt = mb_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
cc->do_unaligned_access = mb_cpu_do_unaligned_access;
cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 63c0f3b94c..a88a138a8d 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -676,7 +676,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
- cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->gdb_read_register = mips_cpu_gdb_read_register;
@@ -690,10 +689,11 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
-#endif
+#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 1177d092c1..36bef4d357 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -107,7 +107,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = moxie_cpu_class_by_name;
cc->has_work = moxie_cpu_has_work;
- cc->do_interrupt = moxie_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 1384836de0..b5fe779ceb 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -221,7 +221,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
- cc->do_interrupt = nios2_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = nios2_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 9857bfde23..1a31f7564f 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,7 +186,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
- cc->do_interrupt = openrisc_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = openrisc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9d813924ef..345b78fc3d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -593,7 +593,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
- cc->do_interrupt = riscv_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = riscv_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 77609728b8..e79f009cbd 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
- cc->do_interrupt = rx_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = rx_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 8ade66178e..e6cf933594 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -496,7 +496,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = s390_cpu_class_by_name,
cc->has_work = s390_cpu_has_work;
#ifdef CONFIG_TCG
- cc->do_interrupt = s390_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = s390_cpu_do_interrupt;
#endif
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 1f6c687c3c..f69360fc16 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
- cc->do_interrupt = superh_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = superh_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 19e90a414d..871b2a83c6 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -863,7 +863,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
- cc->do_interrupt = sparc_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = sparc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 75b3a4bae3..7d4ead4ef1 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -147,7 +147,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
- cc->do_interrupt = tilegx_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = tilegx_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a57d315d2f..e27ffc571a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -131,7 +131,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
- cc->do_interrupt = uc32_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = uc32_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index b6f13ceb32..3ff025f0fe 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -194,7 +194,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
- cc->do_interrupt = xtensa_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = xtensa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 1e0fc5ac3d..b16430a9d4 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,7 +10845,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = ppc_cpu_class_by_name;
cc->has_work = ppc_cpu_has_work;
- cc->do_interrupt = ppc_cpu_do_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -10883,6 +10882,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
+ cc->tcg_ops.do_interrupt = ppc_cpu_do_interrupt;
cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 38/46] cpu: move cc->transaction_failed to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (36 preceding siblings ...)
2021-02-05 22:56 ` [PULL 37/46] cpu: move cc->do_interrupt to tcg_ops Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-23 21:43 ` Philippe Mathieu-Daudé
2021-02-05 22:56 ` [PULL 39/46] cpu: move do_unaligned_access " Richard Henderson
` (9 subsequent siblings)
47 siblings, 1 reply; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Alex Bennée, Claudio Fontana,
Philippe Mathieu-Daudé
From: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
avoiding its use in headers used by common_ss code (should be poisoned).
Note: need to be careful with the use of CONFIG_USER_ONLY,
Message-Id: <20210204163931.7358-11-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 28 +++++++++++++---------------
hw/mips/jazz.c | 9 +++++++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 4 ++--
12 files changed, 34 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 60cf20bf05..41ce1daefc 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -122,6 +122,14 @@ typedef struct TcgCpuOperations {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+ /**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
} TcgCpuOperations;
/**
@@ -133,8 +141,6 @@ typedef struct TcgCpuOperations {
* @has_work: Callback for checking if there is work to do.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -203,10 +209,6 @@ struct CPUClass {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
- void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -879,9 +881,6 @@ CPUState *cpu_by_arch_id(int64_t id);
void cpu_interrupt(CPUState *cpu, int mask);
-#ifdef NEED_CPU_H
-
-#ifdef CONFIG_SOFTMMU
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -900,14 +899,13 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
- cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
+ if (!cpu->ignore_memory_transaction_failures &&
+ cc->tcg_ops.do_transaction_failed) {
+ cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx, attrs,
+ response, retaddr);
}
}
-#endif
-
-#endif /* NEED_CPU_H */
/**
* cpu_set_pc:
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index f9442731dd..46c71a0ac8 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -137,6 +139,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
mmu_idx, attrs, response, retaddr);
}
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
@@ -205,8 +208,10 @@ static void mips_jazz_init(MachineState *machine,
* memory region that catches all memory accesses, as we do on Malta.
*/
cc = CPU_GET_CLASS(cpu);
- real_do_transaction_failed = cc->do_transaction_failed;
- cc->do_transaction_failed = mips_jazz_do_transaction_failed;
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
+ real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 66f1166672..a1696bebeb 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dfb2398392..bd1882944c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2283,11 +2283,11 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-#endif
+#endif /* CONFIG_TCG */
}
#ifdef CONFIG_KVM
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 69093a621f..e68b933c84 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -473,7 +473,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
- cc->do_transaction_failed = m68k_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
#endif
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c93e44b8e5..e405f6422d 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -374,7 +374,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a88a138a8d..ed2a7664e9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -681,7 +681,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
@@ -693,6 +692,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 345b78fc3d..9a23af9a9d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -609,7 +609,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f8350f5f78..2f43939fb6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -671,7 +671,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 871b2a83c6..8d6d7c1f83 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -875,7 +875,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 3ff025f0fe..fc52fde696 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 05e2b7f70a..eeffee297d 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_loop_exit_restore(cs, retaddr);
}
-#else
+#else /* !CONFIG_USER_ONLY */
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
@@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall)
qemu_cpu_kick(cpu);
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* Re: [PULL 38/46] cpu: move cc->transaction_failed to tcg_ops
2021-02-05 22:56 ` [PULL 38/46] cpu: move cc->transaction_failed " Richard Henderson
@ 2021-02-23 21:43 ` Philippe Mathieu-Daudé
2021-02-24 8:46 ` Claudio Fontana
0 siblings, 1 reply; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-23 21:43 UTC (permalink / raw)
To: Richard Henderson, Claudio Fontana, qemu-devel
Cc: peter.maydell, Thomas Huth, Alex Bennée
On 2/5/21 11:56 PM, Richard Henderson wrote:
> From: Claudio Fontana <cfontana@suse.de>
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
>
> avoiding its use in headers used by common_ss code (should be poisoned).
>
> Note: need to be careful with the use of CONFIG_USER_ONLY,
> Message-Id: <20210204163931.7358-11-cfontana@suse.de>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/cpu.h | 28 +++++++++++++---------------
> hw/mips/jazz.c | 9 +++++++--
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 4 ++--
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 4 +++-
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> target/xtensa/helper.c | 4 ++--
> 12 files changed, 34 insertions(+), 29 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 60cf20bf05..41ce1daefc 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -122,6 +122,14 @@ typedef struct TcgCpuOperations {
> /** @debug_excp_handler: Callback for handling debug exceptions */
> void (*debug_excp_handler)(CPUState *cpu);
>
> + /**
> + * @do_transaction_failed: Callback for handling failed memory transactions
> + * (ie bus faults or external aborts; not MMU faults)
> + */
> + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
> + unsigned size, MMUAccessType access_type,
> + int mmu_idx, MemTxAttrs attrs,
> + MemTxResult response, uintptr_t retaddr);
> } TcgCpuOperations;
>
> /**
> @@ -133,8 +141,6 @@ typedef struct TcgCpuOperations {
> * @has_work: Callback for checking if there is work to do.
> * @do_unaligned_access: Callback for unaligned access handling, if
> * the target defines #TARGET_ALIGNED_ONLY.
> - * @do_transaction_failed: Callback for handling failed memory transactions
> - * (ie bus faults or external aborts; not MMU faults)
> * @virtio_is_big_endian: Callback to return %true if a CPU which supports
> * runtime configurable endianness is currently big-endian. Non-configurable
> * CPUs can use the default implementation of this method. This method should
> @@ -203,10 +209,6 @@ struct CPUClass {
> void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr);
> - void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
> - unsigned size, MMUAccessType access_type,
> - int mmu_idx, MemTxAttrs attrs,
> - MemTxResult response, uintptr_t retaddr);
> bool (*virtio_is_big_endian)(CPUState *cpu);
> int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
> uint8_t *buf, int len, bool is_write);
> @@ -879,9 +881,6 @@ CPUState *cpu_by_arch_id(int64_t id);
>
> void cpu_interrupt(CPUState *cpu, int mask);
>
> -#ifdef NEED_CPU_H
> -
> -#ifdef CONFIG_SOFTMMU
> static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> @@ -900,14 +899,13 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
>
> - if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
> - cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
> - mmu_idx, attrs, response, retaddr);
> + if (!cpu->ignore_memory_transaction_failures &&
> + cc->tcg_ops.do_transaction_failed) {
> + cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
> + access_type, mmu_idx, attrs,
> + response, retaddr);
> }
> }
> -#endif
> -
> -#endif /* NEED_CPU_H */
>
> /**
> * cpu_set_pc:
> diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
> index f9442731dd..46c71a0ac8 100644
> --- a/hw/mips/jazz.c
> +++ b/hw/mips/jazz.c
> @@ -116,6 +116,8 @@ static const MemoryRegionOps dma_dummy_ops = {
> #define MAGNUM_BIOS_SIZE_MAX 0x7e000
> #define MAGNUM_BIOS_SIZE \
> (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
> +
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
> vaddr addr, unsigned size,
> MMUAccessType access_type,
> @@ -137,6 +139,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
> mmu_idx, attrs, response, retaddr);
> }
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>
> static void mips_jazz_init(MachineState *machine,
> enum jazz_model_e jazz_model)
> @@ -205,8 +208,10 @@ static void mips_jazz_init(MachineState *machine,
> * memory region that catches all memory accesses, as we do on Malta.
> */
> cc = CPU_GET_CLASS(cpu);
> - real_do_transaction_failed = cc->do_transaction_failed;
> - cc->do_transaction_failed = mips_jazz_do_transaction_failed;
> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
> + real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
> + cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
Why CONFIG_USER_ONLY isn't poisoned under hw/ ?
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 38/46] cpu: move cc->transaction_failed to tcg_ops
2021-02-23 21:43 ` Philippe Mathieu-Daudé
@ 2021-02-24 8:46 ` Claudio Fontana
0 siblings, 0 replies; 57+ messages in thread
From: Claudio Fontana @ 2021-02-24 8:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: peter.maydell, Thomas Huth, Alex Bennée
On 2/23/21 10:43 PM, Philippe Mathieu-Daudé wrote:
> On 2/5/21 11:56 PM, Richard Henderson wrote:
>> From: Claudio Fontana <cfontana@suse.de>
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>
>> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
>>
>> avoiding its use in headers used by common_ss code (should be poisoned).
>>
>> Note: need to be careful with the use of CONFIG_USER_ONLY,
>> Message-Id: <20210204163931.7358-11-cfontana@suse.de>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/hw/core/cpu.h | 28 +++++++++++++---------------
>> hw/mips/jazz.c | 9 +++++++--
>> target/alpha/cpu.c | 2 +-
>> target/arm/cpu.c | 4 ++--
>> target/m68k/cpu.c | 2 +-
>> target/microblaze/cpu.c | 2 +-
>> target/mips/cpu.c | 4 +++-
>> target/riscv/cpu.c | 2 +-
>> target/riscv/cpu_helper.c | 2 +-
>> target/sparc/cpu.c | 2 +-
>> target/xtensa/cpu.c | 2 +-
>> target/xtensa/helper.c | 4 ++--
>> 12 files changed, 34 insertions(+), 29 deletions(-)
>>
>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>> index 60cf20bf05..41ce1daefc 100644
>> --- a/include/hw/core/cpu.h
>> +++ b/include/hw/core/cpu.h
>> @@ -122,6 +122,14 @@ typedef struct TcgCpuOperations {
>> /** @debug_excp_handler: Callback for handling debug exceptions */
>> void (*debug_excp_handler)(CPUState *cpu);
>>
>> + /**
>> + * @do_transaction_failed: Callback for handling failed memory transactions
>> + * (ie bus faults or external aborts; not MMU faults)
>> + */
>> + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
>> + unsigned size, MMUAccessType access_type,
>> + int mmu_idx, MemTxAttrs attrs,
>> + MemTxResult response, uintptr_t retaddr);
>> } TcgCpuOperations;
>>
>> /**
>> @@ -133,8 +141,6 @@ typedef struct TcgCpuOperations {
>> * @has_work: Callback for checking if there is work to do.
>> * @do_unaligned_access: Callback for unaligned access handling, if
>> * the target defines #TARGET_ALIGNED_ONLY.
>> - * @do_transaction_failed: Callback for handling failed memory transactions
>> - * (ie bus faults or external aborts; not MMU faults)
>> * @virtio_is_big_endian: Callback to return %true if a CPU which supports
>> * runtime configurable endianness is currently big-endian. Non-configurable
>> * CPUs can use the default implementation of this method. This method should
>> @@ -203,10 +209,6 @@ struct CPUClass {
>> void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
>> MMUAccessType access_type,
>> int mmu_idx, uintptr_t retaddr);
>> - void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
>> - unsigned size, MMUAccessType access_type,
>> - int mmu_idx, MemTxAttrs attrs,
>> - MemTxResult response, uintptr_t retaddr);
>> bool (*virtio_is_big_endian)(CPUState *cpu);
>> int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
>> uint8_t *buf, int len, bool is_write);
>> @@ -879,9 +881,6 @@ CPUState *cpu_by_arch_id(int64_t id);
>>
>> void cpu_interrupt(CPUState *cpu, int mask);
>>
>> -#ifdef NEED_CPU_H
>> -
>> -#ifdef CONFIG_SOFTMMU
>> static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
>> MMUAccessType access_type,
>> int mmu_idx, uintptr_t retaddr)
>> @@ -900,14 +899,13 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
>> {
>> CPUClass *cc = CPU_GET_CLASS(cpu);
>>
>> - if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
>> - cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
>> - mmu_idx, attrs, response, retaddr);
>> + if (!cpu->ignore_memory_transaction_failures &&
>> + cc->tcg_ops.do_transaction_failed) {
>> + cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
>> + access_type, mmu_idx, attrs,
>> + response, retaddr);
>> }
>> }
>> -#endif
>> -
>> -#endif /* NEED_CPU_H */
>>
>> /**
>> * cpu_set_pc:
>> diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
>> index f9442731dd..46c71a0ac8 100644
>> --- a/hw/mips/jazz.c
>> +++ b/hw/mips/jazz.c
>> @@ -116,6 +116,8 @@ static const MemoryRegionOps dma_dummy_ops = {
>> #define MAGNUM_BIOS_SIZE_MAX 0x7e000
>> #define MAGNUM_BIOS_SIZE \
>> (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
>> +
>> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>> static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
>> vaddr addr, unsigned size,
>> MMUAccessType access_type,
>> @@ -137,6 +139,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
>> (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
>> mmu_idx, attrs, response, retaddr);
>> }
>> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>>
>> static void mips_jazz_init(MachineState *machine,
>> enum jazz_model_e jazz_model)
>> @@ -205,8 +208,10 @@ static void mips_jazz_init(MachineState *machine,
>> * memory region that catches all memory accesses, as we do on Malta.
>> */
>> cc = CPU_GET_CLASS(cpu);
>> - real_do_transaction_failed = cc->do_transaction_failed;
>> - cc->do_transaction_failed = mips_jazz_do_transaction_failed;
>> +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
>> + real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
>> + cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
>> +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
>
> Why CONFIG_USER_ONLY isn't poisoned under hw/ ?
>
As I can see, hw/ contains a wide variety of objects, which go into hw_arch, specific, softmmu or common.
There does not seem to be a common way to handle objects in hw/ .
In the case of hw/mips, it goes to hw_arch in meson.build, so it sees config target.
Other users of CONFIG_USER_ONLY in hw/ are arm semihosting:
semihosting/arm-compat-semi.c which goes to specific_ss
and hw/cpu.c, which uses CONFIG_USER_ONLY but does not see it, since it is a common_ss module.
So the uses of CONFIG_USER_ONLY in hw/cpu.c are wrong for sure, or at least until hw/cpu.c goes to common_ss.
It does not hurt because the tests are in the negative, and those sysemu-only / softmmu-only symbols are actually always visible, including for CONFIG_USER_ONLY.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PULL 39/46] cpu: move do_unaligned_access to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (37 preceding siblings ...)
2021-02-05 22:56 ` [PULL 38/46] cpu: move cc->transaction_failed " Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 40/46] physmem: make watchpoint checking code TCG-only Richard Henderson
` (8 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Alex Bennée, Claudio Fontana,
Philippe Mathieu-Daudé
From: Claudio Fontana <cfontana@suse.de>
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: make the field presence in cpu.h unconditional, removing the ifdefs]
Message-Id: <20210204163931.7358-12-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 13 +++++++------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/hppa/cpu.c | 4 +++-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 3 ++-
target/nios2/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/s390x/excp_helper.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
14 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 41ce1daefc..063814eaa4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -130,6 +130,12 @@ typedef struct TcgCpuOperations {
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+ /**
+ * @do_unaligned_access: Callback for unaligned access handling
+ */
+ void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
} TcgCpuOperations;
/**
@@ -139,8 +145,6 @@ typedef struct TcgCpuOperations {
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_unaligned_access: Callback for unaligned access handling, if
- * the target defines #TARGET_ALIGNED_ONLY.
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -206,9 +210,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -887,7 +888,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+ cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index a1696bebeb..0710298e5a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -226,7 +226,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
- cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index bd1882944c..aa264eec0a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2281,9 +2281,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
- cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 68233acf53..fd7f849a1c 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -71,6 +71,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
info->print_insn = print_insn_hppa;
}
+#ifndef CONFIG_USER_ONLY
static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -87,6 +88,7 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
cpu_loop_exit_restore(cs, retaddr);
}
+#endif /* CONFIG_USER_ONLY */
static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
{
@@ -150,9 +152,9 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
+ cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
dc->vmsd = &vmstate_hppa_cpu;
#endif
- cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->tcg_ops.initialize = hppa_translate_init;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index e405f6422d..6678310f51 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -365,7 +365,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
- cc->do_unaligned_access = mb_cpu_do_unaligned_access;
cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
@@ -375,6 +374,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = mb_cpu_do_unaligned_access;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ed2a7664e9..1e93e295cc 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -681,7 +681,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
#endif
@@ -694,6 +693,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
+
#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index b5fe779ceb..c43aa3d4c4 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -228,7 +228,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9a23af9a9d..5e85fd58b6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -610,7 +610,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
- cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index e6cf933594..a723ede8d1 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -510,7 +510,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
- cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 9cf66d3690..ce16af394b 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -634,4 +634,4 @@ void HELPER(monitor_call)(CPUS390XState *env, uint64_t monitor_code,
}
}
-#endif /* CONFIG_USER_ONLY */
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index f69360fc16..292152b562 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -228,7 +228,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = superh_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 8d6d7c1f83..1b785f60df 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -876,7 +876,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
- cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index fc52fde696..4b6381569f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -203,7 +203,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b16430a9d4..27ab243c6e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10850,7 +10850,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = ppc_cpu_set_pc;
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
- cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
@@ -10887,6 +10886,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+ cc->tcg_ops.do_unaligned_access = ppc_cpu_do_unaligned_access;
#endif /* !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 40/46] physmem: make watchpoint checking code TCG-only
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (38 preceding siblings ...)
2021-02-05 22:56 ` [PULL 39/46] cpu: move do_unaligned_access " Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 41/46] cpu: move adjust_watchpoint_address to tcg_ops Richard Henderson
` (7 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-13-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
softmmu/physmem.c | 141 +++++++++++++++++++++++-----------------------
1 file changed, 72 insertions(+), 69 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 60760a3bdc..51ed600bf9 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -840,6 +840,7 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
}
}
+#ifdef CONFIG_TCG
/* Return true if this watchpoint address matches the specified
* access (ie the address range covered by the watchpoint overlaps
* partially or completely with the address range covered by the
@@ -873,6 +874,77 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
return ret;
}
+/* Generate a debug exception if a watchpoint has been hit. */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ CPUWatchpoint *wp;
+
+ assert(tcg_enabled());
+ if (cpu->watchpoint_hit) {
+ /*
+ * We re-entered the check after replacing the TB.
+ * Now raise the debug interrupt so that it will
+ * trigger after the current instruction.
+ */
+ qemu_mutex_lock_iothread();
+ cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
+ qemu_mutex_unlock_iothread();
+ return;
+ }
+
+ addr = cc->adjust_watchpoint_address(cpu, addr, len);
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
+ if (watchpoint_address_matches(wp, addr, len)
+ && (wp->flags & flags)) {
+ if (replay_running_debug()) {
+ /*
+ * Don't process the watchpoints when we are
+ * in a reverse debugging operation.
+ */
+ replay_breakpoint();
+ return;
+ }
+ if (flags == BP_MEM_READ) {
+ wp->flags |= BP_WATCHPOINT_HIT_READ;
+ } else {
+ wp->flags |= BP_WATCHPOINT_HIT_WRITE;
+ }
+ wp->hitaddr = MAX(addr, wp->vaddr);
+ wp->hitattrs = attrs;
+ if (!cpu->watchpoint_hit) {
+ if (wp->flags & BP_CPU &&
+ !cc->debug_check_watchpoint(cpu, wp)) {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ continue;
+ }
+ cpu->watchpoint_hit = wp;
+
+ mmap_lock();
+ tb_check_watchpoint(cpu, ra);
+ if (wp->flags & BP_STOP_BEFORE_ACCESS) {
+ cpu->exception_index = EXCP_DEBUG;
+ mmap_unlock();
+ cpu_loop_exit_restore(cpu, ra);
+ } else {
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | curr_cflags();
+ mmap_unlock();
+ if (ra) {
+ cpu_restore_state(cpu, ra, true);
+ }
+ cpu_loop_exit_noexc(cpu);
+ }
+ }
+ } else {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ }
+ }
+}
+
+#endif /* CONFIG_TCG */
+
/* Called from RCU critical section */
static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
{
@@ -2359,75 +2431,6 @@ ram_addr_t qemu_ram_addr_from_host(void *ptr)
return block->offset + offset;
}
-/* Generate a debug exception if a watchpoint has been hit. */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUWatchpoint *wp;
-
- assert(tcg_enabled());
- if (cpu->watchpoint_hit) {
- /*
- * We re-entered the check after replacing the TB.
- * Now raise the debug interrupt so that it will
- * trigger after the current instruction.
- */
- qemu_mutex_lock_iothread();
- cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
- qemu_mutex_unlock_iothread();
- return;
- }
-
- addr = cc->adjust_watchpoint_address(cpu, addr, len);
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- if (watchpoint_address_matches(wp, addr, len)
- && (wp->flags & flags)) {
- if (replay_running_debug()) {
- /*
- * Don't process the watchpoints when we are
- * in a reverse debugging operation.
- */
- replay_breakpoint();
- return;
- }
- if (flags == BP_MEM_READ) {
- wp->flags |= BP_WATCHPOINT_HIT_READ;
- } else {
- wp->flags |= BP_WATCHPOINT_HIT_WRITE;
- }
- wp->hitaddr = MAX(addr, wp->vaddr);
- wp->hitattrs = attrs;
- if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU &&
- !cc->debug_check_watchpoint(cpu, wp)) {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- continue;
- }
- cpu->watchpoint_hit = wp;
-
- mmap_lock();
- tb_check_watchpoint(cpu, ra);
- if (wp->flags & BP_STOP_BEFORE_ACCESS) {
- cpu->exception_index = EXCP_DEBUG;
- mmap_unlock();
- cpu_loop_exit_restore(cpu, ra);
- } else {
- /* Force execution of one insn next time. */
- cpu->cflags_next_tb = 1 | curr_cflags();
- mmap_unlock();
- if (ra) {
- cpu_restore_state(cpu, ra, true);
- }
- cpu_loop_exit_noexc(cpu);
- }
- }
- } else {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- }
- }
-}
-
static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
MemTxAttrs attrs, void *buf, hwaddr len);
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 41/46] cpu: move adjust_watchpoint_address to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (39 preceding siblings ...)
2021-02-05 22:56 ` [PULL 40/46] physmem: make watchpoint checking code TCG-only Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 42/46] cpu: move debug_check_watchpoint " Richard Henderson
` (6 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-14-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 6 +++++-
hw/core/cpu.c | 6 ------
softmmu/physmem.c | 5 ++++-
target/arm/cpu.c | 2 +-
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 063814eaa4..832dd26e92 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -136,6 +136,11 @@ typedef struct TcgCpuOperations {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
+ /**
+ * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+ */
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+
} TcgCpuOperations;
/**
@@ -244,7 +249,6 @@ struct CPUClass {
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
- vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 57542b6906..3d5bf9fe02 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -383,11 +383,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
-static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
-{
- return addr;
-}
-
static Property cpu_common_props[] = {
#ifndef CONFIG_USER_ONLY
/* Create a memory property for softmmu CPU object,
@@ -421,7 +416,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
- k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 51ed600bf9..3d9a9c39bd 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -894,7 +894,10 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
return;
}
- addr = cc->adjust_watchpoint_address(cpu, addr, len);
+ if (cc->tcg_ops.adjust_watchpoint_address) {
+ /* this is currently used only by ARM BE32 */
+ addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
+ }
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)
&& (wp->flags & flags)) {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index aa264eec0a..2a14431065 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2284,7 +2284,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
- cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+ cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 42/46] cpu: move debug_check_watchpoint to tcg_ops
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (40 preceding siblings ...)
2021-02-05 22:56 ` [PULL 41/46] cpu: move adjust_watchpoint_address to tcg_ops Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Richard Henderson
` (5 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-15-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 9 ++++++---
accel/tcg/user-exec.c | 3 ++-
hw/core/cpu.c | 9 ---------
softmmu/physmem.c | 4 ++--
target/arm/cpu.c | 4 ++--
5 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 832dd26e92..e76a49754d 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -141,6 +141,12 @@ typedef struct TcgCpuOperations {
*/
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+ /**
+ * @debug_check_watchpoint: return true if the architectural
+ * watchpoint whose address has matched should really fire, used by ARM
+ */
+ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
+
} TcgCpuOperations;
/**
@@ -177,8 +183,6 @@ typedef struct TcgCpuOperations {
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @debug_check_watchpoint: Callback: return true if the architectural
- * watchpoint whose address has matched should really fire.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -232,7 +236,6 @@ struct CPUClass {
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5509dd53e9..9e6e188d19 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -187,7 +187,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
+ cc->tcg_ops.tlb_fill(cpu, address, 0, access_type,
+ MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 3d5bf9fe02..00330ba07d 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -186,14 +186,6 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
-{
- /* If no extra check is required, QEMU watchpoint match can be considered
- * as an architectural match.
- */
- return true;
-}
-
static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
{
return target_words_bigendian();
@@ -415,7 +407,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
- k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 3d9a9c39bd..9e64cf7adf 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -917,8 +917,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU &&
- !cc->debug_check_watchpoint(cpu, wp)) {
+ if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoint &&
+ !cc->tcg_ops.debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2a14431065..c9a66d3103 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2280,12 +2280,12 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
- cc->debug_check_watchpoint = arm_debug_check_watchpoint;
#if !defined(CONFIG_USER_ONLY)
+ cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
- cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
+ cc->tcg_ops.debug_check_watchpoint = arm_debug_check_watchpoint;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (41 preceding siblings ...)
2021-02-05 22:56 ` [PULL 42/46] cpu: move debug_check_watchpoint " Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 44/46] accel: extend AccelState and AccelClass to user-mode Richard Henderson
` (4 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 103 ++------------------------------
include/hw/core/tcg-cpu-ops.h | 97 ++++++++++++++++++++++++++++++
target/arm/internals.h | 6 ++
accel/tcg/cpu-exec.c | 27 +++++----
accel/tcg/cputlb.c | 35 +++++++++--
accel/tcg/user-exec.c | 9 +--
hw/mips/jazz.c | 7 ++-
softmmu/physmem.c | 13 ++--
target/alpha/cpu.c | 21 +++++--
target/arm/cpu.c | 41 ++++++++-----
target/arm/cpu64.c | 7 +--
target/arm/cpu_tcg.c | 28 +++++++--
target/avr/cpu.c | 19 ++++--
target/avr/helper.c | 5 +-
target/cris/cpu.c | 43 ++++++++-----
target/cris/helper.c | 5 +-
target/hppa/cpu.c | 22 ++++---
target/i386/tcg/tcg-cpu.c | 26 ++++----
target/lm32/cpu.c | 19 ++++--
target/m68k/cpu.c | 19 ++++--
target/microblaze/cpu.c | 25 +++++---
target/mips/cpu.c | 36 +++++++----
target/moxie/cpu.c | 15 ++++-
target/nios2/cpu.c | 18 ++++--
target/openrisc/cpu.c | 17 ++++--
target/riscv/cpu.c | 23 ++++---
target/rx/cpu.c | 20 +++++--
target/s390x/cpu.c | 33 ++++++----
target/sh4/cpu.c | 21 +++++--
target/sparc/cpu.c | 25 +++++---
target/tilegx/cpu.c | 17 ++++--
target/tricore/cpu.c | 12 +++-
target/unicore32/cpu.c | 17 ++++--
target/xtensa/cpu.c | 23 ++++---
target/ppc/translate_init.c.inc | 33 ++++++----
MAINTAINERS | 1 +
36 files changed, 582 insertions(+), 306 deletions(-)
create mode 100644 include/hw/core/tcg-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e76a49754d..4f6c6b18c9 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,78 +76,8 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
-/**
- * struct TcgCpuOperations: TCG operations specific to a CPU class
- */
-typedef struct TcgCpuOperations {
- /**
- * @initialize: Initalize TCG state
- *
- * Called when the first CPU is realized.
- */
- void (*initialize)(void);
- /**
- * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
- *
- * This is called when we abandon execution of a TB before starting it,
- * and must set all parts of the CPU state which the previous TB in the
- * chain may not have updated.
- * By default, when this is NULL, a call is made to @set_pc(tb->pc).
- *
- * If more state needs to be restored, the target must implement a
- * function to restore all the state, and register it here.
- */
- void (*synchronize_from_tb)(CPUState *cpu,
- const struct TranslationBlock *tb);
- /** @cpu_exec_enter: Callback for cpu_exec preparation */
- void (*cpu_exec_enter)(CPUState *cpu);
- /** @cpu_exec_exit: Callback for cpu_exec cleanup */
- void (*cpu_exec_exit)(CPUState *cpu);
- /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
- bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
- /** @do_interrupt: Callback for interrupt handling. */
- void (*do_interrupt)(CPUState *cpu);
- /**
- * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
- *
- * For system mode, if the access is valid, call tlb_set_page
- * and return true; if the access is invalid, and probe is
- * true, return false; otherwise raise an exception and do
- * not return. For user-only mode, always raise an exception
- * and do not return.
- */
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
- /** @debug_excp_handler: Callback for handling debug exceptions */
- void (*debug_excp_handler)(CPUState *cpu);
-
- /**
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
- */
- void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
- /**
- * @do_unaligned_access: Callback for unaligned access handling
- */
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
- /**
- * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
- */
- vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
-
- /**
- * @debug_check_watchpoint: return true if the architectural
- * watchpoint whose address has matched should really fire, used by ARM
- */
- bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
-
-} TcgCpuOperations;
+/* see tcg-cpu-ops.h */
+struct TCGCPUOps;
/**
* CPUClass:
@@ -258,7 +188,8 @@ struct CPUClass {
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
- TcgCpuOperations tcg_ops;
+ /* when TCG is not available, this pointer is NULL */
+ struct TCGCPUOps *tcg_ops;
};
/*
@@ -889,32 +820,6 @@ CPUState *cpu_by_arch_id(int64_t id);
void cpu_interrupt(CPUState *cpu, int mask);
-static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
-}
-
-static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cpu->ignore_memory_transaction_failures &&
- cc->tcg_ops.do_transaction_failed) {
- cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
- access_type, mmu_idx, attrs,
- response, retaddr);
- }
-}
-
/**
* cpu_set_pc:
* @cpu: The CPU to set the program counter for.
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
new file mode 100644
index 0000000000..ccc97d1894
--- /dev/null
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -0,0 +1,97 @@
+/*
+ * TCG CPU-specific operations
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPU_OPS_H
+#define TCG_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+struct TCGCPUOps {
+ /**
+ * @initialize: Initalize TCG state
+ *
+ * Called when the first CPU is realized.
+ */
+ void (*initialize)(void);
+ /**
+ * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
+ *
+ * This is called when we abandon execution of a TB before starting it,
+ * and must set all parts of the CPU state which the previous TB in the
+ * chain may not have updated.
+ * By default, when this is NULL, a call is made to @set_pc(tb->pc).
+ *
+ * If more state needs to be restored, the target must implement a
+ * function to restore all the state, and register it here.
+ */
+ void (*synchronize_from_tb)(CPUState *cpu,
+ const struct TranslationBlock *tb);
+ /** @cpu_exec_enter: Callback for cpu_exec preparation */
+ void (*cpu_exec_enter)(CPUState *cpu);
+ /** @cpu_exec_exit: Callback for cpu_exec cleanup */
+ void (*cpu_exec_exit)(CPUState *cpu);
+ /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @do_interrupt: Callback for interrupt handling.
+ *
+ * note that this is in general SOFTMMU only, but it actually isn't
+ * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it
+ * in the SOFTMMU section in general.
+ */
+ void (*do_interrupt)(CPUState *cpu);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
+ *
+ * For system mode, if the access is valid, call tlb_set_page
+ * and return true; if the access is invalid, and probe is
+ * true, return false; otherwise raise an exception and do
+ * not return. For user-only mode, always raise an exception
+ * and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+ /** @debug_excp_handler: Callback for handling debug exceptions */
+ void (*debug_excp_handler)(CPUState *cpu);
+
+#ifdef NEED_CPU_H
+#ifdef CONFIG_SOFTMMU
+ /**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+ /**
+ * @do_unaligned_access: Callback for unaligned access handling
+ */
+ void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
+
+ /**
+ * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
+ */
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
+
+ /**
+ * @debug_check_watchpoint: return true if the architectural
+ * watchpoint whose address has matched should really fire, used by ARM
+ */
+ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
+
+#endif /* CONFIG_SOFTMMU */
+#endif /* NEED_CPU_H */
+
+};
+
+#endif /* TCG_CPU_OPS_H */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 853fa88fd6..448982dd2f 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -171,6 +171,12 @@ static inline int r14_bank_number(int mode)
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
+#ifdef CONFIG_TCG
+void arm_cpu_synchronize_from_tb(CPUState *cs,
+ const struct TranslationBlock *tb);
+#endif /* CONFIG_TCG */
+
+
enum arm_fprounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 633ee3ef9e..d9ef69121c 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -21,6 +21,7 @@
#include "qemu-common.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "trace.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
@@ -213,8 +214,8 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
TARGET_FMT_lx "] %s\n",
last_tb->tc.ptr, last_tb->pc,
lookup_symbol(last_tb->pc));
- if (cc->tcg_ops.synchronize_from_tb) {
- cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
+ if (cc->tcg_ops->synchronize_from_tb) {
+ cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
} else {
assert(cc->set_pc);
cc->set_pc(cpu, last_tb->pc);
@@ -262,8 +263,8 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->tcg_ops.cpu_exec_enter) {
- cc->tcg_ops.cpu_exec_enter(cpu);
+ if (cc->tcg_ops->cpu_exec_enter) {
+ cc->tcg_ops->cpu_exec_enter(cpu);
}
}
@@ -271,8 +272,8 @@ static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->tcg_ops.cpu_exec_exit) {
- cc->tcg_ops.cpu_exec_exit(cpu);
+ if (cc->tcg_ops->cpu_exec_exit) {
+ cc->tcg_ops->cpu_exec_exit(cpu);
}
}
@@ -512,8 +513,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- if (cc->tcg_ops.debug_excp_handler) {
- cc->tcg_ops.debug_excp_handler(cpu);
+ if (cc->tcg_ops->debug_excp_handler) {
+ cc->tcg_ops->debug_excp_handler(cpu);
}
}
@@ -547,7 +548,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.do_interrupt(cpu);
+ cc->tcg_ops->do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;
@@ -556,7 +557,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (replay_exception()) {
CPUClass *cc = CPU_GET_CLASS(cpu);
qemu_mutex_lock_iothread();
- cc->tcg_ops.do_interrupt(cpu);
+ cc->tcg_ops->do_interrupt(cpu);
qemu_mutex_unlock_iothread();
cpu->exception_index = -1;
@@ -655,8 +656,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- if (cc->tcg_ops.cpu_exec_interrupt &&
- cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (cc->tcg_ops->cpu_exec_interrupt &&
+ cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
@@ -834,7 +835,7 @@ void tcg_exec_realizefn(CPUState *cpu, Error **errp)
CPUClass *cc = CPU_GET_CLASS(cpu);
if (!tcg_target_initialized) {
- cc->tcg_ops.initialize();
+ cc->tcg_ops->initialize();
tcg_target_initialized = true;
}
tlb_init(cpu);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b7717803b8..8a7b779270 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
@@ -1305,11 +1306,37 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
- ok = cc->tcg_ops.tlb_fill(cpu, addr, size,
- access_type, mmu_idx, false, retaddr);
+ ok = cc->tcg_ops->tlb_fill(cpu, addr, size,
+ access_type, mmu_idx, false, retaddr);
assert(ok);
}
+static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+}
+
+static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response,
+ uintptr_t retaddr)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!cpu->ignore_memory_transaction_failures &&
+ cc->tcg_ops->do_transaction_failed) {
+ cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx, attrs,
+ response, retaddr);
+ }
+}
+
static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
int mmu_idx, target_ulong addr, uintptr_t retaddr,
MMUAccessType access_type, MemOp op)
@@ -1577,8 +1604,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
CPUState *cs = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cs);
- if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
- mmu_idx, nonfault, retaddr)) {
+ if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
*phost = NULL;
return TLB_INVALID_MASK;
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 9e6e188d19..0b6f56ca40 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
@@ -187,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.tlb_fill(cpu, address, 0, access_type,
- MMU_USER_IDX, false, pc);
+ cc->tcg_ops->tlb_fill(cpu, address, 0, access_type,
+ MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
@@ -218,8 +219,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
} else {
CPUState *cpu = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
- MMU_USER_IDX, false, ra);
+ cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type,
+ MMU_USER_IDX, false, ra);
g_assert_not_reached();
}
}
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 46c71a0ac8..83c8086062 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -53,6 +53,9 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/help_option.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
enum jazz_model_e {
JAZZ_MAGNUM,
@@ -209,8 +212,8 @@ static void mips_jazz_init(MachineState *machine,
*/
cc = CPU_GET_CLASS(cpu);
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
- cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
+ real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
+ cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index 9e64cf7adf..243c3097d3 100644
--- a/softmmu/physmem.c
+++ b/softmmu/physmem.c
@@ -24,6 +24,11 @@
#include "qemu/cutils.h"
#include "qemu/cacheflush.h"
#include "cpu.h"
+
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
+
#include "exec/exec-all.h"
#include "exec/target_page.h"
#include "hw/qdev-core.h"
@@ -894,9 +899,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
return;
}
- if (cc->tcg_ops.adjust_watchpoint_address) {
+ if (cc->tcg_ops->adjust_watchpoint_address) {
/* this is currently used only by ARM BE32 */
- addr = cc->tcg_ops.adjust_watchpoint_address(cpu, addr, len);
+ addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
}
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)
@@ -917,8 +922,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
- if (wp->flags & BP_CPU && cc->tcg_ops.debug_check_watchpoint &&
- !cc->tcg_ops.debug_check_watchpoint(cpu, wp)) {
+ if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint &&
+ !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 0710298e5a..27192b62e2 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,20 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps alpha_tcg_ops = {
+ .initialize = alpha_translate_init,
+ .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
+ .tlb_fill = alpha_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = alpha_cpu_do_interrupt,
+ .do_transaction_failed = alpha_cpu_do_transaction_failed,
+ .do_unaligned_access = alpha_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void alpha_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -217,22 +231,17 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
- cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
- cc->tcg_ops.initialize = alpha_translate_init;
+ cc->tcg_ops = &alpha_tcg_ops;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c9a66d3103..8ddb2556f8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -26,6 +26,9 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "cpu.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
#include "internals.h"
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
@@ -55,8 +58,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
#ifdef CONFIG_TCG
-static void arm_cpu_synchronize_from_tb(CPUState *cs,
- const TranslationBlock *tb)
+void arm_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -590,7 +593,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
return true;
}
@@ -2242,6 +2245,24 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifdef CONFIG_TCG
+static struct TCGCPUOps arm_tcg_ops = {
+ .initialize = arm_translate_init,
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = arm_cpu_exec_interrupt,
+ .tlb_fill = arm_cpu_tlb_fill,
+ .debug_excp_handler = arm_debug_excp_handler,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = arm_cpu_do_interrupt,
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -2274,19 +2295,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
+
#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = arm_translate_init;
- cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
- cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
- cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
- cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
-#if !defined(CONFIG_USER_ONLY)
- cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
- cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
- cc->tcg_ops.adjust_watchpoint_address = arm_adjust_watchpoint_address;
- cc->tcg_ops.debug_check_watchpoint = arm_debug_check_watchpoint;
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+ cc->tcg_ops = &arm_tcg_ops;
#endif /* CONFIG_TCG */
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a9a1cdb871..10c5118176 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -21,6 +21,9 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
#include "qemu/module.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
@@ -805,10 +808,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
-#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
-#endif /* CONFIG_TCG */
-
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index d9c160f1ac..c29b434c60 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -10,6 +10,9 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
#include "internals.h"
/* CPU models. These are not needed for the AArch64 linux-user build. */
@@ -34,7 +37,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
ret = true;
}
return ret;
@@ -660,6 +663,24 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
+#ifdef CONFIG_TCG
+static struct TCGCPUOps arm_v7m_tcg_ops = {
+ .initialize = arm_translate_init,
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
+ .tlb_fill = arm_cpu_tlb_fill,
+ .debug_excp_handler = arm_debug_excp_handler,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
@@ -667,10 +688,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
acc->info = data;
#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_interrupt = arm_v7m_cpu_do_interrupt;
-#endif
+ cc->tcg_ops = &arm_v7m_tcg_ops;
#endif /* CONFIG_TCG */
cc->gdb_core_xml_file = "arm-m-profile.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 476e645b37..fa0f8e0e80 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,19 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps avr_tcg_ops = {
+ .initialize = avr_cpu_tcg_init,
+ .synchronize_from_tb = avr_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = avr_cpu_exec_interrupt,
+ .tlb_fill = avr_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = avr_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void avr_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -198,21 +211,17 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
- cc->tcg_ops.do_interrupt = avr_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->tcg_ops.tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
- cc->tcg_ops.initialize = avr_cpu_tcg_init;
- cc->tcg_ops.synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "avr-cpu.xml";
+ cc->tcg_ops = &avr_tcg_ops;
}
/*
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 69d3b6181f..65880b9928 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/address-spaces.h"
#include "exec/helper-proto.h"
@@ -34,7 +35,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
@@ -45,7 +46,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
int index = ctz32(env->intsrc);
cs->exception_index = EXCP_INT(index);
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index b65743e8ca..ed983380fc 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,15 +193,36 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps crisv10_tcg_ops = {
+ .initialize = cris_initialize_crisv10_tcg,
+ .cpu_exec_interrupt = cris_cpu_exec_interrupt,
+ .tlb_fill = cris_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = crisv10_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static struct TCGCPUOps crisv32_tcg_ops = {
+ .initialize = cris_initialize_tcg,
+ .cpu_exec_interrupt = cris_cpu_exec_interrupt,
+ .tlb_fill = cris_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = cris_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -210,9 +231,8 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -221,9 +241,8 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -232,9 +251,8 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
@@ -243,16 +261,17 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
- cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops = &crisv10_tcg_ops;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 32;
+ cc->tcg_ops = &crisv32_tcg_ops;
}
static void cris_cpu_class_init(ObjectClass *oc, void *data)
@@ -268,13 +287,10 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
- cc->tcg_ops.do_interrupt = cris_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
@@ -284,7 +300,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
- cc->tcg_ops.initialize = cris_initialize_tcg;
}
#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 1f4d6f7d45..7e3bb58fe1 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
#include "mmu.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
@@ -299,7 +300,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
cs->exception_index = EXCP_IRQ;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
ret = true;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
@@ -311,7 +312,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
cs->exception_index = EXCP_NMI;
- cc->tcg_ops.do_interrupt(cs);
+ cc->tcg_ops->do_interrupt(cs);
ret = true;
}
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index fd7f849a1c..d8fad52d1f 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,20 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps hppa_tcg_ops = {
+ .initialize = hppa_translate_init,
+ .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
+ .tlb_fill = hppa_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = hppa_cpu_do_interrupt,
+ .do_unaligned_access = hppa_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void hppa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -142,23 +156,17 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
- cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
dc->vmsd = &vmstate_hppa_cpu;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
- cc->tcg_ops.initialize = hppa_translate_init;
-
cc->gdb_num_core_regs = 128;
+ cc->tcg_ops = &hppa_tcg_ops;
}
static const TypeInfo hppa_cpu_type_info = {
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 4a53cd89e2..1e125d2175 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -57,16 +57,22 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.eip = tb->pc - tb->cs_base;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps x86_tcg_ops = {
+ .initialize = tcg_x86_init,
+ .synchronize_from_tb = x86_cpu_synchronize_from_tb,
+ .cpu_exec_enter = x86_cpu_exec_enter,
+ .cpu_exec_exit = x86_cpu_exec_exit,
+ .cpu_exec_interrupt = x86_cpu_exec_interrupt,
+ .do_interrupt = x86_cpu_do_interrupt,
+ .tlb_fill = x86_cpu_tlb_fill,
+#ifndef CONFIG_USER_ONLY
+ .debug_excp_handler = breakpoint_handler,
+#endif /* !CONFIG_USER_ONLY */
+};
+
void tcg_cpu_common_class_init(CPUClass *cc)
{
- cc->tcg_ops.do_interrupt = x86_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
- cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
- cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
- cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
- cc->tcg_ops.initialize = tcg_x86_init;
- cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.debug_excp_handler = breakpoint_handler;
-#endif
+ cc->tcg_ops = &x86_tcg_ops;
}
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index fb3761b749..c23d72874c 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,19 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps lm32_tcg_ops = {
+ .initialize = lm32_translate_init,
+ .cpu_exec_interrupt = lm32_cpu_exec_interrupt,
+ .tlb_fill = lm32_cpu_tlb_fill,
+ .debug_excp_handler = lm32_debug_excp_handler,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = lm32_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void lm32_cpu_class_init(ObjectClass *oc, void *data)
{
LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
@@ -222,22 +235,18 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
- cc->tcg_ops.do_interrupt = lm32_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = lm32_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
- cc->tcg_ops.debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
- cc->tcg_ops.initialize = lm32_translate_init;
+ cc->tcg_ops = &lm32_tcg_ops;
}
#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index e68b933c84..c6fde8132b 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -453,6 +453,19 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps m68k_tcg_ops = {
+ .initialize = m68k_tcg_init,
+ .cpu_exec_interrupt = m68k_cpu_exec_interrupt,
+ .tlb_fill = m68k_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = m68k_cpu_do_interrupt,
+ .do_transaction_failed = m68k_cpu_transaction_failed,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void m68k_cpu_class_init(ObjectClass *c, void *data)
{
M68kCPUClass *mcc = M68K_CPU_CLASS(c);
@@ -465,22 +478,18 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
- cc->tcg_ops.do_interrupt = m68k_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
- cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
- cc->tcg_ops.initialize = m68k_tcg_init;
cc->gdb_num_core_regs = 18;
+ cc->tcg_ops = &m68k_tcg_ops;
}
static void m68k_cpu_class_init_cf_core(ObjectClass *c, void *data)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6678310f51..433ba20203 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,21 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps mb_tcg_ops = {
+ .initialize = mb_tcg_init,
+ .synchronize_from_tb = mb_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = mb_cpu_exec_interrupt,
+ .tlb_fill = mb_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = mb_cpu_do_interrupt,
+ .do_transaction_failed = mb_cpu_transaction_failed,
+ .do_unaligned_access = mb_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -364,17 +379,13 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
- cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
+
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
+
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
- cc->tcg_ops.do_unaligned_access = mb_cpu_do_unaligned_access;
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
@@ -382,7 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 32 + 27;
cc->disas_set_info = mb_disas_set_info;
- cc->tcg_ops.initialize = mb_tcg_init;
+ cc->tcg_ops = &mb_tcg_ops;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1e93e295cc..ad163ead62 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -663,6 +663,26 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+/*
+ * NB: cannot be const, as some elements are changed for specific
+ * mips hardware (see hw/mips/jazz.c).
+ */
+static struct TCGCPUOps mips_tcg_ops = {
+ .initialize = mips_tcg_init,
+ .synchronize_from_tb = mips_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = mips_cpu_exec_interrupt,
+ .tlb_fill = mips_cpu_tlb_fill,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = mips_cpu_do_interrupt,
+ .do_transaction_failed = mips_cpu_do_transaction_failed,
+ .do_unaligned_access = mips_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void mips_cpu_class_init(ObjectClass *c, void *data)
{
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
@@ -685,21 +705,11 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->vmsd = &vmstate_mips_cpu;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
-#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = mips_tcg_init;
- cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
- cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
- cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
-
-#endif /* CONFIG_USER_ONLY */
-#endif /* CONFIG_TCG */
-
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &mips_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo mips_cpu_type_info = {
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 36bef4d357..83bec34d36 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,17 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps moxie_tcg_ops = {
+ .initialize = moxie_translate_init,
+ .tlb_fill = moxie_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = moxie_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void moxie_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -107,16 +118,14 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = moxie_cpu_class_by_name;
cc->has_work = moxie_cpu_has_work;
- cc->tcg_ops.do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
- cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
- cc->tcg_ops.initialize = moxie_translate_init;
+ cc->tcg_ops = &moxie_tcg_ops;
}
static void moxielite_initfn(Object *obj)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index c43aa3d4c4..e9c9fc3a38 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,18 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps nios2_tcg_ops = {
+ .initialize = nios2_tcg_init,
+ .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
+ .tlb_fill = nios2_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = nios2_cpu_do_interrupt,
+ .do_unaligned_access = nios2_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
static void nios2_cpu_class_init(ObjectClass *oc, void *data)
{
@@ -221,20 +233,16 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
- cc->tcg_ops.do_interrupt = nios2_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
- cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
cc->gdb_num_core_regs = 49;
- cc->tcg_ops.initialize = nios2_tcg_init;
+ cc->tcg_ops = &nios2_tcg_ops;
}
static const TypeInfo nios2_cpu_type_info = {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 1a31f7564f..2c64842f46 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,18 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps openrisc_tcg_ops = {
+ .initialize = openrisc_translate_init,
+ .cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
+ .tlb_fill = openrisc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = openrisc_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
{
OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
@@ -186,20 +198,17 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
- cc->tcg_ops.do_interrupt = openrisc_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
- cc->tcg_ops.initialize = openrisc_translate_init;
cc->disas_set_info = openrisc_disas_set_info;
+ cc->tcg_ops = &openrisc_tcg_ops;
}
/* Sort alphabetically by type name, except for "any". */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5e85fd58b6..16f1a34238 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,6 +580,21 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps riscv_tcg_ops = {
+ .initialize = riscv_translate_init,
+ .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+ .tlb_fill = riscv_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = riscv_cpu_do_interrupt,
+ .do_transaction_failed = riscv_cpu_do_transaction_failed,
+ .do_unaligned_access = riscv_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -593,11 +608,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
- cc->tcg_ops.do_interrupt = riscv_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
@@ -609,16 +621,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
- cc->tcg_ops.initialize = riscv_translate_init;
- cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill;
+ cc->tcg_ops = &riscv_tcg_ops;
device_class_set_props(dc, riscv_cpu_properties);
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index e79f009cbd..7ac6618b26 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,19 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps rx_tcg_ops = {
+ .initialize = rx_translate_init,
+ .synchronize_from_tb = rx_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = rx_cpu_exec_interrupt,
+ .tlb_fill = rx_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = rx_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void rx_cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -186,20 +199,17 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
- cc->tcg_ops.do_interrupt = rx_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
+
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
- cc->tcg_ops.initialize = rx_translate_init;
- cc->tcg_ops.tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "rx-core.xml";
+ cc->tcg_ops = &rx_tcg_ops;
}
static const TypeInfo rx_cpu_info = {
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index a723ede8d1..d35eb39a1b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,22 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps s390_tcg_ops = {
+ .initialize = s390x_translate_init,
+ .tlb_fill = s390_cpu_tlb_fill,
+
+#if !defined(CONFIG_USER_ONLY)
+ .cpu_exec_interrupt = s390_cpu_exec_interrupt,
+ .do_interrupt = s390_cpu_do_interrupt,
+ .debug_excp_handler = s390x_cpu_debug_excp_handler,
+ .do_unaligned_access = s390x_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void s390_cpu_class_init(ObjectClass *oc, void *data)
{
S390CPUClass *scc = S390_CPU_CLASS(oc);
@@ -495,9 +511,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
scc->reset = s390_cpu_reset;
cc->class_by_name = s390_cpu_class_by_name,
cc->has_work = s390_cpu_has_work;
-#ifdef CONFIG_TCG
- cc->tcg_ops.do_interrupt = s390_cpu_do_interrupt;
-#endif
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
cc->gdb_read_register = s390_cpu_gdb_read_register;
@@ -507,23 +520,17 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
-#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
- cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
- cc->tcg_ops.do_unaligned_access = s390x_cpu_do_unaligned_access;
-#endif
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
-#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = s390x_translate_init;
- cc->tcg_ops.tlb_fill = s390_cpu_tlb_fill;
-#endif
-
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
cc->gdb_core_xml_file = "s390x-core64.xml";
cc->gdb_arch_name = s390_gdb_arch_name;
s390_cpu_model_class_register_props(oc);
+
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &s390_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo s390_cpu_type_info = {
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 292152b562..a78d283bc8 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -206,6 +206,20 @@ static const VMStateDescription vmstate_sh_cpu = {
.unmigratable = 1,
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps superh_tcg_ops = {
+ .initialize = sh4_translate_init,
+ .synchronize_from_tb = superh_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = superh_cpu_exec_interrupt,
+ .tlb_fill = superh_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = superh_cpu_do_interrupt,
+ .do_unaligned_access = superh_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void superh_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -219,24 +233,19 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
- cc->tcg_ops.do_interrupt = superh_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
- cc->tcg_ops.initialize = sh4_translate_init;
cc->gdb_num_core_regs = 59;
dc->vmsd = &vmstate_sh_cpu;
+ cc->tcg_ops = &superh_tcg_ops;
}
#define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 1b785f60df..aece2c7dc8 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,23 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps sparc_tcg_ops = {
+ .initialize = sparc_tcg_init,
+ .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
+ .tlb_fill = sparc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = sparc_cpu_do_interrupt,
+ .do_transaction_failed = sparc_cpu_do_transaction_failed,
+ .do_unaligned_access = sparc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
{
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
@@ -863,31 +880,25 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
- cc->tcg_ops.do_interrupt = sparc_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
#endif
cc->set_pc = sparc_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
- cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
- cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
- cc->tcg_ops.initialize = sparc_tcg_init;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;
#else
cc->gdb_num_core_regs = 72;
#endif
+ cc->tcg_ops = &sparc_tcg_ops;
}
static const TypeInfo sparc_cpu_type_info = {
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 7d4ead4ef1..d969c2f133 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -134,6 +134,18 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps tilegx_tcg_ops = {
+ .initialize = tilegx_tcg_init,
+ .cpu_exec_interrupt = tilegx_cpu_exec_interrupt,
+ .tlb_fill = tilegx_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = tilegx_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -147,13 +159,10 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
- cc->tcg_ops.do_interrupt = tilegx_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
- cc->tcg_ops.tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
- cc->tcg_ops.initialize = tilegx_tcg_init;
+ cc->tcg_ops = &tilegx_tcg_ops;
}
static const TypeInfo tilegx_cpu_type_info = {
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 9b21b640e2..0b1e139bcb 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,14 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps tricore_tcg_ops = {
+ .initialize = tricore_tcg_init,
+ .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
+ .tlb_fill = tricore_cpu_tlb_fill,
+};
+
static void tricore_cpu_class_init(ObjectClass *c, void *data)
{
TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
@@ -162,10 +170,8 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
- cc->tcg_ops.initialize = tricore_tcg_init;
- cc->tcg_ops.tlb_fill = tricore_cpu_tlb_fill;
+ cc->tcg_ops = &tricore_tcg_ops;
}
#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index e27ffc571a..0258884f84 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,18 @@ static const VMStateDescription vmstate_uc32_cpu = {
.unmigratable = 1,
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps uc32_tcg_ops = {
+ .initialize = uc32_translate_init,
+ .cpu_exec_interrupt = uc32_cpu_exec_interrupt,
+ .tlb_fill = uc32_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = uc32_cpu_do_interrupt,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void uc32_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -131,14 +143,11 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
- cc->tcg_ops.do_interrupt = uc32_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->tcg_ops.tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
+ cc->tcg_ops = &uc32_tcg_ops;
}
#define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 4b6381569f..e2b2c7a71c 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,21 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.unmigratable = 1,
};
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps xtensa_tcg_ops = {
+ .initialize = xtensa_translate_init,
+ .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
+ .tlb_fill = xtensa_cpu_tlb_fill,
+ .debug_excp_handler = xtensa_breakpoint_handler,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = xtensa_cpu_do_interrupt,
+ .do_transaction_failed = xtensa_cpu_do_transaction_failed,
+ .do_unaligned_access = xtensa_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -194,23 +209,17 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
- cc->tcg_ops.do_interrupt = xtensa_cpu_do_interrupt;
- cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
- cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
- cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
+ cc->tcg_ops = &xtensa_tcg_ops;
}
static const TypeInfo xtensa_cpu_type_info = {
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 27ab243c6e..9867d0a6e4 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10827,6 +10827,23 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifdef CONFIG_TCG
+#include "hw/core/tcg-cpu-ops.h"
+
+static struct TCGCPUOps ppc_tcg_ops = {
+ .initialize = ppc_translate_init,
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+ .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = ppc_cpu_do_interrupt,
+ .cpu_exec_enter = ppc_cpu_exec_enter,
+ .cpu_exec_exit = ppc_cpu_exec_exit,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+#endif /* CONFIG_TCG */
+
static void ppc_cpu_class_init(ObjectClass *oc, void *data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
@@ -10878,21 +10895,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
-#ifdef CONFIG_TCG
- cc->tcg_ops.initialize = ppc_translate_init;
- cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
- cc->tcg_ops.do_interrupt = ppc_cpu_do_interrupt;
- cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
-#ifndef CONFIG_USER_ONLY
- cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
- cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
- cc->tcg_ops.do_unaligned_access = ppc_cpu_do_unaligned_access;
-#endif /* !CONFIG_USER_ONLY */
-#endif /* CONFIG_TCG */
-
cc->disas_set_info = ppc_disas_set_info;
dc->fw_name = "PowerPC,UNKNOWN";
+
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &ppc_tcg_ops;
+#endif /* CONFIG_TCG */
}
static const TypeInfo ppc_cpu_type_info = {
diff --git a/MAINTAINERS b/MAINTAINERS
index 00626941f1..c8559b34d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -129,6 +129,7 @@ F: include/exec/helper*.h
F: include/exec/tb-hash.h
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
+F: include/hw/core/tcg-cpu-ops.h
FPU emulation
M: Aurelien Jarno <aurelien@aurel32.net>
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 44/46] accel: extend AccelState and AccelClass to user-mode
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (42 preceding siblings ...)
2021-02-05 22:56 ` [PULL 43/46] cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass Richard Henderson
` (3 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-17-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/boards.h | 2 +-
include/{sysemu => qemu}/accel.h | 14 +++++----
include/sysemu/hvf.h | 2 +-
include/sysemu/kvm.h | 2 +-
include/sysemu/kvm_int.h | 2 +-
target/i386/hvf/hvf-i386.h | 2 +-
accel/accel-common.c | 50 ++++++++++++++++++++++++++++++
accel/{accel.c => accel-softmmu.c} | 27 ++--------------
accel/accel-user.c | 24 ++++++++++++++
accel/qtest/qtest.c | 2 +-
accel/tcg/tcg-all.c | 15 +++++++--
accel/xen/xen-all.c | 2 +-
bsd-user/main.c | 6 +++-
linux-user/main.c | 6 +++-
softmmu/memory.c | 2 +-
softmmu/qtest.c | 2 +-
softmmu/vl.c | 2 +-
target/i386/hax/hax-all.c | 2 +-
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86_task.c | 2 +-
target/i386/whpx/whpx-all.c | 2 +-
MAINTAINERS | 2 +-
accel/meson.build | 4 ++-
accel/tcg/meson.build | 2 +-
24 files changed, 125 insertions(+), 53 deletions(-)
rename include/{sysemu => qemu}/accel.h (95%)
create mode 100644 accel/accel-common.c
rename accel/{accel.c => accel-softmmu.c} (75%)
create mode 100644 accel/accel-user.c
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 17b1f3f0b9..85af4faf76 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -6,7 +6,7 @@
#include "exec/memory.h"
#include "sysemu/hostmem.h"
#include "sysemu/blockdev.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qapi/qapi-types-machine.h"
#include "qemu/module.h"
#include "qom/object.h"
diff --git a/include/sysemu/accel.h b/include/qemu/accel.h
similarity index 95%
rename from include/sysemu/accel.h
rename to include/qemu/accel.h
index e08b8ab8fa..fac4a18703 100644
--- a/include/sysemu/accel.h
+++ b/include/qemu/accel.h
@@ -20,8 +20,8 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#ifndef HW_ACCEL_H
-#define HW_ACCEL_H
+#ifndef QEMU_ACCEL_H
+#define QEMU_ACCEL_H
#include "qom/object.h"
#include "exec/hwaddr.h"
@@ -37,8 +37,8 @@ typedef struct AccelClass {
/*< public >*/
const char *name;
-#ifndef CONFIG_USER_ONLY
int (*init_machine)(MachineState *ms);
+#ifndef CONFIG_USER_ONLY
void (*setup_post)(MachineState *ms, AccelState *accel);
bool (*has_memory)(MachineState *ms, AddressSpace *as,
hwaddr start_addr, hwaddr size);
@@ -67,11 +67,13 @@ typedef struct AccelClass {
OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL)
AccelClass *accel_find(const char *opt_name);
+AccelState *current_accel(void);
+
+#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
/* Called just before os_setup_post (ie just before drop OS privs) */
void accel_setup_post(MachineState *ms);
+#endif /* !CONFIG_USER_ONLY */
-AccelState *current_accel(void);
-
-#endif
+#endif /* QEMU_ACCEL_H */
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index f893768df9..c98636bc81 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -13,7 +13,7 @@
#ifndef HVF_H
#define HVF_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef CONFIG_HVF
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index bb5d5cf497..739682f3c3 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -17,7 +17,7 @@
#include "qemu/queue.h"
#include "hw/core/cpu.h"
#include "exec/memattrs.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "qom/object.h"
#ifdef NEED_CPU_H
diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h
index 65740806da..ccb8869f01 100644
--- a/include/sysemu/kvm_int.h
+++ b/include/sysemu/kvm_int.h
@@ -10,7 +10,7 @@
#define QEMU_KVM_INT_H
#include "exec/memory.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/kvm.h"
typedef struct KVMSlot
diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h
index e0edffd077..50b914fd67 100644
--- a/target/i386/hvf/hvf-i386.h
+++ b/target/i386/hvf/hvf-i386.h
@@ -16,7 +16,7 @@
#ifndef HVF_I386_H
#define HVF_I386_H
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/hvf.h"
#include "cpu.h"
#include "x86.h"
diff --git a/accel/accel-common.c b/accel/accel-common.c
new file mode 100644
index 0000000000..ddec8cb5ae
--- /dev/null
+++ b/accel/accel-common.c
@@ -0,0 +1,50 @@
+/*
+ * QEMU accel class, components common to system emulation and user mode
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/accel.h"
+
+static const TypeInfo accel_type = {
+ .name = TYPE_ACCEL,
+ .parent = TYPE_OBJECT,
+ .class_size = sizeof(AccelClass),
+ .instance_size = sizeof(AccelState),
+};
+
+/* Lookup AccelClass from opt_name. Returns NULL if not found */
+AccelClass *accel_find(const char *opt_name)
+{
+ char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
+ AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
+ g_free(class_name);
+ return ac;
+}
+
+static void register_accel_types(void)
+{
+ type_register_static(&accel_type);
+}
+
+type_init(register_accel_types);
diff --git a/accel/accel.c b/accel/accel-softmmu.c
similarity index 75%
rename from accel/accel.c
rename to accel/accel-softmmu.c
index cb555e3b06..f89da8f9d1 100644
--- a/accel/accel.c
+++ b/accel/accel-softmmu.c
@@ -1,5 +1,5 @@
/*
- * QEMU System Emulator, accelerator interfaces
+ * QEMU accel class, system emulation components
*
* Copyright (c) 2003-2008 Fabrice Bellard
* Copyright (c) 2014 Red Hat Inc.
@@ -24,28 +24,12 @@
*/
#include "qemu/osdep.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/boards.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
#include "qom/object.h"
-static const TypeInfo accel_type = {
- .name = TYPE_ACCEL,
- .parent = TYPE_OBJECT,
- .class_size = sizeof(AccelClass),
- .instance_size = sizeof(AccelState),
-};
-
-/* Lookup AccelClass from opt_name. Returns NULL if not found */
-AccelClass *accel_find(const char *opt_name)
-{
- char *class_name = g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name);
- AccelClass *ac = ACCEL_CLASS(object_class_by_name(class_name));
- g_free(class_name);
- return ac;
-}
-
int accel_init_machine(AccelState *accel, MachineState *ms)
{
AccelClass *acc = ACCEL_GET_CLASS(accel);
@@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms)
acc->setup_post(ms, accel);
}
}
-
-static void register_accel_types(void)
-{
- type_register_static(&accel_type);
-}
-
-type_init(register_accel_types);
diff --git a/accel/accel-user.c b/accel/accel-user.c
new file mode 100644
index 0000000000..22b6a1a1a8
--- /dev/null
+++ b/accel/accel-user.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU accel class, user-mode components
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/accel.h"
+
+AccelState *current_accel(void)
+{
+ static AccelState *accel;
+
+ if (!accel) {
+ AccelClass *ac = accel_find("tcg");
+
+ g_assert(ac != NULL);
+ accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac)));
+ }
+ return accel;
+}
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index b282cea5cf..b4e731cb2b 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -17,7 +17,7 @@
#include "qemu/module.h"
#include "qemu/option.h"
#include "qemu/config-file.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/qtest.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 2eea8c32ee..642a7b94a7 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -30,9 +30,12 @@
#include "tcg/tcg.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
-#include "hw/boards.h"
+#include "qemu/accel.h"
#include "qapi/qapi-builtin-visit.h"
+
+#ifndef CONFIG_USER_ONLY
#include "tcg-cpus.h"
+#endif /* CONFIG_USER_ONLY */
struct TCGState {
AccelState parent_obj;
@@ -97,7 +100,7 @@ static void tcg_accel_instance_init(Object *obj)
s->mttcg_enabled = default_mttcg_enabled();
/* If debugging enabled, default "auto on", otherwise off. */
-#ifdef CONFIG_DEBUG_TCG
+#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY)
s->splitwx_enabled = -1;
#else
s->splitwx_enabled = 0;
@@ -114,8 +117,12 @@ static int tcg_init(MachineState *ms)
mttcg_enabled = s->mttcg_enabled;
/*
- * Initialize TCG regions
+ * Initialize TCG regions only for softmmu.
+ *
+ * This needs to be done later for user mode, because the prologue
+ * generation needs to be delayed so that GUEST_BASE is already set.
*/
+#ifndef CONFIG_USER_ONLY
tcg_region_init();
if (mttcg_enabled) {
@@ -125,6 +132,8 @@ static int tcg_init(MachineState *ms)
} else {
cpus_register_accel(&tcg_cpus_rr);
}
+#endif /* !CONFIG_USER_ONLY */
+
return 0;
}
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 878a4089d9..594aaf6b49 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -15,7 +15,7 @@
#include "hw/xen/xen-legacy-backend.h"
#include "hw/xen/xen_pt.h"
#include "chardev/char.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/cpus.h"
#include "sysemu/xen.h"
#include "sysemu/runstate.h"
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 65163e1396..6501164e05 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/units.h"
+#include "qemu/accel.h"
#include "sysemu/tcg.h"
#include "qemu-version.h"
#include <machine/trap.h>
@@ -909,8 +910,11 @@ int main(int argc, char **argv)
}
/* init tcg before creating CPUs and to get qemu_host_page_size */
- tcg_exec_init(0, false);
+ {
+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());
+ ac->init_machine(NULL);
+ }
cpu_type = parse_cpu_option(cpu_model);
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
diff --git a/linux-user/main.c b/linux-user/main.c
index bb4e55e8fc..7ed23d9a29 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/units.h"
+#include "qemu/accel.h"
#include "sysemu/tcg.h"
#include "qemu-version.h"
#include <sys/syscall.h>
@@ -701,8 +702,11 @@ int main(int argc, char **argv, char **envp)
cpu_type = parse_cpu_option(cpu_model);
/* init tcg before creating CPUs and to get qemu_host_page_size */
- tcg_exec_init(0, false);
+ {
+ AccelClass *ac = ACCEL_GET_CLASS(current_accel());
+ ac->init_machine(NULL);
+ }
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
cpu_reset(cpu);
diff --git a/softmmu/memory.c b/softmmu/memory.c
index 676c298b60..c0c814fbb9 100644
--- a/softmmu/memory.c
+++ b/softmmu/memory.c
@@ -32,7 +32,7 @@
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "sysemu/tcg.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/boards.h"
#include "migration/vmstate.h"
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 7965dc9a16..130c366615 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -20,7 +20,7 @@
#include "exec/ioport.h"
#include "exec/memory.h"
#include "hw/irq.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/cpu-timers.h"
#include "qemu/config-file.h"
#include "qemu/option.h"
diff --git a/softmmu/vl.c b/softmmu/vl.c
index bd55468669..6105c75bc7 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -44,7 +44,7 @@
#include "qemu/error-report.h"
#include "qemu/sockets.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "hw/usb.h"
#include "hw/isa/isa.h"
#include "hw/scsi/scsi.h"
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index fecfe8cd6e..d7f4bb44a7 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -28,7 +28,7 @@
#include "exec/address-spaces.h"
#include "qemu-common.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "hw/boards.h"
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ed9356565c..ffc9efa40f 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -69,7 +69,7 @@
#include "exec/address-spaces.h"
#include "hw/i386/apic_internal.h"
#include "qemu/main-loop.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "target/i386/cpu.h"
#include "hvf-cpus.h"
diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
index 6f04478b3a..d66dfd7669 100644
--- a/target/i386/hvf/x86_task.c
+++ b/target/i386/hvf/x86_task.c
@@ -28,7 +28,7 @@
#include "hw/i386/apic_internal.h"
#include "qemu/main-loop.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "target/i386/cpu.h"
// TODO: taskswitch handling
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 985ceba8f8..aa5c876138 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -13,7 +13,7 @@
#include "exec/address-spaces.h"
#include "exec/ioport.h"
#include "qemu-common.h"
-#include "sysemu/accel.h"
+#include "qemu/accel.h"
#include "sysemu/whpx.h"
#include "sysemu/cpus.h"
#include "sysemu/runstate.h"
diff --git a/MAINTAINERS b/MAINTAINERS
index c8559b34d7..9356db50c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -438,7 +438,7 @@ Overall
M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
-F: include/sysemu/accel.h
+F: include/qemu/accel.h
F: accel/accel.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/meson.build b/accel/meson.build
index b26cca227a..b44ba30c86 100644
--- a/accel/meson.build
+++ b/accel/meson.build
@@ -1,4 +1,6 @@
-softmmu_ss.add(files('accel.c'))
+specific_ss.add(files('accel-common.c'))
+softmmu_ss.add(files('accel-softmmu.c'))
+user_ss.add(files('accel-user.c'))
subdir('qtest')
subdir('kvm')
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index f39aab0a0c..424d9bb1fc 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,5 +1,6 @@
tcg_ss = ss.source_set()
tcg_ss.add(files(
+ 'tcg-all.c',
'cpu-exec-common.c',
'cpu-exec.c',
'tcg-runtime-gvec.c',
@@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
- 'tcg-all.c',
'cputlb.c',
'tcg-cpus.c',
'tcg-cpus-mttcg.c',
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (43 preceding siblings ...)
2021-02-05 22:56 ` [PULL 44/46] accel: extend AccelState and AccelClass to user-mode Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-02-05 22:56 ` [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass Richard Henderson
` (2 subsequent siblings)
47 siblings, 0 replies; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
This will allow us to centralize the registration of
the cpus.c module accelerator operations (in accel/accel-softmmu.c),
and trigger it automatically using object hierarchy lookup from the
new accel_init_interfaces() initialization step, depending just on
which accelerators are available in the code.
Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c,
kvm-accel-ops.c, etc, matching the object type names.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-18-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/accel-softmmu.h | 15 ++++++
accel/kvm/kvm-cpus.h | 2 -
...g-cpus-icount.h => tcg-accel-ops-icount.h} | 2 +
accel/tcg/tcg-accel-ops-mttcg.h | 19 ++++++++
.../tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h} | 0
accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} | 6 +--
include/qemu/accel.h | 2 +
include/sysemu/accel-ops.h | 45 ++++++++++++++++++
include/sysemu/cpus.h | 26 ++--------
.../i386/hax/{hax-cpus.h => hax-accel-ops.h} | 2 -
target/i386/hax/hax-windows.h | 2 +-
.../i386/hvf/{hvf-cpus.h => hvf-accel-ops.h} | 2 -
.../whpx/{whpx-cpus.h => whpx-accel-ops.h} | 2 -
accel/accel-common.c | 11 +++++
accel/accel-softmmu.c | 44 +++++++++++++++--
accel/kvm/{kvm-cpus.c => kvm-accel-ops.c} | 28 ++++++++---
accel/kvm/kvm-all.c | 2 -
accel/qtest/qtest.c | 23 ++++++---
...g-cpus-icount.c => tcg-accel-ops-icount.c} | 21 +++------
...tcg-cpus-mttcg.c => tcg-accel-ops-mttcg.c} | 14 ++----
.../tcg/{tcg-cpus-rr.c => tcg-accel-ops-rr.c} | 13 ++---
accel/tcg/{tcg-cpus.c => tcg-accel-ops.c} | 47 ++++++++++++++++++-
accel/tcg/tcg-all.c | 12 -----
accel/xen/xen-all.c | 24 ++++++----
bsd-user/main.c | 3 +-
linux-user/main.c | 1 +
softmmu/cpus.c | 12 ++---
softmmu/vl.c | 7 ++-
.../i386/hax/{hax-cpus.c => hax-accel-ops.c} | 33 +++++++++----
target/i386/hax/hax-all.c | 5 +-
target/i386/hax/hax-mem.c | 2 +-
target/i386/hax/hax-posix.c | 2 +-
target/i386/hax/hax-windows.c | 2 +-
.../i386/hvf/{hvf-cpus.c => hvf-accel-ops.c} | 29 +++++++++---
target/i386/hvf/hvf.c | 3 +-
target/i386/hvf/x86hvf.c | 2 +-
.../whpx/{whpx-cpus.c => whpx-accel-ops.c} | 33 +++++++++----
target/i386/whpx/whpx-all.c | 7 +--
MAINTAINERS | 3 +-
accel/kvm/meson.build | 2 +-
accel/tcg/meson.build | 8 ++--
target/i386/hax/meson.build | 2 +-
target/i386/hvf/meson.build | 2 +-
target/i386/whpx/meson.build | 2 +-
44 files changed, 361 insertions(+), 163 deletions(-)
create mode 100644 accel/accel-softmmu.h
rename accel/tcg/{tcg-cpus-icount.h => tcg-accel-ops-icount.h} (88%)
create mode 100644 accel/tcg/tcg-accel-ops-mttcg.h
rename accel/tcg/{tcg-cpus-rr.h => tcg-accel-ops-rr.h} (100%)
rename accel/tcg/{tcg-cpus.h => tcg-accel-ops.h} (72%)
create mode 100644 include/sysemu/accel-ops.h
rename target/i386/hax/{hax-cpus.h => hax-accel-ops.h} (95%)
rename target/i386/hvf/{hvf-cpus.h => hvf-accel-ops.h} (94%)
rename target/i386/whpx/{whpx-cpus.h => whpx-accel-ops.h} (96%)
rename accel/kvm/{kvm-cpus.c => kvm-accel-ops.c} (72%)
rename accel/tcg/{tcg-cpus-icount.c => tcg-accel-ops-icount.c} (89%)
rename accel/tcg/{tcg-cpus-mttcg.c => tcg-accel-ops-mttcg.c} (92%)
rename accel/tcg/{tcg-cpus-rr.c => tcg-accel-ops-rr.c} (97%)
rename accel/tcg/{tcg-cpus.c => tcg-accel-ops.c} (63%)
rename target/i386/hax/{hax-cpus.c => hax-accel-ops.c} (69%)
rename target/i386/hvf/{hvf-cpus.c => hvf-accel-ops.c} (84%)
rename target/i386/whpx/{whpx-cpus.c => whpx-accel-ops.c} (71%)
diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h
new file mode 100644
index 0000000000..5e192f1882
--- /dev/null
+++ b/accel/accel-softmmu.h
@@ -0,0 +1,15 @@
+/*
+ * QEMU System Emulation accel internal functions
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_SOFTMMU_H
+#define ACCEL_SOFTMMU_H
+
+void accel_init_ops_interfaces(AccelClass *ac);
+
+#endif /* ACCEL_SOFTMMU_H */
diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h
index 3df732b816..bf0bd1bee4 100644
--- a/accel/kvm/kvm-cpus.h
+++ b/accel/kvm/kvm-cpus.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel kvm_cpus;
-
int kvm_init_vcpu(CPUState *cpu, Error **errp);
int kvm_cpu_exec(CPUState *cpu);
void kvm_destroy_vcpu(CPUState *cpu);
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-accel-ops-icount.h
similarity index 88%
rename from accel/tcg/tcg-cpus-icount.h
rename to accel/tcg/tcg-accel-ops-icount.h
index b695939dfa..d884aa2aaa 100644
--- a/accel/tcg/tcg-cpus-icount.h
+++ b/accel/tcg/tcg-accel-ops-icount.h
@@ -14,4 +14,6 @@ void icount_handle_deadline(void);
void icount_prepare_for_run(CPUState *cpu);
void icount_process_data(CPUState *cpu);
+void icount_handle_interrupt(CPUState *cpu, int mask);
+
#endif /* TCG_CPUS_ICOUNT_H */
diff --git a/accel/tcg/tcg-accel-ops-mttcg.h b/accel/tcg/tcg-accel-ops-mttcg.h
new file mode 100644
index 0000000000..9fdc5a2ab5
--- /dev/null
+++ b/accel/tcg/tcg-accel-ops-mttcg.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU TCG Multi Threaded vCPUs implementation
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPUS_MTTCG_H
+#define TCG_CPUS_MTTCG_H
+
+/* kick MTTCG vCPU thread */
+void mttcg_kick_vcpu_thread(CPUState *cpu);
+
+/* start an mttcg vCPU thread */
+void mttcg_start_vcpu_thread(CPUState *cpu);
+
+#endif /* TCG_CPUS_MTTCG_H */
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-accel-ops-rr.h
similarity index 100%
rename from accel/tcg/tcg-cpus-rr.h
rename to accel/tcg/tcg-accel-ops-rr.h
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-accel-ops.h
similarity index 72%
rename from accel/tcg/tcg-cpus.h
rename to accel/tcg/tcg-accel-ops.h
index d6893a32f8..48130006de 100644
--- a/accel/tcg/tcg-cpus.h
+++ b/accel/tcg/tcg-accel-ops.h
@@ -14,12 +14,8 @@
#include "sysemu/cpus.h"
-extern const CpusAccel tcg_cpus_mttcg;
-extern const CpusAccel tcg_cpus_icount;
-extern const CpusAccel tcg_cpus_rr;
-
void tcg_cpus_destroy(CPUState *cpu);
int tcg_cpus_exec(CPUState *cpu);
-void tcg_cpus_handle_interrupt(CPUState *cpu, int mask);
+void tcg_handle_interrupt(CPUState *cpu, int mask);
#endif /* TCG_CPUS_H */
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index fac4a18703..b9d6d69eb8 100644
--- a/include/qemu/accel.h
+++ b/include/qemu/accel.h
@@ -69,6 +69,8 @@ typedef struct AccelClass {
AccelClass *accel_find(const char *opt_name);
AccelState *current_accel(void);
+void accel_init_interfaces(AccelClass *ac);
+
#ifndef CONFIG_USER_ONLY
int accel_init_machine(AccelState *accel, MachineState *ms);
diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h
new file mode 100644
index 0000000000..032f6979d7
--- /dev/null
+++ b/include/sysemu/accel-ops.h
@@ -0,0 +1,45 @@
+/*
+ * Accelerator OPS, used for cpus.c module
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_OPS_H
+#define ACCEL_OPS_H
+
+#include "qom/object.h"
+
+#define ACCEL_OPS_SUFFIX "-ops"
+#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX
+#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS)
+
+typedef struct AccelOpsClass AccelOpsClass;
+DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS)
+
+/* cpus.c operations interface */
+struct AccelOpsClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ /* initialization function called when accel is chosen */
+ void (*ops_init)(AccelOpsClass *ops);
+
+ void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */
+ void (*kick_vcpu_thread)(CPUState *cpu);
+
+ void (*synchronize_post_reset)(CPUState *cpu);
+ void (*synchronize_post_init)(CPUState *cpu);
+ void (*synchronize_state)(CPUState *cpu);
+ void (*synchronize_pre_loadvm)(CPUState *cpu);
+
+ void (*handle_interrupt)(CPUState *cpu, int mask);
+
+ int64_t (*get_virtual_clock)(void);
+ int64_t (*get_elapsed_ticks)(void);
+};
+
+#endif /* ACCEL_OPS_H */
diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h
index e8156728c6..2cd74392e0 100644
--- a/include/sysemu/cpus.h
+++ b/include/sysemu/cpus.h
@@ -2,30 +2,14 @@
#define QEMU_CPUS_H
#include "qemu/timer.h"
+#include "sysemu/accel-ops.h"
-/* cpus.c */
+/* register accel-specific operations */
+void cpus_register_accel(const AccelOpsClass *i);
-/* CPU execution threads */
+/* accel/dummy-cpus.c */
-typedef struct CpusAccel {
- void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY */
- void (*kick_vcpu_thread)(CPUState *cpu);
-
- void (*synchronize_post_reset)(CPUState *cpu);
- void (*synchronize_post_init)(CPUState *cpu);
- void (*synchronize_state)(CPUState *cpu);
- void (*synchronize_pre_loadvm)(CPUState *cpu);
-
- void (*handle_interrupt)(CPUState *cpu, int mask);
-
- int64_t (*get_virtual_clock)(void);
- int64_t (*get_elapsed_ticks)(void);
-} CpusAccel;
-
-/* register accel-specific cpus interface implementation */
-void cpus_register_accel(const CpusAccel *i);
-
-/* Create a dummy vcpu for CpusAccel->create_vcpu_thread */
+/* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */
void dummy_start_vcpu_thread(CPUState *);
/* interface available for cpus accelerator threads */
diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-accel-ops.h
similarity index 95%
rename from target/i386/hax/hax-cpus.h
rename to target/i386/hax/hax-accel-ops.h
index ee8ab7a631..c7698519cd 100644
--- a/target/i386/hax/hax-cpus.h
+++ b/target/i386/hax/hax-accel-ops.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel hax_cpus;
-
#include "hax-interface.h"
#include "hax-i386.h"
diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h
index a5ce12d663..b1f5d4f32f 100644
--- a/target/i386/hax/hax-windows.h
+++ b/target/i386/hax/hax-windows.h
@@ -23,7 +23,7 @@
#include <winioctl.h>
#include <windef.h>
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
#define HAX_INVALID_FD INVALID_HANDLE_VALUE
diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-accel-ops.h
similarity index 94%
rename from target/i386/hvf/hvf-cpus.h
rename to target/i386/hvf/hvf-accel-ops.h
index ced31b82c0..8f992da168 100644
--- a/target/i386/hvf/hvf-cpus.h
+++ b/target/i386/hvf/hvf-accel-ops.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel hvf_cpus;
-
int hvf_init_vcpu(CPUState *);
int hvf_vcpu_exec(CPUState *);
void hvf_cpu_synchronize_state(CPUState *);
diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-accel-ops.h
similarity index 96%
rename from target/i386/whpx/whpx-cpus.h
rename to target/i386/whpx/whpx-accel-ops.h
index bdb367d1d0..2dee6d61ea 100644
--- a/target/i386/whpx/whpx-cpus.h
+++ b/target/i386/whpx/whpx-accel-ops.h
@@ -12,8 +12,6 @@
#include "sysemu/cpus.h"
-extern const CpusAccel whpx_cpus;
-
int whpx_init_vcpu(CPUState *cpu);
int whpx_vcpu_exec(CPUState *cpu);
void whpx_destroy_vcpu(CPUState *cpu);
diff --git a/accel/accel-common.c b/accel/accel-common.c
index ddec8cb5ae..6b59873419 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,10 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#ifndef CONFIG_USER_ONLY
+#include "accel-softmmu.h"
+#endif /* !CONFIG_USER_ONLY */
+
static const TypeInfo accel_type = {
.name = TYPE_ACCEL,
.parent = TYPE_OBJECT,
@@ -42,6 +46,13 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+void accel_init_interfaces(AccelClass *ac)
+{
+#ifndef CONFIG_USER_ONLY
+ accel_init_ops_interfaces(ac);
+#endif /* !CONFIG_USER_ONLY */
+}
+
static void register_accel_types(void)
{
type_register_static(&accel_type);
diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c
index f89da8f9d1..50fa5acaa4 100644
--- a/accel/accel-softmmu.c
+++ b/accel/accel-softmmu.c
@@ -26,9 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
#include "hw/boards.h"
-#include "sysemu/arch_init.h"
-#include "sysemu/sysemu.h"
-#include "qom/object.h"
+#include "sysemu/cpus.h"
+
+#include "accel-softmmu.h"
int accel_init_machine(AccelState *accel, MachineState *ms)
{
@@ -60,3 +60,41 @@ void accel_setup_post(MachineState *ms)
acc->setup_post(ms, accel);
}
}
+
+/* initialize the arch-independent accel operation interfaces */
+void accel_init_ops_interfaces(AccelClass *ac)
+{
+ const char *ac_name;
+ char *ops_name;
+ AccelOpsClass *ops;
+
+ ac_name = object_class_get_name(OBJECT_CLASS(ac));
+ g_assert(ac_name != NULL);
+
+ ops_name = g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name);
+ ops = ACCEL_OPS_CLASS(object_class_by_name(ops_name));
+ g_free(ops_name);
+
+ /*
+ * all accelerators need to define ops, providing at least a mandatory
+ * non-NULL create_vcpu_thread operation.
+ */
+ g_assert(ops != NULL);
+ if (ops->ops_init) {
+ ops->ops_init(ops);
+ }
+ cpus_register_accel(ops);
+}
+
+static const TypeInfo accel_ops_type_info = {
+ .name = TYPE_ACCEL_OPS,
+ .parent = TYPE_OBJECT,
+ .abstract = true,
+ .class_size = sizeof(AccelOpsClass),
+};
+
+static void accel_softmmu_register_types(void)
+{
+ type_register_static(&accel_ops_type_info);
+}
+type_init(accel_softmmu_register_types);
diff --git a/accel/kvm/kvm-cpus.c b/accel/kvm/kvm-accel-ops.c
similarity index 72%
rename from accel/kvm/kvm-cpus.c
rename to accel/kvm/kvm-accel-ops.c
index d809b1e74c..7516c67a3f 100644
--- a/accel/kvm/kvm-cpus.c
+++ b/accel/kvm/kvm-accel-ops.c
@@ -74,11 +74,27 @@ static void kvm_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
-const CpusAccel kvm_cpus = {
- .create_vcpu_thread = kvm_start_vcpu_thread,
+static void kvm_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = kvm_cpu_synchronize_post_reset,
- .synchronize_post_init = kvm_cpu_synchronize_post_init,
- .synchronize_state = kvm_cpu_synchronize_state,
- .synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = kvm_start_vcpu_thread;
+ ops->synchronize_post_reset = kvm_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = kvm_cpu_synchronize_post_init;
+ ops->synchronize_state = kvm_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm;
+}
+
+static const TypeInfo kvm_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("kvm"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = kvm_accel_ops_class_init,
+ .abstract = true,
};
+
+static void kvm_accel_ops_register_types(void)
+{
+ type_register_static(&kvm_accel_ops_type);
+}
+type_init(kvm_accel_ops_register_types);
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 3feb17d965..5164d838b9 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -2256,8 +2256,6 @@ static int kvm_init(MachineState *ms)
ret = ram_block_discard_disable(true);
assert(!ret);
}
-
- cpus_register_accel(&kvm_cpus);
return 0;
err:
diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c
index b4e731cb2b..edb29f6fa4 100644
--- a/accel/qtest/qtest.c
+++ b/accel/qtest/qtest.c
@@ -25,14 +25,8 @@
#include "qemu/main-loop.h"
#include "hw/core/cpu.h"
-const CpusAccel qtest_cpus = {
- .create_vcpu_thread = dummy_start_vcpu_thread,
- .get_virtual_clock = qtest_get_virtual_clock,
-};
-
static int qtest_init_accel(MachineState *ms)
{
- cpus_register_accel(&qtest_cpus);
return 0;
}
@@ -52,9 +46,26 @@ static const TypeInfo qtest_accel_type = {
.class_init = qtest_accel_class_init,
};
+static void qtest_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->create_vcpu_thread = dummy_start_vcpu_thread;
+ ops->get_virtual_clock = qtest_get_virtual_clock;
+};
+
+static const TypeInfo qtest_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("qtest"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = qtest_accel_ops_class_init,
+ .abstract = true,
+};
+
static void qtest_type_init(void)
{
type_register_static(&qtest_accel_type);
+ type_register_static(&qtest_accel_ops_type);
}
type_init(qtest_type_init);
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-accel-ops-icount.c
similarity index 89%
rename from accel/tcg/tcg-cpus-icount.c
rename to accel/tcg/tcg-accel-ops-icount.c
index 9f45432275..87762b469c 100644
--- a/accel/tcg/tcg-cpus-icount.c
+++ b/accel/tcg/tcg-accel-ops-icount.c
@@ -32,9 +32,9 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
-#include "tcg-cpus-icount.h"
-#include "tcg-cpus-rr.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-icount.h"
+#include "tcg-accel-ops-rr.h"
static int64_t icount_get_limit(void)
{
@@ -93,7 +93,7 @@ void icount_prepare_for_run(CPUState *cpu)
/*
* These should always be cleared by icount_process_data after
* each vCPU execution. However u16.high can be raised
- * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
*/
g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
g_assert(cpu->icount_extra == 0);
@@ -125,23 +125,14 @@ void icount_process_data(CPUState *cpu)
replay_mutex_unlock();
}
-static void icount_handle_interrupt(CPUState *cpu, int mask)
+void icount_handle_interrupt(CPUState *cpu, int mask)
{
int old_mask = cpu->interrupt_request;
- tcg_cpus_handle_interrupt(cpu, mask);
+ tcg_handle_interrupt(cpu, mask);
if (qemu_cpu_is_self(cpu) &&
!cpu->can_do_io
&& (mask & ~old_mask) != 0) {
cpu_abort(cpu, "Raised interrupt while not in I/O function");
}
}
-
-const CpusAccel tcg_cpus_icount = {
- .create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = rr_kick_vcpu_thread,
-
- .handle_interrupt = icount_handle_interrupt,
- .get_virtual_clock = icount_get,
- .get_elapsed_ticks = icount_get,
-};
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
similarity index 92%
rename from accel/tcg/tcg-cpus-mttcg.c
rename to accel/tcg/tcg-accel-ops-mttcg.c
index 9c3767d260..42973fb062 100644
--- a/accel/tcg/tcg-cpus-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -32,7 +32,8 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-mttcg.h"
/*
* In the multi-threaded case each vCPU has its own thread. The TLS
@@ -103,12 +104,12 @@ static void *mttcg_cpu_thread_fn(void *arg)
return NULL;
}
-static void mttcg_kick_vcpu_thread(CPUState *cpu)
+void mttcg_kick_vcpu_thread(CPUState *cpu)
{
cpu_exit(cpu);
}
-static void mttcg_start_vcpu_thread(CPUState *cpu)
+void mttcg_start_vcpu_thread(CPUState *cpu)
{
char thread_name[VCPU_THREAD_NAME_SIZE];
@@ -131,10 +132,3 @@ static void mttcg_start_vcpu_thread(CPUState *cpu)
cpu->hThread = qemu_thread_get_handle(cpu->thread);
#endif
}
-
-const CpusAccel tcg_cpus_mttcg = {
- .create_vcpu_thread = mttcg_start_vcpu_thread,
- .kick_vcpu_thread = mttcg_kick_vcpu_thread,
-
- .handle_interrupt = tcg_cpus_handle_interrupt,
-};
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-accel-ops-rr.c
similarity index 97%
rename from accel/tcg/tcg-cpus-rr.c
rename to accel/tcg/tcg-accel-ops-rr.c
index 0181d2e4eb..4a66055e0d 100644
--- a/accel/tcg/tcg-cpus-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -32,9 +32,9 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
-#include "tcg-cpus-rr.h"
-#include "tcg-cpus-icount.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-rr.h"
+#include "tcg-accel-ops-icount.h"
/* Kick all RR vCPUs */
void rr_kick_vcpu_thread(CPUState *unused)
@@ -296,10 +296,3 @@ void rr_start_vcpu_thread(CPUState *cpu)
cpu->created = true;
}
}
-
-const CpusAccel tcg_cpus_rr = {
- .create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = rr_kick_vcpu_thread,
-
- .handle_interrupt = tcg_cpus_handle_interrupt,
-};
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-accel-ops.c
similarity index 63%
rename from accel/tcg/tcg-cpus.c
rename to accel/tcg/tcg-accel-ops.c
index e335f9f155..6144d9df87 100644
--- a/accel/tcg/tcg-cpus.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -34,7 +34,10 @@
#include "exec/exec-all.h"
#include "hw/boards.h"
-#include "tcg-cpus.h"
+#include "tcg-accel-ops.h"
+#include "tcg-accel-ops-mttcg.h"
+#include "tcg-accel-ops-rr.h"
+#include "tcg-accel-ops-icount.h"
/* common functionality among all TCG variants */
@@ -64,7 +67,7 @@ int tcg_cpus_exec(CPUState *cpu)
}
/* mask must never be zero, except for A20 change call */
-void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
+void tcg_handle_interrupt(CPUState *cpu, int mask)
{
g_assert(qemu_mutex_iothread_locked());
@@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
}
}
+
+static void tcg_accel_ops_init(AccelOpsClass *ops)
+{
+ if (qemu_tcg_mttcg_enabled()) {
+ ops->create_vcpu_thread = mttcg_start_vcpu_thread;
+ ops->kick_vcpu_thread = mttcg_kick_vcpu_thread;
+ ops->handle_interrupt = tcg_handle_interrupt;
+ } else if (icount_enabled()) {
+ ops->create_vcpu_thread = rr_start_vcpu_thread;
+ ops->kick_vcpu_thread = rr_kick_vcpu_thread;
+ ops->handle_interrupt = icount_handle_interrupt;
+ ops->get_virtual_clock = icount_get;
+ ops->get_elapsed_ticks = icount_get;
+ } else {
+ ops->create_vcpu_thread = rr_start_vcpu_thread;
+ ops->kick_vcpu_thread = rr_kick_vcpu_thread;
+ ops->handle_interrupt = tcg_handle_interrupt;
+ }
+}
+
+static void tcg_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->ops_init = tcg_accel_ops_init;
+}
+
+static const TypeInfo tcg_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = tcg_accel_ops_class_init,
+ .abstract = true,
+};
+
+static void tcg_accel_ops_register_types(void)
+{
+ type_register_static(&tcg_accel_ops_type);
+}
+type_init(tcg_accel_ops_register_types);
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 642a7b94a7..e378c2db73 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -33,10 +33,6 @@
#include "qemu/accel.h"
#include "qapi/qapi-builtin-visit.h"
-#ifndef CONFIG_USER_ONLY
-#include "tcg-cpus.h"
-#endif /* CONFIG_USER_ONLY */
-
struct TCGState {
AccelState parent_obj;
@@ -124,14 +120,6 @@ static int tcg_init(MachineState *ms)
*/
#ifndef CONFIG_USER_ONLY
tcg_region_init();
-
- if (mttcg_enabled) {
- cpus_register_accel(&tcg_cpus_mttcg);
- } else if (icount_enabled()) {
- cpus_register_accel(&tcg_cpus_icount);
- } else {
- cpus_register_accel(&tcg_cpus_rr);
- }
#endif /* !CONFIG_USER_ONLY */
return 0;
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c
index 594aaf6b49..e9d2d6aaaa 100644
--- a/accel/xen/xen-all.c
+++ b/accel/xen/xen-all.c
@@ -154,10 +154,6 @@ static void xen_setup_post(MachineState *ms, AccelState *accel)
}
}
-const CpusAccel xen_cpus = {
- .create_vcpu_thread = dummy_start_vcpu_thread,
-};
-
static int xen_init(MachineState *ms)
{
MachineClass *mc = MACHINE_GET_CLASS(ms);
@@ -185,9 +181,6 @@ static int xen_init(MachineState *ms)
* opt out of system RAM being allocated by generic code
*/
mc->default_ram_id = NULL;
-
- cpus_register_accel(&xen_cpus);
-
return 0;
}
@@ -222,9 +215,24 @@ static const TypeInfo xen_accel_type = {
.class_init = xen_accel_class_init,
};
+static void xen_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
+
+ ops->create_vcpu_thread = dummy_start_vcpu_thread;
+}
+
+static const TypeInfo xen_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("xen"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = xen_accel_ops_class_init,
+ .abstract = true,
+};
+
static void xen_type_init(void)
{
type_register_static(&xen_accel_type);
+ type_register_static(&xen_accel_ops_type);
}
-
type_init(xen_type_init);
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 6501164e05..7cc08024e3 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -909,13 +909,14 @@ int main(int argc, char **argv)
#endif
}
+ cpu_type = parse_cpu_option(cpu_model);
/* init tcg before creating CPUs and to get qemu_host_page_size */
{
AccelClass *ac = ACCEL_GET_CLASS(current_accel());
ac->init_machine(NULL);
+ accel_init_interfaces(ac);
}
- cpu_type = parse_cpu_option(cpu_model);
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
#if defined(TARGET_SPARC) || defined(TARGET_PPC)
diff --git a/linux-user/main.c b/linux-user/main.c
index 7ed23d9a29..2e3c169878 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -706,6 +706,7 @@ int main(int argc, char **argv, char **envp)
AccelClass *ac = ACCEL_GET_CLASS(current_accel());
ac->init_machine(NULL);
+ accel_init_interfaces(ac);
}
cpu = cpu_create(cpu_type);
env = cpu->env_ptr;
diff --git a/softmmu/cpus.c b/softmmu/cpus.c
index 1dc20b9dc3..112eba9d54 100644
--- a/softmmu/cpus.c
+++ b/softmmu/cpus.c
@@ -128,7 +128,7 @@ void hw_error(const char *fmt, ...)
/*
* The chosen accelerator is supposed to register this.
*/
-static const CpusAccel *cpus_accel;
+static const AccelOpsClass *cpus_accel;
void cpu_synchronize_all_states(void)
{
@@ -594,11 +594,11 @@ void cpu_remove_sync(CPUState *cpu)
qemu_mutex_lock_iothread();
}
-void cpus_register_accel(const CpusAccel *ca)
+void cpus_register_accel(const AccelOpsClass *ops)
{
- assert(ca != NULL);
- assert(ca->create_vcpu_thread != NULL); /* mandatory */
- cpus_accel = ca;
+ assert(ops != NULL);
+ assert(ops->create_vcpu_thread != NULL); /* mandatory */
+ cpus_accel = ops;
}
void qemu_init_vcpu(CPUState *cpu)
@@ -618,7 +618,7 @@ void qemu_init_vcpu(CPUState *cpu)
cpu_address_space_init(cpu, 0, "cpu-memory", cpu->memory);
}
- /* accelerators all implement the CpusAccel interface */
+ /* accelerators all implement the AccelOpsClass */
g_assert(cpus_accel != NULL && cpus_accel->create_vcpu_thread != NULL);
cpus_accel->create_vcpu_thread(cpu);
diff --git a/softmmu/vl.c b/softmmu/vl.c
index 6105c75bc7..2bf94ece9c 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -1726,7 +1726,8 @@ static bool object_create_early(const char *type, QemuOpts *opts)
return false;
}
- /* Allocation of large amounts of memory may delay
+ /*
+ * Allocation of large amounts of memory may delay
* chardev initialization for too long, and trigger timeouts
* on software that waits for a monitor socket to be created
* (e.g. libvirt).
@@ -3497,7 +3498,7 @@ void qemu_init(int argc, char **argv, char **envp)
*
* Machine compat properties: object_set_machine_compat_props().
* Accelerator compat props: object_set_accelerator_compat_props(),
- * called from configure_accelerator().
+ * called from do_configure_accelerator().
*/
machine_class = MACHINE_GET_CLASS(current_machine);
@@ -3519,6 +3520,8 @@ void qemu_init(int argc, char **argv, char **envp)
if (cpu_option) {
current_machine->cpu_type = parse_cpu_option(cpu_option);
}
+ /* NB: for machine none cpu_type could STILL be NULL here! */
+ accel_init_interfaces(ACCEL_GET_CLASS(current_machine->accelerator));
qemu_resolve_machine_memdev();
parse_numa_opts(current_machine);
diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-accel-ops.c
similarity index 69%
rename from target/i386/hax/hax-cpus.c
rename to target/i386/hax/hax-accel-ops.c
index f72c85bd49..136630e9b2 100644
--- a/target/i386/hax/hax-cpus.c
+++ b/target/i386/hax/hax-accel-ops.c
@@ -26,7 +26,7 @@
#include "sysemu/cpus.h"
#include "qemu/guest-random.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
static void *hax_cpu_thread_fn(void *arg)
{
@@ -74,12 +74,29 @@ static void hax_start_vcpu_thread(CPUState *cpu)
#endif
}
-const CpusAccel hax_cpus = {
- .create_vcpu_thread = hax_start_vcpu_thread,
- .kick_vcpu_thread = hax_kick_vcpu_thread,
+static void hax_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = hax_cpu_synchronize_post_reset,
- .synchronize_post_init = hax_cpu_synchronize_post_init,
- .synchronize_state = hax_cpu_synchronize_state,
- .synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = hax_start_vcpu_thread;
+ ops->kick_vcpu_thread = hax_kick_vcpu_thread;
+
+ ops->synchronize_post_reset = hax_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = hax_cpu_synchronize_post_init;
+ ops->synchronize_state = hax_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm;
+}
+
+static const TypeInfo hax_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("hax"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = hax_accel_ops_class_init,
+ .abstract = true,
};
+
+static void hax_accel_ops_register_types(void)
+{
+ type_register_static(&hax_accel_ops_type);
+}
+type_init(hax_accel_ops_register_types);
diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c
index d7f4bb44a7..bf65ed6fa9 100644
--- a/target/i386/hax/hax-all.c
+++ b/target/i386/hax/hax-all.c
@@ -33,7 +33,7 @@
#include "sysemu/runstate.h"
#include "hw/boards.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
#define DEBUG_HAX 0
@@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms)
!ret ? "working" : "not working",
!ret ? "fast virt" : "emulation");
}
- if (ret == 0) {
- cpus_register_accel(&hax_cpus);
- }
return ret;
}
diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c
index 71e637cf16..35495f5e82 100644
--- a/target/i386/hax/hax-mem.c
+++ b/target/i386/hax/hax-mem.c
@@ -13,7 +13,7 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
#include "qemu/queue.h"
#define DEBUG_HAX_MEM 0
diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c
index 735a749d4b..ac1a51096e 100644
--- a/target/i386/hax/hax-posix.c
+++ b/target/i386/hax/hax-posix.c
@@ -15,7 +15,7 @@
#include <sys/ioctl.h>
#include "sysemu/cpus.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
hax_fd hax_mod_open(void)
{
diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c
index 6c82dfb54f..59afa213a6 100644
--- a/target/i386/hax/hax-windows.c
+++ b/target/i386/hax/hax-windows.c
@@ -12,7 +12,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "hax-cpus.h"
+#include "hax-accel-ops.h"
/*
* return 0 when success, -1 when driver not loaded,
diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-accel-ops.c
similarity index 84%
rename from target/i386/hvf/hvf-cpus.c
rename to target/i386/hvf/hvf-accel-ops.c
index 817b3d7452..cbaad238e0 100644
--- a/target/i386/hvf/hvf-cpus.c
+++ b/target/i386/hvf/hvf-accel-ops.c
@@ -55,7 +55,7 @@
#include "target/i386/cpu.h"
#include "qemu/guest-random.h"
-#include "hvf-cpus.h"
+#include "hvf-accel-ops.h"
/*
* The HVF-specific vCPU thread function. This one should only run when the host
@@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu)
cpu, QEMU_THREAD_JOINABLE);
}
-const CpusAccel hvf_cpus = {
- .create_vcpu_thread = hvf_start_vcpu_thread,
+static void hvf_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = hvf_cpu_synchronize_post_reset,
- .synchronize_post_init = hvf_cpu_synchronize_post_init,
- .synchronize_state = hvf_cpu_synchronize_state,
- .synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = hvf_start_vcpu_thread;
+
+ ops->synchronize_post_reset = hvf_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = hvf_cpu_synchronize_post_init;
+ ops->synchronize_state = hvf_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm;
};
+static const TypeInfo hvf_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("hvf"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = hvf_accel_ops_class_init,
+ .abstract = true,
+};
+static void hvf_accel_ops_register_types(void)
+{
+ type_register_static(&hvf_accel_ops_type);
+}
+type_init(hvf_accel_ops_register_types);
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ffc9efa40f..5b90dcdf88 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -72,7 +72,7 @@
#include "qemu/accel.h"
#include "target/i386/cpu.h"
-#include "hvf-cpus.h"
+#include "hvf-accel-ops.h"
HVFState *hvf_state;
@@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms)
hvf_state = s;
memory_listener_register(&hvf_memory_listener, &address_space_memory);
- cpus_register_accel(&hvf_cpus);
return 0;
}
diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c
index bbec412b6c..0d7533742e 100644
--- a/target/i386/hvf/x86hvf.c
+++ b/target/i386/hvf/x86hvf.c
@@ -32,7 +32,7 @@
#include <Hypervisor/hv.h>
#include <Hypervisor/hv_vmx.h>
-#include "hvf-cpus.h"
+#include "hvf-accel-ops.h"
void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
SegmentCache *qseg, bool is_tr)
diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-accel-ops.c
similarity index 71%
rename from target/i386/whpx/whpx-cpus.c
rename to target/i386/whpx/whpx-accel-ops.c
index f7e69881a3..6bc47c5309 100644
--- a/target/i386/whpx/whpx-cpus.c
+++ b/target/i386/whpx/whpx-accel-ops.c
@@ -16,7 +16,7 @@
#include "sysemu/whpx.h"
#include "whpx-internal.h"
-#include "whpx-cpus.h"
+#include "whpx-accel-ops.h"
static void *whpx_cpu_thread_fn(void *arg)
{
@@ -83,12 +83,29 @@ static void whpx_kick_vcpu_thread(CPUState *cpu)
}
}
-const CpusAccel whpx_cpus = {
- .create_vcpu_thread = whpx_start_vcpu_thread,
- .kick_vcpu_thread = whpx_kick_vcpu_thread,
+static void whpx_accel_ops_class_init(ObjectClass *oc, void *data)
+{
+ AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
- .synchronize_post_reset = whpx_cpu_synchronize_post_reset,
- .synchronize_post_init = whpx_cpu_synchronize_post_init,
- .synchronize_state = whpx_cpu_synchronize_state,
- .synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm,
+ ops->create_vcpu_thread = whpx_start_vcpu_thread;
+ ops->kick_vcpu_thread = whpx_kick_vcpu_thread;
+
+ ops->synchronize_post_reset = whpx_cpu_synchronize_post_reset;
+ ops->synchronize_post_init = whpx_cpu_synchronize_post_init;
+ ops->synchronize_state = whpx_cpu_synchronize_state;
+ ops->synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm;
+}
+
+static const TypeInfo whpx_accel_ops_type = {
+ .name = ACCEL_OPS_NAME("whpx"),
+
+ .parent = TYPE_ACCEL_OPS,
+ .class_init = whpx_accel_ops_class_init,
+ .abstract = true,
};
+
+static void whpx_accel_ops_register_types(void)
+{
+ type_register_static(&whpx_accel_ops_type);
+}
+type_init(whpx_accel_ops_register_types);
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index aa5c876138..f0a35df3bb 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -28,8 +28,11 @@
#include "migration/blocker.h"
#include <winerror.h>
-#include "whpx-cpus.h"
#include "whpx-internal.h"
+#include "whpx-accel-ops.h"
+
+#include <WinHvPlatform.h>
+#include <WinHvEmulation.h>
#define HYPERV_APIC_BUS_FREQUENCY (200000000ULL)
@@ -1846,8 +1849,6 @@ static int whpx_accel_init(MachineState *ms)
whpx_memory_init();
- cpus_register_accel(&whpx_cpus);
-
printf("Windows Hypervisor Platform accelerator is operational\n");
return 0;
diff --git a/MAINTAINERS b/MAINTAINERS
index 9356db50c3..2e63561ad0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -439,7 +439,8 @@ M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
-F: accel/accel.c
+F: include/sysemu/accel-ops.h
+F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
diff --git a/accel/kvm/meson.build b/accel/kvm/meson.build
index 7e9dafe24c..8d219bea50 100644
--- a/accel/kvm/meson.build
+++ b/accel/kvm/meson.build
@@ -1,7 +1,7 @@
kvm_ss = ss.source_set()
kvm_ss.add(files(
'kvm-all.c',
- 'kvm-cpus.c',
+ 'kvm-accel-ops.c',
))
kvm_ss.add(when: 'CONFIG_SEV', if_false: files('sev-stub.c'))
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 424d9bb1fc..1236ac7b91 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -15,8 +15,8 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
- 'tcg-cpus.c',
- 'tcg-cpus-mttcg.c',
- 'tcg-cpus-icount.c',
- 'tcg-cpus-rr.c'
+ 'tcg-accel-ops.c',
+ 'tcg-accel-ops-mttcg.c',
+ 'tcg-accel-ops-icount.c',
+ 'tcg-accel-ops-rr.c'
))
diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build
index 77ea431b30..d6c520fb6b 100644
--- a/target/i386/hax/meson.build
+++ b/target/i386/hax/meson.build
@@ -1,7 +1,7 @@
i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
'hax-all.c',
'hax-mem.c',
- 'hax-cpus.c',
+ 'hax-accel-ops.c',
))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build
index 409c9a3f14..e9eb5a5da8 100644
--- a/target/i386/hvf/meson.build
+++ b/target/i386/hvf/meson.build
@@ -1,6 +1,6 @@
i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files(
'hvf.c',
- 'hvf-cpus.c',
+ 'hvf-accel-ops.c',
'x86.c',
'x86_cpuid.c',
'x86_decode.c',
diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build
index d8aa683999..95fc31eb81 100644
--- a/target/i386/whpx/meson.build
+++ b/target/i386/whpx/meson.build
@@ -1,5 +1,5 @@
i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
'whpx-all.c',
'whpx-apic.c',
- 'whpx-cpus.c',
+ 'whpx-accel-ops.c',
))
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (44 preceding siblings ...)
2021-02-05 22:56 ` [PULL 45/46] accel: replace struct CpusAccel with AccelOpsClass Richard Henderson
@ 2021-02-05 22:56 ` Richard Henderson
2021-04-26 14:42 ` Philippe Mathieu-Daudé
2021-02-06 14:28 ` [PULL 00/46] tcg patch queue Peter Maydell
2021-02-06 19:38 ` Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue) Stefan Weil
47 siblings, 1 reply; 57+ messages in thread
From: Richard Henderson @ 2021-02-05 22:56 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Claudio Fontana
From: Claudio Fontana <cfontana@suse.de>
add a new optional interface to CPUClass, which allows accelerators
to extend the CPUClass with additional accelerator-specific
initializations.
This will allow to separate the target cpu code that is specific
to each accelerator, and register it automatically with object
hierarchy lookup depending on accelerator code availability,
as part of the accel_init_interfaces() initialization step.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-19-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/accel-cpu.h | 38 ++++++++++++++++++++++++++++++++
include/hw/core/cpu.h | 4 ++++
accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
4 files changed, 87 insertions(+)
create mode 100644 include/hw/core/accel-cpu.h
diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
new file mode 100644
index 0000000000..24a6697412
--- /dev/null
+++ b/include/hw/core/accel-cpu.h
@@ -0,0 +1,38 @@
+/*
+ * Accelerator interface, specializes CPUClass
+ * This header is used only by target-specific code.
+ *
+ * Copyright 2021 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ACCEL_CPU_H
+#define ACCEL_CPU_H
+
+/*
+ * This header is used to define new accelerator-specific target-specific
+ * accelerator cpu subclasses.
+ * It uses CPU_RESOLVING_TYPE, so this is clearly target-specific.
+ *
+ * Do not try to use for any other purpose than the implementation of new
+ * subclasses in target/, or the accel implementation itself in accel/
+ */
+
+#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
+#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
+typedef struct AccelCPUClass AccelCPUClass;
+DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
+
+typedef struct AccelCPUClass {
+ /*< private >*/
+ ObjectClass parent_class;
+ /*< public >*/
+
+ void (*cpu_class_init)(CPUClass *cc);
+ void (*cpu_instance_init)(CPUState *cpu);
+ void (*cpu_realizefn)(CPUState *cpu, Error **errp);
+} AccelCPUClass;
+
+#endif /* ACCEL_CPU_H */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 4f6c6b18c9..38d813c389 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -79,6 +79,9 @@ struct TranslationBlock;
/* see tcg-cpu-ops.h */
struct TCGCPUOps;
+/* see accel-cpu.h */
+struct AccelCPUClass;
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -187,6 +190,7 @@ struct CPUClass {
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+ struct AccelCPUClass *accel_cpu;
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
diff --git a/accel/accel-common.c b/accel/accel-common.c
index 6b59873419..9901b0531c 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -26,6 +26,9 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
+#include "cpu.h"
+#include "hw/core/accel-cpu.h"
+
#ifndef CONFIG_USER_ONLY
#include "accel-softmmu.h"
#endif /* !CONFIG_USER_ONLY */
@@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name)
return ac;
}
+static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
+{
+ CPUClass *cc = CPU_CLASS(klass);
+ AccelCPUClass *accel_cpu = opaque;
+
+ cc->accel_cpu = accel_cpu;
+ if (accel_cpu->cpu_class_init) {
+ accel_cpu->cpu_class_init(cc);
+ }
+}
+
+/* initialize the arch-specific accel CpuClass interfaces */
+static void accel_init_cpu_interfaces(AccelClass *ac)
+{
+ const char *ac_name; /* AccelClass name */
+ char *acc_name; /* AccelCPUClass name */
+ ObjectClass *acc; /* AccelCPUClass */
+
+ ac_name = object_class_get_name(OBJECT_CLASS(ac));
+ g_assert(ac_name != NULL);
+
+ acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
+ acc = object_class_by_name(acc_name);
+ g_free(acc_name);
+
+ if (acc) {
+ object_class_foreach(accel_init_cpu_int_aux,
+ CPU_RESOLVING_TYPE, false, acc);
+ }
+}
+
void accel_init_interfaces(AccelClass *ac)
{
#ifndef CONFIG_USER_ONLY
accel_init_ops_interfaces(ac);
#endif /* !CONFIG_USER_ONLY */
+
+ accel_init_cpu_interfaces(ac);
}
+static const TypeInfo accel_cpu_type = {
+ .name = TYPE_ACCEL_CPU,
+ .parent = TYPE_OBJECT,
+ .abstract = true,
+ .class_size = sizeof(AccelCPUClass),
+};
+
static void register_accel_types(void)
{
type_register_static(&accel_type);
+ type_register_static(&accel_cpu_type);
}
type_init(register_accel_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index 2e63561ad0..8d8b0bf966 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -440,6 +440,7 @@ R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
F: include/sysemu/accel-ops.h
+F: include/hw/core/accel-cpu.h
F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
--
2.25.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* Re: [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass
2021-02-05 22:56 ` [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass Richard Henderson
@ 2021-04-26 14:42 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-26 14:42 UTC (permalink / raw)
To: Claudio Fontana, Eduardo Habkost
Cc: peter.maydell, Richard Henderson, qemu-devel, Paolo Bonzini
Hi Claudio,
+Eduardo/Paolo
On 2/5/21 11:56 PM, Richard Henderson wrote:
> From: Claudio Fontana <cfontana@suse.de>
>
> add a new optional interface to CPUClass, which allows accelerators
> to extend the CPUClass with additional accelerator-specific
> initializations.
>
> This will allow to separate the target cpu code that is specific
> to each accelerator, and register it automatically with object
> hierarchy lookup depending on accelerator code availability,
> as part of the accel_init_interfaces() initialization step.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Message-Id: <20210204163931.7358-19-cfontana@suse.de>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/accel-cpu.h | 38 ++++++++++++++++++++++++++++++++
> include/hw/core/cpu.h | 4 ++++
> accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> 4 files changed, 87 insertions(+)
> create mode 100644 include/hw/core/accel-cpu.h
>
> diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
> new file mode 100644
> index 0000000000..24a6697412
> --- /dev/null
> +++ b/include/hw/core/accel-cpu.h
> @@ -0,0 +1,38 @@
> +/*
> + * Accelerator interface, specializes CPUClass
> + * This header is used only by target-specific code.
> + *
> + * Copyright 2021 SUSE LLC
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef ACCEL_CPU_H
> +#define ACCEL_CPU_H
> +
> +/*
> + * This header is used to define new accelerator-specific target-specific
> + * accelerator cpu subclasses.
> + * It uses CPU_RESOLVING_TYPE, so this is clearly target-specific.
> + *
> + * Do not try to use for any other purpose than the implementation of new
> + * subclasses in target/, or the accel implementation itself in accel/
> + */
> +
> +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
> +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
> +typedef struct AccelCPUClass AccelCPUClass;
> +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU)
> +
> +typedef struct AccelCPUClass {
> + /*< private >*/
> + ObjectClass parent_class;
> + /*< public >*/
> +
> + void (*cpu_class_init)(CPUClass *cc);
> + void (*cpu_instance_init)(CPUState *cpu);
> + void (*cpu_realizefn)(CPUState *cpu, Error **errp);
We could use a const pointer to const AccelCPUOps.
> +} AccelCPUClass;
> +
> +#endif /* ACCEL_CPU_H */
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 4f6c6b18c9..38d813c389 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -79,6 +79,9 @@ struct TranslationBlock;
> /* see tcg-cpu-ops.h */
> struct TCGCPUOps;
>
> +/* see accel-cpu.h */
> +struct AccelCPUClass;
> +
> /**
> * CPUClass:
> * @class_by_name: Callback to map -cpu command line model name to an
> @@ -187,6 +190,7 @@ struct CPUClass {
> /* Keep non-pointer data at the end to minimize holes. */
> int gdb_num_core_regs;
> bool gdb_stop_before_watchpoint;
> + struct AccelCPUClass *accel_cpu;
(so here AccelCPUOps)
>
> /* when TCG is not available, this pointer is NULL */
> struct TCGCPUOps *tcg_ops;
> diff --git a/accel/accel-common.c b/accel/accel-common.c
> index 6b59873419..9901b0531c 100644
> --- a/accel/accel-common.c
> +++ b/accel/accel-common.c
> @@ -26,6 +26,9 @@
> #include "qemu/osdep.h"
> #include "qemu/accel.h"
>
> +#include "cpu.h"
> +#include "hw/core/accel-cpu.h"
> +
> #ifndef CONFIG_USER_ONLY
> #include "accel-softmmu.h"
> #endif /* !CONFIG_USER_ONLY */
> @@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name)
> return ac;
> }
>
> +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque)
> +{
> + CPUClass *cc = CPU_CLASS(klass);
> + AccelCPUClass *accel_cpu = opaque;
> +
> + cc->accel_cpu = accel_cpu;
> + if (accel_cpu->cpu_class_init) {
> + accel_cpu->cpu_class_init(cc);
> + }
> +}
> +
> +/* initialize the arch-specific accel CpuClass interfaces */
> +static void accel_init_cpu_interfaces(AccelClass *ac)
> +{
> + const char *ac_name; /* AccelClass name */
> + char *acc_name; /* AccelCPUClass name */
> + ObjectClass *acc; /* AccelCPUClass */
> +
> + ac_name = object_class_get_name(OBJECT_CLASS(ac));
> + g_assert(ac_name != NULL);
> +
> + acc_name = g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE);
> + acc = object_class_by_name(acc_name);
> + g_free(acc_name);
> +
> + if (acc) {
> + object_class_foreach(accel_init_cpu_int_aux,
> + CPU_RESOLVING_TYPE, false, acc);
> + }
> +}
> +
> void accel_init_interfaces(AccelClass *ac)
> {
> #ifndef CONFIG_USER_ONLY
> accel_init_ops_interfaces(ac);
> #endif /* !CONFIG_USER_ONLY */
> +
> + accel_init_cpu_interfaces(ac);
> }
>
> +static const TypeInfo accel_cpu_type = {
> + .name = TYPE_ACCEL_CPU,
> + .parent = TYPE_OBJECT,
> + .abstract = true,
I'm not convince the abstract QOM parent has to be
per target. All methods in AccelCPUClass use pointers,
so we should be fine with opaque CPU* pointer declarations,
and have one common type for all targets.
> + .class_size = sizeof(AccelCPUClass),
> +};
> +
> static void register_accel_types(void)
> {
> type_register_static(&accel_type);
> + type_register_static(&accel_cpu_type);
> }
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PULL 00/46] tcg patch queue
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (45 preceding siblings ...)
2021-02-05 22:56 ` [PULL 46/46] accel: introduce AccelCPUClass extending CPUClass Richard Henderson
@ 2021-02-06 14:28 ` Peter Maydell
2021-02-06 19:14 ` Philippe Mathieu-Daudé
2021-02-06 19:38 ` Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue) Stefan Weil
47 siblings, 1 reply; 57+ messages in thread
From: Peter Maydell @ 2021-02-06 14:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Fri, 5 Feb 2021 at 22:56, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit d0dddab40e472ba62b5f43f11cc7dba085dabe71:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-02-05 15:27:02 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210205
>
> for you to fetch changes up to fb6916dd6ca8bb4b42d44baba9c67ecaf2279577:
>
> accel: introduce AccelCPUClass extending CPUClass (2021-02-05 10:24:15 -1000)
>
> ----------------------------------------------------------------
> TCGCPUOps cleanups (claudio)
> tcg/s390 compare fix (phil)
> tcg/aarch64 rotli_vec fix
> tcg/tci cleanups and fixes
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 00/46] tcg patch queue
2021-02-06 14:28 ` [PULL 00/46] tcg patch queue Peter Maydell
@ 2021-02-06 19:14 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-02-06 19:14 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson; +Cc: Helge Deller, QEMU Developers
On 2/6/21 3:28 PM, Peter Maydell wrote:
> On Fri, 5 Feb 2021 at 22:56, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> The following changes since commit d0dddab40e472ba62b5f43f11cc7dba085dabe71:
>>
>> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-02-05 15:27:02 +0000)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210205
>>
>> for you to fetch changes up to fb6916dd6ca8bb4b42d44baba9c67ecaf2279577:
>>
>> accel: introduce AccelCPUClass extending CPUClass (2021-02-05 10:24:15 -1000)
>>
>> ----------------------------------------------------------------
>> TCGCPUOps cleanups (claudio)
>> tcg/s390 compare fix (phil)
>> tcg/aarch64 rotli_vec fix
>> tcg/tci cleanups and fixes
>>
>> ----------------------------------------------------------------
>
>
> Applied, thanks.
>
> Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
> for any user-visible changes.
FYI I couldn't do incremental build on my TCI configured directory,
but it works again after blowing away the whole directories. Not a
big deal as there are mostly 3 TCI users and 1.5 testers.
[I had scheduled to test this series during the week-end, no time
during the week. Eventually I'd have reported that issue earlier]
^ permalink raw reply [flat|nested] 57+ messages in thread
* Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue)
2021-02-05 22:56 [PULL 00/46] tcg patch queue Richard Henderson
` (46 preceding siblings ...)
2021-02-06 14:28 ` [PULL 00/46] tcg patch queue Peter Maydell
@ 2021-02-06 19:38 ` Stefan Weil
2021-02-07 3:45 ` Richard Henderson
47 siblings, 1 reply; 57+ messages in thread
From: Stefan Weil @ 2021-02-06 19:38 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Am 05.02.21 um 23:56 schrieb Richard Henderson:
> The following changes since commit d0dddab40e472ba62b5f43f11cc7dba085dabe71:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-02-05 15:27:02 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210205
>
> for you to fetch changes up to fb6916dd6ca8bb4b42d44baba9c67ecaf2279577:
>
> accel: introduce AccelCPUClass extending CPUClass (2021-02-05 10:24:15 -1000)
>
> ----------------------------------------------------------------
> TCGCPUOps cleanups (claudio)
> tcg/s390 compare fix (phil)
> tcg/aarch64 rotli_vec fix
> tcg/tci cleanups and fixes
Hi Richard,
I tested pull-tcg-20210205 on a sparc64 machine.
Timing results for BIOS booting ("./qemu-system-x86_64", no image):
Before pull-tcg-20210205 with my latest patches for TCI:
TCG native: 8 s user time, TCG interpreter: 40 s user time
With pull-tcg-20210205 and
https://patchwork.kernel.org/project/qemu-devel/patch/20210127123446.2037721-1-sw@weilnetz.de/:
TCG native: 8 s user time, TCG interpreter: 50 s user time
So for this test case TCI was about 5 times slower than native TCG, but
the latest changes increased the execution time by about 25 %.
I am still searching what caused this detoriation. My first suspect was
thread local storage, but that wasn't it. Do you have any idea?
Stefan
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue)
2021-02-06 19:38 ` Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue) Stefan Weil
@ 2021-02-07 3:45 ` Richard Henderson
2021-02-07 10:50 ` Stefan Weil
0 siblings, 1 reply; 57+ messages in thread
From: Richard Henderson @ 2021-02-07 3:45 UTC (permalink / raw)
To: Stefan Weil, qemu-devel
On 2/6/21 11:38 AM, Stefan Weil wrote:
> I am still searching what caused this detoriation. My first suspect was thread
> local storage, but that wasn't it. Do you have any idea?
No, but since it's 1/3 of a complete patch set, I don't care to investigate the
intermediate result either.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue)
2021-02-07 3:45 ` Richard Henderson
@ 2021-02-07 10:50 ` Stefan Weil
2021-02-07 18:37 ` Richard Henderson
0 siblings, 1 reply; 57+ messages in thread
From: Stefan Weil @ 2021-02-07 10:50 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Am 07.02.21 um 04:45 schrieb Richard Henderson:
> On 2/6/21 11:38 AM, Stefan Weil wrote:
>> I am still searching what caused this detoriation. My first suspect was thread
>> local storage, but that wasn't it. Do you have any idea?
> No, but since it's 1/3 of a complete patch set, I don't care to investigate the
> intermediate result either.
Your latest code from the rth7680/tci-next branch is twice as fast as my
code with BIOS boot and qemu-x86_64 on sparc64. That's great.
With that code I don't get any BIOS output at all when running
qemu-i386. That's not so good.
Did I test the correct branch? If yes, I could try the same test on
amd64 and arm64 hosts.
Stefan
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue)
2021-02-07 10:50 ` Stefan Weil
@ 2021-02-07 18:37 ` Richard Henderson
2021-02-07 22:00 ` Stefan Weil
0 siblings, 1 reply; 57+ messages in thread
From: Richard Henderson @ 2021-02-07 18:37 UTC (permalink / raw)
To: Stefan Weil, qemu-devel
On 2/7/21 2:50 AM, Stefan Weil wrote:
> Your latest code from the rth7680/tci-next branch is twice as fast as my code
> with BIOS boot and qemu-x86_64 on sparc64. That's great.
>
> With that code I don't get any BIOS output at all when running qemu-i386.
> That's not so good.
>
> Did I test the correct branch? If yes, I could try the same test on amd64 and
> arm64 hosts.
Yes, tci-next is the correct branch. I've just rebased it against master,
which includes the first 30-odd patches.
What host do you not see bios output from qemu-system-i386 (I assume that's a
typo above)? I see correct output on x86_64, sparc64, ppc64le, and aarch64 hosts.
r~
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: Increased execution time with TCI in latest git master (was: Re: [PULL 00/46] tcg patch queue)
2021-02-07 18:37 ` Richard Henderson
@ 2021-02-07 22:00 ` Stefan Weil
0 siblings, 0 replies; 57+ messages in thread
From: Stefan Weil @ 2021-02-07 22:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 07.02.21 19:37, Richard Henderson wrote:
> On 2/7/21 2:50 AM, Stefan Weil wrote:
>> Your latest code from the rth7680/tci-next branch is twice as fast as my code
>> with BIOS boot and qemu-x86_64 on sparc64. That's great.
>>
>> With that code I don't get any BIOS output at all when running qemu-i386.
>> That's not so good.
>>
>> Did I test the correct branch? If yes, I could try the same test on amd64 and
>> arm64 hosts.
>
> Yes, tci-next is the correct branch. I've just rebased it against master,
> which includes the first 30-odd patches.
>
> What host do you not see bios output from qemu-system-i386 (I assume that's a
> typo above)? I see correct output on x86_64, sparc64, ppc64le, and aarch64 hosts.
Right, the TCI test was done with qemu-system-i386 of course.
I repeated the TCI test with qemu-system-i386 and qemu-system-x86_64 and
the rebased branch.
The system emulation for a BIOS boot works on Apple M1 arm64 with less
that 5 s user time (similar fast as before the latest TCI changes):
./qemu-system-i386 --nographic
4,28s user 0,03s system 37% cpu 11,398 total
./qemu-system-x86_64 --nographic
4,39s user 0,03s system 34% cpu 12,982 total
The same test shows similar timings on an AMD64 server:
./qemu-system-i386 --nographic
user 0m4,958s before tcg-next, 0m5,115s after tcg-next
./qemu-system-x86_64 --nographic
user 0m4,967s before tcg-next, 0m5,263s after tcg-next
Here tci-next is slightly slower than the old code.
The results on sparc64 did not change with the rebased tci-next:
qemu-system-i386 still fails to run, and qemu-system-x86_64 takes about
20 s user time.
Stefan
^ permalink raw reply [flat|nested] 57+ messages in thread