[U-Boot] [RFC PATCH v2 00/18] arm: socfpga: gen5: move to DM

[U-Boot] [RFC PATCH v2 00/18] arm: socfpga: gen5: move to DM

[Simon Goldschmidt]

This is an RFC series with the target to move SPL code from arch to
DM drivers.

It is not finished, but I send this here for discussion mainly about
the devicetree format with the goal of keeping the various sub-
architectures (cyclone5, arria10, etc.) in the same style.

Patch 8 adds a C tool to convert existing gen5 qts handoff files to a
handoff dtsi. As an example, the last patch contains the handoff dtsi
for socfpga_socrates.

I have sent v1 some time ago, but this one has heavily changed and is
not finished, thus v2 but RFC. This series also is not edited to fix
patman warnings, yet.

Changes in v2:
- add dts based reset handling (messed up in v1)
- split this patch from v1 5/6
- split this patch from v1 5/6

Simon Goldschmidt (18):
  ddr: socfpga: gen5: constify altera_gen5_sdram_ops
  dts: arm: socfpga: add label for clkmgr
  arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN
  timer: dw-apb: add reset handling
  arm: socfpga: gen5: move initial reset handling to reset driver
  arm: dts: socfpga: add settings for gen5 clk driver
  arm: dts: socfpga: make clock nodes available in SPL
  socfpga: gen5: add new tool to create handoff dtsi files
  sdram: socfpga: gen5: make config structs dts compatible
  ddr: socfpga: gen5: fetch handoff information from 'of_to_platdata'
  ddr: socfpga: gen5: read handoff information from devicetree
  arm: socfpga: gen5: add readonly clk driver
  arm: socfpga: gen5: enable DM CLK
  arm: socfpga: gen5: move clock initialization to CLK driver
  arm: socfpga: gen5: load CLK config from devicetree
  spi: cadence_qspi: support DM_CLK
  arm: socfpga: gen5: parse qspi clock from devictree
  socfpga: gen5: move CLK and SDRAM to DM

 MAINTAINERS                                   |   1 +
 arch/arm/dts/socfpga-common-u-boot.dtsi       |  71 ++
 arch/arm/dts/socfpga.dtsi                     |   7 +-
 .../dts/socfpga_cyclone5_socrates-u-boot.dtsi |   1 +
 .../socfpga_cyclone5_socrates_handoff.dtsi    | 290 +++++++
 arch/arm/mach-socfpga/Kconfig                 |   4 +-
 arch/arm/mach-socfpga/Makefile                |   5 -
 arch/arm/mach-socfpga/clock_manager.c         |  31 +-
 arch/arm/mach-socfpga/clock_manager_gen5.c    | 528 -------------
 arch/arm/mach-socfpga/create_handoff_gen5.c   | 660 ++++++++++++++++
 arch/arm/mach-socfpga/freeze_controller.c     |  10 +-
 .../mach-socfpga/include/mach/clock_manager.h |   2 +
 .../include/mach/clock_manager_gen5.h         |  14 -
 .../mach-socfpga/include/mach/sdram_gen5.h    |  16 +-
 arch/arm/mach-socfpga/qts-to-handoff.sh       |  83 +++
 arch/arm/mach-socfpga/reset_manager_gen5.c    |  13 -
 arch/arm/mach-socfpga/spl_gen5.c              |  29 +-
 arch/arm/mach-socfpga/wrap_pll_config.c       | 146 ----
 arch/arm/mach-socfpga/wrap_sdram_config.c     | 318 --------
 drivers/clk/altera/Makefile                   |   1 +
 drivers/clk/altera/clk-gen5.c                 | 705 ++++++++++++++++++
 drivers/ddr/altera/sdram_gen5.c               |  92 ++-
 drivers/ddr/altera/sequencer.c                |  74 +-
 drivers/ddr/altera/sequencer.h                |   9 +-
 drivers/reset/reset-socfpga.c                 |  37 +-
 drivers/spi/cadence_qspi.c                    |  20 +-
 drivers/timer/dw-apb-timer.c                  |  18 +-
 include/configs/socfpga_common.h              |   5 -
 28 files changed, 2072 insertions(+), 1118 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
 delete mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c
 create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
 create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
 delete mode 100644 arch/arm/mach-socfpga/wrap_pll_config.c
 delete mode 100644 arch/arm/mach-socfpga/wrap_sdram_config.c
 create mode 100644 drivers/clk/altera/clk-gen5.c

-- 
2.20.1

[U-Boot] [RFC PATCH v2 01/18] ddr: socfpga: gen5: constify altera_gen5_sdram_ops

[Simon Goldschmidt]

Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/ddr/altera/sdram_gen5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index fcd89b619d..8c8ea19eb9 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -626,7 +626,7 @@ static int altera_gen5_sdram_get_info(struct udevice *dev,
 	return 0;
 }
 
-static struct ram_ops altera_gen5_sdram_ops = {
+static const struct ram_ops altera_gen5_sdram_ops = {
 	.get_info = altera_gen5_sdram_get_info,
 };
 
-- 
2.20.1

[U-Boot] [RFC PATCH v2 02/18] dts: arm: socfpga: add label for clkmgr

[Simon Goldschmidt]

In preparation for moving socfpga gen5 clock handoff data to devicetree,
add a label to the base devicetree so that dts files including this base
tree can reference clkmgr by label.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 arch/arm/dts/socfpga.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 51a6a51b53..eda558f2fe 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -114,7 +114,7 @@
 			status = "disabled";
 		};
 
-		clkmgr at ffd04000 {
+		clkmgr: clkmgr at ffd04000 {
 				compatible = "altr,clk-mgr";
 				reg = <0xffd04000 0x1000>;
 
-- 
2.20.1

[U-Boot] [RFC PATCH v2 03/18] arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN

[Simon Goldschmidt]

In preparation to adding more DM based drivers, increase the SPL
pre-relocation heap just enough to allow those new drivers to run.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 arch/arm/mach-socfpga/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 1d914648e3..9efdcd6f10 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -13,7 +13,7 @@ config SPL_STACK_R_ADDR
 	default 0x00800000 if TARGET_SOCFPGA_GEN5
 
 config SPL_SYS_MALLOC_F_LEN
-	default 0x800 if TARGET_SOCFPGA_GEN5
+	default 0x1100 if TARGET_SOCFPGA_GEN5
 
 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
 	default 0xa2
-- 
2.20.1

[U-Boot] [RFC PATCH v2 04/18] timer: dw-apb: add reset handling

[Simon Goldschmidt]

To use this timer on socfpga as system tick, it needs to take itself out
of reset.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/timer/dw-apb-timer.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 86312b8dc7..fad22be8c9 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <clk.h>
+#include <reset.h>
 #include <timer.h>
 
 #include <asm/io.h>
@@ -18,7 +19,8 @@
 #define DW_APB_CTRL		0x8
 
 struct dw_apb_timer_priv {
-	fdt_addr_t	regs;
+	fdt_addr_t regs;
+	struct reset_ctl_bulk resets;
 };
 
 static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
@@ -42,6 +44,12 @@ static int dw_apb_timer_probe(struct udevice *dev)
 	struct clk clk;
 	int ret;
 
+	ret = reset_get_bulk(dev, &priv->resets);
+	if (ret)
+		dev_warn(dev, "Can't get reset: %d\n", ret);
+	else
+		reset_deassert_bulk(&priv->resets);
+
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret)
 		return ret;
@@ -67,6 +75,13 @@ static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev)
 	return 0;
 }
 
+static int dw_apb_timer_remove(struct udevice *dev)
+{
+	struct dw_apb_timer_priv *priv = dev_get_priv(dev);
+
+	return reset_release_bulk(&priv->resets);
+}
+
 static const struct timer_ops dw_apb_timer_ops = {
 	.get_count	= dw_apb_timer_get_count,
 };
@@ -83,5 +98,6 @@ U_BOOT_DRIVER(dw_apb_timer) = {
 	.probe		= dw_apb_timer_probe,
 	.of_match	= dw_apb_timer_ids,
 	.ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata,
+	.remove		= dw_apb_timer_remove,
 	.priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv),
 };
-- 
2.20.1

[U-Boot] [RFC PATCH v2 05/18] arm: socfpga: gen5: move initial reset handling to reset driver

[Simon Goldschmidt]

This moves disabling all peripherals from ad-hoc code in arch/arm
to the socfpga reset driver.

To do this, DM initialization and UCLASS_RESET probing has to be done
earlier in the SPL. Also, the gen5 devicetrees need an added property
that tells the reset driver which bits to set and which need to be
left at 0 (L4WD0).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2:
- add dts based reset handling (messed up in v1)

 arch/arm/dts/socfpga-common-u-boot.dtsi    |  1 +
 arch/arm/mach-socfpga/reset_manager_gen5.c | 13 --------
 arch/arm/mach-socfpga/spl_gen5.c           | 21 ++++++------
 drivers/reset/reset-socfpga.c              | 37 ++++++++++++++++++++--
 4 files changed, 45 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index 322c858c4b..aebe476e3f 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -12,6 +12,7 @@
 
 &rst {
 	u-boot,dm-pre-reloc;
+	altr,modrst-reset-val = <1 0xffffffbf 0xffffffff>;
 };
 
 &sdr {
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 9a32f5abfe..34e59b852b 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -48,19 +48,6 @@ void socfpga_per_reset(u32 reset, int set)
 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
-/*
- * Assert reset on every peripheral but L4WD0.
- * Watchdog must be kept intact to prevent glitches
- * and/or hangs.
- */
-void socfpga_per_reset_all(void)
-{
-	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
-
-	writel(~l4wd0, &reset_manager_base->per_mod_reset);
-	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
-}
-
 #define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
 #define L3REGS_REMAP_HPS2FPGA_MASK	0x08
 #define L3REGS_REMAP_OCRAM_MASK		0x01
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 87b76b47de..1ae8025746 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -84,12 +84,19 @@ void board_init_f(ulong dummy)
 	socfpga_sdram_remap_zero();
 	socfpga_pl310_clear();
 
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
-	/* Put everything into reset but L4WD0. */
-	socfpga_per_reset_all();
+	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
+	if (ret)
+		debug("Reset init failed: %d\n", ret);
 
 	if (!socfpga_is_booting_from_fpga()) {
 		/* Put FPGA bridges into reset too. */
@@ -130,16 +137,6 @@ void board_init_f(ulong dummy)
 	debug_uart_init();
 #endif
 
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
-	if (ret)
-		debug("Reset init failed: %d\n", ret);
-
 	/* enable console uart printing */
 	preloader_console_init();
 
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 93ec9cfdb6..c5fd0679c7 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -106,6 +106,39 @@ static const struct reset_ops socfpga_reset_ops = {
 	.rst_deassert = socfpga_reset_deassert,
 };
 
+/*
+ * This function ensures that in SPL, all peripherals are reset at startup.
+ * It does this by reading reset values from the device tree.
+ */
+static int socfpga_reset_set_inital_reset_values(struct udevice *dev)
+{
+#ifdef CONFIG_SPL_BUILD
+	struct socfpga_reset_data *data = dev_get_priv(dev);
+	int ret;
+	u32 modrst_vals[5];
+	size_t i, sz, offset;
+
+	ret = dev_read_size(dev, "altr,modrst-reset-val");
+	if (ret >= sizeof(u32)) {
+		sz = min(ret/sizeof(u32), ARRAY_SIZE(modrst_vals));
+		ret = dev_read_u32_array(dev, "altr,modrst-reset-val",
+					 modrst_vals, sz);
+		if (ret) {
+			dev_warn(dev, "Failed to read modrst reset values\n");
+			return ret;
+		}
+		/* first item is register offset to start */
+		offset = modrst_vals[0] * 4;
+		for (i = 1; i < sz; i++) {
+			writel(modrst_vals[i], data->modrst_base + offset);
+			offset += 4;
+		}
+	}
+#endif
+
+	return 0;
+}
+
 static int socfpga_reset_probe(struct udevice *dev)
 {
 	struct socfpga_reset_data *data = dev_get_priv(dev);
@@ -117,7 +150,7 @@ static int socfpga_reset_probe(struct udevice *dev)
 	modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
 	data->modrst_base = membase + modrst_offset;
 
-	return 0;
+	return socfpga_reset_set_inital_reset_values(dev);
 }
 
 static int socfpga_reset_remove(struct udevice *dev)
@@ -163,5 +196,5 @@ U_BOOT_DRIVER(socfpga_reset) = {
 	.priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
 	.ops = &socfpga_reset_ops,
 	.remove = socfpga_reset_remove,
-	.flags	= DM_FLAG_OS_PREPARE,
+	.flags	= DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
 };
-- 
2.20.1

[U-Boot] [RFC PATCH v2 06/18] arm: dts: socfpga: add settings for gen5 clk driver

[Simon Goldschmidt]

For some clocks, the socfpga gen5 clock driver in preparation needs a
source register, which is used to select the parent clock.

Add these to the socfpga gen5 base device tree.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2:
- split this patch from v1 5/6

 arch/arm/dts/socfpga.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index eda558f2fe..8ff3f211cb 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -332,6 +332,7 @@
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&mainclk>, <&per_base_clk>;
 						div-reg = <0x64 4 3>;
+						src-reg = <0x70 0 1>;
 						clk-gate = <0x60 2>;
 					};
 
@@ -340,6 +341,7 @@
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&mainclk>, <&per_base_clk>;
 						div-reg = <0x64 7 3>;
+						src-reg = <0x70 1 1>;
 						clk-gate = <0x60 3>;
 					};
 
@@ -453,6 +455,7 @@
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						src-reg = <0xac 0 2>;
 						clk-gate = <0xa0 8>;
 						clk-phase = <0 135>;
 					};
@@ -469,6 +472,7 @@
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+						src-reg = <0xac 2 2>;
 						clk-gate = <0xa0 9>;
 					};
 
@@ -491,6 +495,7 @@
 						#clock-cells = <0>;
 						compatible = "altr,socfpga-gate-clk";
 						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+						src-reg = <0xac 4 2>;
 						clk-gate = <0xa0 11>;
 					};
 
-- 
2.20.1

[U-Boot] [RFC PATCH v2 07/18] arm: dts: socfpga: make clock nodes available in SPL

[Simon Goldschmidt]

The socfpga gen5 clock driver will need some of the clock nodes to be
preserved in the SPL devicetree. Mark them appropriately.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2:
- split this patch from v1 5/6

 arch/arm/dts/socfpga-common-u-boot.dtsi | 70 +++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index aebe476e3f..7bc3b0021f 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -7,6 +7,12 @@
 /{
 	soc {
 		u-boot,dm-pre-reloc;
+		clkmgr at ffd04000 {
+			u-boot,dm-pre-reloc;
+			clocks {
+				u-boot,dm-pre-reloc;
+			};
+		};
 	};
 };
 
@@ -18,3 +24,67 @@
 &sdr {
 	u-boot,dm-pre-reloc;
 };
+
+&osc1 {
+	u-boot,dm-pre-reloc;
+};
+
+&osc2 {
+	u-boot,dm-pre-reloc;
+};
+
+&f2s_periph_ref_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_pll {
+	u-boot,dm-pre-reloc;
+};
+
+&mainclk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_qspi_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&main_nand_sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&periph_pll {
+	u-boot,dm-pre-reloc;
+};
+
+&per_qspi_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&per_nand_mmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&per_base_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_mp_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk_divided {
+	u-boot,dm-pre-reloc;
+};
+
+&qspi_clk {
+	u-boot,dm-pre-reloc;
+};
-- 
2.20.1

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Simon Goldschmidt]

This new tool converts handoff information from quartus to "*_handoff.dtsi"
devicetree files. This is in preparation to move from ad-hoc code in arch
that parses the 'qts' header files to drivers parsing the same information
from devicetree.

Converting existing U-Boot 'qts' files is also supported.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
 arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++
 2 files changed, 743 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
 create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh

diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-socfpga/create_handoff_gen5.c
new file mode 100644
index 0000000000..6ec436719d
--- /dev/null
+++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
@@ -0,0 +1,660 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a host-tool that needs to be compiled per board and prints the
+ * handoff.dtsi to stdout.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+
+/* Define kernel types */
+typedef uint8_t u8;
+typedef uint32_t u32;
+
+#ifdef USE_QUARTUS_OUTPUT
+#ifdef ARRIA5
+#include "iocsr_config_arria5.c"
+#include "pinmux_config_arria5.c"
+#else
+#include "iocsr_config_cyclone5.c"
+#include "pinmux_config_cyclone5.c"
+#endif
+#include "pll_config.h"
+#include "sdram/sdram_config.h"
+#include "sequencer_auto.h"
+#include "sequencer_defines.h"
+#include "sequencer_auto_ac_init.c"
+#include "sequencer_auto_inst_init.c"
+#define RW_MGR(x) __RW_MGR_##x
+#else
+#define RW_MGR(x) RW_MGR_##x
+#include <iocsr_config.h>
+#include <pinmux_config.h>
+#include <pll_config.h>
+#include <sdram_config.h>
+#endif
+
+#include "include/mach/clock_manager_gen5.h"
+#include "include/mach/sdram_gen5.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
+#endif
+
+const char handoff_dtsi_hdr[] =
+	"// SPDX-License-Identifier: GPL-2.0\n"
+	"/*\n"
+	" *<auto-generated>\n"
+	" *	This code was generated by a tool based on\n"
+	" *	handoffs from both Qsys and Quartus.\n"
+	" *\n"
+	" *	Changes to this file may be lost if\n"
+	" *	the code is regenerated.\n"
+	" *</auto-generated>\n"
+	" */\n";
+
+/* Wrap PLL config */
+
+#define MAIN_VCO_BASE (					\
+	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
+		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define PERI_VCO_BASE (					\
+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
+		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
+		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define SDR_VCO_BASE (					\
+	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
+		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
+		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+static const struct cm_config cm_default = {
+	/* main group */
+	MAIN_VCO_BASE,
+	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
+
+	/* peripheral group */
+	PERI_VCO_BASE,
+	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
+
+	/* sdram pll group */
+	SDR_VCO_BASE,
+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+
+	/* altera group */
+	CONFIG_HPS_ALTERAGRP_MPUCLK,
+};
+
+/* Wrap SDRAM config */
+static const struct socfpga_sdram_config sdram_config = {
+	.ctrl_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
+	.dram_timing1 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
+	.dram_timing2 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
+	.dram_timing3 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
+	.dram_timing4 =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
+	.lowpwr_timing =
+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
+	.dram_odt =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+	.extratime1 =
+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
+(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
+	.dram_addrw =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
+		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
+	.dram_if_width =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
+	.dram_dev_width =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
+	.dram_intr =
+		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
+	.lowpwr_eq =
+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
+	.static_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
+	.ctrl_width =
+		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
+	.cport_width =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
+	.cport_wmap =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
+	.cport_rmap =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
+	.rfifo_cmap =
+		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
+	.wfifo_cmap =
+		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
+	.cport_rdwr =
+		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
+	.port_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
+	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+	.fifo_cfg =
+		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
+		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
+	.mp_priority =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
+	.mp_weight0 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
+	.mp_weight1 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
+	.mp_weight2 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
+	.mp_weight3 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
+	.mp_pacing0 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
+	.mp_pacing1 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
+	.mp_pacing2 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
+	.mp_pacing3 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
+	.mp_threshold0 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
+	.mp_threshold1 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
+	.mp_threshold2 =
+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
+	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+};
+
+static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
+	.activate_0_and_1		= RW_MGR(ACTIVATE_0_AND_1),
+	.activate_0_and_1_wait1		= RW_MGR(ACTIVATE_0_AND_1_WAIT1),
+	.activate_0_and_1_wait2		= RW_MGR(ACTIVATE_0_AND_1_WAIT2),
+	.activate_1			= RW_MGR(ACTIVATE_1),
+	.clear_dqs_enable		= RW_MGR(CLEAR_DQS_ENABLE),
+	.guaranteed_read		= RW_MGR(GUARANTEED_READ),
+	.guaranteed_read_cont		= RW_MGR(GUARANTEED_READ_CONT),
+	.guaranteed_write		= RW_MGR(GUARANTEED_WRITE),
+	.guaranteed_write_wait0		= RW_MGR(GUARANTEED_WRITE_WAIT0),
+	.guaranteed_write_wait1		= RW_MGR(GUARANTEED_WRITE_WAIT1),
+	.guaranteed_write_wait2		= RW_MGR(GUARANTEED_WRITE_WAIT2),
+	.guaranteed_write_wait3		= RW_MGR(GUARANTEED_WRITE_WAIT3),
+	.idle				= RW_MGR(IDLE),
+	.idle_loop1			= RW_MGR(IDLE_LOOP1),
+	.idle_loop2			= RW_MGR(IDLE_LOOP2),
+	.init_reset_0_cke_0		= RW_MGR(INIT_RESET_0_CKE_0),
+	.init_reset_1_cke_0		= RW_MGR(INIT_RESET_1_CKE_0),
+	.lfsr_wr_rd_bank_0		= RW_MGR(LFSR_WR_RD_BANK_0),
+	.lfsr_wr_rd_bank_0_data		= RW_MGR(LFSR_WR_RD_BANK_0_DATA),
+	.lfsr_wr_rd_bank_0_dqs		= RW_MGR(LFSR_WR_RD_BANK_0_DQS),
+	.lfsr_wr_rd_bank_0_nop		= RW_MGR(LFSR_WR_RD_BANK_0_NOP),
+	.lfsr_wr_rd_bank_0_wait		= RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
+	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
+	.lfsr_wr_rd_dm_bank_0		= RW_MGR(LFSR_WR_RD_DM_BANK_0),
+	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
+	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
+	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
+	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
+	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
+	.mrs0_dll_reset			= RW_MGR(MRS0_DLL_RESET),
+	.mrs0_dll_reset_mirr		= RW_MGR(MRS0_DLL_RESET_MIRR),
+	.mrs0_user			= RW_MGR(MRS0_USER),
+	.mrs0_user_mirr			= RW_MGR(MRS0_USER_MIRR),
+	.mrs1				= RW_MGR(MRS1),
+	.mrs1_mirr			= RW_MGR(MRS1_MIRR),
+	.mrs2				= RW_MGR(MRS2),
+	.mrs2_mirr			= RW_MGR(MRS2_MIRR),
+	.mrs3				= RW_MGR(MRS3),
+	.mrs3_mirr			= RW_MGR(MRS3_MIRR),
+	.precharge_all			= RW_MGR(PRECHARGE_ALL),
+	.read_b2b			= RW_MGR(READ_B2B),
+	.read_b2b_wait1			= RW_MGR(READ_B2B_WAIT1),
+	.read_b2b_wait2			= RW_MGR(READ_B2B_WAIT2),
+	.refresh_all			= RW_MGR(REFRESH_ALL),
+	.rreturn			= RW_MGR(RETURN),
+	.sgle_read			= RW_MGR(SGLE_READ),
+	.zqcl				= RW_MGR(ZQCL),
+
+	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
+	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
+	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
+	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
+	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
+	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
+	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
+	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
+	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
+	.mem_virtual_groups_per_read_dqs =
+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
+	.mem_virtual_groups_per_write_dqs =
+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
+};
+
+static const struct socfpga_sdram_io_config io_config = {
+	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
+	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
+	.delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,
+	.delay_per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
+	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
+	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
+	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
+	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
+	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
+	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
+	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
+	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
+	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
+	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
+	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
+	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
+};
+
+static const struct socfpga_sdram_misc_config misc_config = {
+	.afi_rate_ratio			= AFI_RATE_RATIO,
+	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
+	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
+	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
+	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
+	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
+	.reg_file_init_seq_signature_ll	= REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
+	.reg_file_init_seq_signature_lh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
+	.reg_file_init_seq_signature_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
+	.reg_file_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
+	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
+	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
+	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
+	.treset_cntr0_val		= TRESET_CNTR0_VAL,
+	.treset_cntr1_val		= TRESET_CNTR1_VAL,
+	.treset_cntr2_val		= TRESET_CNTR2_VAL,
+};
+
+static void print_hdr(void)
+{
+	printf(handoff_dtsi_hdr);
+}
+
+static void print_clkmgr_base(void)
+{
+	const char handoff_dtsi_clkmgr_base[] =
+		"\n"
+		"&osc1 {\n"
+		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
+		"};\n"
+		"\n"
+		"&osc2 {\n"
+		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
+		"};\n"
+		"\n"
+		"&f2s_periph_ref_clk {\n"
+		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
+		"};\n"
+		"\n"
+		"&f2s_sdram_ref_clk {\n"
+		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
+		"};\n";
+
+	printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
+	       CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
+	       CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
+}
+
+/*
+ * dtc stores u32 array big endian but we load them raw and expect them to be in
+ * little endian format. To prevent this tool to depend on host endianess, do
+ * the switch manually, not via 'htonl'.
+ */
+static u32 swap_bytes(u32 val)
+{
+	return (val << 24) | ((val & 0xFF00ul) << 8) |
+		((val & 0xFF0000ul) >> 8) | (val >> 24);
+}
+
+static void print_array_ulong(const unsigned long *arr, size_t arr_size,
+			      size_t el_per_line, const char *indent1,
+			      const char *name, const char *indent_next)
+{
+	size_t i;
+
+	printf("%s%s = <", indent1, name);
+	for (i = 0; i < arr_size; i++) {
+		printf("0x%08x", swap_bytes((u32)arr[i]));
+		if (i + 1 < arr_size) {
+			if (i % el_per_line == (el_per_line - 1)) {
+				printf("\n%s", indent_next);
+			} else {
+				printf(" ");
+			}
+		}
+	}
+	printf(">;\n");
+}
+
+#ifdef USE_QUARTUS_OUTPUT
+static void print_array_sysmgrinit(const unsigned long *arr, size_t arr_size,
+				   const char *indent1, const char *name,
+				   const char *indent_next)
+{
+	size_t i;
+
+	printf("%s%s = [", indent1, name);
+	for (i = 0; i < arr_size; i++) {
+		printf("%02x", (u8)arr[i]);
+		if (i + 1 < arr_size) {
+			if (i % 8 == 7) {
+				printf("\n%s", indent_next);
+			} else {
+				printf(" ");
+			}
+		}
+	}
+	printf("];\n");
+}
+#define print_array_alt_u32 print_array_ulong
+#else
+#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz, 8, ind1, n, ind2)
+#define print_array_alt_u32 print_array_u32
+#endif
+
+static void print_array_u32(const u32 *arr, size_t arr_size,
+			    size_t el_per_line, const char *indent1,
+			    const char *name, const char *indent_next)
+{
+	size_t i;
+
+	printf("%s%s = <", indent1, name);
+	for (i = 0; i < arr_size; i++) {
+		printf("0x%08x", swap_bytes(arr[i]));
+		if (i + 1 < arr_size) {
+			if (i % el_per_line == (el_per_line - 1)) {
+				printf("\n%s", indent_next);
+			} else {
+				printf(" ");
+			}
+		}
+	}
+	printf(">;\n");
+}
+
+static void print_array_u8(const u8 *arr, size_t arr_size, size_t el_per_line,
+			   const char *indent1, const char *name,
+			   const char *indent_next)
+{
+	size_t i;
+
+	printf("%s%s = [", indent1, name);
+	for (i = 0; i < arr_size; i++) {
+		printf("%02x", arr[i]);
+		if (i + 1 < arr_size) {
+			if (i % el_per_line == (el_per_line - 1)) {
+				printf("\n%s", indent_next);
+			} else {
+				printf(" ");
+			}
+		}
+	}
+	printf("];\n");
+}
+
+
+static void print_clkmgr_cfg(void)
+{
+	const char handoff_dtsi_clkmgr_cfg_a[] =
+		"\n"
+		"&clkmgr {\n";
+	const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
+	const char clk_mgr_cfg_indent[] = "\t\t\t    ";
+
+	printf(handoff_dtsi_clkmgr_cfg_a);
+	print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
+			"altr,clk-mgr-cfg", clk_mgr_cfg_indent);
+	printf(handoff_dtsi_clkmgr_cfg_b);
+}
+
+static void print_sysmgr(void)
+{
+	const char handoff_dtsi_sysmgr_begin[] =
+		"\n"
+		"&sysmgr {\n";
+	const char handoff_dtsi_sysmgr_end[] = "};\n";
+	const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
+	size_t i;
+
+	printf(handoff_dtsi_sysmgr_begin);
+
+	/* sys_mgr_init_table is an u8 table */
+	print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
+			       "\t", "altr,pinmux-cfg","\t\t\t   ");
+	/* ioscr scan chain table 0 */
+	print_array_ulong(iocsr_scan_chain0_table,
+			  ARRAY_SIZE(iocsr_scan_chain0_table), 4,
+			  "\t", "altr,iocsr-scan-chain0-table",
+			  sysmgr_cfg_indent);
+	/* ioscr scan chain table 0 */
+	print_array_ulong(iocsr_scan_chain1_table,
+			  ARRAY_SIZE(iocsr_scan_chain1_table), 4,
+			  "\t", "altr,iocsr-scan-chain1-table",
+			  sysmgr_cfg_indent);
+	/* ioscr scan chain table 0 */
+	print_array_ulong(iocsr_scan_chain2_table,
+			  ARRAY_SIZE(iocsr_scan_chain2_table), 4,
+			  "\t", "altr,iocsr-scan-chain2-table",
+			  sysmgr_cfg_indent);
+	/* ioscr scan chain table 0 */
+	print_array_ulong(iocsr_scan_chain3_table,
+			  ARRAY_SIZE(iocsr_scan_chain3_table), 4,
+			  "\t", "altr,iocsr-scan-chain3-table",
+			  sysmgr_cfg_indent);
+	printf(handoff_dtsi_sysmgr_end);
+}
+
+static void print_sdram_cfg(void)
+{
+	const char handoff_dtsi_sdram_cfg_begin[] =
+		"\n"
+		"&sdr {\n";
+	const char handoff_dtsi_sdram_cfg_end[] = "};\n";
+
+	printf(handoff_dtsi_sdram_cfg_begin);
+	print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
+			"\t", "altr,sdr-cfg", "\t\t\t");
+	print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
+			"\t", "altr,sdr-rw-mgr-cfg", "\t\t\t       ");
+	print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
+			"\t", "altr,sdr-io-cfg", "\t\t\t   ");
+	print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
+			"\t", "altr,sdr-misc-cfg", "\t\t\t     ");
+	print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
+			"\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
+	print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
+			"\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");
+	printf(handoff_dtsi_sdram_cfg_end);
+}
+
+int main(void)
+{
+	print_hdr();
+	print_clkmgr_base();
+	print_clkmgr_cfg();
+	print_sysmgr();
+	print_sdram_cfg();
+}
diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-to-handoff.sh
new file mode 100755
index 0000000000..b9032a5411
--- /dev/null
+++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
@@ -0,0 +1,83 @@
+#!/bin/sh
+# This script converts Quartus handoff files (in Quartus or U-Boot format)
+# to a handoff.dtsi file.
+
+
+usage() {
+	MY_BASENAME=`basename $0`
+	echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir] [output_file]"
+	echo " or"
+	echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
+	echo ""
+	echo "Process QTS-generated headers into handoff.dtsi:"
+	echo ""
+	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
+	echo "  input_qts_dir - Directory with compiled Quartus project"
+	echo "                  and containing the Quartus project file (QPF)."
+	echo "  input_bsp_dir - Directory with generated bsp containing"
+	echo "                  the settings.bsp file."
+	echo "  output_file   - Full filename to store the handoff dtsi file."
+	echo "  uboot_qts_dir - board/qts directory if input files are in"
+	echo "                  'old-style' U-Boot format."
+	echo ""
+}
+
+soc="$1"
+
+HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
+
+case "$soc" in
+"cyclone5"|"arria5")
+	if [ "$#" -ne 4 ] ; then
+		usage
+		exit 1
+	fi
+	in_qts_dir="$2"
+	in_bsp_dir="$3"
+	output_file="$4"
+	out_dir=`dirname ${output_file}`
+
+	if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
+		! -d "${out_dir}" -o -z "${soc}" ] ; then
+		usage
+		exit 3
+	fi
+
+	if [ "$soc" = "cyclone5" ] ; then
+		CMDLINE_DEFINES="-DCYCLONE5"
+	else
+		CMDLINE_DEFINES="-DARRIA5"
+	fi
+	CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"
+	for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
+		CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
+	done
+	;;
+"u-boot")
+	if [ "$#" -ne 3 ] ; then
+		usage
+		exit 1
+	fi
+	in_qts_dir="$2"
+	output_file="$3"
+	out_dir=`dirname ${output_file}`
+
+	if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
+		usage
+		exit 3
+	fi
+
+	CMDLINE_DEFINES="-I${in_qts_dir}"
+	;;
+*)
+	usage
+	exit 1
+	;;
+esac
+
+# compile
+gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o ${out_dir}/create_handoff_gen5
+${out_dir}/create_handoff_gen5 > ${output_file}
+
+# TODO: remove tmp file:
+#rm $${out_dir}/create_handoff_gen5
-- 
2.20.1

[U-Boot] [RFC PATCH v2 09/18] sdram: socfpga: gen5: make config structs dts compatible

[Simon Goldschmidt]

In preparation of moving SDRAM config from 'qts' files to devicetree,
make the config structs compatible to devicetree by keeping all struct
members of the same type (u8 or u32). That way, these structs can be
stored to devicetree as simple array.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 .../mach-socfpga/include/mach/sdram_gen5.h    |  8 +++-
 arch/arm/mach-socfpga/wrap_sdram_config.c     |  8 +++-
 drivers/ddr/altera/sequencer.c                | 39 +++++++++++--------
 3 files changed, 35 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index c41208591a..7353b1c5e6 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -180,7 +180,8 @@ struct socfpga_sdram_rw_mgr_config {
 };
 
 struct socfpga_sdram_io_config {
-	u16	delay_per_opa_tap;
+	u8	delay_per_opa_tap_lo;
+	u8	delay_per_opa_tap_hi;
 	u8	delay_per_dchain_tap;
 	u8	delay_per_dqs_en_dchain_tap;
 	u8	dll_chain_length;
@@ -198,7 +199,10 @@ struct socfpga_sdram_io_config {
 };
 
 struct socfpga_sdram_misc_config {
-	u32	reg_file_init_seq_signature;
+	u8	reg_file_init_seq_signature_ll;
+	u8	reg_file_init_seq_signature_lh;
+	u8	reg_file_init_seq_signature_hl;
+	u8	reg_file_init_seq_signature_hh;
 	u8	afi_rate_ratio;
 	u8	calib_lfifo_offset;
 	u8	calib_vfifo_offset;
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 2b072cc65e..c43c2423a0 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -254,7 +254,8 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
 static const struct socfpga_sdram_io_config io_config = {
 	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
 	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
-	.delay_per_opa_tap		= IO_DELAY_PER_OPA_TAP,
+	.delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,
+	.delay_per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
 	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
 	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
 	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
@@ -276,7 +277,10 @@ static const struct socfpga_sdram_misc_config misc_config = {
 	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
 	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
 	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
-	.reg_file_init_seq_signature	= REG_FILE_INIT_SEQ_SIGNATURE,
+	.reg_file_init_seq_signature_ll	= REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
+	.reg_file_init_seq_signature_lh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
+	.reg_file_init_seq_signature_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
+	.reg_file_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
 	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
 	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
 	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b85b56efe5..6c632227c2 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -30,6 +30,9 @@ static const struct socfpga_data_mgr *data_mgr =
 static const struct socfpga_sdr_ctrl *sdr_ctrl =
 	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
+#define delay_per_opa_tap(iocfg) ((iocfg)->delay_per_opa_tap_lo | \
+				  ((iocfg)->delay_per_opa_tap_hi << 8))
+
 #define DELTA_D		1
 
 /*
@@ -1623,7 +1626,7 @@ static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
 			*p = 0;
 
 		ret = sdr_find_phase_delay(seq, working, 0, grp, work,
-					   seq->iocfg->delay_per_opa_tap, p);
+					   delay_per_opa_tap(seq->iocfg), p);
 		if (!ret)
 			return 0;
 
@@ -1651,7 +1654,7 @@ static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
 static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp,
 			     u32 *work_bgn, u32 *d, u32 *p, u32 *i)
 {
-	const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
+	const u32 dtaps_per_ptap = delay_per_opa_tap(seq->iocfg) /
 				   seq->iocfg->delay_per_dqs_en_dchain_tap;
 	int ret;
 
@@ -1693,7 +1696,7 @@ static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp,
 	} else {
 		(*p)--;
 	}
-	tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap;
+	tmp_delay = *work_bgn - delay_per_opa_tap(seq->iocfg);
 	scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p);
 
 	for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
@@ -1735,7 +1738,7 @@ static int sdr_nonworking_phase(struct socfpga_sdrseq *seq,
 	int ret;
 
 	(*p)++;
-	*work_end += seq->iocfg->delay_per_opa_tap;
+	*work_end += delay_per_opa_tap(seq->iocfg);
 	if (*p > seq->iocfg->dqs_en_phase_max) {
 		/* Fiddle with FIFO. */
 		*p = 0;
@@ -1774,19 +1777,19 @@ static int sdr_find_window_center(struct socfpga_sdrseq *seq,
 		   work_bgn, work_end, work_mid);
 	/* Get the middle delay to be less than a VFIFO delay */
 	tmp_delay = (seq->iocfg->dqs_en_phase_max + 1)
-		* seq->iocfg->delay_per_opa_tap;
+		* delay_per_opa_tap(seq->iocfg);
 
 	debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
 	work_mid %= tmp_delay;
 	debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
 
-	tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap);
+	tmp_delay = rounddown(work_mid, delay_per_opa_tap(seq->iocfg));
 	if (tmp_delay > seq->iocfg->dqs_en_phase_max
-		* seq->iocfg->delay_per_opa_tap) {
+		* delay_per_opa_tap(seq->iocfg)) {
 		tmp_delay = seq->iocfg->dqs_en_phase_max
-			* seq->iocfg->delay_per_opa_tap;
+			* delay_per_opa_tap(seq->iocfg);
 	}
-	p = tmp_delay / seq->iocfg->delay_per_opa_tap;
+	p = tmp_delay / delay_per_opa_tap(seq->iocfg);
 
 	debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
 
@@ -1850,7 +1853,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
 	scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0);
 
 	/* Step 0: Determine number of delay taps for each phase tap. */
-	dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
+	dtaps_per_ptap = delay_per_opa_tap(seq->iocfg) /
 			 seq->iocfg->delay_per_dqs_en_dchain_tap;
 
 	/* Step 1: First push vfifo until we get a failing read. */
@@ -1894,7 +1897,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
 			p = p - 1;
 		}
 
-		work_end -= seq->iocfg->delay_per_opa_tap;
+		work_end -= delay_per_opa_tap(seq->iocfg);
 		scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
 
 		d = 0;
@@ -2747,7 +2750,7 @@ static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq,
 	failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
 
 	/* USER Determine number of delay taps for each phase tap. */
-	dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
+	dtaps_per_ptap = DIV_ROUND_UP(delay_per_opa_tap(seq->iocfg),
 				      seq->iocfg->delay_per_dqs_en_dchain_tap)
 				      - 1;
 
@@ -3677,8 +3680,12 @@ static void hc_initialize_rom_data(void)
 static void initialize_reg_file(struct socfpga_sdrseq *seq)
 {
 	/* Initialize the register file with the correct data */
-	writel(seq->misccfg->reg_file_init_seq_signature,
-	       &sdr_reg_file->signature);
+	u32 reg_file_init_seq_signature =
+		seq->misccfg->reg_file_init_seq_signature_ll |
+		(seq->misccfg->reg_file_init_seq_signature_lh << 8) |
+		(seq->misccfg->reg_file_init_seq_signature_hl << 16) |
+		(seq->misccfg->reg_file_init_seq_signature_hh << 24);
+	writel(reg_file_init_seq_signature, &sdr_reg_file->signature);
 	writel(0, &sdr_reg_file->debug_data_addr);
 	writel(0, &sdr_reg_file->cur_stage);
 	writel(0, &sdr_reg_file->fom);
@@ -3749,7 +3756,7 @@ static void initialize_tracking(struct socfpga_sdrseq *seq)
 	 * Compute usable version of value in case we skip full
 	 * computation later.
 	 */
-	writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
+	writel(DIV_ROUND_UP(delay_per_opa_tap(seq->iocfg),
 			    seq->iocfg->delay_per_dchain_tap) - 1,
 	       &sdr_reg_file->dtaps_per_ptap);
 
@@ -3834,7 +3841,7 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
 		   seq.rwcfg->mem_if_read_dqs_width,
 		   seq.rwcfg->mem_if_write_dqs_width,
 		   seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width,
-		   seq.iocfg->delay_per_opa_tap,
+		   delay_per_opa_tap(seq.iocfg),
 		   seq.iocfg->delay_per_dchain_tap);
 	debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
 		   seq.iocfg->delay_per_dqs_en_dchain_tap,
-- 
2.20.1

[U-Boot] [RFC PATCH v2 10/18] ddr: socfpga: gen5: fetch handoff information from 'of_to_platdata'

[Simon Goldschmidt]

In preparation to move handoff data from 'qts' files to devicetree, fetch
SDRAM config in 'of_to_platdata' DM callback. That way, this callback
can be changed to fetch the data from devicetree.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/ddr/altera/sdram_gen5.c | 45 +++++++++++++++++++++++++--------
 drivers/ddr/altera/sequencer.c  | 35 +++++++++++++++----------
 drivers/ddr/altera/sequencer.h  |  9 ++++++-
 3 files changed, 64 insertions(+), 25 deletions(-)

diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8c8ea19eb9..91d9f6c0fc 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -25,6 +25,15 @@ struct altera_gen5_sdram_priv {
 
 struct altera_gen5_sdram_platdata {
 	struct socfpga_sdr *sdr;
+	/* Handoff config follows */
+	const struct socfpga_sdram_config *cfg;
+	const struct socfpga_sdram_rw_mgr_config *rwcfg;
+	const struct socfpga_sdram_io_config *iocfg;
+	const struct socfpga_sdram_misc_config *misccf;
+	const u32 *inst_rom_init;
+	unsigned int inst_rom_init_len;
+	const u32 *ac_rom_init;
+	unsigned int ac_rom_init_len;
 };
 
 struct sdram_prot_rule {
@@ -43,7 +52,9 @@ struct sdram_prot_rule {
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
+static unsigned long sdram_calculate_size(
+	struct socfpga_sdr_ctrl *sdr_ctrl,
+	const struct socfpga_sdram_config *cfg);
 
 /**
  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
@@ -446,10 +457,10 @@ static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
  *
  * Initialize the SDRAM MMR.
  */
-int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
-			unsigned int sdr_phy_reg)
+static int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
+			       unsigned int sdr_phy_reg,
+			       const struct socfpga_sdram_config *cfg)
 {
-	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 	const unsigned int rows =
 		(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
@@ -481,7 +492,7 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
 			1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 
 	sdram_set_protection_config(sdr_ctrl, 0,
-				    sdram_calculate_size(sdr_ctrl) - 1);
+				    sdram_calculate_size(sdr_ctrl, cfg) - 1);
 
 	sdram_dump_protection_config(sdr_ctrl);
 
@@ -494,11 +505,12 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
  * Calculate SDRAM device size based on SDRAM controller parameters.
  * Size is specified in bytes.
  */
-static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
+static unsigned long sdram_calculate_size(
+	struct socfpga_sdr_ctrl *sdr_ctrl,
+	const struct socfpga_sdram_config *cfg)
 {
 	unsigned long temp;
 	unsigned long row, bank, col, cs, width;
-	const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 	const unsigned int csbits =
 		((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
@@ -565,6 +577,16 @@ static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
 	if (!plat->sdr)
 		return -ENODEV;
 
+	/* Get handoff config */
+	plat->cfg = socfpga_get_sdram_config();
+	plat->rwcfg = socfpga_get_sdram_rwmgr_config();
+	plat->iocfg = socfpga_get_sdram_io_config();
+	plat->misccf = socfpga_get_sdram_misc_config();
+
+	socfpga_get_seq_inst_init(&plat->inst_rom_init,
+				  &plat->inst_rom_init_len);
+	socfpga_get_seq_ac_init(&plat->ac_rom_init, &plat->ac_rom_init_len);
+
 	return 0;
 }
 
@@ -584,19 +606,22 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
 	}
 	reset_deassert_bulk(&resets);
 
-	if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
+	if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff, plat->cfg) != 0) {
 		puts("SDRAM init failed.\n");
 		goto failed;
 	}
 
 	debug("SDRAM: Calibrating PHY\n");
 	/* SDRAM calibration */
-	if (sdram_calibration_full(plat->sdr) == 0) {
+	if (sdram_calibration_full(plat->sdr, plat->rwcfg, plat->iocfg,
+				   plat->misccf, plat->inst_rom_init,
+				   plat->inst_rom_init_len, plat->ac_rom_init,
+				   plat->ac_rom_init_len) == 0) {
 		puts("SDRAM calibration failed.\n");
 		goto failed;
 	}
 
-	sdram_size = sdram_calculate_size(sdr_ctrl);
+	sdram_size = sdram_calculate_size(sdr_ctrl, plat->cfg);
 	debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 
 	/* Sanity check ensure correct SDRAM size specified */
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6c632227c2..1e03cf3cf6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3655,21 +3655,20 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
  *
  * Initialize ROM data.
  */
-static void hc_initialize_rom_data(void)
+static void hc_initialize_rom_data(const u32 *inst_rom_init,
+				   unsigned int inst_rom_init_len,
+				   const u32 *ac_rom_init,
+				   unsigned int ac_rom_init_len)
 {
-	unsigned int nelem = 0;
-	const u32 *rom_init;
 	u32 i, addr;
 
-	socfpga_get_seq_inst_init(&rom_init, &nelem);
 	addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
-	for (i = 0; i < nelem; i++)
-		writel(rom_init[i], addr + (i << 2));
+	for (i = 0; i < inst_rom_init_len; i++)
+		writel(inst_rom_init[i], addr + (i << 2));
 
-	socfpga_get_seq_ac_init(&rom_init, &nelem);
 	addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
-	for (i = 0; i < nelem; i++)
-		writel(rom_init[i], addr + (i << 2));
+	for (i = 0; i < ac_rom_init_len; i++)
+		writel(ac_rom_init[i], addr + (i << 2));
 }
 
 /**
@@ -3788,7 +3787,14 @@ static void initialize_tracking(struct socfpga_sdrseq *seq)
 	       &sdr_reg_file->trk_rfsh);
 }
 
-int sdram_calibration_full(struct socfpga_sdr *sdr)
+int sdram_calibration_full(struct socfpga_sdr *sdr,
+			   const struct socfpga_sdram_rw_mgr_config *rwcfg,
+			   const struct socfpga_sdram_io_config *iocfg,
+			   const struct socfpga_sdram_misc_config *misccfg,
+			   const u32 *inst_rom_init,
+			   unsigned int inst_rom_init_len,
+			   const u32 *ac_rom_init,
+			   unsigned int ac_rom_init_len)
 {
 	u32 pass;
 	struct socfpga_sdrseq seq;
@@ -3802,9 +3808,9 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
 
 	memset(&seq, 0, sizeof(seq));
 
-	seq.rwcfg = socfpga_get_sdram_rwmgr_config();
-	seq.iocfg = socfpga_get_sdram_io_config();
-	seq.misccfg = socfpga_get_sdram_misc_config();
+	seq.rwcfg = rwcfg;
+	seq.iocfg = iocfg;
+	seq.misccfg = misccfg;
 
 	/* Set the calibration enabled by default */
 	seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
@@ -3856,7 +3862,8 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
 	debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
 		   seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve);
 
-	hc_initialize_rom_data();
+	hc_initialize_rom_data(inst_rom_init, inst_rom_init_len,
+			       ac_rom_init, ac_rom_init_len);
 
 	/* update info for sims */
 	reg_file_set_stage(CAL_STAGE_NIL);
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 4a03c3fdf9..84057d4b4f 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -278,6 +278,13 @@ struct socfpga_sdrseq {
 	struct param_type param;
 };
 
-int sdram_calibration_full(struct socfpga_sdr *sdr);
+int sdram_calibration_full(struct socfpga_sdr *sdr,
+			   const struct socfpga_sdram_rw_mgr_config *rwcfg,
+			   const struct socfpga_sdram_io_config *iocfg,
+			   const struct socfpga_sdram_misc_config *misccfg,
+			   const u32 *inst_rom_init,
+			   unsigned int inst_rom_init_len,
+			   const u32 *ac_rom_init,
+			   unsigned int ac_rom_init_len);
 
 #endif /* _SEQUENCER_H_ */
-- 
2.20.1

[U-Boot] [RFC PATCH v2 11/18] ddr: socfpga: gen5: read handoff information from devicetree

[Simon Goldschmidt]

Instead of reading SDRAM handoff data from 'qts' files, read it from
devicetree.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/ddr/altera/sdram_gen5.c | 61 ++++++++++++++++++++++++++++-----
 1 file changed, 53 insertions(+), 8 deletions(-)

diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 91d9f6c0fc..09ee45026c 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -572,20 +572,65 @@ static unsigned long sdram_calculate_size(
 static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
 {
 	struct altera_gen5_sdram_platdata *plat = dev->platdata;
+	int sz;
 
 	plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
 	if (!plat->sdr)
 		return -ENODEV;
 
 	/* Get handoff config */
-	plat->cfg = socfpga_get_sdram_config();
-	plat->rwcfg = socfpga_get_sdram_rwmgr_config();
-	plat->iocfg = socfpga_get_sdram_io_config();
-	plat->misccf = socfpga_get_sdram_misc_config();
-
-	socfpga_get_seq_inst_init(&plat->inst_rom_init,
-				  &plat->inst_rom_init_len);
-	socfpga_get_seq_ac_init(&plat->ac_rom_init, &plat->ac_rom_init_len);
+	plat->cfg = (const struct socfpga_sdram_config *)
+		dev_read_u8_array_ptr(dev, "altr,sdr-cfg", sizeof(*plat->cfg));
+	if (!plat->cfg) {
+		debug("Failed to parse altr,sdr-cfg\n");
+		return -EINVAL;
+	}
+	plat->rwcfg = (const struct socfpga_sdram_rw_mgr_config *)
+		dev_read_u8_array_ptr(dev, "altr,sdr-rw-mgr-cfg",
+				      sizeof(*plat->rwcfg));
+	if (!plat->rwcfg) {
+		debug("Failed to parse altr,sdr-rw-mgr-cfg\n");
+		return -EINVAL;
+	}
+	plat->iocfg = (const struct socfpga_sdram_io_config *)
+		dev_read_u8_array_ptr(dev, "altr,sdr-io-cfg",
+				      sizeof(*plat->iocfg));
+	if (!plat->iocfg) {
+		debug("Failed to parse altr,sdr-io-cfg\n");
+		return -EINVAL;
+	}
+	plat->misccf = (const struct socfpga_sdram_misc_config *)
+		dev_read_u8_array_ptr(dev, "altr,sdr-misc-cfg",
+				      sizeof(*plat->misccf));
+	if (!plat->misccf) {
+		debug("Failed to parse altr,sdr-misc-cfg\n");
+		return -EINVAL;
+	}
+
+	sz = dev_read_size(dev, "altr,sdr-inst-rom-init");
+	if (sz <= 0) {
+		debug("Failed to read altr,sdr-inst-rom-init size\n");
+		return sz;
+	}
+	plat->inst_rom_init_len = sz / sizeof(u32);
+	plat->inst_rom_init = (const u32*)dev_read_u8_array_ptr(dev,
+		"altr,sdr-inst-rom-init", sz);
+	if (!plat->inst_rom_init) {
+		debug("Failed to parse altr,sdr-inst-rom-init\n");
+		return -EINVAL;
+	}
+	sz = dev_read_size(dev, "altr,sdr-ac-rom-init");
+	if (sz <= 0) {
+		debug("Failed to read altr,sdr-ac-rom-init size\n");
+		return sz;
+	}
+	plat->ac_rom_init_len = sz / sizeof(u32);
+	plat->ac_rom_init = (const u32*)dev_read_u8_array_ptr(dev,
+		"altr,sdr-ac-rom-init", sz);
+	if (!plat->ac_rom_init) {
+		debug("Failed to parse altr,sdr-ac-rom-init\n");
+		return -EINVAL;
+	}
 
 	return 0;
 }
-- 
2.20.1

[U-Boot] [RFC PATCH v2 12/18] arm: socfpga: gen5: add readonly clk driver

[Simon Goldschmidt]

This adds clk-gen5 as a readonly DM_CLK driver that can return clocks for
the peripherals.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 MAINTAINERS                   |   1 +
 drivers/clk/altera/Makefile   |   1 +
 drivers/clk/altera/clk-gen5.c | 338 ++++++++++++++++++++++++++++++++++
 3 files changed, 340 insertions(+)
 create mode 100644 drivers/clk/altera/clk-gen5.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 74a1423f50..be8a38ea07 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -114,6 +114,7 @@ M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
 S:	Maintainted
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
+F:	drivers/clk/altera/clk-gen5.c
 F:	drivers/sysreset/sysreset_socfpga*
 
 ARM AMLOGIC SOC SUPPORT
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index a3ae8b24b0..d0664c6ad5 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += clk-gen5.o
diff --git a/drivers/clk/altera/clk-gen5.c b/drivers/clk/altera/clk-gen5.c
new file mode 100644
index 0000000000..4c197b81b0
--- /dev/null
+++ b/drivers/clk/altera/clk-gen5.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+
+#include <asm/arch/clock_manager.h>
+
+enum socfpga_gen5_clk_type {
+	SOCFPGA_GEN5_CLK_MAIN_PLL,
+	SOCFPGA_GEN5_CLK_PER_PLL,
+	SOCFPGA_GEN5_CLK_PERIP_CLK,
+	SOCFPGA_GEN5_CLK_GATE_CLK,
+	SOCFPGA_GEN5_CLK_UNKNOWN_CLK,
+};
+
+struct socfpga_gen5_clk_platdata {
+	enum socfpga_gen5_clk_type type;
+	struct clk_bulk	clks;
+	u32		regs;
+	/* Fixed divider */
+	u16		fix_div;
+	/* Control register */
+	u16		ctl_reg;
+	/* Divider register */
+	u16		div_reg;
+	u8		div_len;
+	u8		div_off;
+	/* Clock gating register */
+	u16		gate_reg;
+	u8		gate_bit;
+	/* Clock source register */
+	u16		src_reg;
+	u8		src_len;
+	u8		src_off;
+};
+
+static int socfpga_gen5_clk_get_upstream(struct clk *clk, struct clk **upclk)
+{
+	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(clk->dev);
+	u32 reg, maxval;
+
+	if (plat->clks.count == 0)
+		return 0;
+
+	if (plat->src_reg && plat->src_len) {
+		maxval = 1 << plat->src_len;
+		if (plat->clks.count <= maxval) {
+			reg = readl(plat->regs + plat->src_reg);
+			reg >>= plat->src_off;
+			reg &= (maxval - 1);
+			*upclk = &plat->clks.clks[reg];
+			return 0;
+		}
+	}
+
+	if (plat->clks.count == 1) {
+		*upclk = &plat->clks.clks[0];
+		return 0;
+	}
+
+	if (!plat->ctl_reg)
+		return -EINVAL;
+
+	reg = readl(plat->regs + plat->ctl_reg);
+
+	/* Assume PLLs are ON for now */
+	if (plat->type == SOCFPGA_GEN5_CLK_MAIN_PLL) {
+		reg = (reg >> 8) & 0x3;
+		maxval = 2;
+	} else if (plat->type == SOCFPGA_GEN5_CLK_PER_PLL) {
+		reg = (reg >> 8) & 0x3;
+		maxval = 3;
+	} else {
+		reg = (reg >> 16) & 0x7;
+		maxval = 4;
+	}
+
+	if (reg > maxval) {
+		dev_err(clk->dev, "Invalid clock source\n");
+		return -EINVAL;
+	}
+
+	*upclk = &plat->clks.clks[reg];
+	return 0;
+}
+
+static int socfpga_gen5_clk_endisable(struct clk *clk, bool enable)
+{
+	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(clk->dev);
+	struct clk *upclk = NULL;
+	int ret;
+
+	if (!enable && plat->gate_reg)
+		clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
+
+	ret = socfpga_gen5_clk_get_upstream(clk, &upclk);
+	if (ret)
+		return ret;
+
+	if (upclk) {
+		if (enable)
+			clk_enable(upclk);
+		else
+			clk_disable(upclk);
+	}
+
+	if (enable && plat->gate_reg)
+		setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
+
+	return 0;
+}
+
+static int socfpga_gen5_clk_enable(struct clk *clk)
+{
+	return socfpga_gen5_clk_endisable(clk, true);
+}
+
+static int socfpga_gen5_clk_disable(struct clk *clk)
+{
+	return socfpga_gen5_clk_endisable(clk, false);
+}
+
+static ulong socfpga_gen5_clk_get_rate(struct clk *clk)
+{
+	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(clk->dev);
+	struct clk *upclk = NULL;
+	ulong rate, uprate, reg, numer, denom;
+	int ret;
+
+	ret = socfpga_gen5_clk_get_upstream(clk, &upclk);
+	if (ret || !upclk)
+		return 0;
+
+	uprate = clk_get_rate(upclk);
+	rate = uprate;
+
+	if (plat->type == SOCFPGA_GEN5_CLK_MAIN_PLL) {
+		reg = readl(plat->regs + plat->ctl_reg);	/* VCO */
+		numer = (reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
+			CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET;
+		denom = (reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
+			CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET;
+		rate /= denom + 1;
+		rate *= numer + 1;
+	} else if (plat->type == SOCFPGA_GEN5_CLK_PER_PLL) {
+		reg = readl(plat->regs + plat->ctl_reg);	/* VCO */
+		numer = (reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
+			CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET;
+		denom = (reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
+			CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET;
+		rate /= denom + 1;
+		rate *= numer + 1;
+	} else {
+		rate /= plat->fix_div;
+
+		if (plat->fix_div == 1 && plat->ctl_reg) {
+			reg = readl(plat->regs + plat->ctl_reg);
+			reg &= 0x1ff;
+			rate /= reg + 1;
+		}
+
+		if (plat->div_reg) {
+			reg = readl(plat->regs + plat->div_reg);
+			reg >>= plat->div_off;
+			reg &= (1 << plat->div_len) - 1;
+			if (plat->type == SOCFPGA_GEN5_CLK_PERIP_CLK)
+				rate /= reg + 1;
+			if (plat->type == SOCFPGA_GEN5_CLK_GATE_CLK)
+				rate /= 1 << reg;
+		}
+	}
+
+	return rate;
+}
+
+static const struct clk_ops socfpga_gen5_clk_ops = {
+	.enable		= socfpga_gen5_clk_enable,
+	.disable	= socfpga_gen5_clk_disable,
+	.get_rate	= socfpga_gen5_clk_get_rate,
+};
+
+static int socfpga_gen5_clk_bind(struct udevice *dev)
+{
+	const void *fdt = gd->fdt_blob;
+	int offset = dev_of_offset(dev);
+	bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
+	const char *name;
+	int ret;
+	const char *drv_name;
+
+	for (offset = fdt_first_subnode(fdt, offset);
+	     offset > 0;
+	     offset = fdt_next_subnode(fdt, offset)) {
+		name = fdt_get_name(fdt, offset, NULL);
+		if (!name)
+			return -EINVAL;
+
+		if (!strcmp(name, "clocks")) {
+			offset = fdt_first_subnode(fdt, offset);
+			name = fdt_get_name(fdt, offset, NULL);
+			if (!name)
+				return -EINVAL;
+		}
+
+		/* Filter out supported sub-clock */
+		if (fdt_node_check_compatible(fdt, offset,
+					      "altr,socfpga-pll-clock") &&
+		    fdt_node_check_compatible(fdt, offset,
+					      "altr,socfpga-perip-clk") &&
+		    fdt_node_check_compatible(fdt, offset,
+					      "altr,socfpga-gate-clk") &&
+		    fdt_node_check_compatible(fdt, offset, "fixed-clock"))
+			continue;
+
+		if (pre_reloc_only &&
+		    !dm_ofnode_pre_reloc(offset_to_ofnode(offset)))
+			continue;
+
+		if (fdt_node_check_compatible(fdt, offset, "fixed-clock"))
+			drv_name = "clk-gen5";
+		else
+			drv_name = "fixed_rate_clock";
+
+		ret = device_bind_driver_to_node(dev, drv_name, name,
+						 offset_to_ofnode(offset),
+						 NULL);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int socfpga_gen5_clk_probe(struct udevice *dev)
+{
+	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(dev);
+	const void *fdt = gd->fdt_blob;
+	int offset = dev_of_offset(dev);
+
+	clk_get_bulk(dev, &plat->clks);
+
+	if (!fdt_node_check_compatible(fdt, offset,
+				       "altr,socfpga-pll-clock")) {
+		/* Main PLL has 3 upstream clock */
+		if (plat->clks.count == 1)
+			plat->type = SOCFPGA_GEN5_CLK_MAIN_PLL;
+		else
+			plat->type = SOCFPGA_GEN5_CLK_PER_PLL;
+	} else if (!fdt_node_check_compatible(fdt, offset,
+					      "altr,socfpga-perip-clk")) {
+		plat->type = SOCFPGA_GEN5_CLK_PERIP_CLK;
+	} else if (!fdt_node_check_compatible(fdt, offset,
+					      "altr,socfpga-gate-clk")) {
+		plat->type = SOCFPGA_GEN5_CLK_GATE_CLK;
+	} else {
+		plat->type = SOCFPGA_GEN5_CLK_UNKNOWN_CLK;
+	}
+
+	return 0;
+}
+
+static int socfpga_gen5_ofdata_to_platdata(struct udevice *dev)
+{
+	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(dev);
+	struct socfpga_gen5_clk_platdata *pplat;
+	struct udevice *pdev;
+	const void *fdt = gd->fdt_blob;
+	unsigned int divreg[3], gatereg[2], srcreg[3];
+	int ret, offset = dev_of_offset(dev);
+	u32 regs;
+
+	regs = dev_read_u32_default(dev, "reg", 0x0);
+
+	if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
+		plat->regs = devfdt_get_addr(dev);
+	} else {
+		pdev = dev_get_parent(dev);
+		if (!pdev)
+			return -ENODEV;
+
+		pplat = dev_get_platdata(pdev);
+		if (!pplat)
+			return -EINVAL;
+
+		plat->ctl_reg = regs;
+		plat->regs = pplat->regs;
+	}
+
+	plat->type = SOCFPGA_GEN5_CLK_UNKNOWN_CLK;
+
+	plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1);
+
+	ret = dev_read_u32_array(dev, "src-reg", srcreg, ARRAY_SIZE(srcreg));
+	if (!ret) {
+		plat->src_reg = srcreg[0];
+		plat->src_len = srcreg[2];
+		plat->src_off = srcreg[1];
+	}
+
+	ret = dev_read_u32_array(dev, "div-reg", divreg, ARRAY_SIZE(divreg));
+	if (!ret) {
+		plat->div_reg = divreg[0];
+		plat->div_len = divreg[2];
+		plat->div_off = divreg[1];
+	}
+
+	ret = dev_read_u32_array(dev, "clk-gate", gatereg, ARRAY_SIZE(gatereg));
+	if (!ret) {
+		plat->gate_reg = gatereg[0];
+		plat->gate_bit = gatereg[1];
+	}
+
+	return 0;
+}
+
+static const struct udevice_id socfpga_gen5_clk_match[] = {
+	{ .compatible = "altr,clk-mgr" },
+	{}
+};
+
+U_BOOT_DRIVER(socfpga_gen5_clk) = {
+	.name		= "clk-gen5",
+	.id		= UCLASS_CLK,
+	.of_match	= socfpga_gen5_clk_match,
+	.ops		= &socfpga_gen5_clk_ops,
+	.bind		= socfpga_gen5_clk_bind,
+	.probe		= socfpga_gen5_clk_probe,
+	.ofdata_to_platdata = socfpga_gen5_ofdata_to_platdata,
+
+	.platdata_auto_alloc_size = sizeof(struct socfpga_gen5_clk_platdata),
+};
-- 
2.20.1

[U-Boot] [RFC PATCH v2 13/18] arm: socfpga: gen5: enable DM CLK

[Simon Goldschmidt]

Enable CLK and SPL_CLK so that the new readonly clock driver is used.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 arch/arm/mach-socfpga/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9efdcd6f10..81052f27d5 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -53,7 +53,9 @@ config TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_GEN5
 	bool
+	select CLK
 	select SPL_ALTERA_SDRAM
+	select SPL_CLK if SPL
 	imply FPGA_SOCFPGA
 	imply SPL_SIZE_LIMIT_SUBTRACT_GD
 	imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
-- 
2.20.1

[U-Boot] [RFC PATCH v2 14/18] arm: socfpga: gen5: move clock initialization to CLK driver

[Simon Goldschmidt]

This moves setting initial clock values (as defined by Quartus handoff
files) from ad-hoc code in arch to CM_CLK driver.

TODO: CONFIG_CLOCKS and cmd 'clocks' must be fixed for dts access.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 arch/arm/mach-socfpga/Makefile                |   1 -
 arch/arm/mach-socfpga/clock_manager.c         |  31 +-
 arch/arm/mach-socfpga/clock_manager_gen5.c    | 528 ------------------
 .../mach-socfpga/include/mach/clock_manager.h |   2 +
 .../include/mach/clock_manager_gen5.h         |  12 -
 arch/arm/mach-socfpga/spl_gen5.c              |   8 +-
 drivers/clk/altera/clk-gen5.c                 | 361 ++++++++++++
 7 files changed, 388 insertions(+), 555 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index fc1181cb27..4b77990f74 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,7 +10,6 @@ obj-y	+= clock_manager.o
 obj-y	+= misc.o
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
-obj-y	+= clock_manager_gen5.o
 obj-y	+= misc_gen5.o
 obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 9f3c643df8..16760c760f 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,6 +10,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+
 static const struct socfpga_clock_manager *clock_manager_base =
 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
@@ -18,11 +20,7 @@ void cm_wait_for_lock(u32 mask)
 	u32 inter_val;
 	u32 retry = 0;
 	do {
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-		inter_val = readl(&clock_manager_base->inter) & mask;
-#else
 		inter_val = readl(&clock_manager_base->stat) & mask;
-#endif
 		/* Wait for stable lock */
 		if (inter_val == mask)
 			retry++;
@@ -40,14 +38,29 @@ int cm_wait_for_fsm(void)
 				 CLKMGR_STAT_BUSY, false, 20000, false);
 }
 
-int set_cpu_clk_info(void)
+#endif
+
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+static unsigned long cm_get_mpu_clk_hz(void)
 {
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-	/* Calculate the clock frequencies required for drivers */
-	cm_get_l4_sp_clk_hz();
-	cm_get_mmc_controller_clk_hz();
+	return 0; // TODO: use devicetree
+}
+
+static unsigned long cm_get_sdram_clk_hz(void)
+{
+	return 0; // TODO: use devicetree
+}
+
+#ifndef CONFIG_SPL_BUILD
+static void cm_print_clock_quick_summary(void)
+{
+	// TODO: use devicetree
+}
+#endif
 #endif
 
+int set_cpu_clk_info(void)
+{
 	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
 	gd->bd->bi_dsp_freq = 0;
 
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
deleted file mode 100644
index 3a64600861..0000000000
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ /dev/null
@@ -1,528 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <dm.h>
-#include <asm/arch/clock_manager.h>
-#include <wait_bit.h>
-
-static const struct socfpga_clock_manager *clock_manager_base =
-	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(u32 val)
-{
-	writel(val, &clock_manager_base->bypass);
-	cm_wait_for_fsm();
-}
-
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(u32 val)
-{
-	writel(val, &clock_manager_base->ctrl);
-	cm_wait_for_fsm();
-}
-
-/* function to write a clock register that has phase information */
-static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
-{
-	int ret;
-
-	/* poll until phase is zero */
-	ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
-	if (ret)
-		return ret;
-
-	writel(value, reg_address);
-
-	return wait_for_bit_le32(reg_address, mask, false, 20000, false);
-}
-
-/*
- * Setup clocks while making no assumptions about previous state of the clocks.
- *
- * Start by being paranoid and gate all sw managed clocks
- * Put all plls in bypass
- * Put all plls VCO registers back to reset value (bandgap power down).
- * Put peripheral and main pll src to reset value to avoid glitch.
- * Delay 5 us.
- * Deassert bandgap power down and set numerator and denominator
- * Start 7 us timer.
- * set internal dividers
- * Wait for 7 us timer.
- * Enable plls
- * Set external dividers while plls are locking
- * Wait for pll lock
- * Assert/deassert outreset all.
- * Take all pll's out of bypass
- * Clear safe mode
- * set source main and peripheral clocks
- * Ungate clocks
- */
-
-int cm_basic_init(const struct cm_config * const cfg)
-{
-	unsigned long end;
-	int ret;
-
-	/* Start by being paranoid and gate all sw managed clocks */
-
-	/*
-	 * We need to disable nandclk
-	 * and then do another apb access before disabling
-	 * gatting off the rest of the periperal clocks.
-	 */
-	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
-		readl(&clock_manager_base->per_pll.en),
-		&clock_manager_base->per_pll.en);
-
-	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
-	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
-		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
-		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
-		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
-		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
-		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
-		&clock_manager_base->main_pll.en);
-
-	writel(0, &clock_manager_base->sdr_pll.en);
-
-	/* now we can gate off the rest of the peripheral clocks */
-	writel(0, &clock_manager_base->per_pll.en);
-
-	/* Put all plls in bypass */
-	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
-			CLKMGR_BYPASS_MAINPLL);
-
-	/* Put all plls VCO registers back to reset value. */
-	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
-	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->main_pll.vco);
-	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
-	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->per_pll.vco);
-	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
-	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->sdr_pll.vco);
-
-	/*
-	 * The clocks to the flash devices and the L4_MAIN clocks can
-	 * glitch when coming out of safe mode if their source values
-	 * are different from their reset value.  So the trick it to
-	 * put them back to their reset state, and change input
-	 * after exiting safe mode but before ungating the clocks.
-	 */
-	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
-	       &clock_manager_base->per_pll.src);
-	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
-	       &clock_manager_base->main_pll.l4src);
-
-	/* read back for the required 5 us delay. */
-	readl(&clock_manager_base->main_pll.vco);
-	readl(&clock_manager_base->per_pll.vco);
-	readl(&clock_manager_base->sdr_pll.vco);
-
-
-	/*
-	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
-	 * with numerator and denominator.
-	 */
-	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
-	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
-	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
-
-	/*
-	 * Time starts here. Must wait 7 us from
-	 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
-	 */
-	end = timer_get_us() + 7;
-
-	/* main mpu */
-	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
-
-	/* altera group mpuclk */
-	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
-
-	/* main main clock */
-	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
-
-	/* main for dbg */
-	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
-
-	/* main for cfgs2fuser0clk */
-	writel(cfg->cfg2fuser0clk,
-	       &clock_manager_base->main_pll.cfgs2fuser0clk);
-
-	/* Peri emac0 50 MHz default to RMII */
-	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
-
-	/* Peri emac1 50 MHz default to RMII */
-	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
-
-	/* Peri QSPI */
-	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
-
-	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
-
-	/* Peri pernandsdmmcclk */
-	writel(cfg->mainnandsdmmcclk,
-	       &clock_manager_base->main_pll.mainnandsdmmcclk);
-
-	writel(cfg->pernandsdmmcclk,
-	       &clock_manager_base->per_pll.pernandsdmmcclk);
-
-	/* Peri perbaseclk */
-	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
-
-	/* Peri s2fuser1clk */
-	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
-
-	/* 7 us must have elapsed before we can enable the VCO */
-	while (timer_get_us() < end)
-		;
-
-	/* Enable vco */
-	/* main pll vco */
-	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->main_pll.vco);
-
-	/* periferal pll */
-	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->per_pll.vco);
-
-	/* sdram pll vco */
-	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->sdr_pll.vco);
-
-	/* L3 MP and L3 SP */
-	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
-
-	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
-
-	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
-
-	/* L4 MP, L4 SP, can0, and can1 */
-	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
-
-	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
-
-	cm_wait_for_lock(LOCKED_MASK);
-
-	/* write the sdram clock counters before toggling outreset all */
-	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.ddrdqsclk);
-
-	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
-
-	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.ddrdqclk);
-
-	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
-	       &clock_manager_base->sdr_pll.s2fuser2clk);
-
-	/*
-	 * after locking, but before taking out of bypass
-	 * assert/deassert outresetall
-	 */
-	u32 mainvco = readl(&clock_manager_base->main_pll.vco);
-
-	/* assert main outresetall */
-	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->main_pll.vco);
-
-	u32 periphvco = readl(&clock_manager_base->per_pll.vco);
-
-	/* assert pheriph outresetall */
-	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->per_pll.vco);
-
-	/* assert sdram outresetall */
-	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
-		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
-		&clock_manager_base->sdr_pll.vco);
-
-	/* deassert main outresetall */
-	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->main_pll.vco);
-
-	/* deassert pheriph outresetall */
-	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
-	       &clock_manager_base->per_pll.vco);
-
-	/* deassert sdram outresetall */
-	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
-	       &clock_manager_base->sdr_pll.vco);
-
-	/*
-	 * now that we've toggled outreset all, all the clocks
-	 * are aligned nicely; so we can change any phase.
-	 */
-	ret = cm_write_with_phase(cfg->ddrdqsclk,
-				  &clock_manager_base->sdr_pll.ddrdqsclk,
-				  CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
-	if (ret)
-		return ret;
-
-	/* SDRAM DDR2XDQSCLK */
-	ret = cm_write_with_phase(cfg->ddr2xdqsclk,
-				  &clock_manager_base->sdr_pll.ddr2xdqsclk,
-				  CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
-	if (ret)
-		return ret;
-
-	ret = cm_write_with_phase(cfg->ddrdqclk,
-				  &clock_manager_base->sdr_pll.ddrdqclk,
-				  CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
-	if (ret)
-		return ret;
-
-	ret = cm_write_with_phase(cfg->s2fuser2clk,
-				  &clock_manager_base->sdr_pll.s2fuser2clk,
-				  CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
-	if (ret)
-		return ret;
-
-	/* Take all three PLLs out of bypass when safe mode is cleared. */
-	cm_write_bypass(0);
-
-	/* clear safe mode */
-	cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
-
-	/*
-	 * now that safe mode is clear with clocks gated
-	 * it safe to change the source mux for the flashes the the L4_MAIN
-	 */
-	writel(cfg->persrc, &clock_manager_base->per_pll.src);
-	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
-
-	/* Now ungate non-hw-managed clocks */
-	writel(~0, &clock_manager_base->main_pll.en);
-	writel(~0, &clock_manager_base->per_pll.en);
-	writel(~0, &clock_manager_base->sdr_pll.en);
-
-	/* Clear the loss of lock bits (write 1 to clear) */
-	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
-	       CLKMGR_INTER_MAINPLLLOST_MASK,
-	       &clock_manager_base->inter);
-
-	return 0;
-}
-
-static unsigned int cm_get_main_vco_clk_hz(void)
-{
-	u32 reg, clock;
-
-	/* get the main VCO clock */
-	reg = readl(&clock_manager_base->main_pll.vco);
-	clock = cm_get_osc_clk_hz(1);
-	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
-		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
-	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
-		  CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
-
-	return clock;
-}
-
-static unsigned int cm_get_per_vco_clk_hz(void)
-{
-	u32 reg, clock = 0;
-
-	/* identify PER PLL clock source */
-	reg = readl(&clock_manager_base->per_pll.vco);
-	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
-	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
-	if (reg == CLKMGR_VCO_SSRC_EOSC1)
-		clock = cm_get_osc_clk_hz(1);
-	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-		clock = cm_get_osc_clk_hz(2);
-	else if (reg == CLKMGR_VCO_SSRC_F2S)
-		clock = cm_get_f2s_per_ref_clk_hz();
-
-	/* get the PER VCO clock */
-	reg = readl(&clock_manager_base->per_pll.vco);
-	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
-		  CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
-	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
-		  CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
-
-	return clock;
-}
-
-unsigned long cm_get_mpu_clk_hz(void)
-{
-	u32 reg, clock;
-
-	clock = cm_get_main_vco_clk_hz();
-
-	/* get the MPU clock */
-	reg = readl(&clock_manager_base->altera.mpuclk);
-	clock /= (reg + 1);
-	reg = readl(&clock_manager_base->main_pll.mpuclk);
-	clock /= (reg + 1);
-	return clock;
-}
-
-unsigned long cm_get_sdram_clk_hz(void)
-{
-	u32 reg, clock = 0;
-
-	/* identify SDRAM PLL clock source */
-	reg = readl(&clock_manager_base->sdr_pll.vco);
-	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
-	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
-	if (reg == CLKMGR_VCO_SSRC_EOSC1)
-		clock = cm_get_osc_clk_hz(1);
-	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-		clock = cm_get_osc_clk_hz(2);
-	else if (reg == CLKMGR_VCO_SSRC_F2S)
-		clock = cm_get_f2s_sdr_ref_clk_hz();
-
-	/* get the SDRAM VCO clock */
-	reg = readl(&clock_manager_base->sdr_pll.vco);
-	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
-		  CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
-	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
-		  CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
-
-	/* get the SDRAM (DDR_DQS) clock */
-	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
-	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
-	      CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
-	clock /= (reg + 1);
-
-	return clock;
-}
-
-unsigned int cm_get_l4_sp_clk_hz(void)
-{
-	u32 reg, clock = 0;
-
-	/* identify the source of L4 SP clock */
-	reg = readl(&clock_manager_base->main_pll.l4src);
-	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
-	      CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
-
-	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
-		clock = cm_get_main_vco_clk_hz();
-
-		/* get the clock prior L4 SP divider (main clk) */
-		reg = readl(&clock_manager_base->altera.mainclk);
-		clock /= (reg + 1);
-		reg = readl(&clock_manager_base->main_pll.mainclk);
-		clock /= (reg + 1);
-	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
-		clock = cm_get_per_vco_clk_hz();
-
-		/* get the clock prior L4 SP divider (periph_base_clk) */
-		reg = readl(&clock_manager_base->per_pll.perbaseclk);
-		clock /= (reg + 1);
-	}
-
-	/* get the L4 SP clock which supplied to UART */
-	reg = readl(&clock_manager_base->main_pll.maindiv);
-	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
-	      CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
-	clock = clock / (1 << reg);
-
-	return clock;
-}
-
-unsigned int cm_get_mmc_controller_clk_hz(void)
-{
-	u32 reg, clock = 0;
-
-	/* identify the source of MMC clock */
-	reg = readl(&clock_manager_base->per_pll.src);
-	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
-	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
-
-	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
-		clock = cm_get_f2s_per_ref_clk_hz();
-	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
-		clock = cm_get_main_vco_clk_hz();
-
-		/* get the SDMMC clock */
-		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
-		clock /= (reg + 1);
-	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
-		clock = cm_get_per_vco_clk_hz();
-
-		/* get the SDMMC clock */
-		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
-		clock /= (reg + 1);
-	}
-
-	/* further divide by 4 as we have fixed divider at wrapper */
-	clock /= 4;
-	return clock;
-}
-
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
-	u32 reg, clock = 0;
-
-	/* identify the source of QSPI clock */
-	reg = readl(&clock_manager_base->per_pll.src);
-	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
-	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
-
-	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
-		clock = cm_get_f2s_per_ref_clk_hz();
-	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
-		clock = cm_get_main_vco_clk_hz();
-
-		/* get the qspi clock */
-		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
-		clock /= (reg + 1);
-	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
-		clock = cm_get_per_vco_clk_hz();
-
-		/* get the qspi clock */
-		reg = readl(&clock_manager_base->per_pll.perqspiclk);
-		clock /= (reg + 1);
-	}
-
-	return clock;
-}
-
-unsigned int cm_get_spi_controller_clk_hz(void)
-{
-	u32 reg, clock = 0;
-
-	clock = cm_get_per_vco_clk_hz();
-
-	/* get the clock prior L4 SP divider (periph_base_clk) */
-	reg = readl(&clock_manager_base->per_pll.perbaseclk);
-	clock /= (reg + 1);
-
-	return clock;
-}
-
-/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
-int dw_spi_get_clk(struct udevice *bus, ulong *rate)
-{
-	*rate = cm_get_spi_controller_clk_hz();
-
-	return 0;
-}
-
-void cm_print_clock_quick_summary(void)
-{
-	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
-	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
-	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
-	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
-	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
-	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
-	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
-	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
-	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
-	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
-}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index dd80e3a767..fff606e099 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -6,11 +6,13 @@
 #ifndef _CLOCK_MANAGER_H_
 #define _CLOCK_MANAGER_H_
 
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
 #ifndef __ASSEMBLER__
 void cm_wait_for_lock(u32 mask);
 int cm_wait_for_fsm(void);
 void cm_print_clock_quick_summary(void);
 #endif
+#endif
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/clock_manager_gen5.h>
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 5bedf28cf1..a9efe2a377 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -111,19 +111,7 @@ struct socfpga_clock_manager {
 	u32	_pad_0xe8_0x200[70];
 };
 
-/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
-unsigned long cm_get_sdram_clk_hz(void);
-unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
-unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(const int osc);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-
 /* Clock configuration accessors */
-int cm_basic_init(const struct cm_config * const cfg);
 const struct cm_config * const cm_get_default_config(void);
 #endif /* __ASSEMBLER__ */
 
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 1ae8025746..901fd9597e 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -62,7 +62,6 @@ u32 spl_boot_mode(const u32 boot_device)
 
 void board_init_f(ulong dummy)
 {
-	const struct cm_config *cm_default_cfg = cm_get_default_config();
 	unsigned long reg;
 	int ret;
 	struct udevice *dev;
@@ -106,10 +105,9 @@ void board_init_f(ulong dummy)
 	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 	timer_init();
 
-	debug("Reconfigure Clock Manager\n");
-	/* reconfigure the PLLs */
-	if (cm_basic_init(cm_default_cfg))
-		hang();
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret)
+		debug("Reset init failed: %d\n", ret);
 
 	/* Enable bootrom to configure IOs. */
 	sysmgr_config_warmrstcfgio(1);
diff --git a/drivers/clk/altera/clk-gen5.c b/drivers/clk/altera/clk-gen5.c
index 4c197b81b0..e8f435a798 100644
--- a/drivers/clk/altera/clk-gen5.c
+++ b/drivers/clk/altera/clk-gen5.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2019 Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
  */
 
 #include <common.h>
@@ -9,6 +10,7 @@
 #include <dm.h>
 #include <dm/lists.h>
 #include <dm/util.h>
+#include <wait_bit.h>
 
 #include <asm/arch/clock_manager.h>
 
@@ -41,6 +43,353 @@ struct socfpga_gen5_clk_platdata {
 	u8		src_off;
 };
 
+#ifdef CONFIG_SPL_BUILD
+static void socfpga_gen5_clk_wait_for_lock(
+	const struct socfpga_clock_manager *clock_mgr, u32 mask)
+{
+	u32 inter_val;
+	u32 retry = 0;
+	do {
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+		inter_val = readl(&clock_mgr->inter) & mask;
+#else
+		inter_val = readl(&clock_mgr->stat) & mask;
+#endif
+		/* Wait for stable lock */
+		if (inter_val == mask)
+			retry++;
+		else
+			retry = 0;
+		if (retry >= 10)
+			break;
+	} while (1);
+}
+
+/* function to poll in the fsm busy bit */
+static int socfpga_gen5_clk_wait_for_fsm(
+	const struct socfpga_clock_manager *clock_mgr)
+{
+	return wait_for_bit_le32(&clock_mgr->stat,
+				 CLKMGR_STAT_BUSY, false, 20000, false);
+}
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void socfpga_gen5_clk_write_bypass(
+	const struct socfpga_clock_manager *clock_mgr, u32 val)
+{
+	writel(val, &clock_mgr->bypass);
+	socfpga_gen5_clk_wait_for_fsm(clock_mgr);
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void socfpga_gen5_clk_write_ctrl(
+	const struct socfpga_clock_manager *clock_mgr, u32 val)
+{
+	writel(val, &clock_mgr->ctrl);
+	socfpga_gen5_clk_wait_for_fsm(clock_mgr);
+}
+
+/* function to write a clock register that has phase information */
+static int socfpga_gen5_clk_write_with_phase(
+	const struct socfpga_clock_manager *clock_mgr, u32 value,
+	const void *reg_address, u32 mask)
+{
+	int ret;
+
+	/* poll until phase is zero */
+	ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
+	if (ret)
+		return ret;
+
+	writel(value, reg_address);
+
+	return wait_for_bit_le32(reg_address, mask, false, 20000, false);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ *
+ * Start by being paranoid and gate all sw managed clocks
+ * Put all plls in bypass
+ * Put all plls VCO registers back to reset value (bandgap power down).
+ * Put peripheral and main pll src to reset value to avoid glitch.
+ * Delay 5 us.
+ * Deassert bandgap power down and set numerator and denominator
+ * Start 7 us timer.
+ * set internal dividers
+ * Wait for 7 us timer.
+ * Enable plls
+ * Set external dividers while plls are locking
+ * Wait for pll lock
+ * Assert/deassert outreset all.
+ * Take all pll's out of bypass
+ * Clear safe mode
+ * set source main and peripheral clocks
+ * Ungate clocks
+ */
+static int socfpga_gen5_clk_init(struct udevice *dev)
+{
+	unsigned long end;
+	int ret;
+	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(dev);
+	const struct socfpga_clock_manager *clock_manager_base =
+		(const struct socfpga_clock_manager *)plat->regs;
+	const struct cm_config *cfg = cm_get_default_config();
+
+	/* Start by being paranoid and gate all sw managed clocks */
+
+	/*
+	 * We need to disable nandclk
+	 * and then do another apb access before disabling
+	 * gatting off the rest of the periperal clocks.
+	 */
+	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
+		readl(&clock_manager_base->per_pll.en),
+		&clock_manager_base->per_pll.en);
+
+	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
+	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
+		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
+		&clock_manager_base->main_pll.en);
+
+	writel(0, &clock_manager_base->sdr_pll.en);
+
+	/* now we can gate off the rest of the peripheral clocks */
+	writel(0, &clock_manager_base->per_pll.en);
+
+	/* Put all plls in bypass */
+	socfpga_gen5_clk_write_bypass(clock_manager_base,
+				      CLKMGR_BYPASS_PERPLL |
+				      CLKMGR_BYPASS_SDRPLL |
+				      CLKMGR_BYPASS_MAINPLL);
+
+	/* Put all plls VCO registers back to reset value. */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
+	       &clock_manager_base->main_pll.vco);
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
+	       &clock_manager_base->per_pll.vco);
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
+	       &clock_manager_base->sdr_pll.vco);
+
+	/*
+	 * The clocks to the flash devices and the L4_MAIN clocks can
+	 * glitch when coming out of safe mode if their source values
+	 * are different from their reset value.  So the trick it to
+	 * put them back to their reset state, and change input
+	 * after exiting safe mode but before ungating the clocks.
+	 */
+	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
+	       &clock_manager_base->per_pll.src);
+	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
+	       &clock_manager_base->main_pll.l4src);
+
+	/* read back for the required 5 us delay. */
+	readl(&clock_manager_base->main_pll.vco);
+	readl(&clock_manager_base->per_pll.vco);
+	readl(&clock_manager_base->sdr_pll.vco);
+
+
+	/*
+	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
+	 * with numerator and denominator.
+	 */
+	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
+	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
+	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
+
+	/*
+	 * Time starts here. Must wait 7 us from
+	 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
+	 */
+	end = timer_get_us() + 7;
+
+	/* main mpu */
+	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+
+	/* altera group mpuclk */
+	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+
+	/* main main clock */
+	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
+
+	/* main for dbg */
+	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
+
+	/* main for cfgs2fuser0clk */
+	writel(cfg->cfg2fuser0clk,
+	       &clock_manager_base->main_pll.cfgs2fuser0clk);
+
+	/* Peri emac0 50 MHz default to RMII */
+	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
+
+	/* Peri emac1 50 MHz default to RMII */
+	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
+
+	/* Peri QSPI */
+	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
+
+	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
+
+	/* Peri pernandsdmmcclk */
+	writel(cfg->mainnandsdmmcclk,
+	       &clock_manager_base->main_pll.mainnandsdmmcclk);
+
+	writel(cfg->pernandsdmmcclk,
+	       &clock_manager_base->per_pll.pernandsdmmcclk);
+
+	/* Peri perbaseclk */
+	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
+
+	/* Peri s2fuser1clk */
+	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
+
+	/* 7 us must have elapsed before we can enable the VCO */
+	while (timer_get_us() < end)
+		;
+
+	/* Enable vco */
+	/* main pll vco */
+	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->main_pll.vco);
+
+	/* periferal pll */
+	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->per_pll.vco);
+
+	/* sdram pll vco */
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->sdr_pll.vco);
+
+	/* L3 MP and L3 SP */
+	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
+
+	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
+
+	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
+
+	/* L4 MP, L4 SP, can0, and can1 */
+	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
+
+	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+
+	socfpga_gen5_clk_wait_for_lock(clock_manager_base, LOCKED_MASK);
+
+	/* write the sdram clock counters before toggling outreset all */
+	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll.ddrdqsclk);
+
+	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
+
+	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll.ddrdqclk);
+
+	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
+	       &clock_manager_base->sdr_pll.s2fuser2clk);
+
+	/*
+	 * after locking, but before taking out of bypass
+	 * assert/deassert outresetall
+	 */
+	u32 mainvco = readl(&clock_manager_base->main_pll.vco);
+
+	/* assert main outresetall */
+	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll.vco);
+
+	u32 periphvco = readl(&clock_manager_base->per_pll.vco);
+
+	/* assert pheriph outresetall */
+	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll.vco);
+
+	/* assert sdram outresetall */
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
+		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
+		&clock_manager_base->sdr_pll.vco);
+
+	/* deassert main outresetall */
+	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->main_pll.vco);
+
+	/* deassert pheriph outresetall */
+	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
+	       &clock_manager_base->per_pll.vco);
+
+	/* deassert sdram outresetall */
+	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
+	       &clock_manager_base->sdr_pll.vco);
+
+	/*
+	 * now that we've toggled outreset all, all the clocks
+	 * are aligned nicely; so we can change any phase.
+	 */
+	ret = socfpga_gen5_clk_write_with_phase(
+		clock_manager_base, cfg->ddrdqsclk,
+		&clock_manager_base->sdr_pll.ddrdqsclk,
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	/* SDRAM DDR2XDQSCLK */
+	ret = socfpga_gen5_clk_write_with_phase(
+		clock_manager_base, cfg->ddr2xdqsclk,
+		&clock_manager_base->sdr_pll.ddr2xdqsclk,
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	ret = socfpga_gen5_clk_write_with_phase(
+		clock_manager_base, cfg->ddrdqclk,
+		&clock_manager_base->sdr_pll.ddrdqclk,
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	ret = socfpga_gen5_clk_write_with_phase(
+		clock_manager_base, cfg->s2fuser2clk,
+		&clock_manager_base->sdr_pll.s2fuser2clk,
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
+	if (ret)
+		return ret;
+
+	/* Take all three PLLs out of bypass when safe mode is cleared. */
+	socfpga_gen5_clk_write_bypass(clock_manager_base, 0);
+
+	/* clear safe mode */
+	socfpga_gen5_clk_write_ctrl(clock_manager_base,
+				    readl(&clock_manager_base->ctrl) |
+				    CLKMGR_CTRL_SAFEMODE);
+
+	/*
+	 * now that safe mode is clear with clocks gated
+	 * it safe to change the source mux for the flashes the the L4_MAIN
+	 */
+	writel(cfg->persrc, &clock_manager_base->per_pll.src);
+	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
+
+	/* Now ungate non-hw-managed clocks */
+	writel(~0, &clock_manager_base->main_pll.en);
+	writel(~0, &clock_manager_base->per_pll.en);
+	writel(~0, &clock_manager_base->sdr_pll.en);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+	       CLKMGR_INTER_MAINPLLLOST_MASK,
+	       &clock_manager_base->inter);
+	return 0;
+}
+#endif
+
 static int socfpga_gen5_clk_get_upstream(struct clk *clk, struct clk **upclk)
 {
 	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(clk->dev);
@@ -246,6 +595,18 @@ static int socfpga_gen5_clk_probe(struct udevice *dev)
 
 	clk_get_bulk(dev, &plat->clks);
 
+#ifdef CONFIG_SPL_BUILD
+	/* clock tree init is done only one time, in SPL, before relocation */
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
+			/* assign default clocks */
+			int ret = socfpga_gen5_clk_init(dev);
+			if (ret)
+				return ret;
+		}
+	}
+#endif
+
 	if (!fdt_node_check_compatible(fdt, offset,
 				       "altr,socfpga-pll-clock")) {
 		/* Main PLL has 3 upstream clock */
-- 
2.20.1

[U-Boot] [RFC PATCH v2 15/18] arm: socfpga: gen5: load CLK config from devicetree

[Simon Goldschmidt]

Instead of using ad-hoc code in arch/arm, load clock config from devicetree.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/clk/altera/clk-gen5.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/altera/clk-gen5.c b/drivers/clk/altera/clk-gen5.c
index e8f435a798..a5425b7424 100644
--- a/drivers/clk/altera/clk-gen5.c
+++ b/drivers/clk/altera/clk-gen5.c
@@ -136,7 +136,13 @@ static int socfpga_gen5_clk_init(struct udevice *dev)
 	struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(dev);
 	const struct socfpga_clock_manager *clock_manager_base =
 		(const struct socfpga_clock_manager *)plat->regs;
-	const struct cm_config *cfg = cm_get_default_config();
+	const struct cm_config *cfg = (const struct cm_config *)
+		dev_read_u8_array_ptr(dev, "altr,clk-mgr-cfg", sizeof(*cfg));
+
+	if (!cfg) {
+		dev_dbg(dev, "Failed to load CLK config\n");
+		return -EINVAL;
+	}
 
 	/* Start by being paranoid and gate all sw managed clocks */
 
-- 
2.20.1

[U-Boot] [RFC PATCH v2 16/18] spi: cadence_qspi: support DM_CLK

[Simon Goldschmidt]

Support loading clk speed via DM instead of requiring ad-hoc code.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 drivers/spi/cadence_qspi.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index e2e54cd277..0b89115885 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
@@ -22,12 +23,27 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
 {
 	struct cadence_spi_platdata *plat = bus->platdata;
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
+	unsigned int ref_clk_hz;
+	struct clk clk;
+	int ret;
+
+	ret = clk_get_by_index(bus, 0, &clk);
+	if (ret) {
+#ifdef CONFIG_CQSPI_REF_CLK
+		ref_clk_hz = CONFIG_CQSPI_REF_CLK;
+#else
+		return ret;
+#endif
+	} else {
+		ref_clk_hz = clk_get_rate(&clk);
+		clk_free(&clk);
+	}
 
 	cadence_qspi_apb_config_baudrate_div(priv->regbase,
-					     CONFIG_CQSPI_REF_CLK, hz);
+					     ref_clk_hz, hz);
 
 	/* Reconfigure delay timing if speed is changed. */
-	cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+	cadence_qspi_apb_delay(priv->regbase, ref_clk_hz, hz,
 			       plat->tshsl_ns, plat->tsd2d_ns,
 			       plat->tchsh_ns, plat->tslch_ns);
 
-- 
2.20.1

[U-Boot] [RFC PATCH v2 17/18] arm: socfpga: gen5: parse qspi clock from devictree

[Simon Goldschmidt]

Remove the need for ad-hoc code for qspi speed.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 include/configs/socfpga_common.h | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1034ac280..e4a5dfc5ef 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -137,11 +137,6 @@
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SPI_FLASH_MTD
 #endif
-/* QSPI reference clock */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
-#endif
 
 /*
  * USB
-- 
2.20.1

[U-Boot] [RFC PATCH v2 18/18] socfpga: gen5: move CLK and SDRAM to DM

[Simon Goldschmidt]

- removed wrapper files for sdram & pll
- fix freeze_controller to not depend on OSC1 speed
- remove unused function definitions
- add autogenerated handoff dtsi for socfpga_socrates

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

Changes in v2: None

 .../dts/socfpga_cyclone5_socrates-u-boot.dtsi |   1 +
 .../socfpga_cyclone5_socrates_handoff.dtsi    | 290 ++++++++++++++++
 arch/arm/mach-socfpga/Makefile                |   4 -
 arch/arm/mach-socfpga/freeze_controller.c     |  10 +-
 .../include/mach/clock_manager_gen5.h         |   2 -
 .../mach-socfpga/include/mach/sdram_gen5.h    |   8 -
 arch/arm/mach-socfpga/wrap_pll_config.c       | 146 --------
 arch/arm/mach-socfpga/wrap_sdram_config.c     | 322 ------------------
 8 files changed, 297 insertions(+), 486 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
 delete mode 100644 arch/arm/mach-socfpga/wrap_pll_config.c
 delete mode 100644 arch/arm/mach-socfpga/wrap_sdram_config.c

diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
index 0a4d54e304..36ae10ab28 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include "socfpga-common-u-boot.dtsi"
+#include "socfpga_cyclone5_socrates_handoff.dtsi"
 
 /{
 	aliases {
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
new file mode 100644
index 0000000000..4e750796be
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *<auto-generated>
+ *	This code was generated by a tool based on
+ *	handoffs from both Qsys and Quartus.
+ *
+ *	Changes to this file may be lost if
+ *	the code is regenerated.
+ *</auto-generated>
+ */
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&osc2 {
+	clock-frequency = <25000000>;
+};
+
+&f2s_periph_ref_clk {
+	clock-frequency = <0>;
+};
+
+&f2s_sdram_ref_clk {
+	clock-frequency = <0>;
+};
+
+&clkmgr {
+	altr,clk-mgr-cfg = <0xf8010000 0x00000000 0x00000000 0x00000000
+			    0x03000000 0xff010000 0x0f000000 0x95000000
+			    0x04000000 0x00000000 0x03000000 0x38010000
+			    0xff010000 0x03000000 0xff010000 0x04000000
+			    0x04000000 0xff010000 0x40080000 0x69180000
+			    0x1a000000 0x78020200 0x01000000 0x00000000
+			    0x01080000 0x05000000 0x01000000>;
+};
+
+&scanmgr {
+	altr,pinmux-cfg = [00 02 02 02 02 02 02 02
+			   02 00 02 02 02 02 00 00
+			   00 00 00 00 03 00 03 03
+			   00 00 00 00 00 03 03 03
+			   00 01 01 01 01 00 00 01
+			   01 03 03 03 03 02 02 01
+			   01 01 01 00 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   02 02 02 02 02 02 02 02
+			   02 02 02 02 02 02 00 03
+			   03 03 03 03 03 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 01 01 01 01
+			   01 01 01 01 00 00 00 00
+			   00 00 00 00 00 00 00 00
+			   00 00 00 00 00 00 00];
+	altr,iocsr-scan-chain0-table = <0x00000000 0x00000000 0x0000f00f 0x000000c0
+					0x3f000000 0x00800000 0x24480000 0x00902001
+					0x00004082 0x04800100 0x00000000 0x00400000
+					0x12240000 0x00489000 0x00002041 0x02000080
+					0x04090000 0x00200000 0x09120000 0x00244800
+					0x00009020 0x01000040 0x82040000 0x00100000>;
+	altr,iocsr-scan-chain1-table = <0x48900000 0x00204102 0xc0008004 0x09000000
+					0x12240000 0x00800000 0x24480000 0x00902001
+					0x00004082 0x04000000 0x09120000 0x00400000
+					0x12240000 0x00489000 0x00002041 0x02000080
+					0x04090000 0x00200000 0x09120006 0x00244800
+					0x0000fe01 0x000000f8 0x07000000 0x00100080
+					0x04090000 0x00122400 0x00004890 0x00300020
+					0x41020000 0x00080000 0x00000000 0x00000000
+					0x00002448 0x00000090 0x20010000 0x00040000
+					0x00000000 0x80040900 0x03000000 0x00000000
+					0x00000000 0x00020090 0x20016000 0x00000000
+					0x00000912 0x00060024 0x48000000 0x00010048
+					0x90003000 0x204102c0 0x00800409 0x00030012
+					0x24000c00 0x80000000>;
+	altr,iocsr-scan-chain2-table = <0x48900030 0x00000000 0x0000f00f 0x00000000
+					0x1224000c 0x00800000 0x24480018 0x00000000
+					0x00004082 0x04800100 0x09120006 0x00400000
+					0x12240420 0x00489000 0x30000000 0x00000080
+					0x04090003 0x00200000 0x09120010 0x00244800
+					0x00009020 0x01000140 0x82040000 0x00100080
+					0x04090000 0x00000000 0x00004890 0x00800020
+					0x4102c000 0x00080000>;
+	altr,iocsr-scan-chain3-table = <0x800dc20c 0xff00300c 0x0140800a 0x00009007
+					0x00000208 0x00001000 0x0000800a 0x00009007
+					0x00000208 0x00001000 0x00004320 0x0130000c
+					0x8104c000 0x00000000 0x21000000 0x04000082
+					0x00004005 0x0000c803 0x00000104 0x00000800
+					0x00004005 0x0000c803 0x00004005 0x0000c803
+					0x00802190 0x00180086 0x40026000 0x18020980
+					0x01000000 0x02000040 0x0000a002 0x0000e401
+					0x0000a002 0x0000e401 0x0000a002 0x0000e401
+					0x0000a002 0x0000e401 0x00c01048 0x000c0043
+					0x20013000 0x0c8104c0 0x00300412 0x00030020
+					0x00000400 0x00006750 0x10000000 0x00005924
+					0x00100000 0x340000a0 0x0100000d 0x280a68c0
+					0x30400345 0x011a4812 0xd080a280 0x060c0334
+					0x5014a001 0x00000d28 0x0a68c030 0x40034902
+					0x1a0000d0 0x80a28006 0x00000410 0x00002000
+					0x00000410 0x00002000 0x00000015 0x0000200f
+					0x00000015 0x0000200f 0x0000fe01 0x00000018
+					0x02098001 0x60082400 0x06807f00 0x00000000
+					0x0100800a 0x00009007 0x0000800a 0x00009007
+					0x0000800a 0x00009007 0x00000208 0x00001000
+					0x00004320 0x0130000c 0x8104c000 0xf00f0000
+					0x00c01048 0x000c0080 0x00004005 0x00004802
+					0x00000004 0x00000800 0x00004005 0x0000c803
+					0x00004005 0x0000c803 0x00802190 0x00180086
+					0x40026000 0x18020980 0x01600824 0x00060040
+					0x4000a002 0x0000e401 0x0000a002 0x0000e401
+					0x0000a002 0x0000e401 0x0000a002 0x0000e401
+					0x00c01048 0x000c0043 0x20013000 0x0c8104c0
+					0x00300412 0x00030020 0x00000400 0x00006750
+					0x10000000 0x00005924 0x00100000 0x340000a0
+					0x0100000d 0x280a68c0 0x30400349 0x021a4812
+					0xd080a280 0x060c0334 0x4000a001 0x02000d28
+					0x0a68c030 0x40034902 0x1a280ad0 0x80a28006
+					0x00000410 0x00002000 0x00000410 0x00002000
+					0x00000015 0x0000200f 0x00000015 0x0000200f
+					0x0000fe01 0x00000018 0x02098001 0x60082400
+					0x06807f00 0x00000000 0x01003099 0x00343434
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00010400 0x00080000
+					0x00000000 0x08120000 0x00204800 0x00000001
+					0x00000000 0x82044100 0x00a00600 0x00b40100
+					0x00000200 0x00040000 0x00a00200 0x00e40100
+					0x00a00655 0x00d4e100 0x00000000 0x0c094320
+					0x01300000 0x00004090 0x00000000 0x43c22020
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x40000100 0x00020000
+					0x00000000 0x82040000 0x00081200 0x00200000
+					0x00000080 0x20411000 0x00020000 0x805f0dac
+					0xffffffff 0x0d69f314 0x1414041a 0x0000d000
+					0x00408618 0x067a2449 0xd5a328f2 0x1e45d1f6
+					0x88e34203 0x00001a82 0x00d00000 0x80061405
+					0x7a2449d9 0xa328f21e 0x45d1f688 0xe3520300
+					0x00020800 0x00100000 0x00020800 0x00100000
+					0x00800a00 0x00500700 0x00801a54 0x01508703
+					0x00000010 0x00000000 0x00c08000 0x00000041
+					0xc23f0000 0x00008200 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00010400 0x00080000 0x00000000 0x08120000
+					0x00204800 0x00800000 0x00000000 0x82044100
+					0x00a00600 0x00b40100 0x00000200 0x00040000
+					0x80000200 0x00040000 0x00a00655 0x00d4e100
+					0x00000000 0x0c090000 0x10000000 0x00004090
+					0x00000000 0x43c22020 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x00500100 0x00f20000 0x00000000 0x82040000
+					0x00081286 0x40026000 0x00000080 0x20411000
+					0x00020000 0x805f0dac 0xffffffff 0x0d69f314
+					0x1414041a 0x0000d000 0x00408618 0x067a2449
+					0xd523cff3 0x1e45d1f4 0x48924a03 0x8e031a82
+					0x00d00000 0x80060000 0x7a2449d9 0x23cff31e
+					0x45d1f488 0xe3520300 0x00020800 0x00100000
+					0x00020800 0x00100000 0x00800a00 0x00500700
+					0x00801a54 0x01508703 0x00000010 0x00000000
+					0x00c08000 0x00000041 0x02000004 0x00008200
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00010400 0x00080000
+					0x00000000 0x08120000 0x00204800 0x00800000
+					0x00000000 0x82044100 0x00a00600 0x00b40100
+					0x00000200 0x00040000 0x00a00200 0x00e40100
+					0x00a00655 0x00d4e100 0x00000000 0x0c094320
+					0x01300000 0x00004090 0x00000000 0x43c22020
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x40000100 0x00020000
+					0x00000000 0x82040000 0x00081200 0x00200000
+					0x00000080 0x20411000 0x00020000 0x805f0dac
+					0xffffffff 0x0d69f314 0x1414041a 0x0000d000
+					0x00408618 0x067a2449 0xd9a328f2 0x1e45d1f4
+					0x48924a03 0x00001a82 0x00d00000 0x80060000
+					0x7a2449d9 0xa328f21e 0x45d1f488 0xe3520300
+					0x00020800 0x00100000 0x00020800 0x00100000
+					0x00800a00 0x00500700 0x00801a54 0x01508703
+					0x00000010 0x00000000 0x00c08000 0x00000041
+					0x02000004 0x00008200 0x00400daa 0x00a8c301
+					0x00400daa 0x00a8c301 0x00400daa 0x00a8c301
+					0x00010400 0x00080000 0x00000000 0x08120000
+					0x00204800 0x00800000 0x00000000 0x82044100
+					0x00a00600 0x00b40100 0x00000200 0x00040000
+					0x80000200 0x00040000 0x00a00655 0x00d4e100
+					0x00000000 0x0c090000 0x10000000 0x00004090
+					0x00000000 0x43c22020 0x0050832a 0x00ea7000
+					0x0050832a 0x00ea7000 0x0050832a 0x00ea7000
+					0x40000100 0x00020000 0x00000000 0x82040000
+					0x00081200 0x00004000 0x00000080 0x20411000
+					0x00020000 0x805f0dac 0xffffffff 0x0d69f114
+					0x1414041a 0x0000d000 0x00408608 0x027a2449
+					0xd923cff3 0x1e45d1f4 0x88e34203 0x00001a82
+					0x00d00000 0x80060000 0x7a2449d9 0x23cff31e
+					0x79def488 0xa2420300 0x00020800 0x00100000
+					0x00020800 0x00100000 0x00800a00 0x00500700
+					0x00801a54 0x01508703 0x00000010 0x00000000
+					0x00c08000 0x00000041 0x02000004 0x00008200
+					0x00984800 0x1a1a1a80 0x00020000 0x04000080
+					0x00020000 0x04000080 0x00020000 0x04000080
+					0x00020000 0x04000000 0x00000400 0x00000010
+					0x00000000 0x40000000 0x00000100 0x00200040
+					0x00010000 0x02000040 0x00010000 0x02000040
+					0x00010000 0x02000040 0x00010000 0x02000000
+					0x00000200 0x00000008 0x00000000 0x20000000
+					0x00800000 0x00100020 0x80000000 0x01000020
+					0x80000000 0x01000020 0x80000000 0x01000020
+					0x80000000 0x01000000 0x00000100 0x00000004
+					0x0000ff00 0x00000000 0x00400000 0x00080000
+					0x010000c0 0x19140400 0x00000040 0x16080004
+					0x00000d00 0x00680000 0x40030000 0x1a0000d0
+					0x00008006 0x00003400 0x00a00100 0x000d0000
+					0x68000040 0x0300001a 0x0000d000 0x00800600
+					0x00340000 0xa0010000 0x01040000 0x08000000
+					0x01040000 0x08000000 0x01040000 0x08000000
+					0x01040000 0x08000080 0x7f000000 0x00000020
+					0x00000000 0x800000e0 0x1f000000 0x00400000>;
+};
+
+&sdr {
+	altr,sdr-cfg = <0x42800a00 0x060c3975 0x14a5aa08 0xc4222200
+			0x000e0000 0x00000800 0x01000000 0x00000000
+			0xea0d0000 0x20000000 0x08000000 0x00000000
+			0x30000000 0x02000000 0x02000000 0x55450400
+			0x0010012c 0x8800b000 0x10027600 0x43059800
+			0x6aa50500 0x00000000 0x00000000 0x00000000
+			0x8810fd3f 0x10420821 0x84ef8180 0x00000000
+			0x00f80000 0x20088220 0x08822008 0x41100441
+			0x10044100 0x01010101 0x01010101 0x01010000
+			0x00020000>;
+	altr,sdr-rw-mgr-cfg = [0d 0e 10 0f 49 4c 54 18
+			       1b 1f 19 1d 00 7b 7a 6f
+			       74 22 25 24 23 32 21 36
+			       39 38 37 46 35 02 08 07
+			       0c 03 09 04 0a 05 0b 12
+			       59 61 6b 14 01 7d 06 04
+			       00 04 20 08 08 04 04 01
+			       01 01 01];
+	altr,sdr-io-cfg = [77 00 19 19 08 00 1f 00
+			   07 1f 04 04 1f 1f 00 00];
+	altr,sdr-misc-cfg = [8d 04 55 55 01 07 05 00
+			     05 10 52 20 20 52 63 0a];
+	altr,sdr-ac-rom-init = <0x00007020 0x00007820 0x21020810 0x20030810
+				0x44000910 0x08000a10 0x00000b10 0x00043810
+				0x41020810 0xc0020810 0x24000a10 0x10000910
+				0x00000b10 0x00007830 0x00007838 0x00007830
+				0x00006810 0x00006b10 0x00042810 0x00004810
+				0x0000981c 0x00009b1c 0x0800981c 0x08009b1c
+				0x0000f838 0x0000f83c 0x00007838 0x00001818
+				0x00009818 0x00005813 0x00005b13 0x08005813
+				0x08005b13 0x00007833 0x08005810 0x00007810>;
+	altr,sdr-inst-rom-init = <0x00000800 0x80060800 0x80810000 0x00820000
+				  0x80820000 0x00830000 0x80830000 0x00810000
+				  0x80840000 0x00850000 0x80850000 0x00860000
+				  0x00840000 0x00080000 0x80860000 0x80080000
+				  0x80a60000 0x80060800 0x00090000 0x80060800
+				  0x80090000 0x80a60000 0x80860000 0x80060800
+				  0x680b0000 0xe8cc0000 0xe80a0000 0xe88c0000
+				  0x880b0000 0x88ec0000 0x080a0000 0x88ac0000
+				  0x80060800 0x00ce0000 0x80cd0000 0x00e70000
+				  0x000c0000 0xe00c0200 0xe00c0200 0xe00c0200
+				  0xe00c0200 0x000d0000 0x80060000 0x80060000
+				  0x80060000 0x80060000 0x800e0600 0x80100600
+				  0x80100600 0x80100600 0x80a60000 0x80860000
+				  0x80060800 0x00ce0000 0x80cd0000 0x00e70000
+				  0x000c0000 0xe00c0300 0xe00c0300 0xe00c0300
+				  0xe00c0300 0x000d0000 0x80060000 0x80060000
+				  0x80060000 0x80060000 0x800e0700 0x80100700
+				  0x80100700 0x80100700 0x80a60000 0x80860000
+				  0x80060800 0x58110000 0xd8060000 0x80060800
+				  0x68110000 0xe8070000 0xe8070000 0xe8870000
+				  0xe80f0400 0xe8100400 0xe8100400 0xe8100400
+				  0x68110000 0xe8070000 0xe8070000 0xe8a70000
+				  0x80060800 0x880e0400 0x88100400 0x88100400
+				  0x88100400 0x680f0400 0xe8100400 0xe8100400
+				  0xe8100400 0x80a60000 0xe80f0400 0xe8100400
+				  0xe8100400 0xe8100400 0x08100400 0x88100400
+				  0x88100400 0x88100400 0x00110000 0x80c60000
+				  0x80860000 0x80e60000 0x80060800 0x00000000
+				  0x00800000 0x00a00000 0x00c00000 0x00000800
+				  0x80000000 0x80800000 0x80a00000 0x80c00000
+				  0x80000800 0x80910000 0x80860000 0x80a60000
+				  0x80060800 0x080f0400 0x80060800>;
+};
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4b77990f74..c6281373f7 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -15,7 +15,6 @@ obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
 obj-y	+= system_manager_gen5.o
 obj-y	+= timer.o
-obj-y	+= wrap_pll_config.o
 obj-y	+= fpga_manager.o
 endif
 
@@ -44,7 +43,6 @@ obj-y	+= spl_gen5.o
 obj-y	+= freeze_controller.o
 obj-y	+= wrap_iocsr_config.o
 obj-y	+= wrap_pinmux_config.o
-obj-y	+= wrap_sdram_config.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
 obj-y	+= spl_a10.o
@@ -58,6 +56,4 @@ ifdef CONFIG_TARGET_SOCFPGA_GEN5
 # QTS-generated config file wrappers
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
-CFLAGS_wrap_pll_config.o	+= -I$(srctree)/board/$(BOARDDIR)
-CFLAGS_wrap_sdram_config.o	+= -I$(srctree)/board/$(BOARDDIR)
 endif
diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c
index d48aeec374..3ed6229631 100644
--- a/arch/arm/mach-socfpga/freeze_controller.c
+++ b/arch/arm/mach-socfpga/freeze_controller.c
@@ -109,7 +109,6 @@ void sys_mgr_frzctrl_thaw_req(void)
 	u32 reg_cfg_mask;
 	u32 reg_value;
 	u32 channel_id;
-	unsigned long eosc1_freq;
 
 	/* select software FSM */
 	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
@@ -160,9 +159,12 @@ void sys_mgr_frzctrl_thaw_req(void)
 	setbits_le32(&freeze_controller_base->hioctrl,
 		SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
 
-	/* Delay 1000 intosc cycles. The intosc is based on eosc1. */
-	eosc1_freq = cm_get_osc_clk_hz(1) / 1000;	/* kHz */
-	udelay(DIV_ROUND_UP(1000000, eosc1_freq));
+	/*
+	 * Delay 1000 intosc cycles. The intosc is based on eosc1.
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 1000 = 20us
+	 */
+	udelay(20);
 
 	/*
 	 * de-assert active low bhniotri signals,
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index a9efe2a377..3b52986f78 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -111,8 +111,6 @@ struct socfpga_clock_manager {
 	u32	_pad_0xe8_0x200[70];
 };
 
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
 #endif /* __ASSEMBLER__ */
 
 #define LOCKED_MASK \
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index 7353b1c5e6..47b5793271 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -7,14 +7,6 @@
 
 #ifndef __ASSEMBLY__
 
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
 #define SDR_CTRLGRP_ADDRESS	(SOCFPGA_SDR_ADDRESS | 0x5000)
 
 struct socfpga_sdr_ctrl {
diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
deleted file mode 100644
index bd631e0fb5..0000000000
--- a/arch/arm/mach-socfpga/wrap_pll_config.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock_manager.h>
-#include <qts/pll_config.h>
-
-#define MAIN_VCO_BASE (					\
-	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
-		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
-		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define PERI_VCO_BASE (					\
-	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
-		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
-		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
-		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define SDR_VCO_BASE (					\
-	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
-		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
-		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
-		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-static const struct cm_config cm_default_cfg = {
-	/* main group */
-	MAIN_VCO_BASE,
-	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
-		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
-		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
-		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
-		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
-		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
-		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
-		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
-		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
-	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
-		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
-	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
-		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
-	/* peripheral group */
-	PERI_VCO_BASE,
-	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
-		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
-		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
-		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
-		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
-		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
-		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
-		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
-		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
-		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
-		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
-		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
-	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
-		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
-		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
-	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
-		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
-	/* sdram pll group */
-	SDR_VCO_BASE,
-	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
-		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
-		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
-		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
-		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
-	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
-	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
-		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
-	/* altera group */
-	CONFIG_HPS_ALTERAGRP_MPUCLK,
-};
-
-const struct cm_config * const cm_get_default_config(void)
-{
-	return &cm_default_cfg;
-}
-
-const unsigned int cm_get_osc_clk_hz(const int osc)
-{
-	if (osc == 1)
-		return CONFIG_HPS_CLK_OSC1_HZ;
-	else if (osc == 2)
-		return CONFIG_HPS_CLK_OSC2_HZ;
-	else
-		return 0;
-}
-
-const unsigned int cm_get_f2s_per_ref_clk_hz(void)
-{
-	return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-}
-
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
-{
-	return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
-}
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
deleted file mode 100644
index c43c2423a0..0000000000
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ /dev/null
@@ -1,322 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/arch/sdram.h>
-
-/* Board-specific header. */
-#include <qts/sdram_config.h>
-
-static const struct socfpga_sdram_config sdram_config = {
-	.ctrl_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
-			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
-			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
-			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
-			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
-			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
-			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
-			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
-			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
-			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
-	.dram_timing1 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
-			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
-			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
-			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
-			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
-			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
-			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
-	.dram_timing2 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
-			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
-			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
-			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
-			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
-			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
-	.dram_timing3 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
-			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
-			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
-			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
-			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
-			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
-	.dram_timing4 =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
-			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
-			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
-	.lowpwr_timing =
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
-			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
-			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
-	.dram_odt =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
-			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
-			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-	.extratime1 =
-	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
-			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
-	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
-			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
-(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
-			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
-	.dram_addrw =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
-			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
-			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
-			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
-		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
-			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
-	.dram_if_width =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
-			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
-	.dram_dev_width =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
-			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
-	.dram_intr =
-		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
-			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
-	.lowpwr_eq =
-		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
-			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
-	.static_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
-			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
-			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
-	.ctrl_width =
-		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
-			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
-	.cport_width =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
-			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
-	.cport_wmap =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
-			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
-	.cport_rmap =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
-			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
-	.rfifo_cmap =
-		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
-			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
-	.wfifo_cmap =
-		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
-			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
-	.cport_rdwr =
-		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
-			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
-	.port_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
-			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
-	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
-	.fifo_cfg =
-		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
-			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
-		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
-			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
-	.mp_priority =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
-			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
-	.mp_weight0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
-	.mp_weight1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
-	.mp_weight2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
-	.mp_weight3 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
-			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
-	.mp_pacing0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
-	.mp_pacing1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
-	.mp_pacing2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
-	.mp_pacing3 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
-			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
-	.mp_threshold0 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
-			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
-	.mp_threshold1 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
-			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
-	.mp_threshold2 =
-		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
-			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
-	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
-};
-
-static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
-	.activate_0_and_1		= RW_MGR_ACTIVATE_0_AND_1,
-	.activate_0_and_1_wait1		= RW_MGR_ACTIVATE_0_AND_1_WAIT1,
-	.activate_0_and_1_wait2		= RW_MGR_ACTIVATE_0_AND_1_WAIT2,
-	.activate_1			= RW_MGR_ACTIVATE_1,
-	.clear_dqs_enable		= RW_MGR_CLEAR_DQS_ENABLE,
-	.guaranteed_read		= RW_MGR_GUARANTEED_READ,
-	.guaranteed_read_cont		= RW_MGR_GUARANTEED_READ_CONT,
-	.guaranteed_write		= RW_MGR_GUARANTEED_WRITE,
-	.guaranteed_write_wait0		= RW_MGR_GUARANTEED_WRITE_WAIT0,
-	.guaranteed_write_wait1		= RW_MGR_GUARANTEED_WRITE_WAIT1,
-	.guaranteed_write_wait2		= RW_MGR_GUARANTEED_WRITE_WAIT2,
-	.guaranteed_write_wait3		= RW_MGR_GUARANTEED_WRITE_WAIT3,
-	.idle				= RW_MGR_IDLE,
-	.idle_loop1			= RW_MGR_IDLE_LOOP1,
-	.idle_loop2			= RW_MGR_IDLE_LOOP2,
-	.init_reset_0_cke_0		= RW_MGR_INIT_RESET_0_CKE_0,
-	.init_reset_1_cke_0		= RW_MGR_INIT_RESET_1_CKE_0,
-	.lfsr_wr_rd_bank_0		= RW_MGR_LFSR_WR_RD_BANK_0,
-	.lfsr_wr_rd_bank_0_data		= RW_MGR_LFSR_WR_RD_BANK_0_DATA,
-	.lfsr_wr_rd_bank_0_dqs		= RW_MGR_LFSR_WR_RD_BANK_0_DQS,
-	.lfsr_wr_rd_bank_0_nop		= RW_MGR_LFSR_WR_RD_BANK_0_NOP,
-	.lfsr_wr_rd_bank_0_wait		= RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
-	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
-	.lfsr_wr_rd_dm_bank_0		= RW_MGR_LFSR_WR_RD_DM_BANK_0,
-	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
-	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
-	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
-	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
-	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
-	.mrs0_dll_reset			= RW_MGR_MRS0_DLL_RESET,
-	.mrs0_dll_reset_mirr		= RW_MGR_MRS0_DLL_RESET_MIRR,
-	.mrs0_user			= RW_MGR_MRS0_USER,
-	.mrs0_user_mirr			= RW_MGR_MRS0_USER_MIRR,
-	.mrs1				= RW_MGR_MRS1,
-	.mrs1_mirr			= RW_MGR_MRS1_MIRR,
-	.mrs2				= RW_MGR_MRS2,
-	.mrs2_mirr			= RW_MGR_MRS2_MIRR,
-	.mrs3				= RW_MGR_MRS3,
-	.mrs3_mirr			= RW_MGR_MRS3_MIRR,
-	.precharge_all			= RW_MGR_PRECHARGE_ALL,
-	.read_b2b			= RW_MGR_READ_B2B,
-	.read_b2b_wait1			= RW_MGR_READ_B2B_WAIT1,
-	.read_b2b_wait2			= RW_MGR_READ_B2B_WAIT2,
-	.refresh_all			= RW_MGR_REFRESH_ALL,
-	.rreturn			= RW_MGR_RETURN,
-	.sgle_read			= RW_MGR_SGLE_READ,
-	.zqcl				= RW_MGR_ZQCL,
-
-	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
-	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
-	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
-	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
-	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
-	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
-	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
-	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
-	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
-	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
-	.mem_virtual_groups_per_read_dqs =
-		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
-	.mem_virtual_groups_per_write_dqs =
-		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
-};
-
-static const struct socfpga_sdram_io_config io_config = {
-	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
-	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
-	.delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,
-	.delay_per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
-	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
-	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
-	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
-	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
-	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
-	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
-	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
-	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
-	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
-	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
-	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
-	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
-};
-
-static const struct socfpga_sdram_misc_config misc_config = {
-	.afi_rate_ratio			= AFI_RATE_RATIO,
-	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
-	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
-	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
-	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
-	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
-	.reg_file_init_seq_signature_ll	= REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
-	.reg_file_init_seq_signature_lh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
-	.reg_file_init_seq_signature_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
-	.reg_file_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
-	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
-	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
-	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
-	.treset_cntr0_val		= TRESET_CNTR0_VAL,
-	.treset_cntr1_val		= TRESET_CNTR1_VAL,
-	.treset_cntr2_val		= TRESET_CNTR2_VAL,
-};
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
-{
-	return &sdram_config;
-}
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
-{
-	*init = ac_rom_init;
-	*nelem = ARRAY_SIZE(ac_rom_init);
-}
-
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
-{
-	*init = inst_rom_init;
-	*nelem = ARRAY_SIZE(inst_rom_init);
-}
-
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
-{
-	return &rw_mgr_config;
-}
-
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
-{
-	return &io_config;
-}
-
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
-{
-	return &misc_config;
-}
-- 
2.20.1

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Dalon L Westergreen]

I mentioned this before, it would be great to not rely on the generated filesand
do this based purely on the handoff data generated during a quartusbuild.  Did
you look at the python source i pointed you to?
--dalon
On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
> This new tool converts handoff information from quartus to
> "*_handoff.dtsi"devicetree files. This is in preparation to move from ad-hoc
> code in archthat parses the 'qts' header files to drivers parsing the same
> informationfrom devicetree.
> Converting existing U-Boot 'qts' files is also supported.
> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>---
> Changes in v2: None
>  arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
> arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++ 2 files changed, 743
> insertions(+) create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
> create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
> diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-
> socfpga/create_handoff_gen5.cnew file mode 100644index 0000000000..6ec436719d-
> -- /dev/null+++ b/arch/arm/mach-socfpga/create_handoff_gen5.c@@ -0,0 +1,660
> @@+// SPDX-License-Identifier: GPL-2.0+/*+ * This is a host-tool that needs to
> be compiled per board and prints the+ * handoff.dtsi to stdout.+ */++#include
> <stdio.h>+#include <stdint.h>++/* Define kernel types */+typedef uint8_t
> u8;+typedef uint32_t u32;++#ifdef USE_QUARTUS_OUTPUT+#ifdef ARRIA5+#include
> "iocsr_config_arria5.c"+#include "pinmux_config_arria5.c"+#else+#include
> "iocsr_config_cyclone5.c"+#include "pinmux_config_cyclone5.c"+#endif+#include
> "pll_config.h"+#include "sdram/sdram_config.h"+#include
> "sequencer_auto.h"+#include "sequencer_defines.h"+#include
> "sequencer_auto_ac_init.c"+#include "sequencer_auto_inst_init.c"+#define
> RW_MGR(x) __RW_MGR_##x+#else+#define RW_MGR(x) RW_MGR_##x+#include
> <iocsr_config.h>+#include <pinmux_config.h>+#include <pll_config.h>+#include
> <sdram_config.h>+#endif++#include "include/mach/clock_manager_gen5.h"+#include
> "include/mach/sdram_gen5.h"++#ifndef ARRAY_SIZE+#define ARRAY_SIZE(x)
> (sizeof(x)/sizeof((x)[0]))+#endif++const char handoff_dtsi_hdr[] =+	"//
> SPDX-License-Identifier: GPL-2.0\n"+	"/*\n"+	" *<auto-generated>\n"+	" *	
> This code was generated by a tool based on\n"+	" *	handoffs from
> both Qsys and Quartus.\n"+	" *\n"+	" *	Changes to this file may be
> lost if\n"+	" *	the code is regenerated.\n"+	" *</auto-
> generated>\n"+	" */\n";++/* Wrap PLL config */++#define MAIN_VCO_BASE (
> 					\+	(CONFIG_HPS_MAINPLLGRP_VCO_DEN
> OM <<		\+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\+	
> (CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\+		CLKMGR_MAINPLL
> GRP_VCO_NUMER_OFFSET)	\+	)++#define PERI_VCO_BASE (			
> 		\+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\+	
> 	CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\+	(CONFIG_HPS_PERPLLGRP_
> VCO_DENOM <<		\+		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	
> \+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\+		CLKMGR
> _PERPLLGRP_VCO_NUMER_OFFSET)	\+	)++#define SDR_VCO_BASE (		
> 			\+	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		
> \+		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\+	(CONFIG_HPS_SD
> RPLLGRP_VCO_DENOM <<		\+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFF
> SET) |	\+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\+	
> 	CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\+	)++static const struct
> cm_config cm_default = {+	/* main group */+	MAIN_VCO_BASE,+	(CONFIG_HPS_MA
> INPLLGRP_MPUCLK_CNT <<+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),+	
> (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<+		CLKMGR_MAINPLLGRP_MAINCL
> K_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<+		CLKMGR
> _MAINPLLGRP_DBGATCLK_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
> <<+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),+	(CONFIG_HPS_MA
> INPLLGRP_MAINNANDSDMMCCLK_CNT <<+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK
> _CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<+		
> CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_M
> AINDIV_L3MPCLK <<+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |+	
> (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<+		CLKMGR_MAINPLLGRP_MAINDI
> V_L3SPCLK_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<+		
> CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L
> 4SPCLK <<+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),+	(CONFI
> G_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCL
> K_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<+		CLKMGR_MAINPLL
> GRP_DBGDIV_DBGCLK_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<+	
> 	CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),+	(CONFIG_HPS_MAINPLLGRP
> _L4SRC_L4MP <<+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |+	(CONFI
> G_HPS_MAINPLLGRP_L4SRC_L4SP <<+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFF
> SET),++	/* peripheral group */+	PERI_VCO_BASE,+	(CONFIG_HPS_PERPLLGRP_
> EMAC0CLK_CNT <<+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),+	(CONFI
> G_HPS_PERPLLGRP_EMAC1CLK_CNT <<+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OF
> FSET),+	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<+		CLKMGR_PERPLLG
> RP_PERQSPICLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<+	
> 	CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_
> PERBASECLK_CNT <<+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),+	(CONFI
> G_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT
> _OFFSET),+	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<+		CLKMGR_PERPLLG
> RP_DIV_USBCLK_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<+		
> CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CL
> K <<+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_
> DIV_CAN1CLK <<+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),+	(CONFI
> G_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBC
> LK_OFFSET),+	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<+		CLKMGR_PERPLLG
> RP_SRC_QSPI_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<+		
> CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<+	
> 	CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),++	/* sdram pll group */+	SDR_VC
> O_BASE,+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<+		CLKMGR_SDRPLLG
> RP_DDRDQSCLK_PHASE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<+		
> CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCL
> K_PHASE <<+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |+	(CONFI
> G_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT
> _OFFSET),+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<+		CLKMGR_SDRPLLG
> RP_DDRDQCLK_PHASE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<+		
> CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CL
> K_PHASE <<+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |+	(CONFI
> G_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT
> _OFFSET),++	/* altera group */+	CONFIG_HPS_ALTERAGRP_MPUCLK,+};++/*
> Wrap SDRAM config */+static const struct socfpga_sdram_config sdram_config =
> {+	.ctrl_cfg =+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<+	
> 		SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|+		(CONFI
> G_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<+			SDR_CTRLGRP_CTRLCFG_MEMB
> L_LSB)			|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCF
> G_ADDRORDER <<+			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)	
> 	|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<+		
> 	SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|+		(CONFI
> G_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<+			SDR_CTRLGRP_CTRL
> CFG_ECCCORREN_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCF
> G_REORDEREN <<+			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)	
> 	|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<+		
> 	SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|+		(CONFI
> G_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<+			SDR_CTRLGRP_CTRL
> CFG_DQSTRKEN_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCF
> G_NODMPINS <<+			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),+	
> .dram_timing1 =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<+	
> 		SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|+		(CONFI
> G_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<+			SDR_CTRLGRP_DRAMTIMING1_
> TAL_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TC
> L <<+			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|+		
> (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<+			SDR_CTRLGRP_DRAM
> TIMING1_TRRD_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTI
> MING1_TFAW <<+			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		
> |+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<+			
> SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),+	.dram_timing2 =+		(CONFIG_HPS_SD
> R_CTRLCFG_DRAMTIMING2_IF_TREFI <<+			SDR_CTRLGRP_DRAMTIMING2_
> TREFI_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF
> _TRCD <<+			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|+	
> 	(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<+			SDR_CT
> RLGRP_DRAMTIMING2_TRP_LSB)		|+		(CONFIG_HPS_SDR_CTRLCF
> G_DRAMTIMING2_IF_TWR <<+			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)
> 		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
> <<+			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),+	.dram_timing3
> =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<+			
> SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|+		(CONFIG_HPS_SD
> R_CTRLCFG_DRAMTIMING3_TRAS <<+			SDR_CTRLGRP_DRAMTIMING3_
> TRAS_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TR
> C <<+			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|+		
> (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<+			SDR_CTRLGRP_DRAM
> TIMING3_TMRD_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTI
> MING3_TCCD <<+			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),+	
> .dram_timing4 =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
> <<+			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|+		
> (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<+			SDR_CTRL
> GRP_DRAMTIMING4_PWRDOWNEXIT_LSB),+	.lowpwr_timing =+		(CONFIG_HPS_SD
> R_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<+			SDR_CTRLGRP_LOWP
> WRTIMING_AUTOPDCYCLES_LSB)	|+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWR
> TIMING_CLKDISABLECYCLES <<+			SDR_CTRLGRP_LOWPWRTIMING_CLKDISA
> BLECYCLES_LSB),+	.dram_odt =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMOD
> T_READ <<+			SDR_CTRLGRP_DRAMODT_READ_LSB)			
> |+		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<+			SDR_CT
> RLGRP_DRAMODT_WRITE_LSB),+	.extratime1 =+	(CONFIG_HPS_SDR_CTRLCFG_EXTRAT
> IME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<+			SDR_CTRLGRP_EXTRATIME1_R
> D_TO_WR_LSB)		|+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_C
> TL_CLK_RD_TO_WR_BC <<+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_
> BC_LSB)		|+(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_R
> D_TO_WR_DIFF_CHIP <<+			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB
> ),+	.dram_addrw =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<+	
> 		SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|+		
> (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<+			SDR_CTRLGRP_DRAM
> ADDRW_ROWBITS_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMAD
> DRW_BANKBITS <<+			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)	
> 	|+		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<+	
> 		SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),+	.dram_if_width =+	
> 	(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<+			SDR_CT
> RLGRP_DRAMIFWIDTH_IFWIDTH_LSB),+	.dram_dev_width =+		(CONFI
> G_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<+			SDR_CTRLGRP_DRAM
> DEVWIDTH_DEVWIDTH_LSB),+	.dram_intr =+		(CONFIG_HPS_SDR_CTRLCF
> G_DRAMINTR_INTREN <<+			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),+	
> .lowpwr_eq =+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<+		
> 	SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),+	.static_cfg =+		(CONFI
> G_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<+			SDR_CTRLGRP_STATICCFG_ME
> MBL_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEE
> CCASDATA <<+			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),+	.ctrl_
> width =+		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<+		
> 	SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),+	.cport_width =+		(CONFI
> G_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<+			SDR_CTRLGRP_CPOR
> TWIDTH_CMDPORTWIDTH_LSB),+	.cport_wmap =+		(CONFIG_HPS_SDR_CTRLCF
> G_CPORTWMAP_CPORTWMAP <<+			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFO
> MAP_LSB),+	.cport_rmap =+		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPOR
> TRMAP <<+			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),+	
> .rfifo_cmap =+		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<+	
> 		SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),+	.wfifo_cmap =+
> 		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<+			
> SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),+	.cport_rdwr =+		(CONFI
> G_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<+			SDR_CTRLGRP_CPOR
> TRDWR_CPORTRDWR_LSB),+	.port_cfg =+		(CONFIG_HPS_SDR_CTRLCF
> G_PORTCFG_AUTOPCHEN <<+			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LS
> B),+	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,+	.fifo_cfg =+	
> 	(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<+			SDR_CT
> RLGRP_FIFOCFG_SYNCMODE_LSB)		|+		(CONFIG_HPS_SDR_CTRLCF
> G_FIFOCFG_INCSYNC <<+			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),+	
> .mp_priority =+		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
> <<+			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),+	.mp_we
> ight0 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
> <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),+
> 	.mp_weight1 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIG
> HT_49_32 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_
> 32_LSB) |+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<+
> 			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB)
> ,+	.mp_weight2 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGH
> T_45_14 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_
> 14_LSB),+	.mp_weight3 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SU
> MOFWEIGHT_63_46 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEI
> GHTS_63_46_LSB),+	.mp_pacing0 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACI
> NG_0_THRESHOLD1_31_0 <<+			SDR_CTRLGRP_MPPACING_MPPACING_0_
> THRESHOLD1_31_0_LSB),+	.mp_pacing1 =+		(CONFIG_HPS_SDR_CTRLCF
> G_MPPACING_1_THRESHOLD1_59_32 <<+			SDR_CTRLGRP_MPPACING_MPP
> ACING_1_THRESHOLD1_59_32_LSB) |+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING
> _1_THRESHOLD2_3_0 <<+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOL
> D2_3_0_LSB),+	.mp_pacing2 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THR
> ESHOLD2_35_4 <<+			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOL
> D2_35_4_LSB),+	.mp_pacing3 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACI
> NG_3_THRESHOLD2_59_36 <<+			SDR_CTRLGRP_MPPACING_MPPACING_3_
> THRESHOLD2_59_36_LSB),+	.mp_threshold0 =+		(CONFIG_HPS_SDR_CTRLCF
> G_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<+			SDR_CTRL
> GRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),+	.mp_threshold1 =+		
> (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<+			
> SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),+	.mp_threshold2
> =+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_6
> 4 <<+			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LS
> B),+	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,+};++static const
> struct socfpga_sdram_rw_mgr_config rw_mgr_config = {+	.activate_0_and_1		
> = RW_MGR(ACTIVATE_0_AND_1),+	.activate_0_and_1_wait1		=
> RW_MGR(ACTIVATE_0_AND_1_WAIT1),+	.activate_0_and_1_wait2		=
> RW_MGR(ACTIVATE_0_AND_1_WAIT2),+	.activate_1			=
> RW_MGR(ACTIVATE_1),+	.clear_dqs_enable		= RW_MGR(CLEAR_DQS_ENABLE),+	
> .guaranteed_read		= RW_MGR(GUARANTEED_READ),+	.guaranteed_re
> ad_cont		= RW_MGR(GUARANTEED_READ_CONT),+	.guaranteed_write	
> 	= RW_MGR(GUARANTEED_WRITE),+	.guaranteed_write_wait0		=
> RW_MGR(GUARANTEED_WRITE_WAIT0),+	.guaranteed_write_wait1		=
> RW_MGR(GUARANTEED_WRITE_WAIT1),+	.guaranteed_write_wait2		=
> RW_MGR(GUARANTEED_WRITE_WAIT2),+	.guaranteed_write_wait3		=
> RW_MGR(GUARANTEED_WRITE_WAIT3),+	.idle				=
> RW_MGR(IDLE),+	.idle_loop1			= RW_MGR(IDLE_LOOP1),+
> 	.idle_loop2			= RW_MGR(IDLE_LOOP2),+	.init_reset_0_
> cke_0		= RW_MGR(INIT_RESET_0_CKE_0),+	.init_reset_1_cke_0		
> = RW_MGR(INIT_RESET_1_CKE_0),+	.lfsr_wr_rd_bank_0		=
> RW_MGR(LFSR_WR_RD_BANK_0),+	.lfsr_wr_rd_bank_0_data		=
> RW_MGR(LFSR_WR_RD_BANK_0_DATA),+	.lfsr_wr_rd_bank_0_dqs		=
> RW_MGR(LFSR_WR_RD_BANK_0_DQS),+	.lfsr_wr_rd_bank_0_nop		=
> RW_MGR(LFSR_WR_RD_BANK_0_NOP),+	.lfsr_wr_rd_bank_0_wait		=
> RW_MGR(LFSR_WR_RD_BANK_0_WAIT),+	.lfsr_wr_rd_bank_0_wl_1		=
> RW_MGR(LFSR_WR_RD_BANK_0_WL_1),+	.lfsr_wr_rd_dm_bank_0		=
> RW_MGR(LFSR_WR_RD_DM_BANK_0),+	.lfsr_wr_rd_dm_bank_0_data	=
> RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),+	.lfsr_wr_rd_dm_bank_0_dqs	=
> RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),+	.lfsr_wr_rd_dm_bank_0_nop	=
> RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),+	.lfsr_wr_rd_dm_bank_0_wait	=
> RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),+	.lfsr_wr_rd_dm_bank_0_wl_1	=
> RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),+	.mrs0_dll_reset			=
> RW_MGR(MRS0_DLL_RESET),+	.mrs0_dll_reset_mirr		=
> RW_MGR(MRS0_DLL_RESET_MIRR),+	.mrs0_user			=
> RW_MGR(MRS0_USER),+	.mrs0_user_mirr			=
> RW_MGR(MRS0_USER_MIRR),+	.mrs1				=
> RW_MGR(MRS1),+	.mrs1_mirr			= RW_MGR(MRS1_MIRR),+	
> .mrs2				= RW_MGR(MRS2),+	.mrs2_mirr			
> = RW_MGR(MRS2_MIRR),+	.mrs3				= RW_MGR(MRS3),+	
> .mrs3_mirr			= RW_MGR(MRS3_MIRR),+	.precharge_all		
> 	= RW_MGR(PRECHARGE_ALL),+	.read_b2b			=
> RW_MGR(READ_B2B),+	.read_b2b_wait1			=
> RW_MGR(READ_B2B_WAIT1),+	.read_b2b_wait2			=
> RW_MGR(READ_B2B_WAIT2),+	.refresh_all			=
> RW_MGR(REFRESH_ALL),+	.rreturn			= RW_MGR(RETURN),+	.sgle_
> read			= RW_MGR(SGLE_READ),+	.zqcl				
> = RW_MGR(ZQCL),++	.true_mem_data_mask_width	=
> RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,+	.mem_address_mirroring		=
> RW_MGR_MEM_ADDRESS_MIRRORING,+	.mem_data_mask_width		=
> RW_MGR_MEM_DATA_MASK_WIDTH,+	.mem_data_width			=
> RW_MGR_MEM_DATA_WIDTH,+	.mem_dq_per_read_dqs		=
> RW_MGR_MEM_DQ_PER_READ_DQS,+	.mem_dq_per_write_dqs		=
> RW_MGR_MEM_DQ_PER_WRITE_DQS,+	.mem_if_read_dqs_width		=
> RW_MGR_MEM_IF_READ_DQS_WIDTH,+	.mem_if_write_dqs_width		=
> RW_MGR_MEM_IF_WRITE_DQS_WIDTH,+	.mem_number_of_cs_per_dimm	=
> RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,+	.mem_number_of_ranks		=
> RW_MGR_MEM_NUMBER_OF_RANKS,+	.mem_virtual_groups_per_read_dqs =+		
> RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,+	.mem_virtual_groups_per_write_dq
> s =+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,+};++static const struct
> socfpga_sdram_io_config io_config = {+	.delay_per_dchain_tap		
> = IO_DELAY_PER_DCHAIN_TAP,+	.delay_per_dqs_en_dchain_tap	=
> IO_DELAY_PER_DQS_EN_DCHAIN_TAP,+	.delay_per_opa_tap_lo		=
> IO_DELAY_PER_OPA_TAP & 0xff,+	.delay_per_opa_tap_hi		=
> (IO_DELAY_PER_OPA_TAP << 8) & 0xff,+	.dll_chain_length		=
> IO_DLL_CHAIN_LENGTH,+	.dqdqs_out_phase_max		=
> IO_DQDQS_OUT_PHASE_MAX,+	.dqs_en_delay_max		=
> IO_DQS_EN_DELAY_MAX,+	.dqs_en_delay_offset		=
> IO_DQS_EN_DELAY_OFFSET,+	.dqs_en_phase_max		=
> IO_DQS_EN_PHASE_MAX,+	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,+	.dqs_i
> n_reserve			= IO_DQS_IN_RESERVE,+	.dqs_out_reserve	
> 	= IO_DQS_OUT_RESERVE,+	.io_in_delay_max		=
> IO_IO_IN_DELAY_MAX,+	.io_out1_delay_max		=
> IO_IO_OUT1_DELAY_MAX,+	.io_out2_delay_max		=
> IO_IO_OUT2_DELAY_MAX,+	.shift_dqs_en_when_shift_dqs	=
> IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,+};++static const struct
> socfpga_sdram_misc_config misc_config = {+	.afi_rate_ratio			
> = AFI_RATE_RATIO,+	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,+
> 	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,+	.enable_super_
> quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,+	.max_latency_c
> ount_width	= MAX_LATENCY_COUNT_WIDTH,+	.read_valid_fifo_size		
> = READ_VALID_FIFO_SIZE,+	.reg_file_init_seq_signature_ll	=
> REG_FILE_INIT_SEQ_SIGNATURE & 0xff,+	.reg_file_init_seq_signature_lh	=
> (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,+	.reg_file_init_seq_signature_hl	
> = (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,+	.reg_file_init_seq_signa
> ture_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,+	.tinit_cntr0_v
> al		= TINIT_CNTR0_VAL,+	.tinit_cntr1_val		=
> TINIT_CNTR1_VAL,+	.tinit_cntr2_val		= TINIT_CNTR2_VAL,+	.trese
> t_cntr0_val		= TRESET_CNTR0_VAL,+	.treset_cntr1_val		
> = TRESET_CNTR1_VAL,+	.treset_cntr2_val		= TRESET_CNTR2_VAL,+};++static
> void print_hdr(void)+{+	printf(handoff_dtsi_hdr);+}++static void
> print_clkmgr_base(void)+{+	const char handoff_dtsi_clkmgr_base[] =+		
> "\n"+		"&osc1 {\n"+		"	clock-frequency = <%d>;\n" /*
> CONFIG_HPS_CLK_OSC1_HZ */+		"};\n"+		"\n"+		"&osc2
> {\n"+		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */+	
> 	"};\n"+		"\n"+		"&f2s_periph_ref_clk {\n"+		
> "	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */+		
> "};\n"+		"\n"+		"&f2s_sdram_ref_clk {\n"+		
> "	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */+		
> "};\n";++	printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,+	      
>  CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,+	       CONFIG_HP
> S_CLK_F2S_SDR_REF_HZ);+}++/*+ * dtc stores u32 array big endian but we load
> them raw and expect them to be in+ * little endian format. To prevent this
> tool to depend on host endianess, do+ * the switch manually, not via 'htonl'.+
> */+static u32 swap_bytes(u32 val)+{+	return (val << 24) | ((val & 0xFF00ul)
> << 8) |+		((val & 0xFF0000ul) >> 8) | (val >> 24);+}++static void
> print_array_ulong(const unsigned long *arr, size_t arr_size,+			
>       size_t el_per_line, const char *indent1,+			      const
> char *name, const char *indent_next)+{+	size_t i;++	printf("%s%s =
> <", indent1, name);+	for (i = 0; i < arr_size; i++) {+		printf("0x%08x
> ", swap_bytes((u32)arr[i]));+		if (i + 1 < arr_size) {+			
> if (i % el_per_line == (el_per_line - 1)) {+				printf("
> \n%s", indent_next);+			} else {+				printf
> (" ");+			}+		}+	}+	printf(">;\n")
> ;+}++#ifdef USE_QUARTUS_OUTPUT+static void print_array_sysmgrinit(const
> unsigned long *arr, size_t arr_size,+				   const char
> *indent1, const char *name,+				   const char
> *indent_next)+{+	size_t i;++	printf("%s%s = [", indent1, name);+	
> for (i = 0; i < arr_size; i++) {+		printf("%02x", (u8)arr[i]);+	
> 	if (i + 1 < arr_size) {+			if (i % 8 == 7) {+		
> 		printf("\n%s", indent_next);+			} else {+	
> 			printf(" ");+			}+		}+	
> }+	printf("];\n");+}+#define print_array_alt_u32
> print_array_ulong+#else+#define print_array_sysmgrinit(arr, sz, ind1, n, ind2)
> print_array_u8(arr, sz, 8, ind1, n, ind2)+#define print_array_alt_u32
> print_array_u32+#endif++static void print_array_u32(const u32 *arr, size_t
> arr_size,+			    size_t el_per_line, const char *indent1,+	
> 		    const char *name, const char *indent_next)+{+	size_t i;++	
> printf("%s%s = <", indent1, name);+	for (i = 0; i < arr_size; i++) {+		
> printf("0x%08x", swap_bytes(arr[i]));+		if (i + 1 < arr_size) {+
> 			if (i % el_per_line == (el_per_line - 1)) {+		
> 		printf("\n%s", indent_next);+			} else {+	
> 			printf(" ");+			}+		}+	
> }+	printf(">;\n");+}++static void print_array_u8(const u8 *arr, size_t
> arr_size, size_t el_per_line,+			   const char *indent1,
> const char *name,+			   const char *indent_next)+{+	size_t
> i;++	printf("%s%s = [", indent1, name);+	for (i = 0; i < arr_size; i++)
> {+		printf("%02x", arr[i]);+		if (i + 1 < arr_size) {+	
> 		if (i % el_per_line == (el_per_line - 1)) {+			
> 	printf("\n%s", indent_next);+			} else {+		
> 		printf(" ");+			}+		}+	}+	
> printf("];\n");+}+++static void print_clkmgr_cfg(void)+{+	const char
> handoff_dtsi_clkmgr_cfg_a[] =+		"\n"+		"&clkmgr
> {\n";+	const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";+	const char
> clk_mgr_cfg_indent[] = "\t\t\t    ";++	printf(handoff_dtsi_clkmgr_cfg_a
> );+	print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4,
> "\t",+			"altr,clk-mgr-cfg", clk_mgr_cfg_indent);+	printf
> (handoff_dtsi_clkmgr_cfg_b);+}++static void print_sysmgr(void)+{+	const
> char handoff_dtsi_sysmgr_begin[] =+		"\n"+		"&sysmgr
> {\n";+	const char handoff_dtsi_sysmgr_end[] = "};\n";+	const char
> sysmgr_cfg_indent[] = "\t\t\t\t\t";+	size_t i;++	printf(handoff_dtsi_sy
> smgr_begin);++	/* sys_mgr_init_table is an u8 table */+	print_array_sy
> smgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),+			
>        "\t", "altr,pinmux-cfg","\t\t\t   ");+	/* ioscr scan chain table 0
> */+	print_array_ulong(iocsr_scan_chain0_table,+			  ARRA
> Y_SIZE(iocsr_scan_chain0_table), 4,+			  "\t", "altr,iocsr-
> scan-chain0-table",+			  sysmgr_cfg_indent);+	/* ioscr scan
> chain table 0 */+	print_array_ulong(iocsr_scan_chain1_table,+		
> 	  ARRAY_SIZE(iocsr_scan_chain1_table), 4,+			  "\t"
> , "altr,iocsr-scan-chain1-table",+			  sysmgr_cfg_indent);+	
> /* ioscr scan chain table 0 */+	print_array_ulong(iocsr_scan_chain2_tabl
> e,+			  ARRAY_SIZE(iocsr_scan_chain2_table), 4,+		
> 	  "\t", "altr,iocsr-scan-chain2-table",+			  sysmgr_cfg_i
> ndent);+	/* ioscr scan chain table 0 */+	print_array_ulong(iocsr_scan_c
> hain3_table,+			  ARRAY_SIZE(iocsr_scan_chain3_table), 4,+	
> 		  "\t", "altr,iocsr-scan-chain3-table",+			  sysm
> gr_cfg_indent);+	printf(handoff_dtsi_sysmgr_end);+}++static void
> print_sdram_cfg(void)+{+	const char handoff_dtsi_sdram_cfg_begin[] =+	
> 	"\n"+		"&sdr {\n";+	const char
> handoff_dtsi_sdram_cfg_end[] = "};\n";++	printf(handoff_dtsi_sdram_cfg_be
> gin);+	print_array_u32((const u32 *)&sdram_config,
> sizeof(sdram_config)/4, 4,+			"\t", "altr,sdr-cfg",
> "\t\t\t");+	print_array_u8((const u8 *)&rw_mgr_config,
> sizeof(rw_mgr_config), 8,+			"\t", "altr,sdr-rw-mgr-cfg",
> "\t\t\t       ");+	print_array_u8((const u8 *)&io_config,
> sizeof(io_config), 8,+			"\t", "altr,sdr-io-cfg",
> "\t\t\t   ");+	print_array_u8((const u8 *)&misc_config,
> sizeof(misc_config), 8,+			"\t", "altr,sdr-misc-cfg",
> "\t\t\t     ");+	print_array_alt_u32(ac_rom_init,
> ARRAY_SIZE(ac_rom_init), 4,+			"\t", "altr,sdr-ac-rom-init",
> "\t\t\t\t");+	print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init),
> 4,+			"\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");+	printf
> (handoff_dtsi_sdram_cfg_end);+}++int main(void)+{+	print_hdr();+	print_
> clkmgr_base();+	print_clkmgr_cfg();+	print_sysmgr();+	print_
> sdram_cfg();+}diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh
> b/arch/arm/mach-socfpga/qts-to-handoff.shnew file mode 100755index
> 0000000000..b9032a5411--- /dev/null+++ b/arch/arm/mach-socfpga/qts-to-
> handoff.sh@@ -0,0 +1,83 @@+#!/bin/sh+# This script converts Quartus handoff
> files (in Quartus or U-Boot format)+# to a handoff.dtsi file.+++usage() {+	
> MY_BASENAME=`basename $0`+	echo "${MY_BASENAME} [soc_type]
> [input_qts_dir] [input_bsp_dir] [output_file]"+	echo " or"+	echo
> "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"+	echo ""+	echo
> "Process QTS-generated headers into handoff.dtsi:"+	echo ""+	echo
> "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."+	echo
> "  input_qts_dir - Directory with compiled Quartus project"+	echo
> "                  and containing the Quartus project file (QPF)."+	echo
> "  input_bsp_dir - Directory with generated bsp containing"+	echo
> "                  the settings.bsp file."+	echo "  output_file   - Full
> filename to store the handoff dtsi file."+	echo "  uboot_qts_dir -
> board/qts directory if input files are in"+	echo "                  'old-
> style' U-Boot format."+	echo ""+}++soc="$1"++HANDOFF_TEMPLATE="`dirname
> $0`/create_handoff_gen5.c"++case "$soc" in+"cyclone5"|"arria5")+	if [
> "$#" -ne 4 ] ; then+		usage+		exit 1+	fi+	in_qts_dir="$2
> "+	in_bsp_dir="$3"+	output_file="$4"+	out_dir=`dirname
> ${output_file}`++	if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \+	
> 	! -d "${out_dir}" -o -z "${soc}" ] ; then+		usage+		
> exit 3+	fi++	if [ "$soc" = "cyclone5" ] ; then+		CMDLIN
> E_DEFINES="-DCYCLONE5"+	else+		CMDLINE_DEFINES="-DARRIA5"+	
> fi+	CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT
> -I${in_bsp_dir}/generated/"+	for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do+	
> 	CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"+	done+	;;+"u-boot")+	
> if [ "$#" -ne 3 ] ; then+		usage+		exit 1+	fi+	in_qts
> _dir="$2"+	output_file="$3"+	out_dir=`dirname ${output_file}`++	if [ !
> -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then+		usage+		
> exit 3+	fi++	CMDLINE_DEFINES="-I${in_qts_dir}"+	;;+*)+	usage+
> 	exit 1+	;;+esac++# compile+gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE}
> -o ${out_dir}/create_handoff_gen5+${out_dir}/create_handoff_gen5 >
> ${output_file}++# TODO: remove tmp file:+#rm $${out_dir}/create_handoff_gen5

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Simon Goldschmidt]

Dalon L Westergreen <dalon.westergreen@linux.intel.com> schrieb am Di., 22.
Okt. 2019, 19:10:

> I mentioned this before, it would be great to not rely on the generated
> files
> and do this based purely on the handoff data generated during a quartus
> build. Did you look at the python source i pointed you to?
>

No, not yet. But I don't think that will be a problem. I sent this series
mainly to discuss the dts format (boardspecific handoff dtsi vs genetic
dtsi plus boardspecific header file).

I still favor boardspecific handoff dtsi, but I would like to use the same
style for all socfpga flavours.

Plus this tool is required to convert existing boards where we don't have
the quartus project files at hand.

Regards,
Simon


> --dalon
>
> On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
>
> This new tool converts handoff information from quartus to "*_handoff.dtsi"
>
> devicetree files. This is in preparation to move from ad-hoc code in arch
>
> that parses the 'qts' header files to drivers parsing the same information
>
> from devicetree.
>
>
> Converting existing U-Boot 'qts' files is also supported.
>
>
> Signed-off-by: Simon Goldschmidt <
>
> simon.k.r.goldschmidt at gmail.com
>
> >
>
> ---
>
>
> Changes in v2: None
>
>
>  arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
>
>  arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++
>
>  2 files changed, 743 insertions(+)
>
>  create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
>
>  create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
>
>
> diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-socfpga/create_handoff_gen5.c
>
> new file mode 100644
>
> index 0000000000..6ec436719d
>
> --- /dev/null
>
> +++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
>
> @@ -0,0 +1,660 @@
>
> +// SPDX-License-Identifier: GPL-2.0
>
> +/*
>
> + * This is a host-tool that needs to be compiled per board and prints the
>
> + * handoff.dtsi to stdout.
>
> + */
>
> +
>
> +#include <stdio.h>
>
> +#include <stdint.h>
>
> +
>
> +/* Define kernel types */
>
> +typedef uint8_t u8;
>
> +typedef uint32_t u32;
>
> +
>
> +#ifdef USE_QUARTUS_OUTPUT
>
> +#ifdef ARRIA5
>
> +#include "iocsr_config_arria5.c"
>
> +#include "pinmux_config_arria5.c"
>
> +#else
>
> +#include "iocsr_config_cyclone5.c"
>
> +#include "pinmux_config_cyclone5.c"
>
> +#endif
>
> +#include "pll_config.h"
>
> +#include "sdram/sdram_config.h"
>
> +#include "sequencer_auto.h"
>
> +#include "sequencer_defines.h"
>
> +#include "sequencer_auto_ac_init.c"
>
> +#include "sequencer_auto_inst_init.c"
>
> +#define RW_MGR(x) __RW_MGR_##x
>
> +#else
>
> +#define RW_MGR(x) RW_MGR_##x
>
> +#include <iocsr_config.h>
>
> +#include <pinmux_config.h>
>
> +#include <pll_config.h>
>
> +#include <sdram_config.h>
>
> +#endif
>
> +
>
> +#include "include/mach/clock_manager_gen5.h"
>
> +#include "include/mach/sdram_gen5.h"
>
> +
>
> +#ifndef ARRAY_SIZE
>
> +#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
>
> +#endif
>
> +
>
> +const char handoff_dtsi_hdr[] =
>
> +	"// SPDX-License-Identifier: GPL-2.0\n"
>
> +	"/*\n"
>
> +	" *<auto-generated>\n"
>
> +	" *	This code was generated by a tool based on\n"
>
> +	" *	handoffs from both Qsys and Quartus.\n"
>
> +	" *\n"
>
> +	" *	Changes to this file may be lost if\n"
>
> +	" *	the code is regenerated.\n"
>
> +	" *</auto-generated>\n"
>
> +	" */\n";
>
> +
>
> +/* Wrap PLL config */
>
> +
>
> +#define MAIN_VCO_BASE (					\
>
> +	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
>
> +		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
>
> +	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
>
> +		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
>
> +	)
>
> +
>
> +#define PERI_VCO_BASE (					\
>
> +	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
>
> +		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
>
> +	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
>
> +		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
>
> +	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
>
> +		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
>
> +	)
>
> +
>
> +#define SDR_VCO_BASE (					\
>
> +	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
>
> +		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
>
> +	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
>
> +		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
>
> +	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
>
> +		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
>
> +	)
>
> +
>
> +static const struct cm_config cm_default = {
>
> +	/* main group */
>
> +	MAIN_VCO_BASE,
>
> +	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
>
> +		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
>
> +		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
>
> +		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
>
> +		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
>
> +		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
>
> +		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
>
> +		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
>
> +		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
>
> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
>
> +		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
>
> +		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
>
> +	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
>
> +		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
>
> +		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
>
> +	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
>
> +		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
>
> +	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
>
> +		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
>
> +
>
> +	/* peripheral group */
>
> +	PERI_VCO_BASE,
>
> +	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
>
> +		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
>
> +		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
>
> +	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
>
> +		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
>
> +	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
>
> +		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
>
> +	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
>
> +		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
>
> +		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
>
> +	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
>
> +		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
>
> +	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
>
> +		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
>
> +	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
>
> +		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
>
> +
>
> +	/* sdram pll group */
>
> +	SDR_VCO_BASE,
>
> +	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
>
> +		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
>
> +	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
>
> +		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
>
> +		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
>
> +	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
>
> +		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
>
> +		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
>
> +	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
>
> +		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
>
> +	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
>
> +		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
>
> +	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
>
> +		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
>
> +
>
> +	/* altera group */
>
> +	CONFIG_HPS_ALTERAGRP_MPUCLK,
>
> +};
>
> +
>
> +/* Wrap SDRAM config */
>
> +static const struct socfpga_sdram_config sdram_config = {
>
> +	.ctrl_cfg =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
>
> +			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
>
> +			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
>
> +			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
>
> +			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
>
> +			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
>
> +			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
>
> +			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
>
> +			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
>
> +			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
>
> +	.dram_timing1 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
>
> +			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
>
> +			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
>
> +			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
>
> +			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
>
> +			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
>
> +			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
>
> +	.dram_timing2 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
>
> +			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
>
> +			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
>
> +			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
>
> +			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
>
> +			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
>
> +	.dram_timing3 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
>
> +			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
>
> +			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
>
> +			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
>
> +			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
>
> +			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
>
> +	.dram_timing4 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
>
> +			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
>
> +			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
>
> +	.lowpwr_timing =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
>
> +			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
>
> +			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
>
> +	.dram_odt =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
>
> +			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
>
> +			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
>
> +	.extratime1 =
>
> +	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
>
> +			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
>
> +	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
>
> +			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
>
> +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
>
> +			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
>
> +	.dram_addrw =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
>
> +			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
>
> +			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
>
> +			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
>
> +		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
>
> +			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
>
> +	.dram_if_width =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
>
> +			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
>
> +	.dram_dev_width =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
>
> +			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
>
> +	.dram_intr =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
>
> +			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
>
> +	.lowpwr_eq =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
>
> +			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
>
> +	.static_cfg =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
>
> +			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
>
> +			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
>
> +	.ctrl_width =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
>
> +			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
>
> +	.cport_width =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
>
> +			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
>
> +	.cport_wmap =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
>
> +			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
>
> +	.cport_rmap =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
>
> +			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
>
> +	.rfifo_cmap =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
>
> +			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
>
> +	.wfifo_cmap =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
>
> +			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
>
> +	.cport_rdwr =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
>
> +			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
>
> +	.port_cfg =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
>
> +			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
>
> +	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
>
> +	.fifo_cfg =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
>
> +			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
>
> +		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
>
> +			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
>
> +	.mp_priority =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
>
> +			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
>
> +	.mp_weight0 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
>
> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
>
> +	.mp_weight1 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
>
> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
>
> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
>
> +	.mp_weight2 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
>
> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
>
> +	.mp_weight3 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
>
> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
>
> +	.mp_pacing0 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
>
> +			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
>
> +	.mp_pacing1 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
>
> +			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
>
> +			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
>
> +	.mp_pacing2 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
>
> +			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
>
> +	.mp_pacing3 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
>
> +			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
>
> +	.mp_threshold0 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
>
> +			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
>
> +	.mp_threshold1 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
>
> +			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
>
> +	.mp_threshold2 =
>
> +		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
>
> +			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
>
> +	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
>
> +};
>
> +
>
> +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
>
> +	.activate_0_and_1		= RW_MGR(ACTIVATE_0_AND_1),
>
> +	.activate_0_and_1_wait1		= RW_MGR(ACTIVATE_0_AND_1_WAIT1),
>
> +	.activate_0_and_1_wait2		= RW_MGR(ACTIVATE_0_AND_1_WAIT2),
>
> +	.activate_1			= RW_MGR(ACTIVATE_1),
>
> +	.clear_dqs_enable		= RW_MGR(CLEAR_DQS_ENABLE),
>
> +	.guaranteed_read		= RW_MGR(GUARANTEED_READ),
>
> +	.guaranteed_read_cont		= RW_MGR(GUARANTEED_READ_CONT),
>
> +	.guaranteed_write		= RW_MGR(GUARANTEED_WRITE),
>
> +	.guaranteed_write_wait0		= RW_MGR(GUARANTEED_WRITE_WAIT0),
>
> +	.guaranteed_write_wait1		= RW_MGR(GUARANTEED_WRITE_WAIT1),
>
> +	.guaranteed_write_wait2		= RW_MGR(GUARANTEED_WRITE_WAIT2),
>
> +	.guaranteed_write_wait3		= RW_MGR(GUARANTEED_WRITE_WAIT3),
>
> +	.idle				= RW_MGR(IDLE),
>
> +	.idle_loop1			= RW_MGR(IDLE_LOOP1),
>
> +	.idle_loop2			= RW_MGR(IDLE_LOOP2),
>
> +	.init_reset_0_cke_0		= RW_MGR(INIT_RESET_0_CKE_0),
>
> +	.init_reset_1_cke_0		= RW_MGR(INIT_RESET_1_CKE_0),
>
> +	.lfsr_wr_rd_bank_0		= RW_MGR(LFSR_WR_RD_BANK_0),
>
> +	.lfsr_wr_rd_bank_0_data		= RW_MGR(LFSR_WR_RD_BANK_0_DATA),
>
> +	.lfsr_wr_rd_bank_0_dqs		= RW_MGR(LFSR_WR_RD_BANK_0_DQS),
>
> +	.lfsr_wr_rd_bank_0_nop		= RW_MGR(LFSR_WR_RD_BANK_0_NOP),
>
> +	.lfsr_wr_rd_bank_0_wait		= RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
>
> +	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
>
> +	.lfsr_wr_rd_dm_bank_0		= RW_MGR(LFSR_WR_RD_DM_BANK_0),
>
> +	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
>
> +	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
>
> +	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
>
> +	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
>
> +	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
>
> +	.mrs0_dll_reset			= RW_MGR(MRS0_DLL_RESET),
>
> +	.mrs0_dll_reset_mirr		= RW_MGR(MRS0_DLL_RESET_MIRR),
>
> +	.mrs0_user			= RW_MGR(MRS0_USER),
>
> +	.mrs0_user_mirr			= RW_MGR(MRS0_USER_MIRR),
>
> +	.mrs1				= RW_MGR(MRS1),
>
> +	.mrs1_mirr			= RW_MGR(MRS1_MIRR),
>
> +	.mrs2				= RW_MGR(MRS2),
>
> +	.mrs2_mirr			= RW_MGR(MRS2_MIRR),
>
> +	.mrs3				= RW_MGR(MRS3),
>
> +	.mrs3_mirr			= RW_MGR(MRS3_MIRR),
>
> +	.precharge_all			= RW_MGR(PRECHARGE_ALL),
>
> +	.read_b2b			= RW_MGR(READ_B2B),
>
> +	.read_b2b_wait1			= RW_MGR(READ_B2B_WAIT1),
>
> +	.read_b2b_wait2			= RW_MGR(READ_B2B_WAIT2),
>
> +	.refresh_all			= RW_MGR(REFRESH_ALL),
>
> +	.rreturn			= RW_MGR(RETURN),
>
> +	.sgle_read			= RW_MGR(SGLE_READ),
>
> +	.zqcl				= RW_MGR(ZQCL),
>
> +
>
> +	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
>
> +	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
>
> +	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
>
> +	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
>
> +	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
>
> +	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
>
> +	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
>
> +	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
>
> +	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
>
> +	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
>
> +	.mem_virtual_groups_per_read_dqs =
>
> +		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
>
> +	.mem_virtual_groups_per_write_dqs =
>
> +		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
>
> +};
>
> +
>
> +static const struct socfpga_sdram_io_config io_config = {
>
> +	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
>
> +	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
>
> +	.delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,
>
> +	.delay_per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
>
> +	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
>
> +	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
>
> +	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
>
> +	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
>
> +	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
>
> +	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
>
> +	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
>
> +	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
>
> +	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
>
> +	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
>
> +	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
>
> +	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
>
> +};
>
> +
>
> +static const struct socfpga_sdram_misc_config misc_config = {
>
> +	.afi_rate_ratio			= AFI_RATE_RATIO,
>
> +	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
>
> +	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
>
> +	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
>
> +	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
>
> +	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
>
> +	.reg_file_init_seq_signature_ll	= REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
>
> +	.reg_file_init_seq_signature_lh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
>
> +	.reg_file_init_seq_signature_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
>
> +	.reg_file_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
>
> +	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
>
> +	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
>
> +	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
>
> +	.treset_cntr0_val		= TRESET_CNTR0_VAL,
>
> +	.treset_cntr1_val		= TRESET_CNTR1_VAL,
>
> +	.treset_cntr2_val		= TRESET_CNTR2_VAL,
>
> +};
>
> +
>
> +static void print_hdr(void)
>
> +{
>
> +	printf(handoff_dtsi_hdr);
>
> +}
>
> +
>
> +static void print_clkmgr_base(void)
>
> +{
>
> +	const char handoff_dtsi_clkmgr_base[] =
>
> +		"\n"
>
> +		"&osc1 {\n"
>
> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
>
> +		"};\n"
>
> +		"\n"
>
> +		"&osc2 {\n"
>
> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
>
> +		"};\n"
>
> +		"\n"
>
> +		"&f2s_periph_ref_clk {\n"
>
> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
>
> +		"};\n"
>
> +		"\n"
>
> +		"&f2s_sdram_ref_clk {\n"
>
> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
>
> +		"};\n";
>
> +
>
> +	printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
>
> +	       CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
>
> +	       CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
>
> +}
>
> +
>
> +/*
>
> + * dtc stores u32 array big endian but we load them raw and expect them to be in
>
> + * little endian format. To prevent this tool to depend on host endianess, do
>
> + * the switch manually, not via 'htonl'.
>
> + */
>
> +static u32 swap_bytes(u32 val)
>
> +{
>
> +	return (val << 24) | ((val & 0xFF00ul) << 8) |
>
> +		((val & 0xFF0000ul) >> 8) | (val >> 24);
>
> +}
>
> +
>
> +static void print_array_ulong(const unsigned long *arr, size_t arr_size,
>
> +			      size_t el_per_line, const char *indent1,
>
> +			      const char *name, const char *indent_next)
>
> +{
>
> +	size_t i;
>
> +
>
> +	printf("%s%s = <", indent1, name);
>
> +	for (i = 0; i < arr_size; i++) {
>
> +		printf("0x%08x", swap_bytes((u32)arr[i]));
>
> +		if (i + 1 < arr_size) {
>
> +			if (i % el_per_line == (el_per_line - 1)) {
>
> +				printf("\n%s", indent_next);
>
> +			} else {
>
> +				printf(" ");
>
> +			}
>
> +		}
>
> +	}
>
> +	printf(">;\n");
>
> +}
>
> +
>
> +#ifdef USE_QUARTUS_OUTPUT
>
> +static void print_array_sysmgrinit(const unsigned long *arr, size_t arr_size,
>
> +				   const char *indent1, const char *name,
>
> +				   const char *indent_next)
>
> +{
>
> +	size_t i;
>
> +
>
> +	printf("%s%s = [", indent1, name);
>
> +	for (i = 0; i < arr_size; i++) {
>
> +		printf("%02x", (u8)arr[i]);
>
> +		if (i + 1 < arr_size) {
>
> +			if (i % 8 == 7) {
>
> +				printf("\n%s", indent_next);
>
> +			} else {
>
> +				printf(" ");
>
> +			}
>
> +		}
>
> +	}
>
> +	printf("];\n");
>
> +}
>
> +#define print_array_alt_u32 print_array_ulong
>
> +#else
>
> +#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz, 8, ind1, n, ind2)
>
> +#define print_array_alt_u32 print_array_u32
>
> +#endif
>
> +
>
> +static void print_array_u32(const u32 *arr, size_t arr_size,
>
> +			    size_t el_per_line, const char *indent1,
>
> +			    const char *name, const char *indent_next)
>
> +{
>
> +	size_t i;
>
> +
>
> +	printf("%s%s = <", indent1, name);
>
> +	for (i = 0; i < arr_size; i++) {
>
> +		printf("0x%08x", swap_bytes(arr[i]));
>
> +		if (i + 1 < arr_size) {
>
> +			if (i % el_per_line == (el_per_line - 1)) {
>
> +				printf("\n%s", indent_next);
>
> +			} else {
>
> +				printf(" ");
>
> +			}
>
> +		}
>
> +	}
>
> +	printf(">;\n");
>
> +}
>
> +
>
> +static void print_array_u8(const u8 *arr, size_t arr_size, size_t el_per_line,
>
> +			   const char *indent1, const char *name,
>
> +			   const char *indent_next)
>
> +{
>
> +	size_t i;
>
> +
>
> +	printf("%s%s = [", indent1, name);
>
> +	for (i = 0; i < arr_size; i++) {
>
> +		printf("%02x", arr[i]);
>
> +		if (i + 1 < arr_size) {
>
> +			if (i % el_per_line == (el_per_line - 1)) {
>
> +				printf("\n%s", indent_next);
>
> +			} else {
>
> +				printf(" ");
>
> +			}
>
> +		}
>
> +	}
>
> +	printf("];\n");
>
> +}
>
> +
>
> +
>
> +static void print_clkmgr_cfg(void)
>
> +{
>
> +	const char handoff_dtsi_clkmgr_cfg_a[] =
>
> +		"\n"
>
> +		"&clkmgr {\n";
>
> +	const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
>
> +	const char clk_mgr_cfg_indent[] = "\t\t\t    ";
>
> +
>
> +	printf(handoff_dtsi_clkmgr_cfg_a);
>
> +	print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
>
> +			"altr,clk-mgr-cfg", clk_mgr_cfg_indent);
>
> +	printf(handoff_dtsi_clkmgr_cfg_b);
>
> +}
>
> +
>
> +static void print_sysmgr(void)
>
> +{
>
> +	const char handoff_dtsi_sysmgr_begin[] =
>
> +		"\n"
>
> +		"&sysmgr {\n";
>
> +	const char handoff_dtsi_sysmgr_end[] = "};\n";
>
> +	const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
>
> +	size_t i;
>
> +
>
> +	printf(handoff_dtsi_sysmgr_begin);
>
> +
>
> +	/* sys_mgr_init_table is an u8 table */
>
> +	print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
>
> +			       "\t", "altr,pinmux-cfg","\t\t\t   ");
>
> +	/* ioscr scan chain table 0 */
>
> +	print_array_ulong(iocsr_scan_chain0_table,
>
> +			  ARRAY_SIZE(iocsr_scan_chain0_table), 4,
>
> +			  "\t", "altr,iocsr-scan-chain0-table",
>
> +			  sysmgr_cfg_indent);
>
> +	/* ioscr scan chain table 0 */
>
> +	print_array_ulong(iocsr_scan_chain1_table,
>
> +			  ARRAY_SIZE(iocsr_scan_chain1_table), 4,
>
> +			  "\t", "altr,iocsr-scan-chain1-table",
>
> +			  sysmgr_cfg_indent);
>
> +	/* ioscr scan chain table 0 */
>
> +	print_array_ulong(iocsr_scan_chain2_table,
>
> +			  ARRAY_SIZE(iocsr_scan_chain2_table), 4,
>
> +			  "\t", "altr,iocsr-scan-chain2-table",
>
> +			  sysmgr_cfg_indent);
>
> +	/* ioscr scan chain table 0 */
>
> +	print_array_ulong(iocsr_scan_chain3_table,
>
> +			  ARRAY_SIZE(iocsr_scan_chain3_table), 4,
>
> +			  "\t", "altr,iocsr-scan-chain3-table",
>
> +			  sysmgr_cfg_indent);
>
> +	printf(handoff_dtsi_sysmgr_end);
>
> +}
>
> +
>
> +static void print_sdram_cfg(void)
>
> +{
>
> +	const char handoff_dtsi_sdram_cfg_begin[] =
>
> +		"\n"
>
> +		"&sdr {\n";
>
> +	const char handoff_dtsi_sdram_cfg_end[] = "};\n";
>
> +
>
> +	printf(handoff_dtsi_sdram_cfg_begin);
>
> +	print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
>
> +			"\t", "altr,sdr-cfg", "\t\t\t");
>
> +	print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
>
> +			"\t", "altr,sdr-rw-mgr-cfg", "\t\t\t       ");
>
> +	print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
>
> +			"\t", "altr,sdr-io-cfg", "\t\t\t   ");
>
> +	print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
>
> +			"\t", "altr,sdr-misc-cfg", "\t\t\t     ");
>
> +	print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
>
> +			"\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
>
> +	print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
>
> +			"\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");
>
> +	printf(handoff_dtsi_sdram_cfg_end);
>
> +}
>
> +
>
> +int main(void)
>
> +{
>
> +	print_hdr();
>
> +	print_clkmgr_base();
>
> +	print_clkmgr_cfg();
>
> +	print_sysmgr();
>
> +	print_sdram_cfg();
>
> +}
>
> diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-to-handoff.sh
>
> new file mode 100755
>
> index 0000000000..b9032a5411
>
> --- /dev/null
>
> +++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
>
> @@ -0,0 +1,83 @@
>
> +#!/bin/sh
>
> +# This script converts Quartus handoff files (in Quartus or U-Boot format)
>
> +# to a handoff.dtsi file.
>
> +
>
> +
>
> +usage() {
>
> +	MY_BASENAME=`basename $0`
>
> +	echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir] [output_file]"
>
> +	echo " or"
>
> +	echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
>
> +	echo ""
>
> +	echo "Process QTS-generated headers into handoff.dtsi:"
>
> +	echo ""
>
> +	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
>
> +	echo "  input_qts_dir - Directory with compiled Quartus project"
>
> +	echo "                  and containing the Quartus project file (QPF)."
>
> +	echo "  input_bsp_dir - Directory with generated bsp containing"
>
> +	echo "                  the settings.bsp file."
>
> +	echo "  output_file   - Full filename to store the handoff dtsi file."
>
> +	echo "  uboot_qts_dir - board/qts directory if input files are in"
>
> +	echo "                  'old-style' U-Boot format."
>
> +	echo ""
>
> +}
>
> +
>
> +soc="$1"
>
> +
>
> +HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
>
> +
>
> +case "$soc" in
>
> +"cyclone5"|"arria5")
>
> +	if [ "$#" -ne 4 ] ; then
>
> +		usage
>
> +		exit 1
>
> +	fi
>
> +	in_qts_dir="$2"
>
> +	in_bsp_dir="$3"
>
> +	output_file="$4"
>
> +	out_dir=`dirname ${output_file}`
>
> +
>
> +	if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
>
> +		! -d "${out_dir}" -o -z "${soc}" ] ; then
>
> +		usage
>
> +		exit 3
>
> +	fi
>
> +
>
> +	if [ "$soc" = "cyclone5" ] ; then
>
> +		CMDLINE_DEFINES="-DCYCLONE5"
>
> +	else
>
> +		CMDLINE_DEFINES="-DARRIA5"
>
> +	fi
>
> +	CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"
>
> +	for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
>
> +		CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
>
> +	done
>
> +	;;
>
> +"u-boot")
>
> +	if [ "$#" -ne 3 ] ; then
>
> +		usage
>
> +		exit 1
>
> +	fi
>
> +	in_qts_dir="$2"
>
> +	output_file="$3"
>
> +	out_dir=`dirname ${output_file}`
>
> +
>
> +	if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
>
> +		usage
>
> +		exit 3
>
> +	fi
>
> +
>
> +	CMDLINE_DEFINES="-I${in_qts_dir}"
>
> +	;;
>
> +*)
>
> +	usage
>
> +	exit 1
>
> +	;;
>
> +esac
>
> +
>
> +# compile
>
> +gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o ${out_dir}/create_handoff_gen5
>
> +${out_dir}/create_handoff_gen5 > ${output_file}
>
> +
>
> +# TODO: remove tmp file:
>
> +#rm $${out_dir}/create_handoff_gen5
>
>

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Dalon L Westergreen]

On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
> Dalon L Westergreen <dalon.westergreen@linux.intel.com> schrieb am Di., 22.
> Okt. 2019, 19:10:
> > I mentioned this before, it would be great to not rely on the generated
> > files
> > and do this based purely on the handoff data generated during a quartus
> > build.  Did you look at the python source i pointed you to?
> 
> No, not yet. But I don't think that will be a problem. I sent this series
> mainly to discuss the dts format (boardspecific handoff dtsi vs genetic dtsi
> plus boardspecific header file).

The board specific dtsi does look cleaner, but i do like the simplicity of
generating the header in arria10.
I could easily replicate what you do, generate the header, and use it to create
the dtsi.
--dalon
> I still favor boardspecific handoff dtsi, but I would like to use the same
> style for all socfpga flavours.
> 
> Plus this tool is required to convert existing boards where we don't have the
> quartus project files at hand.
> 
> Regards,
> Simon
> 
> > --dalon
> > On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
> > > This new tool converts handoff information from quartus to
> > > "*_handoff.dtsi"devicetree files. This is in preparation to move from ad-
> > > hoc code in archthat parses the 'qts' header files to drivers parsing the
> > > same informationfrom devicetree.
> > > Converting existing U-Boot 'qts' files is also supported.
> > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>---
> > > Changes in v2: None
> > >  arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
> > > arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++ 2 files changed, 743
> > > insertions(+) create mode 100644 arch/arm/mach-
> > > socfpga/create_handoff_gen5.c create mode 100755 arch/arm/mach-
> > > socfpga/qts-to-handoff.sh
> > > diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-
> > > socfpga/create_handoff_gen5.cnew file mode 100644index
> > > 0000000000..6ec436719d--- /dev/null+++ b/arch/arm/mach-
> > > socfpga/create_handoff_gen5.c@@ -0,0 +1,660 @@+// SPDX-License-Identifier: 
> > > GPL-2.0+/*+ * This is a host-tool that needs to be compiled per board and
> > > prints the+ * handoff.dtsi to stdout.+ */++#include <stdio.h>+#include
> > > <stdint.h>++/* Define kernel types */+typedef uint8_t u8;+typedef uint32_t
> > > u32;++#ifdef USE_QUARTUS_OUTPUT+#ifdef ARRIA5+#include
> > > "iocsr_config_arria5.c"+#include "pinmux_config_arria5.c"+#else+#include
> > > "iocsr_config_cyclone5.c"+#include
> > > "pinmux_config_cyclone5.c"+#endif+#include "pll_config.h"+#include
> > > "sdram/sdram_config.h"+#include "sequencer_auto.h"+#include
> > > "sequencer_defines.h"+#include "sequencer_auto_ac_init.c"+#include
> > > "sequencer_auto_inst_init.c"+#define RW_MGR(x) __RW_MGR_##x+#else+#define
> > > RW_MGR(x) RW_MGR_##x+#include <iocsr_config.h>+#include
> > > <pinmux_config.h>+#include <pll_config.h>+#include
> > > <sdram_config.h>+#endif++#include
> > > "include/mach/clock_manager_gen5.h"+#include
> > > "include/mach/sdram_gen5.h"++#ifndef ARRAY_SIZE+#define ARRAY_SIZE(x)
> > > (sizeof(x)/sizeof((x)[0]))+#endif++const char handoff_dtsi_hdr[] =+	
> > > "// SPDX-License-Identifier: GPL-2.0\n"+	"/*\n"+	" *<auto-
> > > generated>\n"+	" *	This code was generated by a tool based on\n"+	"
> > > *	handoffs from both Qsys and Quartus.\n"+	" *\n"+	" *	Changes to
> > > this file may be lost if\n"+	" *	the code is regenerated.\n"+	"
> > > *</auto-generated>\n"+	" */\n";++/* Wrap PLL config */++#define
> > > MAIN_VCO_BASE (					\+	(CONFIG_HPS_MAINPL
> > > LGRP_VCO_DENOM <<		\+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET
> > > ) |	\+	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\+		
> > > CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\+	)++#define PERI_VCO_BASE (
> > > 					\+	(CONFIG_HPS_PERPLLGRP_VCO_
> > > PSRC <<		\+		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\+
> > > 	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\+		CL
> > > KMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\+	(CONFIG_HPS_PERPLLGRP_VCO_
> > > NUMER <<		\+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\+
> > > 	)++#define SDR_VCO_BASE (					\+
> > > 	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\+		CL
> > > KMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\+	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<
> > > 		\+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\+
> > > 	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\+		CL
> > > KMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\+	)++static const struct cm_config
> > > cm_default = {+	/* main group */+	MAIN_VCO_BASE,+	(CONFIG_HPS_MAINPL
> > > LGRP_MPUCLK_CNT <<+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),+	
> > > (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<+		CLKMGR_MAINPLLGRP_MAINCL
> > > K_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<+		CL
> > > KMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_MAINQSPIC
> > > LK_CNT <<+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),+	(C
> > > ONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<+		CLKMGR_PERPLLGRP
> > > _PERNANDSDMMCCLK_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CN
> > > T <<+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),+	(C
> > > ONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<+		CLKMGR_MAINPLLGRP_MAINDI
> > > V_L3MPCLK_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<+		
> > > CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_M
> > > AINDIV_L4MPCLK <<+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET
> > > ) |+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<+		CLKMGR_MAI
> > > NPLLGRP_MAINDIV_L4SPCLK_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
> > > <<+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |+	(CONFIG_HP
> > > S_MAINPLLGRP_DBGDIV_DBGCLK <<+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_
> > > OFFSET),+	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<+		CLKMGR_MAI
> > > NPLLGRP_TRACEDIV_TRACECLK_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4M
> > > P <<+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |+	(CONFIG_HP
> > > S_MAINPLLGRP_L4SRC_L4SP <<+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFF
> > > SET),++	/* peripheral group */+	PERI_VCO_BASE,+	(CONFIG_HPS_PERPLL
> > > GRP_EMAC0CLK_CNT <<+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),+	
> > > (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<+		CLKMGR_PERPLLGRP_EMAC1CL
> > > K_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<+		CL
> > > KMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_PERNANDSDM
> > > MCCLK_CNT <<+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),+	
> > > (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<+		CLKMGR_PERPLLGRP_PERBASE
> > > CLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<+		CL
> > > KMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK
> > > <<+		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |+	(CONFIG_HP
> > > S_PERPLLGRP_DIV_SPIMCLK <<+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFF
> > > SET) |+	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<+		CLKMGR_PERPLLGRP_D
> > > IV_CAN0CLK_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<+		CL
> > > KMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),+	(CONFIG_HPS_PERPLLGRP_GPIODIV_GP
> > > IODBCLK <<+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),+	(C
> > > ONFIG_HPS_PERPLLGRP_SRC_QSPI <<+		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET
> > > ) |+	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<+		CLKMGR_PERPLLGRP_S
> > > RC_NAND_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<+		CL
> > > KMGR_PERPLLGRP_SRC_SDMMC_OFFSET),++	/* sdram pll group */+	SD
> > > R_VCO_BASE,+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<+		CL
> > > KMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_
> > > CNT <<+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),+	(CONFIG_HP
> > > S_SDRPLLGRP_DDR2XDQSCLK_PHASE <<+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHA
> > > SE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<+		CL
> > > KMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_P
> > > HASE <<+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |+	(CONFIG_HP
> > > S_SDRPLLGRP_DDRDQCLK_CNT <<+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OF
> > > FSET),+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<+		CLKMGR_SDR
> > > PLLGRP_S2FUSER2CLK_PHASE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CL
> > > K_CNT <<+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),++	/* altera
> > > group */+	CONFIG_HPS_ALTERAGRP_MPUCLK,+};++/* Wrap SDRAM config */+static
> > > const struct socfpga_sdram_config sdram_config = {+	.ctrl_cfg =+		
> > > (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<+			SDR_CTRL
> > > GRP_CTRLCFG_MEMTYPE_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_CT
> > > RLCFG_MEMBL <<+			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)		
> > > 	|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<+			
> > > SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|+		(CONFIG_HP
> > > S_SDR_CTRLCFG_CTRLCFG_ECCEN <<+			SDR_CTRLGRP_CTRLCFG_ECCE
> > > N_LSB)			|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_EC
> > > CCORREN <<+			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		
> > > |+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<+			
> > > SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|+		(CONFIG_HP
> > > S_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<+			SDR_CTRLGRP_CTRL
> > > CFG_STARVELIMIT_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_CT
> > > RLCFG_DQSTRKEN <<+			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB
> > > )		|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<+		
> > > 	SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),+	.dram_timing1 =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<+			SDR_CTRL
> > > GRP_DRAMTIMING1_TCWL_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DR
> > > AMTIMING1_AL <<+			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		
> > > |+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<+			
> > > SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|+		(CONFIG_HPS_SDR_CT
> > > RLCFG_DRAMTIMING1_TRRD <<+			SDR_CTRLGRP_DRAMTIMING1_
> > > TRRD_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
> > > <<+			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|+
> > > 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<+			
> > > SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),+	.dram_timing2 =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<+			SDR_CTRL
> > > GRP_DRAMTIMING2_TREFI_LSB)		|+		(CONFIG_HPS_SDR_CT
> > > RLCFG_DRAMTIMING2_IF_TRCD <<+			SDR_CTRLGRP_DRAMTIMING2_
> > > TRCD_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
> > > <<+			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|+
> > > 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<+			
> > > SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|+		(CONFIG_HPS_SDR_CT
> > > RLCFG_DRAMTIMING2_IF_TWTR <<+			SDR_CTRLGRP_DRAMTIMING2_
> > > TWTR_LSB),+	.dram_timing3 =+		(CONFIG_HPS_SDR_CTRLCFG_DR
> > > AMTIMING3_TRTP <<+			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB
> > > )		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<+		
> > > 	SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|+		(CONFIG_HP
> > > S_SDR_CTRLCFG_DRAMTIMING3_TRC <<+			SDR_CTRLGRP_DRAMTIMING3_
> > > TRC_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
> > > <<+			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|+
> > > 		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<+			
> > > SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),+	.dram_timing4 =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<+			
> > > SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|+		(CONFIG_HP
> > > S_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<+			SDR_CTRLGRP_DRAM
> > > TIMING4_PWRDOWNEXIT_LSB),+	.lowpwr_timing =+		(CONFIG_HP
> > > S_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<+			SDR_CTRL
> > > GRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|+		(CONFIG_HPS_SDR_CT
> > > RLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<+			SDR_CTRLGRP_LOWP
> > > WRTIMING_CLKDISABLECYCLES_LSB),+	.dram_odt =+		(CONFIG_HPS_SDR_CT
> > > RLCFG_DRAMODT_READ <<+			SDR_CTRLGRP_DRAMODT_READ_LSB)		
> > > 	|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<+			
> > > SDR_CTRLGRP_DRAMODT_WRITE_LSB),+	.extratime1 =+	(CONFIG_HPS_SDR_CT
> > > RLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<+			SDR_CTRL
> > > GRP_EXTRATIME1_RD_TO_WR_LSB)		|+	(CONFIG_HPS_SDR_CTRLCFG_EX
> > > TRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<+			SDR_CTRL
> > > GRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|+(CONFIG_HPS_SDR_CTRLCFG_EXTRAT
> > > IME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<+			SDR_CTRL
> > > GRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),+	.dram_addrw =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<+			SDR_CTRL
> > > GRP_DRAMADDRW_COLBITS_LSB)		|+		(CONFIG_HPS_SDR_CT
> > > RLCFG_DRAMADDRW_ROWBITS <<+			SDR_CTRLGRP_DRAMADDRW_RO
> > > WBITS_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_
> > > BANKBITS <<+			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		
> > > |+		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<+		
> > > 	SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),+	.dram_if_width =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<+			SDR_CTRL
> > > GRP_DRAMIFWIDTH_IFWIDTH_LSB),+	.dram_dev_width =+		(CONFIG_HP
> > > S_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<+			SDR_CTRLGRP_DRAM
> > > DEVWIDTH_DEVWIDTH_LSB),+	.dram_intr =+		(CONFIG_HPS_SDR_CTRLCFG_DR
> > > AMINTR_INTREN <<+			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),+	.l
> > > owpwr_eq =+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
> > > <<+			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),+	.s
> > > tatic_cfg =+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<+		
> > > 	SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|+		(CONFIG_HP
> > > S_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<+			SDR_CTRLGRP_STAT
> > > ICCFG_USEECCASDATA_LSB),+	.ctrl_width =+		(CONFIG_HPS_SDR_CT
> > > RLCFG_CTRLWIDTH_CTRLWIDTH <<+			SDR_CTRLGRP_CTRLWIDTH_CT
> > > RLWIDTH_LSB),+	.cport_width =+		(CONFIG_HPS_SDR_CTRLCFG_CP
> > > ORTWIDTH_CPORTWIDTH <<+			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWI
> > > DTH_LSB),+	.cport_wmap =+		(CONFIG_HPS_SDR_CTRLCFG_CP
> > > ORTWMAP_CPORTWMAP <<+			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFO
> > > MAP_LSB),+	.cport_rmap =+		(CONFIG_HPS_SDR_CTRLCFG_CP
> > > ORTRMAP_CPORTRMAP <<+			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFO
> > > MAP_LSB),+	.rfifo_cmap =+		(CONFIG_HPS_SDR_CTRLCFG_RF
> > > IFOCMAP_RFIFOCMAP <<+			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORT
> > > MAP_LSB),+	.wfifo_cmap =+		(CONFIG_HPS_SDR_CTRLCFG_WF
> > > IFOCMAP_WFIFOCMAP <<+			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORT
> > > MAP_LSB),+	.cport_rdwr =+		(CONFIG_HPS_SDR_CTRLCFG_CP
> > > ORTRDWR_CPORTRDWR <<+			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_
> > > LSB),+	.port_cfg =+		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
> > > <<+			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),+	.fpgaport_
> > > rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,+	.fifo_cfg =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<+			SDR_CTRL
> > > GRP_FIFOCFG_SYNCMODE_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_FI
> > > FOCFG_INCSYNC <<+			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),+	.m
> > > p_priority =+		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
> > > <<+			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),+	.m
> > > p_weight0 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT
> > > _31_0 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_
> > > 0_LSB),+	.mp_weight1 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_
> > > 1_STATICWEIGHT_49_32 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_
> > > STATICWEIGHT_49_32_LSB) |+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGH
> > > T_1_SUMOFWEIGHT_13_0 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_
> > > SUMOFWEIGHTS_13_0_LSB),+	.mp_weight2 =+		(CONFIG_HPS_SDR_CT
> > > RLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<+			SDR_CTRLGRP_MPWE
> > > IGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),+	.mp_weight3 =+		(C
> > > ONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<+			
> > > SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),+	.mp_pacing
> > > 0 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<+	
> > > 		SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),+	.m
> > > p_pacing1 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59
> > > _32 <<+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32
> > > _LSB) |+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<+		
> > > 	SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),+	.mp_pacing2 =+		
> > > (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<+			
> > > SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),+	.mp_pacing3 =+		
> > > (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<+			
> > > SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),+	.mp_threshold0 =+	
> > > 	(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<+		
> > > 	SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),+	.mp_thresh
> > > old1 =+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYC
> > > LES_63_32 <<+			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRS
> > > TCYCLES_63_32_LSB),+	.mp_threshold2 =+		(CONFIG_HPS_SDR_CT
> > > RLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<+			
> > > SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),+	.phy_ctrl0
> > > = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,+};++static const struct
> > > socfpga_sdram_rw_mgr_config rw_mgr_config = {+	.activate_0_and_1		
> > > = RW_MGR(ACTIVATE_0_AND_1),+	.activate_0_and_1_wait1		=
> > > RW_MGR(ACTIVATE_0_AND_1_WAIT1),+	.activate_0_and_1_wait2		=
> > > RW_MGR(ACTIVATE_0_AND_1_WAIT2),+	.activate_1			=
> > > RW_MGR(ACTIVATE_1),+	.clear_dqs_enable		=
> > > RW_MGR(CLEAR_DQS_ENABLE),+	.guaranteed_read		=
> > > RW_MGR(GUARANTEED_READ),+	.guaranteed_read_cont		=
> > > RW_MGR(GUARANTEED_READ_CONT),+	.guaranteed_write		=
> > > RW_MGR(GUARANTEED_WRITE),+	.guaranteed_write_wait0		=
> > > RW_MGR(GUARANTEED_WRITE_WAIT0),+	.guaranteed_write_wait1		=
> > > RW_MGR(GUARANTEED_WRITE_WAIT1),+	.guaranteed_write_wait2		=
> > > RW_MGR(GUARANTEED_WRITE_WAIT2),+	.guaranteed_write_wait3		=
> > > RW_MGR(GUARANTEED_WRITE_WAIT3),+	.idle				=
> > > RW_MGR(IDLE),+	.idle_loop1			= RW_MGR(IDLE_LOOP1),+	.i
> > > dle_loop2			= RW_MGR(IDLE_LOOP2),+	.init_reset_0_cke_
> > > 0		= RW_MGR(INIT_RESET_0_CKE_0),+	.init_reset_1_cke_0		
> > > = RW_MGR(INIT_RESET_1_CKE_0),+	.lfsr_wr_rd_bank_0		=
> > > RW_MGR(LFSR_WR_RD_BANK_0),+	.lfsr_wr_rd_bank_0_data		=
> > > RW_MGR(LFSR_WR_RD_BANK_0_DATA),+	.lfsr_wr_rd_bank_0_dqs		=
> > > RW_MGR(LFSR_WR_RD_BANK_0_DQS),+	.lfsr_wr_rd_bank_0_nop		=
> > > RW_MGR(LFSR_WR_RD_BANK_0_NOP),+	.lfsr_wr_rd_bank_0_wait		=
> > > RW_MGR(LFSR_WR_RD_BANK_0_WAIT),+	.lfsr_wr_rd_bank_0_wl_1		=
> > > RW_MGR(LFSR_WR_RD_BANK_0_WL_1),+	.lfsr_wr_rd_dm_bank_0		=
> > > RW_MGR(LFSR_WR_RD_DM_BANK_0),+	.lfsr_wr_rd_dm_bank_0_data	=
> > > RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),+	.lfsr_wr_rd_dm_bank_0_dqs	=
> > > RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),+	.lfsr_wr_rd_dm_bank_0_nop	=
> > > RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),+	.lfsr_wr_rd_dm_bank_0_wait	=
> > > RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),+	.lfsr_wr_rd_dm_bank_0_wl_1	=
> > > RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),+	.mrs0_dll_reset			
> > > = RW_MGR(MRS0_DLL_RESET),+	.mrs0_dll_reset_mirr		=
> > > RW_MGR(MRS0_DLL_RESET_MIRR),+	.mrs0_user			=
> > > RW_MGR(MRS0_USER),+	.mrs0_user_mirr			=
> > > RW_MGR(MRS0_USER_MIRR),+	.mrs1				= RW_MGR(MRS1),+	
> > > .mrs1_mirr			= RW_MGR(MRS1_MIRR),+	.mrs2			
> > > 	= RW_MGR(MRS2),+	.mrs2_mirr			=
> > > RW_MGR(MRS2_MIRR),+	.mrs3				= RW_MGR(MRS3),+	
> > > .mrs3_mirr			= RW_MGR(MRS3_MIRR),+	.precharge_all		
> > > 	= RW_MGR(PRECHARGE_ALL),+	.read_b2b			=
> > > RW_MGR(READ_B2B),+	.read_b2b_wait1			=
> > > RW_MGR(READ_B2B_WAIT1),+	.read_b2b_wait2			=
> > > RW_MGR(READ_B2B_WAIT2),+	.refresh_all			=
> > > RW_MGR(REFRESH_ALL),+	.rreturn			= RW_MGR(RETURN),+
> > > 	.sgle_read			= RW_MGR(SGLE_READ),+	.zqcl		
> > > 		= RW_MGR(ZQCL),++	.true_mem_data_mask_width	=
> > > RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,+	.mem_address_mirroring		=
> > > RW_MGR_MEM_ADDRESS_MIRRORING,+	.mem_data_mask_width		=
> > > RW_MGR_MEM_DATA_MASK_WIDTH,+	.mem_data_width			=
> > > RW_MGR_MEM_DATA_WIDTH,+	.mem_dq_per_read_dqs		=
> > > RW_MGR_MEM_DQ_PER_READ_DQS,+	.mem_dq_per_write_dqs		=
> > > RW_MGR_MEM_DQ_PER_WRITE_DQS,+	.mem_if_read_dqs_width		=
> > > RW_MGR_MEM_IF_READ_DQS_WIDTH,+	.mem_if_write_dqs_width		=
> > > RW_MGR_MEM_IF_WRITE_DQS_WIDTH,+	.mem_number_of_cs_per_dimm	=
> > > RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,+	.mem_number_of_ranks		=
> > > RW_MGR_MEM_NUMBER_OF_RANKS,+	.mem_virtual_groups_per_read_dqs =+		
> > > RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,+	.mem_virtual_groups_per_write_dq
> > > s =+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,+};++static
> > > const struct socfpga_sdram_io_config io_config = {+	.delay_per_dchai
> > > n_tap		= IO_DELAY_PER_DCHAIN_TAP,+	.delay_per_dqs_en_dchain_t
> > > ap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,+	.delay_per_opa_tap_lo		
> > > = IO_DELAY_PER_OPA_TAP & 0xff,+	.delay_per_opa_tap_hi		=
> > > (IO_DELAY_PER_OPA_TAP << 8) & 0xff,+	.dll_chain_length		=
> > > IO_DLL_CHAIN_LENGTH,+	.dqdqs_out_phase_max		=
> > > IO_DQDQS_OUT_PHASE_MAX,+	.dqs_en_delay_max		=
> > > IO_DQS_EN_DELAY_MAX,+	.dqs_en_delay_offset		=
> > > IO_DQS_EN_DELAY_OFFSET,+	.dqs_en_phase_max		=
> > > IO_DQS_EN_PHASE_MAX,+	.dqs_in_delay_max		=
> > > IO_DQS_IN_DELAY_MAX,+	.dqs_in_reserve			=
> > > IO_DQS_IN_RESERVE,+	.dqs_out_reserve		=
> > > IO_DQS_OUT_RESERVE,+	.io_in_delay_max		=
> > > IO_IO_IN_DELAY_MAX,+	.io_out1_delay_max		=
> > > IO_IO_OUT1_DELAY_MAX,+	.io_out2_delay_max		=
> > > IO_IO_OUT2_DELAY_MAX,+	.shift_dqs_en_when_shift_dqs	=
> > > IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,+};++static const struct
> > > socfpga_sdram_misc_config misc_config = {+	.afi_rate_ratio		
> > > 	= AFI_RATE_RATIO,+	.calib_lfifo_offset		=
> > > CALIB_LFIFO_OFFSET,+	.calib_vfifo_offset		=
> > > CALIB_VFIFO_OFFSET,+	.enable_super_quick_calibration	=
> > > ENABLE_SUPER_QUICK_CALIBRATION,+	.max_latency_count_width	=
> > > MAX_LATENCY_COUNT_WIDTH,+	.read_valid_fifo_size		=
> > > READ_VALID_FIFO_SIZE,+	.reg_file_init_seq_signature_ll	=
> > > REG_FILE_INIT_SEQ_SIGNATURE & 0xff,+	.reg_file_init_seq_signature_lh	
> > > = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,+	.reg_file_init_seq_signa
> > > ture_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,+	.reg_file_
> > > init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,+	
> > > .tinit_cntr0_val		= TINIT_CNTR0_VAL,+	.tinit_cntr1_val		
> > > = TINIT_CNTR1_VAL,+	.tinit_cntr2_val		=
> > > TINIT_CNTR2_VAL,+	.treset_cntr0_val		= TRESET_CNTR0_VAL,+	.t
> > > reset_cntr1_val		= TRESET_CNTR1_VAL,+	.treset_cntr2_val		
> > > = TRESET_CNTR2_VAL,+};++static void print_hdr(void)+{+	printf(handoff_d
> > > tsi_hdr);+}++static void print_clkmgr_base(void)+{+	const char
> > > handoff_dtsi_clkmgr_base[] =+		"\n"+		"&osc1 {\n"+		
> > > "	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */+		"}
> > > ;\n"+		"\n"+		"&osc2 {\n"+		"	clock-
> > > frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */+		"};\n"+	
> > > 	"\n"+		"&f2s_periph_ref_clk {\n"+		"	clock-
> > > frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */+		"};\n"+	
> > > 	"\n"+		"&f2s_sdram_ref_clk {\n"+		"	clock-
> > > frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */+		"};\n";+
> > > +	printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,+	       CON
> > > FIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,+	       CONFIG_HP
> > > S_CLK_F2S_SDR_REF_HZ);+}++/*+ * dtc stores u32 array big endian but we
> > > load them raw and expect them to be in+ * little endian format. To prevent
> > > this tool to depend on host endianess, do+ * the switch manually, not via
> > > 'htonl'.+ */+static u32 swap_bytes(u32 val)+{+	return (val << 24) |
> > > ((val & 0xFF00ul) << 8) |+		((val & 0xFF0000ul) >> 8) | (val
> > > >> 24);+}++static void print_array_ulong(const unsigned long *arr, size_t
> > > arr_size,+			      size_t el_per_line, const char
> > > *indent1,+			      const char *name, const char
> > > *indent_next)+{+	size_t i;++	printf("%s%s = <", indent1, name);+	fo
> > > r (i = 0; i < arr_size; i++) {+		printf("0x%08x",
> > > swap_bytes((u32)arr[i]));+		if (i + 1 < arr_size) {+		
> > > 	if (i % el_per_line == (el_per_line - 1)) {+				pr
> > > intf("\n%s", indent_next);+			} else {+			
> > > 	printf(" ");+			}+		}+	}+	printf(">;
> > > \n");+}++#ifdef USE_QUARTUS_OUTPUT+static void
> > > print_array_sysmgrinit(const unsigned long *arr, size_t arr_size,+		
> > > 		   const char *indent1, const char *name,+				
> > >    const char *indent_next)+{+	size_t i;++	printf("%s%s = [",
> > > indent1, name);+	for (i = 0; i < arr_size; i++) {+		printf("%0
> > > 2x", (u8)arr[i]);+		if (i + 1 < arr_size) {+			
> > > if (i % 8 == 7) {+				printf("\n%s",
> > > indent_next);+			} else {+				pr
> > > intf(" ");+			}+		}+	}+	printf("];
> > > \n");+}+#define print_array_alt_u32 print_array_ulong+#else+#define
> > > print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz, 8,
> > > ind1, n, ind2)+#define print_array_alt_u32 print_array_u32+#endif++static
> > > void print_array_u32(const u32 *arr, size_t arr_size,+			
> > >     size_t el_per_line, const char *indent1,+			    const
> > > char *name, const char *indent_next)+{+	size_t i;++	printf("%s%s = <",
> > > indent1, name);+	for (i = 0; i < arr_size; i++) {+		printf("0x
> > > %08x", swap_bytes(arr[i]));+		if (i + 1 < arr_size) {+		
> > > 	if (i % el_per_line == (el_per_line - 1)) {+				pr
> > > intf("\n%s", indent_next);+			} else {+			
> > > 	printf(" ");+			}+		}+	}+	printf(">;
> > > \n");+}++static void print_array_u8(const u8 *arr, size_t arr_size, size_t
> > > el_per_line,+			   const char *indent1, const char
> > > *name,+			   const char *indent_next)+{+	size_t
> > > i;++	printf("%s%s = [", indent1, name);+	for (i = 0; i < arr_size;
> > > i++) {+		printf("%02x", arr[i]);+		if (i + 1 <
> > > arr_size) {+			if (i % el_per_line == (el_per_line -
> > > 1)) {+				printf("\n%s", indent_next);+			
> > > } else {+				printf(" ");+			}+		
> > > }+	}+	printf("];\n");+}+++static void print_clkmgr_cfg(void)+{+	
> > > const char handoff_dtsi_clkmgr_cfg_a[] =+		"\n"+		"&clkmgr
> > > {\n";+	const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";+	const char
> > > clk_mgr_cfg_indent[] = "\t\t\t    ";++	printf(handoff_dtsi_clkmgr_cfg_a
> > > );+	print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4,
> > > 4, "\t",+			"altr,clk-mgr-cfg", clk_mgr_cfg_indent);+	pr
> > > intf(handoff_dtsi_clkmgr_cfg_b);+}++static void print_sysmgr(void)+{+	
> > > const char handoff_dtsi_sysmgr_begin[] =+		"\n"+		"&
> > > sysmgr {\n";+	const char handoff_dtsi_sysmgr_end[] = "};\n";+	co
> > > nst char sysmgr_cfg_indent[] = "\t\t\t\t\t";+	size_t i;++	printf(han
> > > doff_dtsi_sysmgr_begin);++	/* sys_mgr_init_table is an u8 table */+
> > > 	print_array_sysmgrinit(sys_mgr_init_table,
> > > ARRAY_SIZE(sys_mgr_init_table),+			       "\t",
> > > "altr,pinmux-cfg","\t\t\t   ");+	/* ioscr scan chain table 0 */+	pr
> > > int_array_ulong(iocsr_scan_chain0_table,+			  ARRAY_SIZE(ioc
> > > sr_scan_chain0_table), 4,+			  "\t", "altr,iocsr-
> > > scan-chain0-table",+			  sysmgr_cfg_indent);+	/*
> > > ioscr scan chain table 0 */+	print_array_ulong(iocsr_scan_chain1_tabl
> > > e,+			  ARRAY_SIZE(iocsr_scan_chain1_table), 4,+		
> > > 	  "\t", "altr,iocsr-scan-chain1-table",+			  sysmgr_c
> > > fg_indent);+	/* ioscr scan chain table 0 */+	print_array_ulong(
> > > iocsr_scan_chain2_table,+			  ARRAY_SIZE(iocsr_scan_chain2_t
> > > able), 4,+			  "\t", "altr,iocsr-scan-chain2-table",+
> > > 			  sysmgr_cfg_indent);+	/* ioscr scan chain table
> > > 0 */+	print_array_ulong(iocsr_scan_chain3_table,+			  
> > > ARRAY_SIZE(iocsr_scan_chain3_table), 4,+			  "\t",
> > > "altr,iocsr-scan-chain3-table",+			  sysmgr_cfg_indent);+	
> > > printf(handoff_dtsi_sysmgr_end);+}++static void print_sdram_cfg(void)+{+	
> > > const char handoff_dtsi_sdram_cfg_begin[] =+		"\n"+		"&
> > > sdr {\n";+	const char handoff_dtsi_sdram_cfg_end[] = "};\n";++	pr
> > > intf(handoff_dtsi_sdram_cfg_begin);+	print_array_u32((const u32
> > > *)&sdram_config, sizeof(sdram_config)/4, 4,+			"\t",
> > > "altr,sdr-cfg", "\t\t\t");+	print_array_u8((const u8
> > > *)&rw_mgr_config, sizeof(rw_mgr_config), 8,+			"\t",
> > > "altr,sdr-rw-mgr-cfg", "\t\t\t       ");+	print_array_u8((const u8
> > > *)&io_config, sizeof(io_config), 8,+			"\t", "altr,sdr-
> > > io-cfg", "\t\t\t   ");+	print_array_u8((const u8 *)&misc_config,
> > > sizeof(misc_config), 8,+			"\t", "altr,sdr-misc-cfg",
> > > "\t\t\t     ");+	print_array_alt_u32(ac_rom_init,
> > > ARRAY_SIZE(ac_rom_init), 4,+			"\t", "altr,sdr-ac-rom-
> > > init", "\t\t\t\t");+	print_array_alt_u32(inst_rom_init,
> > > ARRAY_SIZE(inst_rom_init), 4,+			"\t", "altr,sdr-inst-
> > > rom-init", "\t\t\t\t  ");+	printf(handoff_dtsi_sdram_cfg_end);+}++i
> > > nt main(void)+{+	print_hdr();+	print_clkmgr_base();+	print_clkmgr_cfg()
> > > ;+	print_sysmgr();+	print_sdram_cfg();+}diff --git
> > > a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-to-
> > > handoff.shnew file mode 100755index 0000000000..b9032a5411--- /dev/null+++
> > > b/arch/arm/mach-socfpga/qts-to-handoff.sh@@ -0,0 +1,83 @@+#!/bin/sh+# This
> > > script converts Quartus handoff files (in Quartus or U-Boot format)+# to a
> > > handoff.dtsi file.+++usage() {+	MY_BASENAME=`basename $0`+	echo
> > > "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir] [output_file]"+	
> > > echo " or"+	echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir]
> > > [output_file]"+	echo ""+	echo "Process QTS-generated headers into
> > > handoff.dtsi:"+	echo ""+	echo "  soc_type      - Type of SoC,
> > > either 'cyclone5' or 'arria5'."+	echo "  input_qts_dir - Directory with
> > > compiled Quartus project"+	echo "                  and containing
> > > the Quartus project file (QPF)."+	echo "  input_bsp_dir - Directory with
> > > generated bsp containing"+	echo "                  the settings.bsp
> > > file."+	echo "  output_file   - Full filename to store the handoff dtsi
> > > file."+	echo "  uboot_qts_dir - board/qts directory if input files are
> > > in"+	echo "                  'old-style' U-Boot format."+	echo
> > > ""+}++soc="$1"++HANDOFF_TEMPLATE="`dirname
> > > $0`/create_handoff_gen5.c"++case "$soc" in+"cyclone5"|"arria5")+	if [
> > > "$#" -ne 4 ] ; then+		usage+		exit 1+	fi+	in
> > > _qts_dir="$2"+	in_bsp_dir="$3"+	output_file="$4"+	out_dir=`d
> > > irname ${output_file}`++	if [ ! -d "${in_qts_dir}" -o ! -d
> > > "${in_bsp_dir}" -o \+		! -d "${out_dir}" -o -z "${soc}" ] ;
> > > then+		usage+		exit 3+	fi++	if [ "$soc" =
> > > "cyclone5" ] ; then+		CMDLINE_DEFINES="-DCYCLONE5"+	else+		
> > > CMDLINE_DEFINES="-DARRIA5"+	fi+	CMDLINE_DEFINES="${CMDLINE_DEFINES
> > > } -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"+	for d in
> > > ${in_qts_dir}/hps_isw_handoff/*/ ; do+		CMDLINE_DEFINES="${CMDLI
> > > NE_DEFINES} -I$d"+	done+	;;+"u-boot")+	if [ "$#" -ne 3 ] ; then+	
> > > 	usage+		exit 1+	fi+	in_qts_dir="$2"+	output_fil
> > > e="$3"+	out_dir=`dirname ${output_file}`++	if [ ! -d "${in_qts_dir}"
> > > -o ! -d "${out_dir}" ] ; then+		usage+		exit 3+	fi
> > > ++	CMDLINE_DEFINES="-I${in_qts_dir}"+	;;+*)+	usage+	exit 1+	;;
> > > +esac++# compile+gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o
> > > ${out_dir}/create_handoff_gen5+${out_dir}/create_handoff_gen5 >
> > > ${output_file}++# TODO: remove tmp file:+#rm
> > > $${out_dir}/create_handoff_gen5

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Simon Goldschmidt]

Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
> 
> 
> On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
>>
>>
>> Dalon L Westergreen <dalon.westergreen@linux.intel.com 
>> <mailto:dalon.westergreen@linux.intel.com>> schrieb am Di., 22. Okt. 
>> 2019, 19:10:
>>> I mentioned this before, it would be great to not rely on the 
>>> generated files
>>> and do this based purely on the handoff data generated during a quartus
>>> build. Did you look at the python source i pointed you to?
>>
>> No, not yet. But I don't think that will be a problem. I sent this 
>> series mainly to discuss the dts format (boardspecific handoff dtsi vs 
>> genetic dtsi plus boardspecific header file).
> 
> The board specific dtsi does look cleaner, but i do like the simplicity 
> of generating the header in arria10.
> 
> I could easily replicate what you do, generate the header, and use it to 
> create the dtsi.

I'm not too fond myself of that tool I created, as it requires you to 
have a compiler. I just was too lazy write a script for that.

However, I would prefer having a script that does it. And if the sources 
are quartus output files instead of existing qts files, my tool doesn't 
work any more, anway.

So I think we should come up with a script (e.g. sh or py) that parses 
quartus output and creates a handoff dtsi (without a header). We'll only 
need something different for converting existing qts files then...

Regards,
Simon

> 
> --dalon
> 
>>
>> I still favor boardspecific handoff dtsi, but I would like to use the 
>> same style for all socfpga flavours.
>>
>> Plus this tool is required to convert existing boards where we don't 
>> have the quartus project files at hand.
>>
>> Regards,
>> Simon
>>
>>>
>>> --dalon
>>>
>>> On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
>>>> This new tool converts handoff information from quartus to "*_handoff.dtsi"
>>>> devicetree files. This is in preparation to move from ad-hoc code in arch
>>>> that parses the 'qts' header files to drivers parsing the same information
>>>> from devicetree.
>>>>
>>>> Converting existing U-Boot 'qts' files is also supported.
>>>>
>>>> Signed-off-by: Simon Goldschmidt <
>>>> simon.k.r.goldschmidt at gmail.com
>>>>  <mailto:simon.k.r.goldschmidt@gmail.com>
>>>> >
>>>> ---
>>>>
>>>> Changes in v2: None
>>>>
>>>>   arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
>>>>   arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++
>>>>   2 files changed, 743 insertions(+)
>>>>   create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
>>>>   create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-socfpga/create_handoff_gen5.c
>>>> new file mode 100644
>>>> index 0000000000..6ec436719d
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
>>>> @@ -0,0 +1,660 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * This is a host-tool that needs to be compiled per board and prints the
>>>> + * handoff.dtsi to stdout.
>>>> + */
>>>> +
>>>> +#include <stdio.h>
>>>> +#include <stdint.h>
>>>> +
>>>> +/* Define kernel types */
>>>> +typedef uint8_t u8;
>>>> +typedef uint32_t u32;
>>>> +
>>>> +#ifdef USE_QUARTUS_OUTPUT
>>>> +#ifdef ARRIA5
>>>> +#include "iocsr_config_arria5.c"
>>>> +#include "pinmux_config_arria5.c"
>>>> +#else
>>>> +#include "iocsr_config_cyclone5.c"
>>>> +#include "pinmux_config_cyclone5.c"
>>>> +#endif
>>>> +#include "pll_config.h"
>>>> +#include "sdram/sdram_config.h"
>>>> +#include "sequencer_auto.h"
>>>> +#include "sequencer_defines.h"
>>>> +#include "sequencer_auto_ac_init.c"
>>>> +#include "sequencer_auto_inst_init.c"
>>>> +#define RW_MGR(x) __RW_MGR_##x
>>>> +#else
>>>> +#define RW_MGR(x) RW_MGR_##x
>>>> +#include <iocsr_config.h>
>>>> +#include <pinmux_config.h>
>>>> +#include <pll_config.h>
>>>> +#include <sdram_config.h>
>>>> +#endif
>>>> +
>>>> +#include "include/mach/clock_manager_gen5.h"
>>>> +#include "include/mach/sdram_gen5.h"
>>>> +
>>>> +#ifndef ARRAY_SIZE
>>>> +#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
>>>> +#endif
>>>> +
>>>> +const char handoff_dtsi_hdr[] =
>>>> +	"// SPDX-License-Identifier: GPL-2.0\n"
>>>> +	"/*\n"
>>>> +	" *<auto-generated>\n"
>>>> +	" *	This code was generated by a tool based on\n"
>>>> +	" *	handoffs from both Qsys and Quartus.\n"
>>>> +	" *\n"
>>>> +	" *	Changes to this file may be lost if\n"
>>>> +	" *	the code is regenerated.\n"
>>>> +	" *</auto-generated>\n"
>>>> +	" */\n";
>>>> +
>>>> +/* Wrap PLL config */
>>>> +
>>>> +#define MAIN_VCO_BASE (					\
>>>> +	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
>>>> +		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
>>>> +	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
>>>> +		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
>>>> +	)
>>>> +
>>>> +#define PERI_VCO_BASE (					\
>>>> +	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
>>>> +		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
>>>> +	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
>>>> +		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
>>>> +	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
>>>> +		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
>>>> +	)
>>>> +
>>>> +#define SDR_VCO_BASE (					\
>>>> +	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
>>>> +		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
>>>> +	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
>>>> +		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
>>>> +	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
>>>> +		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
>>>> +	)
>>>> +
>>>> +static const struct cm_config cm_default = {
>>>> +	/* main group */
>>>> +	MAIN_VCO_BASE,
>>>> +	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
>>>> +		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
>>>> +		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
>>>> +		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
>>>> +		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
>>>> +		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
>>>> +		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
>>>> +		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
>>>> +		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
>>>> +	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
>>>> +		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
>>>> +		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
>>>> +	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
>>>> +		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
>>>> +		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
>>>> +	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
>>>> +		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
>>>> +	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
>>>> +		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
>>>> +
>>>> +	/* peripheral group */
>>>> +	PERI_VCO_BASE,
>>>> +	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
>>>> +		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
>>>> +		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
>>>> +	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
>>>> +		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
>>>> +	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
>>>> +		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
>>>> +	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
>>>> +		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
>>>> +		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
>>>> +	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
>>>> +		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
>>>> +	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
>>>> +		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
>>>> +	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
>>>> +		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
>>>> +
>>>> +	/* sdram pll group */
>>>> +	SDR_VCO_BASE,
>>>> +	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
>>>> +		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
>>>> +	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
>>>> +		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
>>>> +		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
>>>> +	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
>>>> +		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
>>>> +		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
>>>> +	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
>>>> +		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
>>>> +	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
>>>> +		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
>>>> +	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
>>>> +		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
>>>> +
>>>> +	/* altera group */
>>>> +	CONFIG_HPS_ALTERAGRP_MPUCLK,
>>>> +};
>>>> +
>>>> +/* Wrap SDRAM config */
>>>> +static const struct socfpga_sdram_config sdram_config = {
>>>> +	.ctrl_cfg =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
>>>> +			SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
>>>> +			SDR_CTRLGRP_CTRLCFG_MEMBL_LSB)			|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
>>>> +			SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
>>>> +			SDR_CTRLGRP_CTRLCFG_ECCEN_LSB)			|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
>>>> +			SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
>>>> +			SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
>>>> +			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
>>>> +			SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
>>>> +			SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
>>>> +	.dram_timing1 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
>>>> +			SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
>>>> +			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
>>>> +			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
>>>> +			SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
>>>> +			SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
>>>> +			SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
>>>> +	.dram_timing2 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
>>>> +			SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
>>>> +			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
>>>> +			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
>>>> +			SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
>>>> +			SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
>>>> +	.dram_timing3 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
>>>> +			SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
>>>> +			SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
>>>> +			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
>>>> +			SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
>>>> +			SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
>>>> +	.dram_timing4 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
>>>> +			SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
>>>> +			SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
>>>> +	.lowpwr_timing =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
>>>> +			SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
>>>> +			SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
>>>> +	.dram_odt =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
>>>> +			SDR_CTRLGRP_DRAMODT_READ_LSB)			|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
>>>> +			SDR_CTRLGRP_DRAMODT_WRITE_LSB),
>>>> +	.extratime1 =
>>>> +	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
>>>> +			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)		|
>>>> +	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
>>>> +			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)		|
>>>> +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
>>>> +			SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
>>>> +	.dram_addrw =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
>>>> +			SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
>>>> +			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
>>>> +			SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB)		|
>>>> +		((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
>>>> +			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
>>>> +	.dram_if_width =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
>>>> +			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
>>>> +	.dram_dev_width =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
>>>> +			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
>>>> +	.dram_intr =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
>>>> +			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
>>>> +	.lowpwr_eq =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
>>>> +			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
>>>> +	.static_cfg =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
>>>> +			SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
>>>> +			SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
>>>> +	.ctrl_width =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
>>>> +			SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
>>>> +	.cport_width =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
>>>> +			SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
>>>> +	.cport_wmap =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
>>>> +			SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
>>>> +	.cport_rmap =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
>>>> +			SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
>>>> +	.rfifo_cmap =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
>>>> +			SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
>>>> +	.wfifo_cmap =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
>>>> +			SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
>>>> +	.cport_rdwr =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
>>>> +			SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
>>>> +	.port_cfg =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
>>>> +			SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
>>>> +	.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
>>>> +	.fifo_cfg =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
>>>> +			SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB)		|
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
>>>> +			SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
>>>> +	.mp_priority =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
>>>> +			SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
>>>> +	.mp_weight0 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
>>>> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
>>>> +	.mp_weight1 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
>>>> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
>>>> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
>>>> +	.mp_weight2 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
>>>> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
>>>> +	.mp_weight3 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
>>>> +			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
>>>> +	.mp_pacing0 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
>>>> +			SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
>>>> +	.mp_pacing1 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
>>>> +			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
>>>> +			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
>>>> +	.mp_pacing2 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
>>>> +			SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
>>>> +	.mp_pacing3 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
>>>> +			SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
>>>> +	.mp_threshold0 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
>>>> +			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
>>>> +	.mp_threshold1 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
>>>> +			SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
>>>> +	.mp_threshold2 =
>>>> +		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
>>>> +			SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
>>>> +	.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
>>>> +};
>>>> +
>>>> +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
>>>> +	.activate_0_and_1		= RW_MGR(ACTIVATE_0_AND_1),
>>>> +	.activate_0_and_1_wait1		= RW_MGR(ACTIVATE_0_AND_1_WAIT1),
>>>> +	.activate_0_and_1_wait2		= RW_MGR(ACTIVATE_0_AND_1_WAIT2),
>>>> +	.activate_1			= RW_MGR(ACTIVATE_1),
>>>> +	.clear_dqs_enable		= RW_MGR(CLEAR_DQS_ENABLE),
>>>> +	.guaranteed_read		= RW_MGR(GUARANTEED_READ),
>>>> +	.guaranteed_read_cont		= RW_MGR(GUARANTEED_READ_CONT),
>>>> +	.guaranteed_write		= RW_MGR(GUARANTEED_WRITE),
>>>> +	.guaranteed_write_wait0		= RW_MGR(GUARANTEED_WRITE_WAIT0),
>>>> +	.guaranteed_write_wait1		= RW_MGR(GUARANTEED_WRITE_WAIT1),
>>>> +	.guaranteed_write_wait2		= RW_MGR(GUARANTEED_WRITE_WAIT2),
>>>> +	.guaranteed_write_wait3		= RW_MGR(GUARANTEED_WRITE_WAIT3),
>>>> +	.idle				= RW_MGR(IDLE),
>>>> +	.idle_loop1			= RW_MGR(IDLE_LOOP1),
>>>> +	.idle_loop2			= RW_MGR(IDLE_LOOP2),
>>>> +	.init_reset_0_cke_0		= RW_MGR(INIT_RESET_0_CKE_0),
>>>> +	.init_reset_1_cke_0		= RW_MGR(INIT_RESET_1_CKE_0),
>>>> +	.lfsr_wr_rd_bank_0		= RW_MGR(LFSR_WR_RD_BANK_0),
>>>> +	.lfsr_wr_rd_bank_0_data		= RW_MGR(LFSR_WR_RD_BANK_0_DATA),
>>>> +	.lfsr_wr_rd_bank_0_dqs		= RW_MGR(LFSR_WR_RD_BANK_0_DQS),
>>>> +	.lfsr_wr_rd_bank_0_nop		= RW_MGR(LFSR_WR_RD_BANK_0_NOP),
>>>> +	.lfsr_wr_rd_bank_0_wait		= RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
>>>> +	.lfsr_wr_rd_bank_0_wl_1		= RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
>>>> +	.lfsr_wr_rd_dm_bank_0		= RW_MGR(LFSR_WR_RD_DM_BANK_0),
>>>> +	.lfsr_wr_rd_dm_bank_0_data	= RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
>>>> +	.lfsr_wr_rd_dm_bank_0_dqs	= RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
>>>> +	.lfsr_wr_rd_dm_bank_0_nop	= RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
>>>> +	.lfsr_wr_rd_dm_bank_0_wait	= RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
>>>> +	.lfsr_wr_rd_dm_bank_0_wl_1	= RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
>>>> +	.mrs0_dll_reset			= RW_MGR(MRS0_DLL_RESET),
>>>> +	.mrs0_dll_reset_mirr		= RW_MGR(MRS0_DLL_RESET_MIRR),
>>>> +	.mrs0_user			= RW_MGR(MRS0_USER),
>>>> +	.mrs0_user_mirr			= RW_MGR(MRS0_USER_MIRR),
>>>> +	.mrs1				= RW_MGR(MRS1),
>>>> +	.mrs1_mirr			= RW_MGR(MRS1_MIRR),
>>>> +	.mrs2				= RW_MGR(MRS2),
>>>> +	.mrs2_mirr			= RW_MGR(MRS2_MIRR),
>>>> +	.mrs3				= RW_MGR(MRS3),
>>>> +	.mrs3_mirr			= RW_MGR(MRS3_MIRR),
>>>> +	.precharge_all			= RW_MGR(PRECHARGE_ALL),
>>>> +	.read_b2b			= RW_MGR(READ_B2B),
>>>> +	.read_b2b_wait1			= RW_MGR(READ_B2B_WAIT1),
>>>> +	.read_b2b_wait2			= RW_MGR(READ_B2B_WAIT2),
>>>> +	.refresh_all			= RW_MGR(REFRESH_ALL),
>>>> +	.rreturn			= RW_MGR(RETURN),
>>>> +	.sgle_read			= RW_MGR(SGLE_READ),
>>>> +	.zqcl				= RW_MGR(ZQCL),
>>>> +
>>>> +	.true_mem_data_mask_width	= RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
>>>> +	.mem_address_mirroring		= RW_MGR_MEM_ADDRESS_MIRRORING,
>>>> +	.mem_data_mask_width		= RW_MGR_MEM_DATA_MASK_WIDTH,
>>>> +	.mem_data_width			= RW_MGR_MEM_DATA_WIDTH,
>>>> +	.mem_dq_per_read_dqs		= RW_MGR_MEM_DQ_PER_READ_DQS,
>>>> +	.mem_dq_per_write_dqs		= RW_MGR_MEM_DQ_PER_WRITE_DQS,
>>>> +	.mem_if_read_dqs_width		= RW_MGR_MEM_IF_READ_DQS_WIDTH,
>>>> +	.mem_if_write_dqs_width		= RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
>>>> +	.mem_number_of_cs_per_dimm	= RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
>>>> +	.mem_number_of_ranks		= RW_MGR_MEM_NUMBER_OF_RANKS,
>>>> +	.mem_virtual_groups_per_read_dqs =
>>>> +		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
>>>> +	.mem_virtual_groups_per_write_dqs =
>>>> +		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
>>>> +};
>>>> +
>>>> +static const struct socfpga_sdram_io_config io_config = {
>>>> +	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,
>>>> +	.delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
>>>> +	.delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,
>>>> +	.delay_per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
>>>> +	.dll_chain_length		= IO_DLL_CHAIN_LENGTH,
>>>> +	.dqdqs_out_phase_max		= IO_DQDQS_OUT_PHASE_MAX,
>>>> +	.dqs_en_delay_max		= IO_DQS_EN_DELAY_MAX,
>>>> +	.dqs_en_delay_offset		= IO_DQS_EN_DELAY_OFFSET,
>>>> +	.dqs_en_phase_max		= IO_DQS_EN_PHASE_MAX,
>>>> +	.dqs_in_delay_max		= IO_DQS_IN_DELAY_MAX,
>>>> +	.dqs_in_reserve			= IO_DQS_IN_RESERVE,
>>>> +	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,
>>>> +	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,
>>>> +	.io_out1_delay_max		= IO_IO_OUT1_DELAY_MAX,
>>>> +	.io_out2_delay_max		= IO_IO_OUT2_DELAY_MAX,
>>>> +	.shift_dqs_en_when_shift_dqs	= IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
>>>> +};
>>>> +
>>>> +static const struct socfpga_sdram_misc_config misc_config = {
>>>> +	.afi_rate_ratio			= AFI_RATE_RATIO,
>>>> +	.calib_lfifo_offset		= CALIB_LFIFO_OFFSET,
>>>> +	.calib_vfifo_offset		= CALIB_VFIFO_OFFSET,
>>>> +	.enable_super_quick_calibration	= ENABLE_SUPER_QUICK_CALIBRATION,
>>>> +	.max_latency_count_width	= MAX_LATENCY_COUNT_WIDTH,
>>>> +	.read_valid_fifo_size		= READ_VALID_FIFO_SIZE,
>>>> +	.reg_file_init_seq_signature_ll	= REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
>>>> +	.reg_file_init_seq_signature_lh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
>>>> +	.reg_file_init_seq_signature_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
>>>> +	.reg_file_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
>>>> +	.tinit_cntr0_val		= TINIT_CNTR0_VAL,
>>>> +	.tinit_cntr1_val		= TINIT_CNTR1_VAL,
>>>> +	.tinit_cntr2_val		= TINIT_CNTR2_VAL,
>>>> +	.treset_cntr0_val		= TRESET_CNTR0_VAL,
>>>> +	.treset_cntr1_val		= TRESET_CNTR1_VAL,
>>>> +	.treset_cntr2_val		= TRESET_CNTR2_VAL,
>>>> +};
>>>> +
>>>> +static void print_hdr(void)
>>>> +{
>>>> +	printf(handoff_dtsi_hdr);
>>>> +}
>>>> +
>>>> +static void print_clkmgr_base(void)
>>>> +{
>>>> +	const char handoff_dtsi_clkmgr_base[] =
>>>> +		"\n"
>>>> +		"&osc1 {\n"
>>>> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
>>>> +		"};\n"
>>>> +		"\n"
>>>> +		"&osc2 {\n"
>>>> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
>>>> +		"};\n"
>>>> +		"\n"
>>>> +		"&f2s_periph_ref_clk {\n"
>>>> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
>>>> +		"};\n"
>>>> +		"\n"
>>>> +		"&f2s_sdram_ref_clk {\n"
>>>> +		"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
>>>> +		"};\n";
>>>> +
>>>> +	printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
>>>> +	       CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
>>>> +	       CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
>>>> +}
>>>> +
>>>> +/*
>>>> + * dtc stores u32 array big endian but we load them raw and expect them to be in
>>>> + * little endian format. To prevent this tool to depend on host endianess, do
>>>> + * the switch manually, not via 'htonl'.
>>>> + */
>>>> +static u32 swap_bytes(u32 val)
>>>> +{
>>>> +	return (val << 24) | ((val & 0xFF00ul) << 8) |
>>>> +		((val & 0xFF0000ul) >> 8) | (val >> 24);
>>>> +}
>>>> +
>>>> +static void print_array_ulong(const unsigned long *arr, size_t arr_size,
>>>> +			      size_t el_per_line, const char *indent1,
>>>> +			      const char *name, const char *indent_next)
>>>> +{
>>>> +	size_t i;
>>>> +
>>>> +	printf("%s%s = <", indent1, name);
>>>> +	for (i = 0; i < arr_size; i++) {
>>>> +		printf("0x%08x", swap_bytes((u32)arr[i]));
>>>> +		if (i + 1 < arr_size) {
>>>> +			if (i % el_per_line == (el_per_line - 1)) {
>>>> +				printf("\n%s", indent_next);
>>>> +			} else {
>>>> +				printf(" ");
>>>> +			}
>>>> +		}
>>>> +	}
>>>> +	printf(">;\n");
>>>> +}
>>>> +
>>>> +#ifdef USE_QUARTUS_OUTPUT
>>>> +static void print_array_sysmgrinit(const unsigned long *arr, size_t arr_size,
>>>> +				   const char *indent1, const char *name,
>>>> +				   const char *indent_next)
>>>> +{
>>>> +	size_t i;
>>>> +
>>>> +	printf("%s%s = [", indent1, name);
>>>> +	for (i = 0; i < arr_size; i++) {
>>>> +		printf("%02x", (u8)arr[i]);
>>>> +		if (i + 1 < arr_size) {
>>>> +			if (i % 8 == 7) {
>>>> +				printf("\n%s", indent_next);
>>>> +			} else {
>>>> +				printf(" ");
>>>> +			}
>>>> +		}
>>>> +	}
>>>> +	printf("];\n");
>>>> +}
>>>> +#define print_array_alt_u32 print_array_ulong
>>>> +#else
>>>> +#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz, 8, ind1, n, ind2)
>>>> +#define print_array_alt_u32 print_array_u32
>>>> +#endif
>>>> +
>>>> +static void print_array_u32(const u32 *arr, size_t arr_size,
>>>> +			    size_t el_per_line, const char *indent1,
>>>> +			    const char *name, const char *indent_next)
>>>> +{
>>>> +	size_t i;
>>>> +
>>>> +	printf("%s%s = <", indent1, name);
>>>> +	for (i = 0; i < arr_size; i++) {
>>>> +		printf("0x%08x", swap_bytes(arr[i]));
>>>> +		if (i + 1 < arr_size) {
>>>> +			if (i % el_per_line == (el_per_line - 1)) {
>>>> +				printf("\n%s", indent_next);
>>>> +			} else {
>>>> +				printf(" ");
>>>> +			}
>>>> +		}
>>>> +	}
>>>> +	printf(">;\n");
>>>> +}
>>>> +
>>>> +static void print_array_u8(const u8 *arr, size_t arr_size, size_t el_per_line,
>>>> +			   const char *indent1, const char *name,
>>>> +			   const char *indent_next)
>>>> +{
>>>> +	size_t i;
>>>> +
>>>> +	printf("%s%s = [", indent1, name);
>>>> +	for (i = 0; i < arr_size; i++) {
>>>> +		printf("%02x", arr[i]);
>>>> +		if (i + 1 < arr_size) {
>>>> +			if (i % el_per_line == (el_per_line - 1)) {
>>>> +				printf("\n%s", indent_next);
>>>> +			} else {
>>>> +				printf(" ");
>>>> +			}
>>>> +		}
>>>> +	}
>>>> +	printf("];\n");
>>>> +}
>>>> +
>>>> +
>>>> +static void print_clkmgr_cfg(void)
>>>> +{
>>>> +	const char handoff_dtsi_clkmgr_cfg_a[] =
>>>> +		"\n"
>>>> +		"&clkmgr {\n";
>>>> +	const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
>>>> +	const char clk_mgr_cfg_indent[] = "\t\t\t    ";
>>>> +
>>>> +	printf(handoff_dtsi_clkmgr_cfg_a);
>>>> +	print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
>>>> +			"altr,clk-mgr-cfg", clk_mgr_cfg_indent);
>>>> +	printf(handoff_dtsi_clkmgr_cfg_b);
>>>> +}
>>>> +
>>>> +static void print_sysmgr(void)
>>>> +{
>>>> +	const char handoff_dtsi_sysmgr_begin[] =
>>>> +		"\n"
>>>> +		"&sysmgr {\n";
>>>> +	const char handoff_dtsi_sysmgr_end[] = "};\n";
>>>> +	const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
>>>> +	size_t i;
>>>> +
>>>> +	printf(handoff_dtsi_sysmgr_begin);
>>>> +
>>>> +	/* sys_mgr_init_table is an u8 table */
>>>> +	print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
>>>> +			       "\t", "altr,pinmux-cfg","\t\t\t   ");
>>>> +	/* ioscr scan chain table 0 */
>>>> +	print_array_ulong(iocsr_scan_chain0_table,
>>>> +			  ARRAY_SIZE(iocsr_scan_chain0_table), 4,
>>>> +			  "\t", "altr,iocsr-scan-chain0-table",
>>>> +			  sysmgr_cfg_indent);
>>>> +	/* ioscr scan chain table 0 */
>>>> +	print_array_ulong(iocsr_scan_chain1_table,
>>>> +			  ARRAY_SIZE(iocsr_scan_chain1_table), 4,
>>>> +			  "\t", "altr,iocsr-scan-chain1-table",
>>>> +			  sysmgr_cfg_indent);
>>>> +	/* ioscr scan chain table 0 */
>>>> +	print_array_ulong(iocsr_scan_chain2_table,
>>>> +			  ARRAY_SIZE(iocsr_scan_chain2_table), 4,
>>>> +			  "\t", "altr,iocsr-scan-chain2-table",
>>>> +			  sysmgr_cfg_indent);
>>>> +	/* ioscr scan chain table 0 */
>>>> +	print_array_ulong(iocsr_scan_chain3_table,
>>>> +			  ARRAY_SIZE(iocsr_scan_chain3_table), 4,
>>>> +			  "\t", "altr,iocsr-scan-chain3-table",
>>>> +			  sysmgr_cfg_indent);
>>>> +	printf(handoff_dtsi_sysmgr_end);
>>>> +}
>>>> +
>>>> +static void print_sdram_cfg(void)
>>>> +{
>>>> +	const char handoff_dtsi_sdram_cfg_begin[] =
>>>> +		"\n"
>>>> +		"&sdr {\n";
>>>> +	const char handoff_dtsi_sdram_cfg_end[] = "};\n";
>>>> +
>>>> +	printf(handoff_dtsi_sdram_cfg_begin);
>>>> +	print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
>>>> +			"\t", "altr,sdr-cfg", "\t\t\t");
>>>> +	print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
>>>> +			"\t", "altr,sdr-rw-mgr-cfg", "\t\t\t       ");
>>>> +	print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
>>>> +			"\t", "altr,sdr-io-cfg", "\t\t\t   ");
>>>> +	print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
>>>> +			"\t", "altr,sdr-misc-cfg", "\t\t\t     ");
>>>> +	print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
>>>> +			"\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
>>>> +	print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
>>>> +			"\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");
>>>> +	printf(handoff_dtsi_sdram_cfg_end);
>>>> +}
>>>> +
>>>> +int main(void)
>>>> +{
>>>> +	print_hdr();
>>>> +	print_clkmgr_base();
>>>> +	print_clkmgr_cfg();
>>>> +	print_sysmgr();
>>>> +	print_sdram_cfg();
>>>> +}
>>>> diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-to-handoff.sh
>>>> new file mode 100755
>>>> index 0000000000..b9032a5411
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
>>>> @@ -0,0 +1,83 @@
>>>> +#!/bin/sh
>>>> +# This script converts Quartus handoff files (in Quartus or U-Boot format)
>>>> +# to a handoff.dtsi file.
>>>> +
>>>> +
>>>> +usage() {
>>>> +	MY_BASENAME=`basename $0`
>>>> +	echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir] [output_file]"
>>>> +	echo " or"
>>>> +	echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
>>>> +	echo ""
>>>> +	echo "Process QTS-generated headers into handoff.dtsi:"
>>>> +	echo ""
>>>> +	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
>>>> +	echo "  input_qts_dir - Directory with compiled Quartus project"
>>>> +	echo "                  and containing the Quartus project file (QPF)."
>>>> +	echo "  input_bsp_dir - Directory with generated bsp containing"
>>>> +	echo "                  the settings.bsp file."
>>>> +	echo "  output_file   - Full filename to store the handoff dtsi file."
>>>> +	echo "  uboot_qts_dir - board/qts directory if input files are in"
>>>> +	echo "                  'old-style' U-Boot format."
>>>> +	echo ""
>>>> +}
>>>> +
>>>> +soc="$1"
>>>> +
>>>> +HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
>>>> +
>>>> +case "$soc" in
>>>> +"cyclone5"|"arria5")
>>>> +	if [ "$#" -ne 4 ] ; then
>>>> +		usage
>>>> +		exit 1
>>>> +	fi
>>>> +	in_qts_dir="$2"
>>>> +	in_bsp_dir="$3"
>>>> +	output_file="$4"
>>>> +	out_dir=`dirname ${output_file}`
>>>> +
>>>> +	if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
>>>> +		! -d "${out_dir}" -o -z "${soc}" ] ; then
>>>> +		usage
>>>> +		exit 3
>>>> +	fi
>>>> +
>>>> +	if [ "$soc" = "cyclone5" ] ; then
>>>> +		CMDLINE_DEFINES="-DCYCLONE5"
>>>> +	else
>>>> +		CMDLINE_DEFINES="-DARRIA5"
>>>> +	fi
>>>> +	CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"
>>>> +	for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
>>>> +		CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
>>>> +	done
>>>> +	;;
>>>> +"u-boot")
>>>> +	if [ "$#" -ne 3 ] ; then
>>>> +		usage
>>>> +		exit 1
>>>> +	fi
>>>> +	in_qts_dir="$2"
>>>> +	output_file="$3"
>>>> +	out_dir=`dirname ${output_file}`
>>>> +
>>>> +	if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
>>>> +		usage
>>>> +		exit 3
>>>> +	fi
>>>> +
>>>> +	CMDLINE_DEFINES="-I${in_qts_dir}"
>>>> +	;;
>>>> +*)
>>>> +	usage
>>>> +	exit 1
>>>> +	;;
>>>> +esac
>>>> +
>>>> +# compile
>>>> +gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o ${out_dir}/create_handoff_gen5
>>>> +${out_dir}/create_handoff_gen5 > ${output_file}
>>>> +
>>>> +# TODO: remove tmp file:
>>>> +#rm $${out_dir}/create_handoff_gen5

[U-Boot] [RFC PATCH v2 00/18] arm: socfpga: gen5: move to DM

[Simon Goldschmidt]

Am 15.10.2019 um 22:10 schrieb Simon Goldschmidt:
> This is an RFC series with the target to move SPL code from arch to
> DM drivers.

I've sent a few patches of this series now as non-RFC, as I don't know 
if I will make it this merge window: I still have trouble getting the 
existing defconfigs into the 64 KB of SRAM for SPL :-(

Might need some work regarding size of DM in SPL...

Regards,
Simon

> 
> It is not finished, but I send this here for discussion mainly about
> the devicetree format with the goal of keeping the various sub-
> architectures (cyclone5, arria10, etc.) in the same style.
> 
> Patch 8 adds a C tool to convert existing gen5 qts handoff files to a
> handoff dtsi. As an example, the last patch contains the handoff dtsi
> for socfpga_socrates.
> 
> I have sent v1 some time ago, but this one has heavily changed and is
> not finished, thus v2 but RFC. This series also is not edited to fix
> patman warnings, yet.
> 
> Changes in v2:
> - add dts based reset handling (messed up in v1)
> - split this patch from v1 5/6
> - split this patch from v1 5/6
> 
> Simon Goldschmidt (18):
>    ddr: socfpga: gen5: constify altera_gen5_sdram_ops
>    dts: arm: socfpga: add label for clkmgr
>    arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN
>    timer: dw-apb: add reset handling
>    arm: socfpga: gen5: move initial reset handling to reset driver
>    arm: dts: socfpga: add settings for gen5 clk driver
>    arm: dts: socfpga: make clock nodes available in SPL
>    socfpga: gen5: add new tool to create handoff dtsi files
>    sdram: socfpga: gen5: make config structs dts compatible
>    ddr: socfpga: gen5: fetch handoff information from 'of_to_platdata'
>    ddr: socfpga: gen5: read handoff information from devicetree
>    arm: socfpga: gen5: add readonly clk driver
>    arm: socfpga: gen5: enable DM CLK
>    arm: socfpga: gen5: move clock initialization to CLK driver
>    arm: socfpga: gen5: load CLK config from devicetree
>    spi: cadence_qspi: support DM_CLK
>    arm: socfpga: gen5: parse qspi clock from devictree
>    socfpga: gen5: move CLK and SDRAM to DM
> 
>   MAINTAINERS                                   |   1 +
>   arch/arm/dts/socfpga-common-u-boot.dtsi       |  71 ++
>   arch/arm/dts/socfpga.dtsi                     |   7 +-
>   .../dts/socfpga_cyclone5_socrates-u-boot.dtsi |   1 +
>   .../socfpga_cyclone5_socrates_handoff.dtsi    | 290 +++++++
>   arch/arm/mach-socfpga/Kconfig                 |   4 +-
>   arch/arm/mach-socfpga/Makefile                |   5 -
>   arch/arm/mach-socfpga/clock_manager.c         |  31 +-
>   arch/arm/mach-socfpga/clock_manager_gen5.c    | 528 -------------
>   arch/arm/mach-socfpga/create_handoff_gen5.c   | 660 ++++++++++++++++
>   arch/arm/mach-socfpga/freeze_controller.c     |  10 +-
>   .../mach-socfpga/include/mach/clock_manager.h |   2 +
>   .../include/mach/clock_manager_gen5.h         |  14 -
>   .../mach-socfpga/include/mach/sdram_gen5.h    |  16 +-
>   arch/arm/mach-socfpga/qts-to-handoff.sh       |  83 +++
>   arch/arm/mach-socfpga/reset_manager_gen5.c    |  13 -
>   arch/arm/mach-socfpga/spl_gen5.c              |  29 +-
>   arch/arm/mach-socfpga/wrap_pll_config.c       | 146 ----
>   arch/arm/mach-socfpga/wrap_sdram_config.c     | 318 --------
>   drivers/clk/altera/Makefile                   |   1 +
>   drivers/clk/altera/clk-gen5.c                 | 705 ++++++++++++++++++
>   drivers/ddr/altera/sdram_gen5.c               |  92 ++-
>   drivers/ddr/altera/sequencer.c                |  74 +-
>   drivers/ddr/altera/sequencer.h                |   9 +-
>   drivers/reset/reset-socfpga.c                 |  37 +-
>   drivers/spi/cadence_qspi.c                    |  20 +-
>   drivers/timer/dw-apb-timer.c                  |  18 +-
>   include/configs/socfpga_common.h              |   5 -
>   28 files changed, 2072 insertions(+), 1118 deletions(-)
>   create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi
>   delete mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c
>   create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
>   create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
>   delete mode 100644 arch/arm/mach-socfpga/wrap_pll_config.c
>   delete mode 100644 arch/arm/mach-socfpga/wrap_sdram_config.c
>   create mode 100644 drivers/clk/altera/clk-gen5.c
> 

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Dalon L Westergreen]

On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
> Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
> > On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
> > > Dalon L Westergreen <dalon.westergreen@linux.intel.com <mailto:
> > > dalon.westergreen at linux.intel.com>> schrieb am Di., 22. Okt. 2019, 19:10:
> > > > I mentioned this before, it would be great to not rely on the generated
> > > > filesand do this based purely on the handoff data generated during a
> > > > quartusbuild. Did you look at the python source i pointed you to?
> > > 
> > > No, not yet. But I don't think that will be a problem. I sent this series
> > > mainly to discuss the dts format (boardspecific handoff dtsi vs genetic
> > > dtsi plus boardspecific header file).
> > 
> > The board specific dtsi does look cleaner, but i do like the simplicity of
> > generating the header in arria10.
> > I could easily replicate what you do, generate the header, and use it to
> > create the dtsi.
> 
> I'm not too fond myself of that tool I created, as it requires you to have a
> compiler. I just was too lazy write a script for that.
> However, I would prefer having a script that does it. And if the sources are
> quartus output files instead of existing qts files, my tool doesn't work any
> more, anway.
> So I think we should come up with a script (e.g. sh or py) that parses quartus
> output and creates a handoff dtsi (without a header). We'll only need
> something different for converting existing qts files then...

In that case, i would stick with adding a .h file along with a common handoff
dtsi as i didin the a10 filter script i sent the other week. I would suggest
your source is perfectfor migrating existing c5/a5 platforms.
Is there a preference for python?  It would fit nicely b/c we could re-use the
codeI pointed out previously for binary parsing.
Dinh, Marek, Ley Foon, comments?
--dalon
> Regards,Simon
> > --dalon
> > > I still favor boardspecific handoff dtsi, but I would like to use the same
> > > style for all socfpga flavours.
> > > Plus this tool is required to convert existing boards where we don't have
> > > the quartus project files at hand.
> > > Regards,Simon
> > > > --dalon
> > > > On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
> > > > > This new tool converts handoff information from quartus to
> > > > > "*_handoff.dtsi"devicetree files. This is in preparation to move from
> > > > > ad-hoc code in archthat parses the 'qts' header files to drivers
> > > > > parsing the same informationfrom devicetree.
> > > > > Converting existing U-Boot 'qts' files is also supported.
> > > > > Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com
> > > > >  <mailto:simon.k.r.goldschmidt@gmail.com>
> > > > > ---
> > > > > Changes in v2: None
> > > > >   arch/arm/mach-socfpga/create_handoff_gen5.c | 660
> > > > > ++++++++++++++++++++  arch/arm/mach-socfpga/qts-to-
> > > > > handoff.sh     |  83 +++  2 files changed, 743 insertions(+)  create
> > > > > mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c  create mode
> > > > > 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
> > > > > diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c
> > > > > b/arch/arm/mach-socfpga/create_handoff_gen5.cnew file mode 100644index
> > > > > 0000000000..6ec436719d--- /dev/null+++ b/arch/arm/mach-
> > > > > socfpga/create_handoff_gen5.c@@ -0,0 +1,660 @@+// SPDX-License-
> > > > > Identifier: GPL-2.0+/*+ * This is a host-tool that needs to be
> > > > > compiled per board and prints the+ * handoff.dtsi to stdout.+
> > > > > */++#include <stdio.h>+#include <stdint.h>++/* Define kernel types
> > > > > */+typedef uint8_t u8;+typedef uint32_t u32;++#ifdef
> > > > > USE_QUARTUS_OUTPUT+#ifdef ARRIA5+#include
> > > > > "iocsr_config_arria5.c"+#include
> > > > > "pinmux_config_arria5.c"+#else+#include
> > > > > "iocsr_config_cyclone5.c"+#include
> > > > > "pinmux_config_cyclone5.c"+#endif+#include "pll_config.h"+#include
> > > > > "sdram/sdram_config.h"+#include "sequencer_auto.h"+#include
> > > > > "sequencer_defines.h"+#include "sequencer_auto_ac_init.c"+#include
> > > > > "sequencer_auto_inst_init.c"+#define RW_MGR(x)
> > > > > __RW_MGR_##x+#else+#define RW_MGR(x) RW_MGR_##x+#include
> > > > > <iocsr_config.h>+#include <pinmux_config.h>+#include
> > > > > <pll_config.h>+#include <sdram_config.h>+#endif++#include
> > > > > "include/mach/clock_manager_gen5.h"+#include
> > > > > "include/mach/sdram_gen5.h"++#ifndef ARRAY_SIZE+#define ARRAY_SIZE(x)
> > > > > (sizeof(x)/sizeof((x)[0]))+#endif++const char handoff_dtsi_hdr[] =+	
> > > > > "// SPDX-License-Identifier: GPL-2.0\n"+	"/*\n"+	" *<auto-
> > > > > generated>\n"+	" *	This code was generated by a tool
> > > > > based on\n"+	" *	handoffs from both Qsys and Quartus.\n"+	
> > > > > " *\n"+	" *	Changes to this file may be lost if\n"+	" *	
> > > > > the code is regenerated.\n"+	" *</auto-generated>\n"+	" */\n";++/*
> > > > > Wrap PLL config */++#define MAIN_VCO_BASE (					
> > > > > \+	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\+		
> > > > > CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\+	(CONFIG_HPS_MAINPLLGRP
> > > > > _VCO_NUMER <<		\+		CLKMGR_MAINPLLGRP_VCO_NUMER_OF
> > > > > FSET)	\+	)++#define PERI_VCO_BASE (				
> > > > > 	\+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\+	
> > > > > 	CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\+	(CONFIG_HPS_PE
> > > > > RPLLGRP_VCO_DENOM <<		\+		CLKMGR_PERPLLGRP_VCO_D
> > > > > ENOM_OFFSET) |	\+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<	
> > > > > 	\+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\+	
> > > > > )++#define SDR_VCO_BASE (					\+	
> > > > > (CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\+		CLKMGR
> > > > > _SDRPLLGRP_VCO_SSRC_OFFSET) |	\+	(CONFIG_HPS_SDRPLLGRP_VCO_DENO
> > > > > M <<		\+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	
> > > > > \+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\+		
> > > > > CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\+	)++static const struct
> > > > > cm_config cm_default = {+	/* main group */+	MAIN_VCO_BASE,+	(CONFI
> > > > > G_HPS_MAINPLLGRP_MPUCLK_CNT <<+		CLKMGR_MAINPLLGRP_MPUCLK
> > > > > _CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<+		
> > > > > CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_D
> > > > > BGATCLK_CNT <<+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),+
> > > > > 	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<+		CLKMGR
> > > > > _MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_MAINNANDS
> > > > > DMMCCLK_CNT <<+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFF
> > > > > SET),+	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<+		
> > > > > CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),+	(CONFIG_HPS_MAIN
> > > > > PLLGRP_MAINDIV_L3MPCLK <<+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCL
> > > > > K_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<+		
> > > > > CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_M
> > > > > AINDIV_L4MPCLK <<+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET
> > > > > ) |+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<+		CLKMGR
> > > > > _MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DB
> > > > > GATCLK <<+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |+	
> > > > > (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<+		CLKMGR_MAINPLLGR
> > > > > P_DBGDIV_DBGCLK_OFFSET),+	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
> > > > > <<+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),+	(CONFI
> > > > > G_HPS_MAINPLLGRP_L4SRC_L4MP <<+		CLKMGR_MAINPLLGRP_L4SRC_
> > > > > L4MP_OFFSET) |+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<+		
> > > > > CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),++	/* peripheral group */+	
> > > > > PERI_VCO_BASE,+	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<+		
> > > > > CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_EM
> > > > > AC1CLK_CNT <<+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),+	
> > > > > (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<+		CLKMGR_PERPLLGRP
> > > > > _PERQSPICLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CN
> > > > > T <<+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),+	(CONFI
> > > > > G_HPS_PERPLLGRP_PERBASECLK_CNT <<+		CLKMGR_PERPLLGRP_PERBASE
> > > > > CLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<+		
> > > > > CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),+	(CONFIG_HPS_PERPLLGRP_DI
> > > > > V_USBCLK <<+		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |+	(CONFI
> > > > > G_HPS_PERPLLGRP_DIV_SPIMCLK <<+		CLKMGR_PERPLLGRP_DIV_SPI
> > > > > MCLK_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<+		
> > > > > CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_DI
> > > > > V_CAN1CLK <<+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),+	(CONFI
> > > > > G_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<+		CLKMGR_PERPLLGRP_GPIODIV
> > > > > _GPIODBCLK_OFFSET),+	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<+		
> > > > > CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |+	(CONFIG_HPS_PERPLLGRP_SRC_NAND
> > > > > <<+		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |+	(CONFIG_HPS_PE
> > > > > RPLLGRP_SRC_SDMMC <<+		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),++	
> > > > > /* sdram pll group */+	SDR_VCO_BASE,+	(CONFIG_HPS_SDRPLLGRP_
> > > > > DDRDQSCLK_PHASE <<+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET)
> > > > > |+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<+		CLKMGR_SDRPLLG
> > > > > RP_DDRDQSCLK_CNT_OFFSET),+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
> > > > > <<+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |+	(CONFI
> > > > > G_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<+		CLKMGR_SDRPLLGRP_DDR2XDQ
> > > > > SCLK_CNT_OFFSET),+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<+		
> > > > > CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_DD
> > > > > RDQCLK_CNT <<+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),+	
> > > > > (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<+		CLKMGR_SDRPLLGRP
> > > > > _S2FUSER2CLK_PHASE_OFFSET) |+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
> > > > > <<+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),++	/*
> > > > > altera group */+	CONFIG_HPS_ALTERAGRP_MPUCLK,+};++/* Wrap SDRAM
> > > > > config */+static const struct socfpga_sdram_config sdram_config = {+	
> > > > > .ctrl_cfg =+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<+	
> > > > > 		SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB)		|+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<+			SDR_CTRL
> > > > > GRP_CTRLCFG_MEMBL_LSB)			|+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<+			SDR_CTRL
> > > > > GRP_CTRLCFG_ADDRORDER_LSB)		|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_CTRLCFG_ECCEN <<+			SDR_CTRLGRP_CTRLCFG_ECCE
> > > > > N_LSB)			|+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_CTRLCFG_ECCCORREN <<+			SDR_CTRLGRP_CTRLCFG_ECCC
> > > > > ORREN_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCF
> > > > > G_REORDEREN <<+			SDR_CTRLGRP_CTRLCFG_REORDEREN_LS
> > > > > B)		|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVE
> > > > > LIMIT <<+			SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB)	
> > > > > 	|+		(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<+	
> > > > > 		SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB)		|+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<+			SDR_CTRL
> > > > > GRP_CTRLCFG_NODMPINS_LSB),+	.dram_timing1 =+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMTIMING1_TCWL <<+			SDR_CTRLGRP_DRAM
> > > > > TIMING1_TCWL_LSB)		|+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_DRAMTIMING1_AL <<+			SDR_CTRLGRP_DRAMTIMING1_TAL_LSB)
> > > > > 		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TC
> > > > > L <<+			SDR_CTRLGRP_DRAMTIMING1_TCL_LSB)		|+	
> > > > > 	(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<+			
> > > > > SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB)		|+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<+			SDR_CTRL
> > > > > GRP_DRAMTIMING1_TFAW_LSB)		|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMTIMING1_TRFC <<+			SDR_CTRLGRP_DRAM
> > > > > TIMING1_TRFC_LSB),+	.dram_timing2 =+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_DRAMTIMING2_IF_TREFI <<+			SDR_CTRLGRP_DRAMTIMING2_
> > > > > TREFI_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTI
> > > > > MING2_IF_TRCD <<+			SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB
> > > > > )		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF
> > > > > _TRP <<+			SDR_CTRLGRP_DRAMTIMING2_TRP_LSB)		
> > > > > |+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<+		
> > > > > 	SDR_CTRLGRP_DRAMTIMING2_TWR_LSB)		|+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<+			SDR_CTRL
> > > > > GRP_DRAMTIMING2_TWTR_LSB),+	.dram_timing3 =+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMTIMING3_TRTP <<+			SDR_CTRLGRP_DRAM
> > > > > TIMING3_TRTP_LSB)		|+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_DRAMTIMING3_TRAS <<+			SDR_CTRLGRP_DRAMTIMING3_
> > > > > TRAS_LSB)		|+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTI
> > > > > MING3_TRC <<+			SDR_CTRLGRP_DRAMTIMING3_TRC_LSB)		
> > > > > |+		(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<+		
> > > > > 	SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB)		|+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<+			SDR_CTRL
> > > > > GRP_DRAMTIMING3_TCCD_LSB),+	.dram_timing4 =+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<+			SDR_CTRL
> > > > > GRP_DRAMTIMING4_SELFRFSHEXIT_LSB)	|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<+			SDR_CTRLGRP_DRAM
> > > > > TIMING4_PWRDOWNEXIT_LSB),+	.lowpwr_timing =+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<+			SDR_CTRL
> > > > > GRP_LOWPWRTIMING_AUTOPDCYCLES_LSB)	|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<+			SDR_CTRL
> > > > > GRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),+	.dram_odt =+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<+			SDR_CTRL
> > > > > GRP_DRAMODT_READ_LSB)			|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMODT_WRITE <<+			SDR_CTRLGRP_DRAMODT_WRIT
> > > > > E_LSB),+	.extratime1 =+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG
> > > > > _EXTRA_CTL_CLK_RD_TO_WR <<+			SDR_CTRLGRP_EXTRATIME1_R
> > > > > D_TO_WR_LSB)		|+	(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG
> > > > > _EXTRA_CTL_CLK_RD_TO_WR_BC <<+			SDR_CTRLGRP_EXTR
> > > > > ATIME1_RD_TO_WR_BC_LSB)		|+(CONFIG_HPS_SDR_CTRLCFG_EXTRAT
> > > > > IME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<+			SDR_CTRL
> > > > > GRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),+	.dram_addrw =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<+			SDR_CTRL
> > > > > GRP_DRAMADDRW_COLBITS_LSB)		|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_DRAMADDRW_ROWBITS <<+			SDR_CTRLGRP_DRAM
> > > > > ADDRW_ROWBITS_LSB)		|+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_DRAMADDRW_BANKBITS <<+			SDR_CTRLGRP_DRAMADDRW_BA
> > > > > NKBITS_LSB)		|+		((CONFIG_HPS_SDR_CTRLCFG_DRAMA
> > > > > DDRW_CSBITS - 1) <<+			SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB
> > > > > ),+	.dram_if_width =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IF
> > > > > WIDTH <<+			SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),+	
> > > > > .dram_dev_width =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEV
> > > > > WIDTH <<+			SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),+
> > > > > 	.dram_intr =+		(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTRE
> > > > > N <<+			SDR_CTRLGRP_DRAMINTR_INTREN_LSB),+	.lowpw
> > > > > r_eq =+		(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
> > > > > <<+			SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),+	.stati
> > > > > c_cfg =+		(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<+	
> > > > > 		SDR_CTRLGRP_STATICCFG_MEMBL_LSB)		|+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<+			
> > > > > SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),+	.ctrl_width =+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<+			
> > > > > SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),+	.cport_width =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<+			SDR_CTRL
> > > > > GRP_CPORTWIDTH_CMDPORTWIDTH_LSB),+	.cport_wmap =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<+			SDR_CTRL
> > > > > GRP_CPORTWMAP_CPORTWFIFOMAP_LSB),+	.cport_rmap =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<+			SDR_CTRL
> > > > > GRP_CPORTRMAP_CPORTRFIFOMAP_LSB),+	.rfifo_cmap =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<+			SDR_CTRL
> > > > > GRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),+	.wfifo_cmap =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<+			SDR_CTRL
> > > > > GRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),+	.cport_rdwr =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<+			SDR_CTRL
> > > > > GRP_CPORTRDWR_CPORTRDWR_LSB),+	.port_cfg =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<+			SDR_CTRL
> > > > > GRP_PORTCFG_AUTOPCHEN_LSB),+	.fpgaport_rst =
> > > > > CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,+	.fifo_cfg =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<+			SDR_CTRL
> > > > > GRP_FIFOCFG_SYNCMODE_LSB)		|+		(CONFIG_HPS_SD
> > > > > R_CTRLCFG_FIFOCFG_INCSYNC <<+			SDR_CTRLGRP_FIFOCFG_INCS
> > > > > YNC_LSB),+	.mp_priority =+		(CONFIG_HPS_SDR_CTRLCFG_MPPRIO
> > > > > RITY_USERPRIORITY <<+			SDR_CTRLGRP_MPPRIORITY_USERPRIOR
> > > > > ITY_LSB),+	.mp_weight0 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEI
> > > > > GHT_0_STATICWEIGHT_31_0 <<+			SDR_CTRLGRP_MPWEIGHT_MPW
> > > > > EIGHT_0_STATICWEIGHT_31_0_LSB),+	.mp_weight1 =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<+			
> > > > > SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<+			
> > > > > SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),+	.mp_weig
> > > > > ht2 =+		(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_
> > > > > 45_14 <<+			SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEI
> > > > > GHTS_45_14_LSB),+	.mp_weight3 =+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<+			SDR_CTRLGRP_MPWE
> > > > > IGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),+	.mp_pacing0 =+		
> > > > > (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<+			
> > > > > SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),+	.mp_paci
> > > > > ng1 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59
> > > > > _32 <<+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOL
> > > > > D1_59_32_LSB) |+		(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRES
> > > > > HOLD2_3_0 <<+			SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOL
> > > > > D2_3_0_LSB),+	.mp_pacing2 =+		(CONFIG_HPS_SDR_CTRLCFG_MPPACI
> > > > > NG_2_THRESHOLD2_35_4 <<+			SDR_CTRLGRP_MPPACING_MPP
> > > > > ACING_2_THRESHOLD2_35_4_LSB),+	.mp_pacing3 =+		(CONFI
> > > > > G_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<+			
> > > > > SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),+	.mp_threshold0
> > > > > =+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYC
> > > > > LES_31_0 <<+			SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRS
> > > > > TCYCLES_31_0_LSB),+	.mp_threshold1 =+		(CONFIG_HPS_SDR_CTRLCF
> > > > > G_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<+			
> > > > > SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),+	.mp_th
> > > > > reshold2 =+		(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHO
> > > > > LDRSTCYCLES_79_64 <<+			SDR_CTRLGRP_MPTHRESHOLDRST_2_THR
> > > > > ESHOLDRSTCYCLES_79_64_LSB),+	.phy_ctrl0 =
> > > > > CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,+};++static const struct
> > > > > socfpga_sdram_rw_mgr_config rw_mgr_config = {+	.activate_0_and_
> > > > > 1		= RW_MGR(ACTIVATE_0_AND_1),+	.activate_0_and_1_wait
> > > > > 1		= RW_MGR(ACTIVATE_0_AND_1_WAIT1),+	.activate_0_an
> > > > > d_1_wait2		= RW_MGR(ACTIVATE_0_AND_1_WAIT2),+	.activ
> > > > > ate_1			= RW_MGR(ACTIVATE_1),+	.clear_dqs_enable	
> > > > > 	= RW_MGR(CLEAR_DQS_ENABLE),+	.guaranteed_read		
> > > > > = RW_MGR(GUARANTEED_READ),+	.guaranteed_read_cont		=
> > > > > RW_MGR(GUARANTEED_READ_CONT),+	.guaranteed_write		=
> > > > > RW_MGR(GUARANTEED_WRITE),+	.guaranteed_write_wait0		=
> > > > > RW_MGR(GUARANTEED_WRITE_WAIT0),+	.guaranteed_write_wait1		
> > > > > = RW_MGR(GUARANTEED_WRITE_WAIT1),+	.guaranteed_write_wait2		
> > > > > = RW_MGR(GUARANTEED_WRITE_WAIT2),+	.guaranteed_write_wait3		
> > > > > = RW_MGR(GUARANTEED_WRITE_WAIT3),+	.idle				
> > > > > = RW_MGR(IDLE),+	.idle_loop1			=
> > > > > RW_MGR(IDLE_LOOP1),+	.idle_loop2			=
> > > > > RW_MGR(IDLE_LOOP2),+	.init_reset_0_cke_0		=
> > > > > RW_MGR(INIT_RESET_0_CKE_0),+	.init_reset_1_cke_0		=
> > > > > RW_MGR(INIT_RESET_1_CKE_0),+	.lfsr_wr_rd_bank_0		=
> > > > > RW_MGR(LFSR_WR_RD_BANK_0),+	.lfsr_wr_rd_bank_0_data		=
> > > > > RW_MGR(LFSR_WR_RD_BANK_0_DATA),+	.lfsr_wr_rd_bank_0_dqs		
> > > > > = RW_MGR(LFSR_WR_RD_BANK_0_DQS),+	.lfsr_wr_rd_bank_0_nop		
> > > > > = RW_MGR(LFSR_WR_RD_BANK_0_NOP),+	.lfsr_wr_rd_bank_0_wait		
> > > > > = RW_MGR(LFSR_WR_RD_BANK_0_WAIT),+	.lfsr_wr_rd_bank_0_wl_1		
> > > > > = RW_MGR(LFSR_WR_RD_BANK_0_WL_1),+	.lfsr_wr_rd_dm_bank_0		
> > > > > = RW_MGR(LFSR_WR_RD_DM_BANK_0),+	.lfsr_wr_rd_dm_bank_0_data	
> > > > > = RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),+	.lfsr_wr_rd_dm_bank_0_dqs	=
> > > > > RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),+	.lfsr_wr_rd_dm_bank_0_nop	=
> > > > > RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),+	.lfsr_wr_rd_dm_bank_0_wait	
> > > > > = RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),+	.lfsr_wr_rd_dm_bank_0_wl_1	
> > > > > = RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),+	.mrs0_dll_reset			
> > > > > = RW_MGR(MRS0_DLL_RESET),+	.mrs0_dll_reset_mirr		=
> > > > > RW_MGR(MRS0_DLL_RESET_MIRR),+	.mrs0_user			=
> > > > > RW_MGR(MRS0_USER),+	.mrs0_user_mirr			=
> > > > > RW_MGR(MRS0_USER_MIRR),+	.mrs1				=
> > > > > RW_MGR(MRS1),+	.mrs1_mirr			=
> > > > > RW_MGR(MRS1_MIRR),+	.mrs2				=
> > > > > RW_MGR(MRS2),+	.mrs2_mirr			=
> > > > > RW_MGR(MRS2_MIRR),+	.mrs3				=
> > > > > RW_MGR(MRS3),+	.mrs3_mirr			=
> > > > > RW_MGR(MRS3_MIRR),+	.precharge_all			=
> > > > > RW_MGR(PRECHARGE_ALL),+	.read_b2b			=
> > > > > RW_MGR(READ_B2B),+	.read_b2b_wait1			=
> > > > > RW_MGR(READ_B2B_WAIT1),+	.read_b2b_wait2			=
> > > > > RW_MGR(READ_B2B_WAIT2),+	.refresh_all			=
> > > > > RW_MGR(REFRESH_ALL),+	.rreturn			= RW_MGR(RETURN),+	
> > > > > .sgle_read			= RW_MGR(SGLE_READ),+	.zqcl		
> > > > > 		= RW_MGR(ZQCL),++	.true_mem_data_mask_width	=
> > > > > RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,+	.mem_address_mirroring		
> > > > > = RW_MGR_MEM_ADDRESS_MIRRORING,+	.mem_data_mask_width		
> > > > > = RW_MGR_MEM_DATA_MASK_WIDTH,+	.mem_data_width			
> > > > > = RW_MGR_MEM_DATA_WIDTH,+	.mem_dq_per_read_dqs		=
> > > > > RW_MGR_MEM_DQ_PER_READ_DQS,+	.mem_dq_per_write_dqs		=
> > > > > RW_MGR_MEM_DQ_PER_WRITE_DQS,+	.mem_if_read_dqs_width		=
> > > > > RW_MGR_MEM_IF_READ_DQS_WIDTH,+	.mem_if_write_dqs_width		
> > > > > = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,+	.mem_number_of_cs_per_dimm	
> > > > > = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,+	.mem_number_of_ranks		
> > > > > = RW_MGR_MEM_NUMBER_OF_RANKS,+	.mem_virtual_groups_per_read_dqs
> > > > > =+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,+	.mem_virtual_g
> > > > > roups_per_write_dqs =+		RW_MGR_MEM_VIRTUAL_GROUPS_PER_WR
> > > > > ITE_DQS,+};++static const struct socfpga_sdram_io_config io_config =
> > > > > {+	.delay_per_dchain_tap		= IO_DELAY_PER_DCHAIN_TAP,+	
> > > > > .delay_per_dqs_en_dchain_tap	= IO_DELAY_PER_DQS_EN_DCHAIN_TAP,+	
> > > > > .delay_per_opa_tap_lo		= IO_DELAY_PER_OPA_TAP & 0xff,+	.delay
> > > > > _per_opa_tap_hi		= (IO_DELAY_PER_OPA_TAP << 8) & 0xff,+	
> > > > > .dll_chain_length		= IO_DLL_CHAIN_LENGTH,+	.dqdqs_out_pha
> > > > > se_max		= IO_DQDQS_OUT_PHASE_MAX,+	.dqs_en_delay_
> > > > > max		= IO_DQS_EN_DELAY_MAX,+	.dqs_en_delay_offset		
> > > > > = IO_DQS_EN_DELAY_OFFSET,+	.dqs_en_phase_max		=
> > > > > IO_DQS_EN_PHASE_MAX,+	.dqs_in_delay_max		=
> > > > > IO_DQS_IN_DELAY_MAX,+	.dqs_in_reserve			=
> > > > > IO_DQS_IN_RESERVE,+	.dqs_out_reserve		= IO_DQS_OUT_RESERVE,+
> > > > > 	.io_in_delay_max		= IO_IO_IN_DELAY_MAX,+	.io_ou
> > > > > t1_delay_max		= IO_IO_OUT1_DELAY_MAX,+	.io_out2_delay_max	
> > > > > 	= IO_IO_OUT2_DELAY_MAX,+	.shift_dqs_en_when_shift_dqs	=
> > > > > IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,+};++static const struct
> > > > > socfpga_sdram_misc_config misc_config = {+	.afi_rate_ratio		
> > > > > 	= AFI_RATE_RATIO,+	.calib_lfifo_offset		=
> > > > > CALIB_LFIFO_OFFSET,+	.calib_vfifo_offset		=
> > > > > CALIB_VFIFO_OFFSET,+	.enable_super_quick_calibration	=
> > > > > ENABLE_SUPER_QUICK_CALIBRATION,+	.max_latency_count_width	=
> > > > > MAX_LATENCY_COUNT_WIDTH,+	.read_valid_fifo_size		=
> > > > > READ_VALID_FIFO_SIZE,+	.reg_file_init_seq_signature_ll	=
> > > > > REG_FILE_INIT_SEQ_SIGNATURE & 0xff,+	.reg_file_init_seq_signature_lh	
> > > > > = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,+	.reg_file_init_seq_signa
> > > > > ture_hl	= (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,+	.reg_f
> > > > > ile_init_seq_signature_hh	= (REG_FILE_INIT_SEQ_SIGNATURE >> 24) &
> > > > > 0xff,+	.tinit_cntr0_val		= TINIT_CNTR0_VAL,+	.tinit
> > > > > _cntr1_val		= TINIT_CNTR1_VAL,+	.tinit_cntr2_val	
> > > > > 	= TINIT_CNTR2_VAL,+	.treset_cntr0_val		=
> > > > > TRESET_CNTR0_VAL,+	.treset_cntr1_val		= TRESET_CNTR1_VAL,+	
> > > > > .treset_cntr2_val		= TRESET_CNTR2_VAL,+};++static void
> > > > > print_hdr(void)+{+	printf(handoff_dtsi_hdr);+}++static void
> > > > > print_clkmgr_base(void)+{+	const char handoff_dtsi_clkmgr_base[] =+
> > > > > 		"\n"+		"&osc1 {\n"+		"	clock-
> > > > > frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */+		"};\n"+	
> > > > > 	"\n"+		"&osc2 {\n"+		"	clock-
> > > > > frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */+		"};\n"+	
> > > > > 	"\n"+		"&f2s_periph_ref_clk {\n"+		"	
> > > > > clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */+		
> > > > > "};\n"+		"\n"+		"&f2s_sdram_ref_clk {\n"+	
> > > > > 	"	clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ
> > > > > */+		"};\n";++	printf(handoff_dtsi_clkmgr_base,
> > > > > CONFIG_HPS_CLK_OSC1_HZ,+	       CONFIG_HPS_CLK_OSC2_HZ,
> > > > > CONFIG_HPS_CLK_F2S_PER_REF_HZ,+	       CONFIG_HPS_CLK_F2S_SDR_RE
> > > > > F_HZ);+}++/*+ * dtc stores u32 array big endian but we load them raw
> > > > > and expect them to be in+ * little endian format. To prevent this tool
> > > > > to depend on host endianess, do+ * the switch manually, not via
> > > > > 'htonl'.+ */+static u32 swap_bytes(u32 val)+{+	return (val <<
> > > > > 24) | ((val & 0xFF00ul) << 8) |+		((val & 0xFF0000ul) >>
> > > > > 8) | (val >> 24);+}++static void print_array_ulong(const unsigned long
> > > > > *arr, size_t arr_size,+			      size_t
> > > > > el_per_line, const char *indent1,+			      const char
> > > > > *name, const char *indent_next)+{+	size_t i;++	printf("%s%s =
> > > > > <", indent1, name);+	for (i = 0; i < arr_size; i++) {+		printf
> > > > > ("0x%08x", swap_bytes((u32)arr[i]));+		if (i + 1 < arr_size) {+
> > > > > 			if (i % el_per_line == (el_per_line - 1)) {+	
> > > > > 			printf("\n%s", indent_next);+			
> > > > > } else {+				printf(" ");+			
> > > > > }+		}+	}+	printf(">;\n");+}++#ifdef
> > > > > USE_QUARTUS_OUTPUT+static void print_array_sysmgrinit(const unsigned
> > > > > long *arr, size_t arr_size,+				   const char
> > > > > *indent1, const char *name,+				   const char
> > > > > *indent_next)+{+	size_t i;++	printf("%s%s = [", indent1,
> > > > > name);+	for (i = 0; i < arr_size; i++) {+		printf("%02x",
> > > > > (u8)arr[i]);+		if (i + 1 < arr_size) {+			if (i
> > > > > % 8 == 7) {+				printf("\n%s", indent_next);+	
> > > > > 		} else {+				printf(" ");+		
> > > > > 	}+		}+	}+	printf("];\n");+}+#define
> > > > > print_array_alt_u32 print_array_ulong+#else+#define
> > > > > print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz,
> > > > > 8, ind1, n, ind2)+#define print_array_alt_u32
> > > > > print_array_u32+#endif++static void print_array_u32(const u32 *arr,
> > > > > size_t arr_size,+			    size_t el_per_line, const
> > > > > char *indent1,+			    const char *name, const char
> > > > > *indent_next)+{+	size_t i;++	printf("%s%s = <", indent1,
> > > > > name);+	for (i = 0; i < arr_size; i++) {+		printf("0x%08x
> > > > > ", swap_bytes(arr[i]));+		if (i + 1 < arr_size) {+		
> > > > > 	if (i % el_per_line == (el_per_line - 1)) {+			
> > > > > 	printf("\n%s", indent_next);+			} else {+	
> > > > > 			printf(" ");+			}+		
> > > > > }+	}+	printf(">;\n");+}++static void print_array_u8(const u8
> > > > > *arr, size_t arr_size, size_t el_per_line,+			   const
> > > > > char *indent1, const char *name,+			   const char
> > > > > *indent_next)+{+	size_t i;++	printf("%s%s = [", indent1,
> > > > > name);+	for (i = 0; i < arr_size; i++) {+		printf("%02x",
> > > > > arr[i]);+		if (i + 1 < arr_size) {+			if (i
> > > > > % el_per_line == (el_per_line - 1)) {+				
> > > > > printf("\n%s", indent_next);+			} else {+		
> > > > > 		printf(" ");+			}+		}+	
> > > > > }+	printf("];\n");+}+++static void print_clkmgr_cfg(void)+{+	const
> > > > > char handoff_dtsi_clkmgr_cfg_a[] =+		"\n"+		"&clkm
> > > > > gr {\n";+	const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";+	const
> > > > > char clk_mgr_cfg_indent[] = "\t\t\t    ";++	printf(handoff_dtsi_clkm
> > > > > gr_cfg_a);+	print_array_u32((const u32 *)&cm_default,
> > > > > sizeof(cm_default)/4, 4, "\t",+			"altr,clk-mgr-
> > > > > cfg", clk_mgr_cfg_indent);+	printf(handoff_dtsi_clkmgr_cfg_b);+}++st
> > > > > atic void print_sysmgr(void)+{+	const char
> > > > > handoff_dtsi_sysmgr_begin[] =+		"\n"+		"&sysm
> > > > > gr {\n";+	const char handoff_dtsi_sysmgr_end[] = "};\n";+	const
> > > > > char sysmgr_cfg_indent[] = "\t\t\t\t\t";+	size_t i;++	printf
> > > > > (handoff_dtsi_sysmgr_begin);++	/* sys_mgr_init_table is an u8
> > > > > table */+	print_array_sysmgrinit(sys_mgr_init_table,
> > > > > ARRAY_SIZE(sys_mgr_init_table),+			       "\t",
> > > > > "altr,pinmux-cfg","\t\t\t   ");+	/* ioscr scan chain table 0 */+	
> > > > > print_array_ulong(iocsr_scan_chain0_table,+			  ARRAY_
> > > > > SIZE(iocsr_scan_chain0_table), 4,+			  "\t",
> > > > > "altr,iocsr-scan-chain0-table",+			  sysmgr_cfg_ind
> > > > > ent);+	/* ioscr scan chain table 0 */+	print_array_ulong(iocs
> > > > > r_scan_chain1_table,+			  ARRAY_SIZE(iocsr_scan_chain1_t
> > > > > able), 4,+			  "\t", "altr,iocsr-scan-chain1-table",+
> > > > > 			  sysmgr_cfg_indent);+	/* ioscr scan chain
> > > > > table 0 */+	print_array_ulong(iocsr_scan_chain2_table,+		
> > > > > 	  ARRAY_SIZE(iocsr_scan_chain2_table), 4,+			
> > > > >   "\t", "altr,iocsr-scan-chain2-table",+			  sysmgr
> > > > > _cfg_indent);+	/* ioscr scan chain table 0 */+	print_array_ul
> > > > > ong(iocsr_scan_chain3_table,+			  ARRAY_SIZE(iocsr_scan_
> > > > > chain3_table), 4,+			  "\t", "altr,iocsr-scan-chain3-
> > > > > table",+			  sysmgr_cfg_indent);+	printf(handoff
> > > > > _dtsi_sysmgr_end);+}++static void print_sdram_cfg(void)+{+	const
> > > > > char handoff_dtsi_sdram_cfg_begin[] =+		"\n"+		
> > > > > "&sdr {\n";+	const char handoff_dtsi_sdram_cfg_end[] = "};\n";++	
> > > > > printf(handoff_dtsi_sdram_cfg_begin);+	print_array_u32((const
> > > > > u32 *)&sdram_config, sizeof(sdram_config)/4, 4,+			
> > > > > "\t", "altr,sdr-cfg", "\t\t\t");+	print_array_u8((const u8
> > > > > *)&rw_mgr_config, sizeof(rw_mgr_config), 8,+			"\t",
> > > > > "altr,sdr-rw-mgr-cfg", "\t\t\t       ");+	print_array_u8((const u8
> > > > > *)&io_config, sizeof(io_config), 8,+			"\t", "altr,sdr-
> > > > > io-cfg", "\t\t\t   ");+	print_array_u8((const u8 *)&misc_config,
> > > > > sizeof(misc_config), 8,+			"\t", "altr,sdr-misc-
> > > > > cfg", "\t\t\t     ");+	print_array_alt_u32(ac_rom_init,
> > > > > ARRAY_SIZE(ac_rom_init), 4,+			"\t", "altr,sdr-ac-rom-
> > > > > init", "\t\t\t\t");+	print_array_alt_u32(inst_rom_init,
> > > > > ARRAY_SIZE(inst_rom_init), 4,+			"\t", "altr,sdr-
> > > > > inst-rom-init", "\t\t\t\t  ");+	printf(handoff_dtsi_sdram_cfg_en
> > > > > d);+}++int main(void)+{+	print_hdr();+	print_clkmgr_base();+	
> > > > > print_clkmgr_cfg();+	print_sysmgr();+	print_sdram_cfg();+}diff --git 
> > > > > a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-
> > > > > to-handoff.shnew file mode 100755index 0000000000..b9032a5411---
> > > > > /dev/null+++ b/arch/arm/mach-socfpga/qts-to-handoff.sh@@ -0,0 +1,83
> > > > > @@+#!/bin/sh+# This script converts Quartus handoff files (in Quartus
> > > > > or U-Boot format)+# to a handoff.dtsi file.+++usage() {+	MY_BASEN
> > > > > AME=`basename $0`+	echo "${MY_BASENAME} [soc_type] [input_qts_dir]
> > > > > [input_bsp_dir] [output_file]"+	echo " or"+	echo
> > > > > "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"+	echo ""+
> > > > > 	echo "Process QTS-generated headers into handoff.dtsi:"+	
> > > > > echo ""+	echo "  soc_type      - Type of SoC, either 'cyclone5'
> > > > > or 'arria5'."+	echo "  input_qts_dir - Directory with compiled
> > > > > Quartus project"+	echo "                  and containing the
> > > > > Quartus project file (QPF)."+	echo "  input_bsp_dir - Directory with
> > > > > generated bsp containing"+	echo "                  the settings.bsp
> > > > > file."+	echo "  output_file   - Full filename to store the
> > > > > handoff dtsi file."+	echo "  uboot_qts_dir - board/qts directory if
> > > > > input files are in"+	echo "                  'old-style' U-Boot
> > > > > format."+	echo ""+}++soc="$1"++HANDOFF_TEMPLATE="`dirname
> > > > > $0`/create_handoff_gen5.c"++case "$soc" in+"cyclone5"|"arria5")+	
> > > > > if [ "$#" -ne 4 ] ; then+		usage+		exit 1+	fi+	
> > > > > in_qts_dir="$2"+	in_bsp_dir="$3"+	output_file="$4"+	out_di
> > > > > r=`dirname ${output_file}`++	if [ ! -d "${in_qts_dir}" -o ! -d
> > > > > "${in_bsp_dir}" -o \+		! -d "${out_dir}" -o -z "${soc}" ] ;
> > > > > then+		usage+		exit 3+	fi++	if [ "$soc" =
> > > > > "cyclone5" ] ; then+		CMDLINE_DEFINES="-DCYCLONE5"+	else+	
> > > > > 	CMDLINE_DEFINES="-DARRIA5"+	fi+	CMDLINE_DEFINES="${CMD
> > > > > LINE_DEFINES} -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"+	
> > > > > for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do+		CMDLINE_DEFINE
> > > > > S="${CMDLINE_DEFINES} -I$d"+	done+	;;+"u-boot")+	if [ "$#" -ne
> > > > > 3 ] ; then+		usage+		exit 1+	fi+	in_qts_dir="$2
> > > > > "+	output_file="$3"+	out_dir=`dirname ${output_file}`++	if [ !
> > > > > -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then+		usage+	
> > > > > 	exit 3+	fi++	CMDLINE_DEFINES="-I${in_qts_dir}"+	;;+*)+
> > > > > 	usage+	exit 1+	;;+esac++# compile+gcc ${CMDLINE_DEFINES}
> > > > > ${HANDOFF_TEMPLATE} -o
> > > > > ${out_dir}/create_handoff_gen5+${out_dir}/create_handoff_gen5 >
> > > > > ${output_file}++# TODO: remove tmp file:+#rm
> > > > > $${out_dir}/create_handoff_gen5

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Simon Goldschmidt]

On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen
<dalon.westergreen@linux.intel.com> wrote:
>
>
>
> On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
>
> Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
>
>
>
> On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
>
>
>
> Dalon L Westergreen <
>
> dalon.westergreen at linux.intel.com
>
>
>
> <mailto:
>
> dalon.westergreen at linux.intel.com
>
> >> schrieb am Di., 22. Okt.
>
> 2019, 19:10:
>
> I mentioned this before, it would be great to not rely on the
>
> generated files
>
> and do this based purely on the handoff data generated during a quartus
>
> build. Did you look at the python source i pointed you to?
>
>
> No, not yet. But I don't think that will be a problem. I sent this
>
> series mainly to discuss the dts format (boardspecific handoff dtsi vs
>
> genetic dtsi plus boardspecific header file).
>
>
> The board specific dtsi does look cleaner, but i do like the simplicity
>
> of generating the header in arria10.
>
>
> I could easily replicate what you do, generate the header, and use it to
>
> create the dtsi.
>
>
> I'm not too fond myself of that tool I created, as it requires you to
>
> have a compiler. I just was too lazy write a script for that.
>
>
> However, I would prefer having a script that does it. And if the sources
>
> are quartus output files instead of existing qts files, my tool doesn't
>
> work any more, anway.
>
>
> So I think we should come up with a script (e.g. sh or py) that parses
>
> quartus output and creates a handoff dtsi (without a header). We'll only
>
> need something different for converting existing qts files then...
>
>
> In that case, i would stick with adding a .h file along with a common handoff dtsi as i did
> in the a10 filter script i sent the other week. I would suggest your source is perfect
> for migrating existing c5/a5 platforms.

Why can't we change that a10 script to create handoff dtsi files as well?

>
> Is there a preference for python? It would fit nicely b/c we could re-use the code
> I pointed out previously for binary parsing.

Well, *my* preference would be to not depend on having gcc installed to convert
from quartus output to dtsi. I just did that because C was easier to
get started.

I'm not a big fan of python, but since it's used everywhere in U-Boot, I
figured it should be ok? Having a standard shell script do the job would even
lower the requirements of course.

Regards,
Simon

>
> Dinh, Marek, Ley Foon, comments?
>
> --dalon
>
>
> Regards,
>
> Simon
>
>
>
> --dalon
>
>
>
> I still favor boardspecific handoff dtsi, but I would like to use the
>
> same style for all socfpga flavours.
>
>
> Plus this tool is required to convert existing boards where we don't
>
> have the quartus project files at hand.
>
>
> Regards,
>
> Simon
>
>
>
> --dalon
>
>
> On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
>
> This new tool converts handoff information from quartus to "*_handoff.dtsi"
>
> devicetree files. This is in preparation to move from ad-hoc code in arch
>
> that parses the 'qts' header files to drivers parsing the same information
>
> from devicetree.
>
>
> Converting existing U-Boot 'qts' files is also supported.
>
>
> Signed-off-by: Simon Goldschmidt <
>
> simon.k.r.goldschmidt at gmail.com
>
>
>  <mailto:
>
> simon.k.r.goldschmidt at gmail.com
>
> >
>
>
> ---
>
>
> Changes in v2: None
>
>
>   arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
>
>   arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++
>
>   2 files changed, 743 insertions(+)
>
>   create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
>
>   create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
>
>
> diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-socfpga/create_handoff_gen5.c
>
> new file mode 100644
>
> index 0000000000..6ec436719d
>
> --- /dev/null
>
> +++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
>
> @@ -0,0 +1,660 @@
>
> +// SPDX-License-Identifier: GPL-2.0
>
> +/*
>
> + * This is a host-tool that needs to be compiled per board and prints the
>
> + * handoff.dtsi to stdout.
>
> + */
>
> +
>
> +#include <stdio.h>
>
> +#include <stdint.h>
>
> +
>
> +/* Define kernel types */
>
> +typedef uint8_t u8;
>
> +typedef uint32_t u32;
>
> +
>
> +#ifdef USE_QUARTUS_OUTPUT
>
> +#ifdef ARRIA5
>
> +#include "iocsr_config_arria5.c"
>
> +#include "pinmux_config_arria5.c"
>
> +#else
>
> +#include "iocsr_config_cyclone5.c"
>
> +#include "pinmux_config_cyclone5.c"
>
> +#endif
>
> +#include "pll_config.h"
>
> +#include "sdram/sdram_config.h"
>
> +#include "sequencer_auto.h"
>
> +#include "sequencer_defines.h"
>
> +#include "sequencer_auto_ac_init.c"
>
> +#include "sequencer_auto_inst_init.c"
>
> +#define RW_MGR(x) __RW_MGR_##x
>
> +#else
>
> +#define RW_MGR(x) RW_MGR_##x
>
> +#include <iocsr_config.h>
>
> +#include <pinmux_config.h>
>
> +#include <pll_config.h>
>
> +#include <sdram_config.h>
>
> +#endif
>
> +
>
> +#include "include/mach/clock_manager_gen5.h"
>
> +#include "include/mach/sdram_gen5.h"
>
> +
>
> +#ifndef ARRAY_SIZE
>
> +#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
>
> +#endif
>
> +
>
> +const char handoff_dtsi_hdr[] =
>
> + "// SPDX-License-Identifier: GPL-2.0\n"
>
> + "/*\n"
>
> + " *<auto-generated>\n"
>
> + " * This code was generated by a tool based on\n"
>
> + " * handoffs from both Qsys and Quartus.\n"
>
> + " *\n"
>
> + " * Changes to this file may be lost if\n"
>
> + " * the code is regenerated.\n"
>
> + " *</auto-generated>\n"
>
> + " */\n";
>
> +
>
> +/* Wrap PLL config */
>
> +
>
> +#define MAIN_VCO_BASE ( \
>
> + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
>
> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
>
> + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
>
> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
>
> + )
>
> +
>
> +#define PERI_VCO_BASE ( \
>
> + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
>
> + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
>
> + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
>
> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
>
> + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
>
> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
>
> + )
>
> +
>
> +#define SDR_VCO_BASE ( \
>
> + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
>
> + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
>
> + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
>
> + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
>
> + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
>
> + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
>
> + )
>
> +
>
> +static const struct cm_config cm_default = {
>
> + /* main group */
>
> + MAIN_VCO_BASE,
>
> + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
>
> + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
>
> + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
>
> + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
>
> + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
>
> + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
>
> + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
>
> + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
>
> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
>
> + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
>
> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
>
> + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
>
> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
>
> + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
>
> + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
>
> + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
>
> + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
>
> + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
>
> + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
>
> + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
>
> + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
>
> + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
>
> +
>
> + /* peripheral group */
>
> + PERI_VCO_BASE,
>
> + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
>
> + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
>
> + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
>
> + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
>
> + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
>
> + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
>
> + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
>
> + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
>
> + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
>
> + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
>
> + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
>
> + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
>
> + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
>
> + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
>
> + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
>
> + (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
>
> + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
>
> + (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
>
> + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
>
> + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
>
> + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
>
> +
>
> + /* sdram pll group */
>
> + SDR_VCO_BASE,
>
> + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
>
> + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
>
> + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
>
> + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
>
> + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
>
> + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
>
> + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
>
> + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
>
> + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
>
> + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
>
> + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
>
> + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
>
> + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
>
> + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
>
> +
>
> + /* altera group */
>
> + CONFIG_HPS_ALTERAGRP_MPUCLK,
>
> +};
>
> +
>
> +/* Wrap SDRAM config */
>
> +static const struct socfpga_sdram_config sdram_config = {
>
> + .ctrl_cfg =
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
>
> + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
>
> + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
>
> + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
>
> + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
>
> + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
>
> + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
>
> + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
>
> + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
>
> + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
>
> + .dram_timing1 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
>
> + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
>
> + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
>
> + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
>
> + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
>
> + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
>
> + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
>
> + .dram_timing2 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
>
> + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
>
> + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
>
> + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
>
> + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
>
> + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
>
> + .dram_timing3 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
>
> + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
>
> + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
>
> + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
>
> + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
>
> + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
>
> + .dram_timing4 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
>
> + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
>
> + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
>
> + .lowpwr_timing =
>
> + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
>
> + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
>
> + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
>
> + .dram_odt =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
>
> + SDR_CTRLGRP_DRAMODT_READ_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
>
> + SDR_CTRLGRP_DRAMODT_WRITE_LSB),
>
> + .extratime1 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
>
> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
>
> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
>
> +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
>
> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
>
> + .dram_addrw =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
>
> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
>
> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
>
> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
>
> + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
>
> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
>
> + .dram_if_width =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
>
> + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
>
> + .dram_dev_width =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
>
> + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
>
> + .dram_intr =
>
> + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
>
> + SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
>
> + .lowpwr_eq =
>
> + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
>
> + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
>
> + .static_cfg =
>
> + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
>
> + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
>
> + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
>
> + .ctrl_width =
>
> + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
>
> + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
>
> + .cport_width =
>
> + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
>
> + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
>
> + .cport_wmap =
>
> + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
>
> + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
>
> + .cport_rmap =
>
> + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
>
> + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
>
> + .rfifo_cmap =
>
> + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
>
> + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
>
> + .wfifo_cmap =
>
> + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
>
> + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
>
> + .cport_rdwr =
>
> + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
>
> + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
>
> + .port_cfg =
>
> + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
>
> + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
>
> + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
>
> + .fifo_cfg =
>
> + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
>
> + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
>
> + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
>
> + .mp_priority =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
>
> + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
>
> + .mp_weight0 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
>
> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
>
> + .mp_weight1 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
>
> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
>
> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
>
> + .mp_weight2 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
>
> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
>
> + .mp_weight3 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
>
> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
>
> + .mp_pacing0 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
>
> + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
>
> + .mp_pacing1 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
>
> + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
>
> + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
>
> + .mp_pacing2 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
>
> + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
>
> + .mp_pacing3 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
>
> + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
>
> + .mp_threshold0 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
>
> + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
>
> + .mp_threshold1 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
>
> + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
>
> + .mp_threshold2 =
>
> + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
>
> + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
>
> + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
>
> +};
>
> +
>
> +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
>
> + .activate_0_and_1 = RW_MGR(ACTIVATE_0_AND_1),
>
> + .activate_0_and_1_wait1 = RW_MGR(ACTIVATE_0_AND_1_WAIT1),
>
> + .activate_0_and_1_wait2 = RW_MGR(ACTIVATE_0_AND_1_WAIT2),
>
> + .activate_1 = RW_MGR(ACTIVATE_1),
>
> + .clear_dqs_enable = RW_MGR(CLEAR_DQS_ENABLE),
>
> + .guaranteed_read = RW_MGR(GUARANTEED_READ),
>
> + .guaranteed_read_cont = RW_MGR(GUARANTEED_READ_CONT),
>
> + .guaranteed_write = RW_MGR(GUARANTEED_WRITE),
>
> + .guaranteed_write_wait0 = RW_MGR(GUARANTEED_WRITE_WAIT0),
>
> + .guaranteed_write_wait1 = RW_MGR(GUARANTEED_WRITE_WAIT1),
>
> + .guaranteed_write_wait2 = RW_MGR(GUARANTEED_WRITE_WAIT2),
>
> + .guaranteed_write_wait3 = RW_MGR(GUARANTEED_WRITE_WAIT3),
>
> + .idle = RW_MGR(IDLE),
>
> + .idle_loop1 = RW_MGR(IDLE_LOOP1),
>
> + .idle_loop2 = RW_MGR(IDLE_LOOP2),
>
> + .init_reset_0_cke_0 = RW_MGR(INIT_RESET_0_CKE_0),
>
> + .init_reset_1_cke_0 = RW_MGR(INIT_RESET_1_CKE_0),
>
> + .lfsr_wr_rd_bank_0 = RW_MGR(LFSR_WR_RD_BANK_0),
>
> + .lfsr_wr_rd_bank_0_data = RW_MGR(LFSR_WR_RD_BANK_0_DATA),
>
> + .lfsr_wr_rd_bank_0_dqs = RW_MGR(LFSR_WR_RD_BANK_0_DQS),
>
> + .lfsr_wr_rd_bank_0_nop = RW_MGR(LFSR_WR_RD_BANK_0_NOP),
>
> + .lfsr_wr_rd_bank_0_wait = RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
>
> + .lfsr_wr_rd_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
>
> + .lfsr_wr_rd_dm_bank_0 = RW_MGR(LFSR_WR_RD_DM_BANK_0),
>
> + .lfsr_wr_rd_dm_bank_0_data = RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
>
> + .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
>
> + .lfsr_wr_rd_dm_bank_0_nop = RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
>
> + .lfsr_wr_rd_dm_bank_0_wait = RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
>
> + .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
>
> + .mrs0_dll_reset = RW_MGR(MRS0_DLL_RESET),
>
> + .mrs0_dll_reset_mirr = RW_MGR(MRS0_DLL_RESET_MIRR),
>
> + .mrs0_user = RW_MGR(MRS0_USER),
>
> + .mrs0_user_mirr = RW_MGR(MRS0_USER_MIRR),
>
> + .mrs1 = RW_MGR(MRS1),
>
> + .mrs1_mirr = RW_MGR(MRS1_MIRR),
>
> + .mrs2 = RW_MGR(MRS2),
>
> + .mrs2_mirr = RW_MGR(MRS2_MIRR),
>
> + .mrs3 = RW_MGR(MRS3),
>
> + .mrs3_mirr = RW_MGR(MRS3_MIRR),
>
> + .precharge_all = RW_MGR(PRECHARGE_ALL),
>
> + .read_b2b = RW_MGR(READ_B2B),
>
> + .read_b2b_wait1 = RW_MGR(READ_B2B_WAIT1),
>
> + .read_b2b_wait2 = RW_MGR(READ_B2B_WAIT2),
>
> + .refresh_all = RW_MGR(REFRESH_ALL),
>
> + .rreturn = RW_MGR(RETURN),
>
> + .sgle_read = RW_MGR(SGLE_READ),
>
> + .zqcl = RW_MGR(ZQCL),
>
> +
>
> + .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
>
> + .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
>
> + .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
>
> + .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
>
> + .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
>
> + .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
>
> + .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
>
> + .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
>
> + .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
>
> + .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
>
> + .mem_virtual_groups_per_read_dqs =
>
> + RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
>
> + .mem_virtual_groups_per_write_dqs =
>
> + RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
>
> +};
>
> +
>
> +static const struct socfpga_sdram_io_config io_config = {
>
> + .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
>
> + .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
>
> + .delay_per_opa_tap_lo = IO_DELAY_PER_OPA_TAP & 0xff,
>
> + .delay_per_opa_tap_hi = (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
>
> + .dll_chain_length = IO_DLL_CHAIN_LENGTH,
>
> + .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
>
> + .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
>
> + .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
>
> + .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
>
> + .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
>
> + .dqs_in_reserve = IO_DQS_IN_RESERVE,
>
> + .dqs_out_reserve = IO_DQS_OUT_RESERVE,
>
> + .io_in_delay_max = IO_IO_IN_DELAY_MAX,
>
> + .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
>
> + .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
>
> + .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
>
> +};
>
> +
>
> +static const struct socfpga_sdram_misc_config misc_config = {
>
> + .afi_rate_ratio = AFI_RATE_RATIO,
>
> + .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
>
> + .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
>
> + .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
>
> + .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
>
> + .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
>
> + .reg_file_init_seq_signature_ll = REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
>
> + .reg_file_init_seq_signature_lh = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
>
> + .reg_file_init_seq_signature_hl = (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
>
> + .reg_file_init_seq_signature_hh = (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
>
> + .tinit_cntr0_val = TINIT_CNTR0_VAL,
>
> + .tinit_cntr1_val = TINIT_CNTR1_VAL,
>
> + .tinit_cntr2_val = TINIT_CNTR2_VAL,
>
> + .treset_cntr0_val = TRESET_CNTR0_VAL,
>
> + .treset_cntr1_val = TRESET_CNTR1_VAL,
>
> + .treset_cntr2_val = TRESET_CNTR2_VAL,
>
> +};
>
> +
>
> +static void print_hdr(void)
>
> +{
>
> + printf(handoff_dtsi_hdr);
>
> +}
>
> +
>
> +static void print_clkmgr_base(void)
>
> +{
>
> + const char handoff_dtsi_clkmgr_base[] =
>
> + "\n"
>
> + "&osc1 {\n"
>
> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
>
> + "};\n"
>
> + "\n"
>
> + "&osc2 {\n"
>
> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
>
> + "};\n"
>
> + "\n"
>
> + "&f2s_periph_ref_clk {\n"
>
> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
>
> + "};\n"
>
> + "\n"
>
> + "&f2s_sdram_ref_clk {\n"
>
> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
>
> + "};\n";
>
> +
>
> + printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
>
> +       CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
>
> +       CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
>
> +}
>
> +
>
> +/*
>
> + * dtc stores u32 array big endian but we load them raw and expect them to be in
>
> + * little endian format. To prevent this tool to depend on host endianess, do
>
> + * the switch manually, not via 'htonl'.
>
> + */
>
> +static u32 swap_bytes(u32 val)
>
> +{
>
> + return (val << 24) | ((val & 0xFF00ul) << 8) |
>
> + ((val & 0xFF0000ul) >> 8) | (val >> 24);
>
> +}
>
> +
>
> +static void print_array_ulong(const unsigned long *arr, size_t arr_size,
>
> +      size_t el_per_line, const char *indent1,
>
> +      const char *name, const char *indent_next)
>
> +{
>
> + size_t i;
>
> +
>
> + printf("%s%s = <", indent1, name);
>
> + for (i = 0; i < arr_size; i++) {
>
> + printf("0x%08x", swap_bytes((u32)arr[i]));
>
> + if (i + 1 < arr_size) {
>
> + if (i % el_per_line == (el_per_line - 1)) {
>
> + printf("\n%s", indent_next);
>
> + } else {
>
> + printf(" ");
>
> + }
>
> + }
>
> + }
>
> + printf(">;\n");
>
> +}
>
> +
>
> +#ifdef USE_QUARTUS_OUTPUT
>
> +static void print_array_sysmgrinit(const unsigned long *arr, size_t arr_size,
>
> +   const char *indent1, const char *name,
>
> +   const char *indent_next)
>
> +{
>
> + size_t i;
>
> +
>
> + printf("%s%s = [", indent1, name);
>
> + for (i = 0; i < arr_size; i++) {
>
> + printf("%02x", (u8)arr[i]);
>
> + if (i + 1 < arr_size) {
>
> + if (i % 8 == 7) {
>
> + printf("\n%s", indent_next);
>
> + } else {
>
> + printf(" ");
>
> + }
>
> + }
>
> + }
>
> + printf("];\n");
>
> +}
>
> +#define print_array_alt_u32 print_array_ulong
>
> +#else
>
> +#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz, 8, ind1, n, ind2)
>
> +#define print_array_alt_u32 print_array_u32
>
> +#endif
>
> +
>
> +static void print_array_u32(const u32 *arr, size_t arr_size,
>
> +    size_t el_per_line, const char *indent1,
>
> +    const char *name, const char *indent_next)
>
> +{
>
> + size_t i;
>
> +
>
> + printf("%s%s = <", indent1, name);
>
> + for (i = 0; i < arr_size; i++) {
>
> + printf("0x%08x", swap_bytes(arr[i]));
>
> + if (i + 1 < arr_size) {
>
> + if (i % el_per_line == (el_per_line - 1)) {
>
> + printf("\n%s", indent_next);
>
> + } else {
>
> + printf(" ");
>
> + }
>
> + }
>
> + }
>
> + printf(">;\n");
>
> +}
>
> +
>
> +static void print_array_u8(const u8 *arr, size_t arr_size, size_t el_per_line,
>
> +   const char *indent1, const char *name,
>
> +   const char *indent_next)
>
> +{
>
> + size_t i;
>
> +
>
> + printf("%s%s = [", indent1, name);
>
> + for (i = 0; i < arr_size; i++) {
>
> + printf("%02x", arr[i]);
>
> + if (i + 1 < arr_size) {
>
> + if (i % el_per_line == (el_per_line - 1)) {
>
> + printf("\n%s", indent_next);
>
> + } else {
>
> + printf(" ");
>
> + }
>
> + }
>
> + }
>
> + printf("];\n");
>
> +}
>
> +
>
> +
>
> +static void print_clkmgr_cfg(void)
>
> +{
>
> + const char handoff_dtsi_clkmgr_cfg_a[] =
>
> + "\n"
>
> + "&clkmgr {\n";
>
> + const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
>
> + const char clk_mgr_cfg_indent[] = "\t\t\t    ";
>
> +
>
> + printf(handoff_dtsi_clkmgr_cfg_a);
>
> + print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
>
> + "altr,clk-mgr-cfg", clk_mgr_cfg_indent);
>
> + printf(handoff_dtsi_clkmgr_cfg_b);
>
> +}
>
> +
>
> +static void print_sysmgr(void)
>
> +{
>
> + const char handoff_dtsi_sysmgr_begin[] =
>
> + "\n"
>
> + "&sysmgr {\n";
>
> + const char handoff_dtsi_sysmgr_end[] = "};\n";
>
> + const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
>
> + size_t i;
>
> +
>
> + printf(handoff_dtsi_sysmgr_begin);
>
> +
>
> + /* sys_mgr_init_table is an u8 table */
>
> + print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
>
> +       "\t", "altr,pinmux-cfg","\t\t\t   ");
>
> + /* ioscr scan chain table 0 */
>
> + print_array_ulong(iocsr_scan_chain0_table,
>
> +  ARRAY_SIZE(iocsr_scan_chain0_table), 4,
>
> +  "\t", "altr,iocsr-scan-chain0-table",
>
> +  sysmgr_cfg_indent);
>
> + /* ioscr scan chain table 0 */
>
> + print_array_ulong(iocsr_scan_chain1_table,
>
> +  ARRAY_SIZE(iocsr_scan_chain1_table), 4,
>
> +  "\t", "altr,iocsr-scan-chain1-table",
>
> +  sysmgr_cfg_indent);
>
> + /* ioscr scan chain table 0 */
>
> + print_array_ulong(iocsr_scan_chain2_table,
>
> +  ARRAY_SIZE(iocsr_scan_chain2_table), 4,
>
> +  "\t", "altr,iocsr-scan-chain2-table",
>
> +  sysmgr_cfg_indent);
>
> + /* ioscr scan chain table 0 */
>
> + print_array_ulong(iocsr_scan_chain3_table,
>
> +  ARRAY_SIZE(iocsr_scan_chain3_table), 4,
>
> +  "\t", "altr,iocsr-scan-chain3-table",
>
> +  sysmgr_cfg_indent);
>
> + printf(handoff_dtsi_sysmgr_end);
>
> +}
>
> +
>
> +static void print_sdram_cfg(void)
>
> +{
>
> + const char handoff_dtsi_sdram_cfg_begin[] =
>
> + "\n"
>
> + "&sdr {\n";
>
> + const char handoff_dtsi_sdram_cfg_end[] = "};\n";
>
> +
>
> + printf(handoff_dtsi_sdram_cfg_begin);
>
> + print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
>
> + "\t", "altr,sdr-cfg", "\t\t\t");
>
> + print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
>
> + "\t", "altr,sdr-rw-mgr-cfg", "\t\t\t       ");
>
> + print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
>
> + "\t", "altr,sdr-io-cfg", "\t\t\t   ");
>
> + print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
>
> + "\t", "altr,sdr-misc-cfg", "\t\t\t     ");
>
> + print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
>
> + "\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
>
> + print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
>
> + "\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");
>
> + printf(handoff_dtsi_sdram_cfg_end);
>
> +}
>
> +
>
> +int main(void)
>
> +{
>
> + print_hdr();
>
> + print_clkmgr_base();
>
> + print_clkmgr_cfg();
>
> + print_sysmgr();
>
> + print_sdram_cfg();
>
> +}
>
> diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-to-handoff.sh
>
> new file mode 100755
>
> index 0000000000..b9032a5411
>
> --- /dev/null
>
> +++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
>
> @@ -0,0 +1,83 @@
>
> +#!/bin/sh
>
> +# This script converts Quartus handoff files (in Quartus or U-Boot format)
>
> +# to a handoff.dtsi file.
>
> +
>
> +
>
> +usage() {
>
> + MY_BASENAME=`basename $0`
>
> + echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir] [output_file]"
>
> + echo " or"
>
> + echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
>
> + echo ""
>
> + echo "Process QTS-generated headers into handoff.dtsi:"
>
> + echo ""
>
> + echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
>
> + echo "  input_qts_dir - Directory with compiled Quartus project"
>
> + echo "                  and containing the Quartus project file (QPF)."
>
> + echo "  input_bsp_dir - Directory with generated bsp containing"
>
> + echo "                  the settings.bsp file."
>
> + echo "  output_file   - Full filename to store the handoff dtsi file."
>
> + echo "  uboot_qts_dir - board/qts directory if input files are in"
>
> + echo "                  'old-style' U-Boot format."
>
> + echo ""
>
> +}
>
> +
>
> +soc="$1"
>
> +
>
> +HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
>
> +
>
> +case "$soc" in
>
> +"cyclone5"|"arria5")
>
> + if [ "$#" -ne 4 ] ; then
>
> + usage
>
> + exit 1
>
> + fi
>
> + in_qts_dir="$2"
>
> + in_bsp_dir="$3"
>
> + output_file="$4"
>
> + out_dir=`dirname ${output_file}`
>
> +
>
> + if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
>
> + ! -d "${out_dir}" -o -z "${soc}" ] ; then
>
> + usage
>
> + exit 3
>
> + fi
>
> +
>
> + if [ "$soc" = "cyclone5" ] ; then
>
> + CMDLINE_DEFINES="-DCYCLONE5"
>
> + else
>
> + CMDLINE_DEFINES="-DARRIA5"
>
> + fi
>
> + CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"
>
> + for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
>
> + CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
>
> + done
>
> + ;;
>
> +"u-boot")
>
> + if [ "$#" -ne 3 ] ; then
>
> + usage
>
> + exit 1
>
> + fi
>
> + in_qts_dir="$2"
>
> + output_file="$3"
>
> + out_dir=`dirname ${output_file}`
>
> +
>
> + if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
>
> + usage
>
> + exit 3
>
> + fi
>
> +
>
> + CMDLINE_DEFINES="-I${in_qts_dir}"
>
> + ;;
>
> +*)
>
> + usage
>
> + exit 1
>
> + ;;
>
> +esac
>
> +
>
> +# compile
>
> +gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o ${out_dir}/create_handoff_gen5
>
> +${out_dir}/create_handoff_gen5 > ${output_file}
>
> +
>
> +# TODO: remove tmp file:
>
> +#rm $${out_dir}/create_handoff_gen5
>
>

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Dalon L Westergreen]

On Thu, 2019-10-24 at 16:29 +0200, Simon Goldschmidt wrote:
> On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen<
> dalon.westergreen at linux.intel.com> wrote:
> > 
> > On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
> > Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
> > 
> > 
> > On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
> > 
> > 
> > Dalon L Westergreen <
> > dalon.westergreen at linux.intel.com
> > 
> > 
> > 
> > <mailto:
> > dalon.westergreen at linux.intel.com
> > 
> > > > schrieb am Di., 22. Okt.
> > 
> > 2019, 19:10:
> > I mentioned this before, it would be great to not rely on the
> > generated files
> > and do this based purely on the handoff data generated during a quartus
> > build. Did you look at the python source i pointed you to?
> > 
> > No, not yet. But I don't think that will be a problem. I sent this
> > series mainly to discuss the dts format (boardspecific handoff dtsi vs
> > genetic dtsi plus boardspecific header file).
> > 
> > The board specific dtsi does look cleaner, but i do like the simplicity
> > of generating the header in arria10.
> > 
> > I could easily replicate what you do, generate the header, and use it to
> > create the dtsi.
> > 
> > I'm not too fond myself of that tool I created, as it requires you to
> > have a compiler. I just was too lazy write a script for that.
> > 
> > However, I would prefer having a script that does it. And if the sources
> > are quartus output files instead of existing qts files, my tool doesn't
> > work any more, anway.
> > 
> > So I think we should come up with a script (e.g. sh or py) that parses
> > quartus output and creates a handoff dtsi (without a header). We'll only
> > need something different for converting existing qts files then...
> > 
> > In that case, i would stick with adding a .h file along with a common
> > handoff dtsi as i didin the a10 filter script i sent the other week. I would
> > suggest your source is perfectfor migrating existing c5/a5 platforms.
> 
> Why can't we change that a10 script to create handoff dtsi files as well?

I just dont like building the dtsi in source, the code to create a header is
simpler and cleaner.  Froma files perspective, 1 dtsi + a header for each board,
or a dtsi for each board, not sure there is muchdifference either way.  but
using headers keeps the utility simpler.
--dalon
> > Is there a preference for python? It would fit nicely b/c we could re-use
> > the codeI pointed out previously for binary parsing.
> 
> Well, *my* preference would be to not depend on having gcc installed to
> convertfrom quartus output to dtsi. I just did that because C was easier toget
> started.
> I'm not a big fan of python, but since it's used everywhere in U-Boot,
> Ifigured it should be ok? Having a standard shell script do the job would
> evenlower the requirements of course.
> Regards,Simon
> > Dinh, Marek, Ley Foon, comments?
> > --dalon
> > 
> > Regards,
> > Simon
> > 
> > 
> > --dalon
> > 
> > 
> > I still favor boardspecific handoff dtsi, but I would like to use the
> > same style for all socfpga flavours.
> > 
> > Plus this tool is required to convert existing boards where we don't
> > have the quartus project files at hand.
> > 
> > Regards,
> > Simon
> > 
> > 
> > --dalon
> > 
> > On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
> > This new tool converts handoff information from quartus to "*_handoff.dtsi"
> > devicetree files. This is in preparation to move from ad-hoc code in arch
> > that parses the 'qts' header files to drivers parsing the same information
> > from devicetree.
> > 
> > Converting existing U-Boot 'qts' files is also supported.
> > 
> > Signed-off-by: Simon Goldschmidt <
> > simon.k.r.goldschmidt at gmail.com
> > 
> > 
> >  <mailto:
> > simon.k.r.goldschmidt at gmail.com
> > 
> > 
> > ---
> > 
> > Changes in v2: None
> > 
> >   arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
> >   arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++
> >   2 files changed, 743 insertions(+)
> >   create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
> >   create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
> > 
> > diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-
> > socfpga/create_handoff_gen5.c
> > new file mode 100644
> > index 0000000000..6ec436719d
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
> > @@ -0,0 +1,660 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * This is a host-tool that needs to be compiled per board and prints the
> > + * handoff.dtsi to stdout.
> > + */
> > +
> > +#include <stdio.h>
> > +#include <stdint.h>
> > +
> > +/* Define kernel types */
> > +typedef uint8_t u8;
> > +typedef uint32_t u32;
> > +
> > +#ifdef USE_QUARTUS_OUTPUT
> > +#ifdef ARRIA5
> > +#include "iocsr_config_arria5.c"
> > +#include "pinmux_config_arria5.c"
> > +#else
> > +#include "iocsr_config_cyclone5.c"
> > +#include "pinmux_config_cyclone5.c"
> > +#endif
> > +#include "pll_config.h"
> > +#include "sdram/sdram_config.h"
> > +#include "sequencer_auto.h"
> > +#include "sequencer_defines.h"
> > +#include "sequencer_auto_ac_init.c"
> > +#include "sequencer_auto_inst_init.c"
> > +#define RW_MGR(x) __RW_MGR_##x
> > +#else
> > +#define RW_MGR(x) RW_MGR_##x
> > +#include <iocsr_config.h>
> > +#include <pinmux_config.h>
> > +#include <pll_config.h>
> > +#include <sdram_config.h>
> > +#endif
> > +
> > +#include "include/mach/clock_manager_gen5.h"
> > +#include "include/mach/sdram_gen5.h"
> > +
> > +#ifndef ARRAY_SIZE
> > +#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
> > +#endif
> > +
> > +const char handoff_dtsi_hdr[] =
> > + "// SPDX-License-Identifier: GPL-2.0\n"
> > + "/*\n"
> > + " *<auto-generated>\n"
> > + " * This code was generated by a tool based on\n"
> > + " * handoffs from both Qsys and Quartus.\n"
> > + " *\n"
> > + " * Changes to this file may be lost if\n"
> > + " * the code is regenerated.\n"
> > + " *</auto-generated>\n"
> > + " */\n";
> > +
> > +/* Wrap PLL config */
> > +
> > +#define MAIN_VCO_BASE ( \
> > + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
> > + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
> > + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
> > + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
> > + )
> > +
> > +#define PERI_VCO_BASE ( \
> > + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
> > + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
> > + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
> > + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
> > + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
> > + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
> > + )
> > +
> > +#define SDR_VCO_BASE ( \
> > + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
> > + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
> > + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
> > + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
> > + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
> > + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
> > + )
> > +
> > +static const struct cm_config cm_default = {
> > + /* main group */
> > + MAIN_VCO_BASE,
> > + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
> > + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
> > + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
> > + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
> > + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
> > + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
> > + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
> > + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
> > + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
> > + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
> > + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
> > + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
> > + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
> > + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
> > +
> > + /* peripheral group */
> > + PERI_VCO_BASE,
> > + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
> > + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
> > + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
> > + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
> > + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
> > + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
> > + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
> > + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
> > + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
> > + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
> > + (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
> > + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
> > + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
> > + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
> > + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
> > +
> > + /* sdram pll group */
> > + SDR_VCO_BASE,
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
> > + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
> > + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
> > + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
> > + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
> > + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
> > + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
> > + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
> > + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
> > +
> > + /* altera group */
> > + CONFIG_HPS_ALTERAGRP_MPUCLK,
> > +};
> > +
> > +/* Wrap SDRAM config */
> > +static const struct socfpga_sdram_config sdram_config = {
> > + .ctrl_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
> > + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
> > + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
> > + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
> > + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
> > + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
> > + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
> > + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
> > + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
> > + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
> > + .dram_timing1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
> > + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
> > + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
> > + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
> > + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
> > + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
> > + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
> > + .dram_timing2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
> > + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
> > + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
> > + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
> > + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
> > + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
> > + .dram_timing3 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
> > + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
> > + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
> > + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
> > + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
> > + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
> > + .dram_timing4 =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
> > + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
> > + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
> > + .lowpwr_timing =
> > + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
> > + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
> > + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
> > + .dram_odt =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
> > + SDR_CTRLGRP_DRAMODT_READ_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> > + SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> > + .extratime1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
> > +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
> > + .dram_addrw =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
> > + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
> > + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
> > + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
> > + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
> > + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
> > + .dram_if_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
> > + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
> > + .dram_dev_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
> > + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
> > + .dram_intr =
> > + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
> > + SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
> > + .lowpwr_eq =
> > + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
> > + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
> > + .static_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
> > + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
> > + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
> > + .ctrl_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
> > + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
> > + .cport_width =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
> > + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
> > + .cport_wmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
> > + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
> > + .cport_rmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
> > + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
> > + .rfifo_cmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
> > + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
> > + .wfifo_cmap =
> > + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
> > + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
> > + .cport_rdwr =
> > + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
> > + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
> > + .port_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
> > + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
> > + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
> > + .fifo_cfg =
> > + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
> > + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
> > + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
> > + .mp_priority =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
> > + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
> > + .mp_weight0 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
> > + .mp_weight1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
> > + .mp_weight2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
> > + .mp_weight3 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
> > + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
> > + .mp_pacing0 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
> > + .mp_pacing1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
> > + .mp_pacing2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
> > + .mp_pacing3 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
> > + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
> > + .mp_threshold0 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
> > + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
> > + .mp_threshold1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
> > + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
> > + .mp_threshold2 =
> > + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
> > + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
> > + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
> > +};
> > +
> > +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
> > + .activate_0_and_1 = RW_MGR(ACTIVATE_0_AND_1),
> > + .activate_0_and_1_wait1 = RW_MGR(ACTIVATE_0_AND_1_WAIT1),
> > + .activate_0_and_1_wait2 = RW_MGR(ACTIVATE_0_AND_1_WAIT2),
> > + .activate_1 = RW_MGR(ACTIVATE_1),
> > + .clear_dqs_enable = RW_MGR(CLEAR_DQS_ENABLE),
> > + .guaranteed_read = RW_MGR(GUARANTEED_READ),
> > + .guaranteed_read_cont = RW_MGR(GUARANTEED_READ_CONT),
> > + .guaranteed_write = RW_MGR(GUARANTEED_WRITE),
> > + .guaranteed_write_wait0 = RW_MGR(GUARANTEED_WRITE_WAIT0),
> > + .guaranteed_write_wait1 = RW_MGR(GUARANTEED_WRITE_WAIT1),
> > + .guaranteed_write_wait2 = RW_MGR(GUARANTEED_WRITE_WAIT2),
> > + .guaranteed_write_wait3 = RW_MGR(GUARANTEED_WRITE_WAIT3),
> > + .idle = RW_MGR(IDLE),
> > + .idle_loop1 = RW_MGR(IDLE_LOOP1),
> > + .idle_loop2 = RW_MGR(IDLE_LOOP2),
> > + .init_reset_0_cke_0 = RW_MGR(INIT_RESET_0_CKE_0),
> > + .init_reset_1_cke_0 = RW_MGR(INIT_RESET_1_CKE_0),
> > + .lfsr_wr_rd_bank_0 = RW_MGR(LFSR_WR_RD_BANK_0),
> > + .lfsr_wr_rd_bank_0_data = RW_MGR(LFSR_WR_RD_BANK_0_DATA),
> > + .lfsr_wr_rd_bank_0_dqs = RW_MGR(LFSR_WR_RD_BANK_0_DQS),
> > + .lfsr_wr_rd_bank_0_nop = RW_MGR(LFSR_WR_RD_BANK_0_NOP),
> > + .lfsr_wr_rd_bank_0_wait = RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
> > + .lfsr_wr_rd_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
> > + .lfsr_wr_rd_dm_bank_0 = RW_MGR(LFSR_WR_RD_DM_BANK_0),
> > + .lfsr_wr_rd_dm_bank_0_data = RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
> > + .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
> > + .lfsr_wr_rd_dm_bank_0_nop = RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
> > + .lfsr_wr_rd_dm_bank_0_wait = RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
> > + .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
> > + .mrs0_dll_reset = RW_MGR(MRS0_DLL_RESET),
> > + .mrs0_dll_reset_mirr = RW_MGR(MRS0_DLL_RESET_MIRR),
> > + .mrs0_user = RW_MGR(MRS0_USER),
> > + .mrs0_user_mirr = RW_MGR(MRS0_USER_MIRR),
> > + .mrs1 = RW_MGR(MRS1),
> > + .mrs1_mirr = RW_MGR(MRS1_MIRR),
> > + .mrs2 = RW_MGR(MRS2),
> > + .mrs2_mirr = RW_MGR(MRS2_MIRR),
> > + .mrs3 = RW_MGR(MRS3),
> > + .mrs3_mirr = RW_MGR(MRS3_MIRR),
> > + .precharge_all = RW_MGR(PRECHARGE_ALL),
> > + .read_b2b = RW_MGR(READ_B2B),
> > + .read_b2b_wait1 = RW_MGR(READ_B2B_WAIT1),
> > + .read_b2b_wait2 = RW_MGR(READ_B2B_WAIT2),
> > + .refresh_all = RW_MGR(REFRESH_ALL),
> > + .rreturn = RW_MGR(RETURN),
> > + .sgle_read = RW_MGR(SGLE_READ),
> > + .zqcl = RW_MGR(ZQCL),
> > +
> > + .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
> > + .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
> > + .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
> > + .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
> > + .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
> > + .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
> > + .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
> > + .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
> > + .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
> > + .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
> > + .mem_virtual_groups_per_read_dqs =
> > + RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
> > + .mem_virtual_groups_per_write_dqs =
> > + RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
> > +};
> > +
> > +static const struct socfpga_sdram_io_config io_config = {
> > + .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
> > + .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
> > + .delay_per_opa_tap_lo = IO_DELAY_PER_OPA_TAP & 0xff,
> > + .delay_per_opa_tap_hi = (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
> > + .dll_chain_length = IO_DLL_CHAIN_LENGTH,
> > + .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
> > + .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
> > + .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
> > + .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
> > + .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
> > + .dqs_in_reserve = IO_DQS_IN_RESERVE,
> > + .dqs_out_reserve = IO_DQS_OUT_RESERVE,
> > + .io_in_delay_max = IO_IO_IN_DELAY_MAX,
> > + .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
> > + .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
> > + .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
> > +};
> > +
> > +static const struct socfpga_sdram_misc_config misc_config = {
> > + .afi_rate_ratio = AFI_RATE_RATIO,
> > + .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
> > + .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
> > + .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
> > + .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
> > + .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
> > + .reg_file_init_seq_signature_ll = REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
> > + .reg_file_init_seq_signature_lh = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) &
> > 0xff,
> > + .reg_file_init_seq_signature_hl = (REG_FILE_INIT_SEQ_SIGNATURE >> 16) &
> > 0xff,
> > + .reg_file_init_seq_signature_hh = (REG_FILE_INIT_SEQ_SIGNATURE >> 24) &
> > 0xff,
> > + .tinit_cntr0_val = TINIT_CNTR0_VAL,
> > + .tinit_cntr1_val = TINIT_CNTR1_VAL,
> > + .tinit_cntr2_val = TINIT_CNTR2_VAL,
> > + .treset_cntr0_val = TRESET_CNTR0_VAL,
> > + .treset_cntr1_val = TRESET_CNTR1_VAL,
> > + .treset_cntr2_val = TRESET_CNTR2_VAL,
> > +};
> > +
> > +static void print_hdr(void)
> > +{
> > + printf(handoff_dtsi_hdr);
> > +}
> > +
> > +static void print_clkmgr_base(void)
> > +{
> > + const char handoff_dtsi_clkmgr_base[] =
> > + "\n"
> > + "&osc1 {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
> > + "};\n"
> > + "\n"
> > + "&osc2 {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
> > + "};\n"
> > + "\n"
> > + "&f2s_periph_ref_clk {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
> > + "};\n"
> > + "\n"
> > + "&f2s_sdram_ref_clk {\n"
> > + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
> > + "};\n";
> > +
> > + printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
> > +       CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
> > +       CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
> > +}
> > +
> > +/*
> > + * dtc stores u32 array big endian but we load them raw and expect them to
> > be in
> > + * little endian format. To prevent this tool to depend on host endianess,
> > do
> > + * the switch manually, not via 'htonl'.
> > + */
> > +static u32 swap_bytes(u32 val)
> > +{
> > + return (val << 24) | ((val & 0xFF00ul) << 8) |
> > + ((val & 0xFF0000ul) >> 8) | (val >> 24);
> > +}
> > +
> > +static void print_array_ulong(const unsigned long *arr, size_t arr_size,
> > +      size_t el_per_line, const char *indent1,
> > +      const char *name, const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = <", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("0x%08x", swap_bytes((u32)arr[i]));
> > + if (i + 1 < arr_size) {
> > + if (i % el_per_line == (el_per_line - 1)) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf(">;\n");
> > +}
> > +
> > +#ifdef USE_QUARTUS_OUTPUT
> > +static void print_array_sysmgrinit(const unsigned long *arr, size_t
> > arr_size,
> > +   const char *indent1, const char *name,
> > +   const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = [", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("%02x", (u8)arr[i]);
> > + if (i + 1 < arr_size) {
> > + if (i % 8 == 7) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf("];\n");
> > +}
> > +#define print_array_alt_u32 print_array_ulong
> > +#else
> > +#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr,
> > sz, 8, ind1, n, ind2)
> > +#define print_array_alt_u32 print_array_u32
> > +#endif
> > +
> > +static void print_array_u32(const u32 *arr, size_t arr_size,
> > +    size_t el_per_line, const char *indent1,
> > +    const char *name, const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = <", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("0x%08x", swap_bytes(arr[i]));
> > + if (i + 1 < arr_size) {
> > + if (i % el_per_line == (el_per_line - 1)) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf(">;\n");
> > +}
> > +
> > +static void print_array_u8(const u8 *arr, size_t arr_size, size_t
> > el_per_line,
> > +   const char *indent1, const char *name,
> > +   const char *indent_next)
> > +{
> > + size_t i;
> > +
> > + printf("%s%s = [", indent1, name);
> > + for (i = 0; i < arr_size; i++) {
> > + printf("%02x", arr[i]);
> > + if (i + 1 < arr_size) {
> > + if (i % el_per_line == (el_per_line - 1)) {
> > + printf("\n%s", indent_next);
> > + } else {
> > + printf(" ");
> > + }
> > + }
> > + }
> > + printf("];\n");
> > +}
> > +
> > +
> > +static void print_clkmgr_cfg(void)
> > +{
> > + const char handoff_dtsi_clkmgr_cfg_a[] =
> > + "\n"
> > + "&clkmgr {\n";
> > + const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
> > + const char clk_mgr_cfg_indent[] = "\t\t\t    ";
> > +
> > + printf(handoff_dtsi_clkmgr_cfg_a);
> > + print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
> > + "altr,clk-mgr-cfg", clk_mgr_cfg_indent);
> > + printf(handoff_dtsi_clkmgr_cfg_b);
> > +}
> > +
> > +static void print_sysmgr(void)
> > +{
> > + const char handoff_dtsi_sysmgr_begin[] =
> > + "\n"
> > + "&sysmgr {\n";
> > + const char handoff_dtsi_sysmgr_end[] = "};\n";
> > + const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
> > + size_t i;
> > +
> > + printf(handoff_dtsi_sysmgr_begin);
> > +
> > + /* sys_mgr_init_table is an u8 table */
> > + print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
> > +       "\t", "altr,pinmux-cfg","\t\t\t   ");
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain0_table,
> > +  ARRAY_SIZE(iocsr_scan_chain0_table), 4,
> > +  "\t", "altr,iocsr-scan-chain0-table",
> > +  sysmgr_cfg_indent);
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain1_table,
> > +  ARRAY_SIZE(iocsr_scan_chain1_table), 4,
> > +  "\t", "altr,iocsr-scan-chain1-table",
> > +  sysmgr_cfg_indent);
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain2_table,
> > +  ARRAY_SIZE(iocsr_scan_chain2_table), 4,
> > +  "\t", "altr,iocsr-scan-chain2-table",
> > +  sysmgr_cfg_indent);
> > + /* ioscr scan chain table 0 */
> > + print_array_ulong(iocsr_scan_chain3_table,
> > +  ARRAY_SIZE(iocsr_scan_chain3_table), 4,
> > +  "\t", "altr,iocsr-scan-chain3-table",
> > +  sysmgr_cfg_indent);
> > + printf(handoff_dtsi_sysmgr_end);
> > +}
> > +
> > +static void print_sdram_cfg(void)
> > +{
> > + const char handoff_dtsi_sdram_cfg_begin[] =
> > + "\n"
> > + "&sdr {\n";
> > + const char handoff_dtsi_sdram_cfg_end[] = "};\n";
> > +
> > + printf(handoff_dtsi_sdram_cfg_begin);
> > + print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
> > + "\t", "altr,sdr-cfg", "\t\t\t");
> > + print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
> > + "\t", "altr,sdr-rw-mgr-cfg", "\t\t\t       ");
> > + print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
> > + "\t", "altr,sdr-io-cfg", "\t\t\t   ");
> > + print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
> > + "\t", "altr,sdr-misc-cfg", "\t\t\t     ");
> > + print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
> > + "\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
> > + print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
> > + "\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");
> > + printf(handoff_dtsi_sdram_cfg_end);
> > +}
> > +
> > +int main(void)
> > +{
> > + print_hdr();
> > + print_clkmgr_base();
> > + print_clkmgr_cfg();
> > + print_sysmgr();
> > + print_sdram_cfg();
> > +}
> > diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-
> > socfpga/qts-to-handoff.sh
> > new file mode 100755
> > index 0000000000..b9032a5411
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
> > @@ -0,0 +1,83 @@
> > +#!/bin/sh
> > +# This script converts Quartus handoff files (in Quartus or U-Boot format)
> > +# to a handoff.dtsi file.
> > +
> > +
> > +usage() {
> > + MY_BASENAME=`basename $0`
> > + echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir]
> > [output_file]"
> > + echo " or"
> > + echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
> > + echo ""
> > + echo "Process QTS-generated headers into handoff.dtsi:"
> > + echo ""
> > + echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
> > + echo "  input_qts_dir - Directory with compiled Quartus project"
> > + echo "                  and containing the Quartus project file (QPF)."
> > + echo "  input_bsp_dir - Directory with generated bsp containing"
> > + echo "                  the settings.bsp file."
> > + echo "  output_file   - Full filename to store the handoff dtsi file."
> > + echo "  uboot_qts_dir - board/qts directory if input files are in"
> > + echo "                  'old-style' U-Boot format."
> > + echo ""
> > +}
> > +
> > +soc="$1"
> > +
> > +HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
> > +
> > +case "$soc" in
> > +"cyclone5"|"arria5")
> > + if [ "$#" -ne 4 ] ; then
> > + usage
> > + exit 1
> > + fi
> > + in_qts_dir="$2"
> > + in_bsp_dir="$3"
> > + output_file="$4"
> > + out_dir=`dirname ${output_file}`
> > +
> > + if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
> > + ! -d "${out_dir}" -o -z "${soc}" ] ; then
> > + usage
> > + exit 3
> > + fi
> > +
> > + if [ "$soc" = "cyclone5" ] ; then
> > + CMDLINE_DEFINES="-DCYCLONE5"
> > + else
> > + CMDLINE_DEFINES="-DARRIA5"
> > + fi
> > + CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT
> > -I${in_bsp_dir}/generated/"
> > + for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
> > + CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
> > + done
> > + ;;
> > +"u-boot")
> > + if [ "$#" -ne 3 ] ; then
> > + usage
> > + exit 1
> > + fi
> > + in_qts_dir="$2"
> > + output_file="$3"
> > + out_dir=`dirname ${output_file}`
> > +
> > + if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
> > + usage
> > + exit 3
> > + fi
> > +
> > + CMDLINE_DEFINES="-I${in_qts_dir}"
> > + ;;
> > +*)
> > + usage
> > + exit 1
> > + ;;
> > +esac
> > +
> > +# compile
> > +gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o
> > ${out_dir}/create_handoff_gen5
> > +${out_dir}/create_handoff_gen5 > ${output_file}
> > +
> > +# TODO: remove tmp file:
> > +#rm $${out_dir}/create_handoff_gen5
> > 

[U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files

[Simon Goldschmidt]

Am 24.10.2019 um 19:29 schrieb Dalon L Westergreen:
> 
> 
> On Thu, 2019-10-24 at 16:29 +0200, Simon Goldschmidt wrote:
>> On Thu, Oct 24, 2019 at 4:25 PM Dalon L Westergreen
>> <
>> dalon.westergreen at linux.intel.com
>>  <mailto:dalon.westergreen@linux.intel.com>
>> > wrote:
>>>
>>>
>>>
>>> On Wed, 2019-10-23 at 21:22 +0200, Simon Goldschmidt wrote:
>>>
>>> Am 23.10.2019 um 18:03 schrieb Dalon L Westergreen:
>>>
>>>
>>>
>>> On Tue, 2019-10-22 at 19:13 +0200, Simon Goldschmidt wrote:
>>>
>>>
>>>
>>> Dalon L Westergreen <
>>>
>>> dalon.westergreen at linux.intel.com
>>>  <mailto:dalon.westergreen@linux.intel.com>
>>>
>>>
>>>
>>>
>>> <mailto:
>>>
>>> dalon.westergreen at linux.intel.com
>>>  <mailto:dalon.westergreen@linux.intel.com>
>>>
>>>
>>>>> schrieb am Di., 22. Okt.
>>>
>>> 2019, 19:10:
>>>
>>> I mentioned this before, it would be great to not rely on the
>>>
>>> generated files
>>>
>>> and do this based purely on the handoff data generated during a quartus
>>>
>>> build. Did you look at the python source i pointed you to?
>>>
>>>
>>> No, not yet. But I don't think that will be a problem. I sent this
>>>
>>> series mainly to discuss the dts format (boardspecific handoff dtsi vs
>>>
>>> genetic dtsi plus boardspecific header file).
>>>
>>>
>>> The board specific dtsi does look cleaner, but i do like the simplicity
>>>
>>> of generating the header in arria10.
>>>
>>>
>>> I could easily replicate what you do, generate the header, and use it to
>>>
>>> create the dtsi.
>>>
>>>
>>> I'm not too fond myself of that tool I created, as it requires you to
>>>
>>> have a compiler. I just was too lazy write a script for that.
>>>
>>>
>>> However, I would prefer having a script that does it. And if the sources
>>>
>>> are quartus output files instead of existing qts files, my tool doesn't
>>>
>>> work any more, anway.
>>>
>>>
>>> So I think we should come up with a script (e.g. sh or py) that parses
>>>
>>> quartus output and creates a handoff dtsi (without a header). We'll only
>>>
>>> need something different for converting existing qts files then...
>>>
>>>
>>> In that case, i would stick with adding a .h file along with a common handoff dtsi as i did
>>> in the a10 filter script i sent the other week. I would suggest your source is perfect
>>> for migrating existing c5/a5 platforms.
>>
>> Why can't we change that a10 script to create handoff dtsi files as well?
> 
> I just dont like building the dtsi in source, the code to create a 
> header is simpler and cleaner. From
> a files perspective, 1 dtsi + a header for each board, or a dtsi for 
> each board, not sure there is much
> difference either way. but using headers keeps the utility simpler.

Well, you're right that writing the conversion tool is probably simpler 
when creating a header file compared to a dtsi. On the other hand, it 
only has to be written once, so it should not be too much of an issue?

However, looking at arch/arm/dts, socfpga would be the first mach to add 
board specific header files. I don't know if it's acceptable to do it 
like that? I'm not the gatekeeper here :-)

Regards,
Simon

> 
> --dalon
> 
>>
>>>
>>> Is there a preference for python? It would fit nicely b/c we could re-use the code
>>> I pointed out previously for binary parsing.
>>
>> Well, *my* preference would be to not depend on having gcc installed to convert
>> from quartus output to dtsi. I just did that because C was easier to
>> get started.
>>
>> I'm not a big fan of python, but since it's used everywhere in U-Boot, I
>> figured it should be ok? Having a standard shell script do the job would even
>> lower the requirements of course.
>>
>> Regards,
>> Simon
>>
>>>
>>> Dinh, Marek, Ley Foon, comments?
>>>
>>> --dalon
>>>
>>>
>>> Regards,
>>>
>>> Simon
>>>
>>>
>>>
>>> --dalon
>>>
>>>
>>>
>>> I still favor boardspecific handoff dtsi, but I would like to use the
>>>
>>> same style for all socfpga flavours.
>>>
>>>
>>> Plus this tool is required to convert existing boards where we don't
>>>
>>> have the quartus project files at hand.
>>>
>>>
>>> Regards,
>>>
>>> Simon
>>>
>>>
>>>
>>> --dalon
>>>
>>>
>>> On Tue, 2019-10-15 at 22:10 +0200, Simon Goldschmidt wrote:
>>>
>>> This new tool converts handoff information from quartus to "*_handoff.dtsi"
>>>
>>> devicetree files. This is in preparation to move from ad-hoc code in arch
>>>
>>> that parses the 'qts' header files to drivers parsing the same information
>>>
>>> from devicetree.
>>>
>>>
>>> Converting existing U-Boot 'qts' files is also supported.
>>>
>>>
>>> Signed-off-by: Simon Goldschmidt <
>>>
>>> simon.k.r.goldschmidt at gmail.com
>>>  <mailto:simon.k.r.goldschmidt@gmail.com>
>>>
>>>
>>>
>>>   <mailto:
>>>
>>> simon.k.r.goldschmidt at gmail.com
>>>  <mailto:simon.k.r.goldschmidt@gmail.com>
>>>
>>>
>>>>
>>>
>>>
>>> ---
>>>
>>>
>>> Changes in v2: None
>>>
>>>
>>>    arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++++++
>>>
>>>    arch/arm/mach-socfpga/qts-to-handoff.sh     |  83 +++
>>>
>>>    2 files changed, 743 insertions(+)
>>>
>>>    create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c
>>>
>>>    create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh
>>>
>>>
>>> diff --git a/arch/arm/mach-socfpga/create_handoff_gen5.c b/arch/arm/mach-socfpga/create_handoff_gen5.c
>>>
>>> new file mode 100644
>>>
>>> index 0000000000..6ec436719d
>>>
>>> --- /dev/null
>>>
>>> +++ b/arch/arm/mach-socfpga/create_handoff_gen5.c
>>>
>>> @@ -0,0 +1,660 @@
>>>
>>> +// SPDX-License-Identifier: GPL-2.0
>>>
>>> +/*
>>>
>>> + * This is a host-tool that needs to be compiled per board and prints the
>>>
>>> + * handoff.dtsi to stdout.
>>>
>>> + */
>>>
>>> +
>>>
>>> +#include <stdio.h>
>>>
>>> +#include <stdint.h>
>>>
>>> +
>>>
>>> +/* Define kernel types */
>>>
>>> +typedef uint8_t u8;
>>>
>>> +typedef uint32_t u32;
>>>
>>> +
>>>
>>> +#ifdef USE_QUARTUS_OUTPUT
>>>
>>> +#ifdef ARRIA5
>>>
>>> +#include "iocsr_config_arria5.c"
>>>
>>> +#include "pinmux_config_arria5.c"
>>>
>>> +#else
>>>
>>> +#include "iocsr_config_cyclone5.c"
>>>
>>> +#include "pinmux_config_cyclone5.c"
>>>
>>> +#endif
>>>
>>> +#include "pll_config.h"
>>>
>>> +#include "sdram/sdram_config.h"
>>>
>>> +#include "sequencer_auto.h"
>>>
>>> +#include "sequencer_defines.h"
>>>
>>> +#include "sequencer_auto_ac_init.c"
>>>
>>> +#include "sequencer_auto_inst_init.c"
>>>
>>> +#define RW_MGR(x) __RW_MGR_##x
>>>
>>> +#else
>>>
>>> +#define RW_MGR(x) RW_MGR_##x
>>>
>>> +#include <iocsr_config.h>
>>>
>>> +#include <pinmux_config.h>
>>>
>>> +#include <pll_config.h>
>>>
>>> +#include <sdram_config.h>
>>>
>>> +#endif
>>>
>>> +
>>>
>>> +#include "include/mach/clock_manager_gen5.h"
>>>
>>> +#include "include/mach/sdram_gen5.h"
>>>
>>> +
>>>
>>> +#ifndef ARRAY_SIZE
>>>
>>> +#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
>>>
>>> +#endif
>>>
>>> +
>>>
>>> +const char handoff_dtsi_hdr[] =
>>>
>>> + "// SPDX-License-Identifier: GPL-2.0\n"
>>>
>>> + "/*\n"
>>>
>>> + " *<auto-generated>\n"
>>>
>>> + " * This code was generated by a tool based on\n"
>>>
>>> + " * handoffs from both Qsys and Quartus.\n"
>>>
>>> + " *\n"
>>>
>>> + " * Changes to this file may be lost if\n"
>>>
>>> + " * the code is regenerated.\n"
>>>
>>> + " *</auto-generated>\n"
>>>
>>> + " */\n";
>>>
>>> +
>>>
>>> +/* Wrap PLL config */
>>>
>>> +
>>>
>>> +#define MAIN_VCO_BASE ( \
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
>>>
>>> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
>>>
>>> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
>>>
>>> + )
>>>
>>> +
>>>
>>> +#define PERI_VCO_BASE ( \
>>>
>>> + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
>>>
>>> + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
>>>
>>> + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
>>>
>>> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
>>>
>>> + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
>>>
>>> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
>>>
>>> + )
>>>
>>> +
>>>
>>> +#define SDR_VCO_BASE ( \
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
>>>
>>> + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
>>>
>>> + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
>>>
>>> + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
>>>
>>> + )
>>>
>>> +
>>>
>>> +static const struct cm_config cm_default = {
>>>
>>> + /* main group */
>>>
>>> + MAIN_VCO_BASE,
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
>>>
>>> + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
>>>
>>> + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
>>>
>>> + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
>>>
>>> + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
>>>
>>> + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
>>>
>>> + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
>>>
>>> + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
>>>
>>> + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
>>>
>>> + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
>>>
>>> +
>>>
>>> + /* peripheral group */
>>>
>>> + PERI_VCO_BASE,
>>>
>>> + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
>>>
>>> + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
>>>
>>> + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
>>>
>>> + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
>>>
>>> + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
>>>
>>> + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
>>>
>>> + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
>>>
>>> + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
>>>
>>> + (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
>>>
>>> + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
>>>
>>> + (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
>>>
>>> + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
>>>
>>> + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
>>>
>>> + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
>>>
>>> +
>>>
>>> + /* sdram pll group */
>>>
>>> + SDR_VCO_BASE,
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
>>>
>>> + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
>>>
>>> + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
>>>
>>> + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
>>>
>>> + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
>>>
>>> + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
>>>
>>> + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
>>>
>>> + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
>>>
>>> + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
>>>
>>> + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
>>>
>>> +
>>>
>>> + /* altera group */
>>>
>>> + CONFIG_HPS_ALTERAGRP_MPUCLK,
>>>
>>> +};
>>>
>>> +
>>>
>>> +/* Wrap SDRAM config */
>>>
>>> +static const struct socfpga_sdram_config sdram_config = {
>>>
>>> + .ctrl_cfg =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
>>>
>>> + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
>>>
>>> + .dram_timing1 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
>>>
>>> + .dram_timing2 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
>>>
>>> + .dram_timing3 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
>>>
>>> + .dram_timing4 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
>>>
>>> + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
>>>
>>> + .lowpwr_timing =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
>>>
>>> + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
>>>
>>> + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
>>>
>>> + .dram_odt =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
>>>
>>> + SDR_CTRLGRP_DRAMODT_READ_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
>>>
>>> + SDR_CTRLGRP_DRAMODT_WRITE_LSB),
>>>
>>> + .extratime1 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
>>>
>>> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
>>>
>>> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
>>>
>>> +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
>>>
>>> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
>>>
>>> + .dram_addrw =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
>>>
>>> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
>>>
>>> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
>>>
>>> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
>>>
>>> + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
>>>
>>> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
>>>
>>> + .dram_if_width =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
>>>
>>> + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
>>>
>>> + .dram_dev_width =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
>>>
>>> + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
>>>
>>> + .dram_intr =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
>>>
>>> + SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
>>>
>>> + .lowpwr_eq =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
>>>
>>> + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
>>>
>>> + .static_cfg =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
>>>
>>> + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
>>>
>>> + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
>>>
>>> + .ctrl_width =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
>>>
>>> + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
>>>
>>> + .cport_width =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
>>>
>>> + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
>>>
>>> + .cport_wmap =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
>>>
>>> + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
>>>
>>> + .cport_rmap =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
>>>
>>> + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
>>>
>>> + .rfifo_cmap =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
>>>
>>> + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
>>>
>>> + .wfifo_cmap =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
>>>
>>> + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
>>>
>>> + .cport_rdwr =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
>>>
>>> + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
>>>
>>> + .port_cfg =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
>>>
>>> + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
>>>
>>> + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
>>>
>>> + .fifo_cfg =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
>>>
>>> + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
>>>
>>> + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
>>>
>>> + .mp_priority =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
>>>
>>> + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
>>>
>>> + .mp_weight0 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
>>>
>>> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
>>>
>>> + .mp_weight1 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
>>>
>>> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
>>>
>>> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
>>>
>>> + .mp_weight2 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
>>>
>>> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
>>>
>>> + .mp_weight3 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
>>>
>>> + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
>>>
>>> + .mp_pacing0 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
>>>
>>> + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
>>>
>>> + .mp_pacing1 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
>>>
>>> + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
>>>
>>> + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
>>>
>>> + .mp_pacing2 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
>>>
>>> + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
>>>
>>> + .mp_pacing3 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
>>>
>>> + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
>>>
>>> + .mp_threshold0 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
>>>
>>> + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
>>>
>>> + .mp_threshold1 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
>>>
>>> + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
>>>
>>> + .mp_threshold2 =
>>>
>>> + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
>>>
>>> + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
>>>
>>> + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
>>>
>>> +};
>>>
>>> +
>>>
>>> +static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
>>>
>>> + .activate_0_and_1 = RW_MGR(ACTIVATE_0_AND_1),
>>>
>>> + .activate_0_and_1_wait1 = RW_MGR(ACTIVATE_0_AND_1_WAIT1),
>>>
>>> + .activate_0_and_1_wait2 = RW_MGR(ACTIVATE_0_AND_1_WAIT2),
>>>
>>> + .activate_1 = RW_MGR(ACTIVATE_1),
>>>
>>> + .clear_dqs_enable = RW_MGR(CLEAR_DQS_ENABLE),
>>>
>>> + .guaranteed_read = RW_MGR(GUARANTEED_READ),
>>>
>>> + .guaranteed_read_cont = RW_MGR(GUARANTEED_READ_CONT),
>>>
>>> + .guaranteed_write = RW_MGR(GUARANTEED_WRITE),
>>>
>>> + .guaranteed_write_wait0 = RW_MGR(GUARANTEED_WRITE_WAIT0),
>>>
>>> + .guaranteed_write_wait1 = RW_MGR(GUARANTEED_WRITE_WAIT1),
>>>
>>> + .guaranteed_write_wait2 = RW_MGR(GUARANTEED_WRITE_WAIT2),
>>>
>>> + .guaranteed_write_wait3 = RW_MGR(GUARANTEED_WRITE_WAIT3),
>>>
>>> + .idle = RW_MGR(IDLE),
>>>
>>> + .idle_loop1 = RW_MGR(IDLE_LOOP1),
>>>
>>> + .idle_loop2 = RW_MGR(IDLE_LOOP2),
>>>
>>> + .init_reset_0_cke_0 = RW_MGR(INIT_RESET_0_CKE_0),
>>>
>>> + .init_reset_1_cke_0 = RW_MGR(INIT_RESET_1_CKE_0),
>>>
>>> + .lfsr_wr_rd_bank_0 = RW_MGR(LFSR_WR_RD_BANK_0),
>>>
>>> + .lfsr_wr_rd_bank_0_data = RW_MGR(LFSR_WR_RD_BANK_0_DATA),
>>>
>>> + .lfsr_wr_rd_bank_0_dqs = RW_MGR(LFSR_WR_RD_BANK_0_DQS),
>>>
>>> + .lfsr_wr_rd_bank_0_nop = RW_MGR(LFSR_WR_RD_BANK_0_NOP),
>>>
>>> + .lfsr_wr_rd_bank_0_wait = RW_MGR(LFSR_WR_RD_BANK_0_WAIT),
>>>
>>> + .lfsr_wr_rd_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_BANK_0_WL_1),
>>>
>>> + .lfsr_wr_rd_dm_bank_0 = RW_MGR(LFSR_WR_RD_DM_BANK_0),
>>>
>>> + .lfsr_wr_rd_dm_bank_0_data = RW_MGR(LFSR_WR_RD_DM_BANK_0_DATA),
>>>
>>> + .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR(LFSR_WR_RD_DM_BANK_0_DQS),
>>>
>>> + .lfsr_wr_rd_dm_bank_0_nop = RW_MGR(LFSR_WR_RD_DM_BANK_0_NOP),
>>>
>>> + .lfsr_wr_rd_dm_bank_0_wait = RW_MGR(LFSR_WR_RD_DM_BANK_0_WAIT),
>>>
>>> + .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR(LFSR_WR_RD_DM_BANK_0_WL_1),
>>>
>>> + .mrs0_dll_reset = RW_MGR(MRS0_DLL_RESET),
>>>
>>> + .mrs0_dll_reset_mirr = RW_MGR(MRS0_DLL_RESET_MIRR),
>>>
>>> + .mrs0_user = RW_MGR(MRS0_USER),
>>>
>>> + .mrs0_user_mirr = RW_MGR(MRS0_USER_MIRR),
>>>
>>> + .mrs1 = RW_MGR(MRS1),
>>>
>>> + .mrs1_mirr = RW_MGR(MRS1_MIRR),
>>>
>>> + .mrs2 = RW_MGR(MRS2),
>>>
>>> + .mrs2_mirr = RW_MGR(MRS2_MIRR),
>>>
>>> + .mrs3 = RW_MGR(MRS3),
>>>
>>> + .mrs3_mirr = RW_MGR(MRS3_MIRR),
>>>
>>> + .precharge_all = RW_MGR(PRECHARGE_ALL),
>>>
>>> + .read_b2b = RW_MGR(READ_B2B),
>>>
>>> + .read_b2b_wait1 = RW_MGR(READ_B2B_WAIT1),
>>>
>>> + .read_b2b_wait2 = RW_MGR(READ_B2B_WAIT2),
>>>
>>> + .refresh_all = RW_MGR(REFRESH_ALL),
>>>
>>> + .rreturn = RW_MGR(RETURN),
>>>
>>> + .sgle_read = RW_MGR(SGLE_READ),
>>>
>>> + .zqcl = RW_MGR(ZQCL),
>>>
>>> +
>>>
>>> + .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
>>>
>>> + .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
>>>
>>> + .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
>>>
>>> + .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
>>>
>>> + .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
>>>
>>> + .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
>>>
>>> + .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
>>>
>>> + .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
>>>
>>> + .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
>>>
>>> + .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
>>>
>>> + .mem_virtual_groups_per_read_dqs =
>>>
>>> + RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
>>>
>>> + .mem_virtual_groups_per_write_dqs =
>>>
>>> + RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
>>>
>>> +};
>>>
>>> +
>>>
>>> +static const struct socfpga_sdram_io_config io_config = {
>>>
>>> + .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
>>>
>>> + .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
>>>
>>> + .delay_per_opa_tap_lo = IO_DELAY_PER_OPA_TAP & 0xff,
>>>
>>> + .delay_per_opa_tap_hi = (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
>>>
>>> + .dll_chain_length = IO_DLL_CHAIN_LENGTH,
>>>
>>> + .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
>>>
>>> + .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
>>>
>>> + .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
>>>
>>> + .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
>>>
>>> + .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
>>>
>>> + .dqs_in_reserve = IO_DQS_IN_RESERVE,
>>>
>>> + .dqs_out_reserve = IO_DQS_OUT_RESERVE,
>>>
>>> + .io_in_delay_max = IO_IO_IN_DELAY_MAX,
>>>
>>> + .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
>>>
>>> + .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
>>>
>>> + .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
>>>
>>> +};
>>>
>>> +
>>>
>>> +static const struct socfpga_sdram_misc_config misc_config = {
>>>
>>> + .afi_rate_ratio = AFI_RATE_RATIO,
>>>
>>> + .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
>>>
>>> + .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
>>>
>>> + .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
>>>
>>> + .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
>>>
>>> + .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
>>>
>>> + .reg_file_init_seq_signature_ll = REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
>>>
>>> + .reg_file_init_seq_signature_lh = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
>>>
>>> + .reg_file_init_seq_signature_hl = (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
>>>
>>> + .reg_file_init_seq_signature_hh = (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
>>>
>>> + .tinit_cntr0_val = TINIT_CNTR0_VAL,
>>>
>>> + .tinit_cntr1_val = TINIT_CNTR1_VAL,
>>>
>>> + .tinit_cntr2_val = TINIT_CNTR2_VAL,
>>>
>>> + .treset_cntr0_val = TRESET_CNTR0_VAL,
>>>
>>> + .treset_cntr1_val = TRESET_CNTR1_VAL,
>>>
>>> + .treset_cntr2_val = TRESET_CNTR2_VAL,
>>>
>>> +};
>>>
>>> +
>>>
>>> +static void print_hdr(void)
>>>
>>> +{
>>>
>>> + printf(handoff_dtsi_hdr);
>>>
>>> +}
>>>
>>> +
>>>
>>> +static void print_clkmgr_base(void)
>>>
>>> +{
>>>
>>> + const char handoff_dtsi_clkmgr_base[] =
>>>
>>> + "\n"
>>>
>>> + "&osc1 {\n"
>>>
>>> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC1_HZ */
>>>
>>> + "};\n"
>>>
>>> + "\n"
>>>
>>> + "&osc2 {\n"
>>>
>>> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_OSC2_HZ */
>>>
>>> + "};\n"
>>>
>>> + "\n"
>>>
>>> + "&f2s_periph_ref_clk {\n"
>>>
>>> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_PER_REF_HZ */
>>>
>>> + "};\n"
>>>
>>> + "\n"
>>>
>>> + "&f2s_sdram_ref_clk {\n"
>>>
>>> + " clock-frequency = <%d>;\n" /* CONFIG_HPS_CLK_F2S_SDR_REF_HZ */
>>>
>>> + "};\n";
>>>
>>> +
>>>
>>> + printf(handoff_dtsi_clkmgr_base, CONFIG_HPS_CLK_OSC1_HZ,
>>>
>>> +       CONFIG_HPS_CLK_OSC2_HZ, CONFIG_HPS_CLK_F2S_PER_REF_HZ,
>>>
>>> +       CONFIG_HPS_CLK_F2S_SDR_REF_HZ);
>>>
>>> +}
>>>
>>> +
>>>
>>> +/*
>>>
>>> + * dtc stores u32 array big endian but we load them raw and expect them to be in
>>>
>>> + * little endian format. To prevent this tool to depend on host endianess, do
>>>
>>> + * the switch manually, not via 'htonl'.
>>>
>>> + */
>>>
>>> +static u32 swap_bytes(u32 val)
>>>
>>> +{
>>>
>>> + return (val << 24) | ((val & 0xFF00ul) << 8) |
>>>
>>> + ((val & 0xFF0000ul) >> 8) | (val >> 24);
>>>
>>> +}
>>>
>>> +
>>>
>>> +static void print_array_ulong(const unsigned long *arr, size_t arr_size,
>>>
>>> +      size_t el_per_line, const char *indent1,
>>>
>>> +      const char *name, const char *indent_next)
>>>
>>> +{
>>>
>>> + size_t i;
>>>
>>> +
>>>
>>> + printf("%s%s = <", indent1, name);
>>>
>>> + for (i = 0; i < arr_size; i++) {
>>>
>>> + printf("0x%08x", swap_bytes((u32)arr[i]));
>>>
>>> + if (i + 1 < arr_size) {
>>>
>>> + if (i % el_per_line == (el_per_line - 1)) {
>>>
>>> + printf("\n%s", indent_next);
>>>
>>> + } else {
>>>
>>> + printf(" ");
>>>
>>> + }
>>>
>>> + }
>>>
>>> + }
>>>
>>> + printf(">;\n");
>>>
>>> +}
>>>
>>> +
>>>
>>> +#ifdef USE_QUARTUS_OUTPUT
>>>
>>> +static void print_array_sysmgrinit(const unsigned long *arr, size_t arr_size,
>>>
>>> +   const char *indent1, const char *name,
>>>
>>> +   const char *indent_next)
>>>
>>> +{
>>>
>>> + size_t i;
>>>
>>> +
>>>
>>> + printf("%s%s = [", indent1, name);
>>>
>>> + for (i = 0; i < arr_size; i++) {
>>>
>>> + printf("%02x", (u8)arr[i]);
>>>
>>> + if (i + 1 < arr_size) {
>>>
>>> + if (i % 8 == 7) {
>>>
>>> + printf("\n%s", indent_next);
>>>
>>> + } else {
>>>
>>> + printf(" ");
>>>
>>> + }
>>>
>>> + }
>>>
>>> + }
>>>
>>> + printf("];\n");
>>>
>>> +}
>>>
>>> +#define print_array_alt_u32 print_array_ulong
>>>
>>> +#else
>>>
>>> +#define print_array_sysmgrinit(arr, sz, ind1, n, ind2) print_array_u8(arr, sz, 8, ind1, n, ind2)
>>>
>>> +#define print_array_alt_u32 print_array_u32
>>>
>>> +#endif
>>>
>>> +
>>>
>>> +static void print_array_u32(const u32 *arr, size_t arr_size,
>>>
>>> +    size_t el_per_line, const char *indent1,
>>>
>>> +    const char *name, const char *indent_next)
>>>
>>> +{
>>>
>>> + size_t i;
>>>
>>> +
>>>
>>> + printf("%s%s = <", indent1, name);
>>>
>>> + for (i = 0; i < arr_size; i++) {
>>>
>>> + printf("0x%08x", swap_bytes(arr[i]));
>>>
>>> + if (i + 1 < arr_size) {
>>>
>>> + if (i % el_per_line == (el_per_line - 1)) {
>>>
>>> + printf("\n%s", indent_next);
>>>
>>> + } else {
>>>
>>> + printf(" ");
>>>
>>> + }
>>>
>>> + }
>>>
>>> + }
>>>
>>> + printf(">;\n");
>>>
>>> +}
>>>
>>> +
>>>
>>> +static void print_array_u8(const u8 *arr, size_t arr_size, size_t el_per_line,
>>>
>>> +   const char *indent1, const char *name,
>>>
>>> +   const char *indent_next)
>>>
>>> +{
>>>
>>> + size_t i;
>>>
>>> +
>>>
>>> + printf("%s%s = [", indent1, name);
>>>
>>> + for (i = 0; i < arr_size; i++) {
>>>
>>> + printf("%02x", arr[i]);
>>>
>>> + if (i + 1 < arr_size) {
>>>
>>> + if (i % el_per_line == (el_per_line - 1)) {
>>>
>>> + printf("\n%s", indent_next);
>>>
>>> + } else {
>>>
>>> + printf(" ");
>>>
>>> + }
>>>
>>> + }
>>>
>>> + }
>>>
>>> + printf("];\n");
>>>
>>> +}
>>>
>>> +
>>>
>>> +
>>>
>>> +static void print_clkmgr_cfg(void)
>>>
>>> +{
>>>
>>> + const char handoff_dtsi_clkmgr_cfg_a[] =
>>>
>>> + "\n"
>>>
>>> + "&clkmgr {\n";
>>>
>>> + const char handoff_dtsi_clkmgr_cfg_b[] = "};\n";
>>>
>>> + const char clk_mgr_cfg_indent[] = "\t\t\t    ";
>>>
>>> +
>>>
>>> + printf(handoff_dtsi_clkmgr_cfg_a);
>>>
>>> + print_array_u32((const u32 *)&cm_default, sizeof(cm_default)/4, 4, "\t",
>>>
>>> + "altr,clk-mgr-cfg", clk_mgr_cfg_indent);
>>>
>>> + printf(handoff_dtsi_clkmgr_cfg_b);
>>>
>>> +}
>>>
>>> +
>>>
>>> +static void print_sysmgr(void)
>>>
>>> +{
>>>
>>> + const char handoff_dtsi_sysmgr_begin[] =
>>>
>>> + "\n"
>>>
>>> + "&sysmgr {\n";
>>>
>>> + const char handoff_dtsi_sysmgr_end[] = "};\n";
>>>
>>> + const char sysmgr_cfg_indent[] = "\t\t\t\t\t";
>>>
>>> + size_t i;
>>>
>>> +
>>>
>>> + printf(handoff_dtsi_sysmgr_begin);
>>>
>>> +
>>>
>>> + /* sys_mgr_init_table is an u8 table */
>>>
>>> + print_array_sysmgrinit(sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table),
>>>
>>> +       "\t", "altr,pinmux-cfg","\t\t\t   ");
>>>
>>> + /* ioscr scan chain table 0 */
>>>
>>> + print_array_ulong(iocsr_scan_chain0_table,
>>>
>>> +  ARRAY_SIZE(iocsr_scan_chain0_table), 4,
>>>
>>> +  "\t", "altr,iocsr-scan-chain0-table",
>>>
>>> +  sysmgr_cfg_indent);
>>>
>>> + /* ioscr scan chain table 0 */
>>>
>>> + print_array_ulong(iocsr_scan_chain1_table,
>>>
>>> +  ARRAY_SIZE(iocsr_scan_chain1_table), 4,
>>>
>>> +  "\t", "altr,iocsr-scan-chain1-table",
>>>
>>> +  sysmgr_cfg_indent);
>>>
>>> + /* ioscr scan chain table 0 */
>>>
>>> + print_array_ulong(iocsr_scan_chain2_table,
>>>
>>> +  ARRAY_SIZE(iocsr_scan_chain2_table), 4,
>>>
>>> +  "\t", "altr,iocsr-scan-chain2-table",
>>>
>>> +  sysmgr_cfg_indent);
>>>
>>> + /* ioscr scan chain table 0 */
>>>
>>> + print_array_ulong(iocsr_scan_chain3_table,
>>>
>>> +  ARRAY_SIZE(iocsr_scan_chain3_table), 4,
>>>
>>> +  "\t", "altr,iocsr-scan-chain3-table",
>>>
>>> +  sysmgr_cfg_indent);
>>>
>>> + printf(handoff_dtsi_sysmgr_end);
>>>
>>> +}
>>>
>>> +
>>>
>>> +static void print_sdram_cfg(void)
>>>
>>> +{
>>>
>>> + const char handoff_dtsi_sdram_cfg_begin[] =
>>>
>>> + "\n"
>>>
>>> + "&sdr {\n";
>>>
>>> + const char handoff_dtsi_sdram_cfg_end[] = "};\n";
>>>
>>> +
>>>
>>> + printf(handoff_dtsi_sdram_cfg_begin);
>>>
>>> + print_array_u32((const u32 *)&sdram_config, sizeof(sdram_config)/4, 4,
>>>
>>> + "\t", "altr,sdr-cfg", "\t\t\t");
>>>
>>> + print_array_u8((const u8 *)&rw_mgr_config, sizeof(rw_mgr_config), 8,
>>>
>>> + "\t", "altr,sdr-rw-mgr-cfg", "\t\t\t       ");
>>>
>>> + print_array_u8((const u8 *)&io_config, sizeof(io_config), 8,
>>>
>>> + "\t", "altr,sdr-io-cfg", "\t\t\t   ");
>>>
>>> + print_array_u8((const u8 *)&misc_config, sizeof(misc_config), 8,
>>>
>>> + "\t", "altr,sdr-misc-cfg", "\t\t\t     ");
>>>
>>> + print_array_alt_u32(ac_rom_init, ARRAY_SIZE(ac_rom_init), 4,
>>>
>>> + "\t", "altr,sdr-ac-rom-init", "\t\t\t\t");
>>>
>>> + print_array_alt_u32(inst_rom_init, ARRAY_SIZE(inst_rom_init), 4,
>>>
>>> + "\t", "altr,sdr-inst-rom-init", "\t\t\t\t  ");
>>>
>>> + printf(handoff_dtsi_sdram_cfg_end);
>>>
>>> +}
>>>
>>> +
>>>
>>> +int main(void)
>>>
>>> +{
>>>
>>> + print_hdr();
>>>
>>> + print_clkmgr_base();
>>>
>>> + print_clkmgr_cfg();
>>>
>>> + print_sysmgr();
>>>
>>> + print_sdram_cfg();
>>>
>>> +}
>>>
>>> diff --git a/arch/arm/mach-socfpga/qts-to-handoff.sh b/arch/arm/mach-socfpga/qts-to-handoff.sh
>>>
>>> new file mode 100755
>>>
>>> index 0000000000..b9032a5411
>>>
>>> --- /dev/null
>>>
>>> +++ b/arch/arm/mach-socfpga/qts-to-handoff.sh
>>>
>>> @@ -0,0 +1,83 @@
>>>
>>> +#!/bin/sh
>>>
>>> +# This script converts Quartus handoff files (in Quartus or U-Boot format)
>>>
>>> +# to a handoff.dtsi file.
>>>
>>> +
>>>
>>> +
>>>
>>> +usage() {
>>>
>>> + MY_BASENAME=`basename $0`
>>>
>>> + echo "${MY_BASENAME} [soc_type] [input_qts_dir] [input_bsp_dir] [output_file]"
>>>
>>> + echo " or"
>>>
>>> + echo "${MY_BASENAME} 'u-boot' [uboot_qts_dir] [output_file]"
>>>
>>> + echo ""
>>>
>>> + echo "Process QTS-generated headers into handoff.dtsi:"
>>>
>>> + echo ""
>>>
>>> + echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
>>>
>>> + echo "  input_qts_dir - Directory with compiled Quartus project"
>>>
>>> + echo "                  and containing the Quartus project file (QPF)."
>>>
>>> + echo "  input_bsp_dir - Directory with generated bsp containing"
>>>
>>> + echo "                  the settings.bsp file."
>>>
>>> + echo "  output_file   - Full filename to store the handoff dtsi file."
>>>
>>> + echo "  uboot_qts_dir - board/qts directory if input files are in"
>>>
>>> + echo "                  'old-style' U-Boot format."
>>>
>>> + echo ""
>>>
>>> +}
>>>
>>> +
>>>
>>> +soc="$1"
>>>
>>> +
>>>
>>> +HANDOFF_TEMPLATE="`dirname $0`/create_handoff_gen5.c"
>>>
>>> +
>>>
>>> +case "$soc" in
>>>
>>> +"cyclone5"|"arria5")
>>>
>>> + if [ "$#" -ne 4 ] ; then
>>>
>>> + usage
>>>
>>> + exit 1
>>>
>>> + fi
>>>
>>> + in_qts_dir="$2"
>>>
>>> + in_bsp_dir="$3"
>>>
>>> + output_file="$4"
>>>
>>> + out_dir=`dirname ${output_file}`
>>>
>>> +
>>>
>>> + if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
>>>
>>> + ! -d "${out_dir}" -o -z "${soc}" ] ; then
>>>
>>> + usage
>>>
>>> + exit 3
>>>
>>> + fi
>>>
>>> +
>>>
>>> + if [ "$soc" = "cyclone5" ] ; then
>>>
>>> + CMDLINE_DEFINES="-DCYCLONE5"
>>>
>>> + else
>>>
>>> + CMDLINE_DEFINES="-DARRIA5"
>>>
>>> + fi
>>>
>>> + CMDLINE_DEFINES="${CMDLINE_DEFINES} -DUSE_QUARTUS_OUTPUT -I${in_bsp_dir}/generated/"
>>>
>>> + for d in ${in_qts_dir}/hps_isw_handoff/*/ ; do
>>>
>>> + CMDLINE_DEFINES="${CMDLINE_DEFINES} -I$d"
>>>
>>> + done
>>>
>>> + ;;
>>>
>>> +"u-boot")
>>>
>>> + if [ "$#" -ne 3 ] ; then
>>>
>>> + usage
>>>
>>> + exit 1
>>>
>>> + fi
>>>
>>> + in_qts_dir="$2"
>>>
>>> + output_file="$3"
>>>
>>> + out_dir=`dirname ${output_file}`
>>>
>>> +
>>>
>>> + if [ ! -d "${in_qts_dir}" -o ! -d "${out_dir}" ] ; then
>>>
>>> + usage
>>>
>>> + exit 3
>>>
>>> + fi
>>>
>>> +
>>>
>>> + CMDLINE_DEFINES="-I${in_qts_dir}"
>>>
>>> + ;;
>>>
>>> +*)
>>>
>>> + usage
>>>
>>> + exit 1
>>>
>>> + ;;
>>>
>>> +esac
>>>
>>> +
>>>
>>> +# compile
>>>
>>> +gcc ${CMDLINE_DEFINES} ${HANDOFF_TEMPLATE} -o ${out_dir}/create_handoff_gen5
>>>
>>> +${out_dir}/create_handoff_gen5 > ${output_file}
>>>
>>> +
>>>
>>> +# TODO: remove tmp file:
>>>
>>> +#rm $${out_dir}/create_handoff_gen5
>>>
>>>