* [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers
@ 2023-03-14 13:02 Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC* Ville Syrjala
` (12 more replies)
0 siblings, 13 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Do a bit of cleanup/reorganization around mostly plane
relatd stuff, and also add some more plane/pipe registers
that are useful for development/debugging.
Ville Syrjälä (9):
drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
drm/i915: s/PIPEMISC/PIPE_MISC/
drm/i915: Define more pipe timestamp registers
drm/i915: Program VLV/CHV PIPE_MSA_MISC register
drm/i915: Define skl+ universal plane SURFLIVE registers
drm/i915: Define vlv/chv sprite plane SURFLIVE registers
drm/i915: Clean up skl+ plane alpha bits
drm/i915: Relocate intel_plane_check_src_coordinates()
drm/i915: Extract intel_sprite_uapi.c
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 1 -
drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
drivers/gpu/drm/i915/display/intel_display.c | 59 +++---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 183 ------------------
.../gpu/drm/i915/display/intel_sprite_uapi.c | 127 ++++++++++++
.../gpu/drm/i915/display/intel_sprite_uapi.h | 15 ++
.../drm/i915/display/skl_universal_plane.c | 1 -
drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 77 ++++++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +-
15 files changed, 295 insertions(+), 243 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_uapi.c
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_uapi.h
--
2.39.2
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 2/9] drm/i915: s/PIPEMISC/PIPE_MISC/ Ville Syrjala
` (11 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The PIPE_MISC registers don't exist on pre-bdw hardware,
so there is no point in using pipe_offsets[] for them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9db6b3f06a74..aff3f4365b97 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3519,14 +3519,14 @@
#define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
#define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
#define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
-#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
+#define PIPEMISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
#define _PIPE_MISC2_A 0x7002C
#define _PIPE_MISC2_B 0x7102C
#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
-#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A)
+#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
/* Skylake+ pipe bottom (background) color */
#define _SKL_BOTTOM_COLOR_A 0x70034
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/9] drm/i915: s/PIPEMISC/PIPE_MISC/
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC* Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers Ville Syrjala
` (10 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
This PIPEMISC vs. PIPE_MISC inconsitency is ugly. Unify
the naming (PIPE_MISC is also what bspec has always called it).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++++----------
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 34 ++++++------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +--
6 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 50dcaa895854..4ff10b00ffbd 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1500,7 +1500,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
- pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
+ pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
/* Get the details on which TE should be enabled */
if (is_cmd_mode(intel_dsi))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 410c84fd905c..d95817288966 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -131,7 +131,7 @@
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
-static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
+static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
/* returns HPLL frequency in kHz */
@@ -1793,7 +1793,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_set_pipe_src_size(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(new_crtc_state);
+ bdw_set_pipe_misc(new_crtc_state);
if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
!transcoder_is_dsi(cpu_transcoder))
@@ -3074,20 +3074,20 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
}
static enum intel_output_format
-bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
+bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
- tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
+ tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
- if (tmp & PIPEMISC_YUV420_ENABLE) {
+ if (tmp & PIPE_MISC_YUV420_ENABLE) {
/* We support 4:2:0 in full blend mode only */
drm_WARN_ON(&dev_priv->drm,
- (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
+ (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
return INTEL_OUTPUT_FORMAT_YCBCR420;
- } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
+ } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
return INTEL_OUTPUT_FORMAT_YCBCR444;
} else {
return INTEL_OUTPUT_FORMAT_RGB;
@@ -3330,7 +3330,7 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
}
-static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
+static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -3338,18 +3338,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
switch (crtc_state->pipe_bpp) {
case 18:
- val |= PIPEMISC_BPC_6;
+ val |= PIPE_MISC_BPC_6;
break;
case 24:
- val |= PIPEMISC_BPC_8;
+ val |= PIPE_MISC_BPC_8;
break;
case 30:
- val |= PIPEMISC_BPC_10;
+ val |= PIPE_MISC_BPC_10;
break;
case 36:
/* Port output 12BPC defined for ADLP+ */
if (DISPLAY_VER(dev_priv) > 12)
- val |= PIPEMISC_BPC_12_ADLP;
+ val |= PIPE_MISC_BPC_12_ADLP;
break;
default:
MISSING_CASE(crtc_state->pipe_bpp);
@@ -3357,38 +3357,38 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
}
if (crtc_state->dither)
- val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
+ val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
- val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
+ val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- val |= PIPEMISC_YUV420_ENABLE |
- PIPEMISC_YUV420_MODE_FULL_BLEND;
+ val |= PIPE_MISC_YUV420_ENABLE |
+ PIPE_MISC_YUV420_MODE_FULL_BLEND;
if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
- val |= PIPEMISC_HDR_MODE_PRECISION;
+ val |= PIPE_MISC_HDR_MODE_PRECISION;
if (DISPLAY_VER(dev_priv) >= 12)
- val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
+ val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
- intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
+ intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
}
-int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
+int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
- tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
+ tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
- switch (tmp & PIPEMISC_BPC_MASK) {
- case PIPEMISC_BPC_6:
+ switch (tmp & PIPE_MISC_BPC_MASK) {
+ case PIPE_MISC_BPC_6:
return 18;
- case PIPEMISC_BPC_8:
+ case PIPE_MISC_BPC_8:
return 24;
- case PIPEMISC_BPC_10:
+ case PIPE_MISC_BPC_10:
return 30;
/*
* PORT OUTPUT 12 BPC defined for ADLP+.
@@ -3400,7 +3400,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
* on older platforms, need to find a workaround for 12 BPC
* MIPI DSI HW readout.
*/
- case PIPEMISC_BPC_12_ADLP:
+ case PIPE_MISC_BPC_12_ADLP:
if (DISPLAY_VER(dev_priv) > 12)
return 36;
fallthrough;
@@ -3981,7 +3981,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
} else {
pipe_config->output_format =
- bdw_get_pipemisc_output_format(crtc);
+ bdw_get_pipe_misc_output_format(crtc);
}
pipe_config->gamma_mode = intel_de_read(dev_priv,
@@ -6971,7 +6971,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
intel_color_commit_arm(new_crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(new_crtc_state);
+ bdw_set_pipe_misc(new_crtc_state);
if (intel_crtc_needs_fastset(new_crtc_state))
intel_pipe_fastset(old_crtc_state, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 50285fb4fcf5..beef930ebfbb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -511,7 +511,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
-int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
+int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 8d2e6e151ba0..028965ab442d 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1072,7 +1072,7 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
bpp = mipi_dsi_pixel_format_to_bpp(
pixel_format_from_register_bits(fmt));
- pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
+ pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
/* Enable Frame time stamo based scanline reporting */
pipe_config->mode_flags |=
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aff3f4365b97..a383397ebeca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3497,29 +3497,29 @@
#define _PIPE_MISC_A 0x70030
#define _PIPE_MISC_B 0x71030
-#define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
-#define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
-#define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
-#define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
-#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
+#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
+#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
+#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
+#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
+#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
/*
* For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
* valid values of: 6, 8, 10 BPC.
* ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
* 6, 8, 10, 12 BPC.
*/
-#define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
-#define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
-#define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
-#define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
-#define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
-#define PIPEMISC_DITHER_ENABLE REG_BIT(4)
-#define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
-#define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)
-#define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)
-#define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)
-#define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)
-#define PIPEMISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
+#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
+#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
+#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
+#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
+#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
+#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
+#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
+#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
+#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
+#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
+#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
#define _PIPE_MISC2_A 0x7002C
#define _PIPE_MISC2_B 0x7102C
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 2b3fe469b360..091743e32e17 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -789,9 +789,9 @@ static int iterate_bdw_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_RING_D(RING_REG);
#undef RING_REG
- MMIO_D(PIPEMISC(PIPE_A));
- MMIO_D(PIPEMISC(PIPE_B));
- MMIO_D(PIPEMISC(PIPE_C));
+ MMIO_D(PIPE_MISC(PIPE_A));
+ MMIO_D(PIPE_MISC(PIPE_B));
+ MMIO_D(PIPE_MISC(PIPE_C));
MMIO_D(_MMIO(0x1c1d0));
MMIO_D(GEN6_MBCUNIT_SNPCR);
MMIO_D(GEN7_MISCCPCTL);
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC* Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 2/9] drm/i915: s/PIPEMISC/PIPE_MISC/ Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-16 8:43 ` Hogander, Jouni
2023-03-14 13:02 ` [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register Ville Syrjala
` (9 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add definitions for various pipe timestamp registers:
- frame timestamp (last start of vblank) (g4x+), already had this defined
- flip timestamp (when SURF was last written) (g4x+)
- flipdone timestamp (when last flipdone was signalled) (tgl+)
Note that on pre-tgl the flip related timestamps are only updated
for primary plane flips, but on tgl+ we can select which plane
updates them (via PIPE_MISC2). Let's define those related bits
as well.
Curiously VLV/CHV do not have the frame/flip timestamp registers,
despite all the other related registers being inherited from g4x.
This means we can get rid of the pipe_offsets[] usage for these,
and thus the implicit dev_priv is gone as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a383397ebeca..66b6f451b80a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3526,6 +3526,8 @@
#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
+#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
+#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
/* Skylake+ pipe bottom (background) color */
@@ -7545,9 +7547,23 @@ enum skl_power_gate {
#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
+/* g4x+, except vlv/chv! */
#define _PIPE_FRMTMSTMP_A 0x70048
+#define _PIPE_FRMTMSTMP_B 0x71048
#define PIPE_FRMTMSTMP(pipe) \
- _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
+ _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
+
+/* g4x+, except vlv/chv! */
+#define _PIPE_FLIPTMSTMP_A 0x7004C
+#define _PIPE_FLIPTMSTMP_B 0x7104C
+#define PIPE_FLIPTMSTMP(pipe) \
+ _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
+
+/* tgl+ */
+#define _PIPE_FLIPDONETMSTMP_A 0x70054
+#define _PIPE_FLIPDONETMSTMP_B 0x71054
+#define PIPE_FLIPDONETIMSTMP(pipe) \
+ _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
#define GGC _MMIO(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (2 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-16 8:55 ` Hogander, Jouni
2023-03-14 13:02 ` [Intel-gfx] [PATCH 5/9] drm/i915: Define skl+ universal plane SURFLIVE registers Ville Syrjala
` (8 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VLV/CHV have an extra register to configure some stereo3d
signalling details via DP MSA. Make sure we reset that
register to zero (since we don't do any stereo3d stuff).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d95817288966..7b371d2746b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2139,6 +2139,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
intel_set_pipe_src_size(new_crtc_state);
+ intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
+
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 66b6f451b80a..8f301bf4e2b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7565,6 +7565,12 @@ enum skl_power_gate {
#define PIPE_FLIPDONETIMSTMP(pipe) \
_MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
+#define _VLV_PIPE_MSA_MISC_A 0x70048
+#define VLV_PIPE_MSA_MISC(pipe) \
+ _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
+#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
+#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
+
#define GGC _MMIO(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
#define GGMS_MASK REG_GENMASK(7, 6)
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 5/9] drm/i915: Define skl+ universal plane SURFLIVE registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (3 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite " Ville Syrjala
` (7 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add the definitions for the skl+ univerals plane SURFLIVE
registers. Despite not being used for anything real
these came in suprisingly handy during some DSB debugging
recently, so having the defines around can be useful.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f301bf4e2b6..a2b4af711e6d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4592,6 +4592,8 @@
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define _PLANE_SURFLIVE_1_A 0x701ac
+#define _PLANE_SURFLIVE_2_A 0x702ac
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_AUX_DIST_1_A 0x701c0
@@ -4776,6 +4778,13 @@
#define PLANE_KEYMAX(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+#define _PLANE_SURFLIVE_1_B 0x711ac
+#define _PLANE_SURFLIVE_2_B 0x712ac
+#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
+#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
+#define PLANE_SURFLIVE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
+
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite plane SURFLIVE registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (4 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 5/9] drm/i915: Define skl+ universal plane SURFLIVE registers Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-16 9:12 ` Hogander, Jouni
2023-03-14 13:02 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up skl+ plane alpha bits Ville Syrjala
` (6 subsequent siblings)
12 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Might as well complete the SURFLIVE register definitions
for all platforms/plane types. We are only missing the
VLV/CHV sprite planes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2b4af711e6d..e908959dba4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4394,6 +4394,7 @@
#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
+#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
@@ -4417,6 +4418,7 @@
#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
+#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
@@ -4437,6 +4439,7 @@
#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 7/9] drm/i915: Clean up skl+ plane alpha bits
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (5 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite " Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 8/9] drm/i915: Relocate intel_plane_check_src_coordinates() Ville Syrjala
` (5 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert a few more skl+ plane registers to REG_BIT() & co.
Somehow thse were missed during the earlier cleanup.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e908959dba4a..334e96d45c8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4591,10 +4591,11 @@
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYMSK_1_A 0x70198
#define _PLANE_KEYMSK_2_A 0x70298
-#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31)
+#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
#define _PLANE_KEYMAX_1_A 0x701a0
#define _PLANE_KEYMAX_2_A 0x702a0
-#define PLANE_KEYMAX_ALPHA(a) ((a) << 24)
+#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
+#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
#define _PLANE_SURFLIVE_1_A 0x701ac
#define _PLANE_SURFLIVE_2_A 0x702ac
#define _PLANE_CC_VAL_1_A 0x701b4
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 8/9] drm/i915: Relocate intel_plane_check_src_coordinates()
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (6 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up skl+ plane alpha bits Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 9/9] drm/i915: Extract intel_sprite_uapi.c Ville Syrjala
` (4 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_plane_check_src_coordinates() from the pre-skl sprite
plane specific code to a more suitable place for common plane code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 60 ++++++++++++++++++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 1 -
drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers/gpu/drm/i915/display/intel_sprite.c | 58 ------------------
.../drm/i915/display/skl_universal_plane.c | 1 -
7 files changed, 60 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 719a60e278f3..40de9f0f171b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -32,6 +32,7 @@
*/
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
#include <drm/drm_fourcc.h>
#include "i915_config.h"
@@ -42,7 +43,6 @@
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_fb_pin.h"
-#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_watermark.h"
@@ -940,6 +940,64 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
return 0;
}
+int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct drm_rect *src = &plane_state->uapi.src;
+ u32 src_x, src_y, src_w, src_h, hsub, vsub;
+ bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
+
+ /*
+ * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
+ * abuses hsub/vsub so we can't use them here. But as they
+ * are limited to 32bpp RGB formats we don't actually need
+ * to check anything.
+ */
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
+ return 0;
+
+ /*
+ * Hardware doesn't handle subpixel coordinates.
+ * Adjust to (macro)pixel boundary, but be careful not to
+ * increase the source viewport size, because that could
+ * push the downscaling factor out of bounds.
+ */
+ src_x = src->x1 >> 16;
+ src_w = drm_rect_width(src) >> 16;
+ src_y = src->y1 >> 16;
+ src_h = drm_rect_height(src) >> 16;
+
+ drm_rect_init(src, src_x << 16, src_y << 16,
+ src_w << 16, src_h << 16);
+
+ if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
+ hsub = 2;
+ vsub = 2;
+ } else {
+ hsub = fb->format->hsub;
+ vsub = fb->format->vsub;
+ }
+
+ if (rotated)
+ hsub = vsub = max(hsub, vsub);
+
+ if (src_x % hsub || src_w % hsub) {
+ drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
+ src_x, src_w, hsub, str_yes_no(rotated));
+ return -EINVAL;
+ }
+
+ if (src_y % vsub || src_h % vsub) {
+ drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
+ src_y, src_h, vsub, str_yes_no(rotated));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
/**
* intel_prepare_plane_fb - Prepare fb for usage on plane
* @_plane: drm plane to prepare for
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 74b6d3b169a7..191dad0efc8e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -62,6 +62,7 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
struct intel_crtc_state *crtc_state,
int min_scale, int max_scale,
bool can_position);
+int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
void intel_plane_helper_add(struct intel_plane *plane);
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index c3173c0c2068..31bef0427377 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -21,7 +21,6 @@
#include "intel_fb_pin.h"
#include "intel_frontbuffer.h"
#include "intel_psr.h"
-#include "intel_sprite.h"
#include "skl_watermark.h"
/* Cursor formats */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0950bcfea4c0..fe8d6f3e9e2f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -65,7 +65,6 @@
#include "intel_psr.h"
#include "intel_quirks.h"
#include "intel_snps_phy.h"
-#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vdsc_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7b371d2746b5..8a6884571843 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -111,7 +111,6 @@
#include "intel_quirks.h"
#include "intel_sdvo.h"
#include "intel_snps_phy.h"
-#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_tv.h"
#include "intel_vblank.h"
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index a16e56a60c30..3563fecee838 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -54,64 +54,6 @@
#include "intel_sprite.h"
#include "intel_vrr.h"
-int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
-{
- struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
- struct drm_rect *src = &plane_state->uapi.src;
- u32 src_x, src_y, src_w, src_h, hsub, vsub;
- bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
-
- /*
- * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
- * abuses hsub/vsub so we can't use them here. But as they
- * are limited to 32bpp RGB formats we don't actually need
- * to check anything.
- */
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
- return 0;
-
- /*
- * Hardware doesn't handle subpixel coordinates.
- * Adjust to (macro)pixel boundary, but be careful not to
- * increase the source viewport size, because that could
- * push the downscaling factor out of bounds.
- */
- src_x = src->x1 >> 16;
- src_w = drm_rect_width(src) >> 16;
- src_y = src->y1 >> 16;
- src_h = drm_rect_height(src) >> 16;
-
- drm_rect_init(src, src_x << 16, src_y << 16,
- src_w << 16, src_h << 16);
-
- if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
- hsub = 2;
- vsub = 2;
- } else {
- hsub = fb->format->hsub;
- vsub = fb->format->vsub;
- }
-
- if (rotated)
- hsub = vsub = max(hsub, vsub);
-
- if (src_x % hsub || src_w % hsub) {
- drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
- src_x, src_w, hsub, str_yes_no(rotated));
- return -EINVAL;
- }
-
- if (src_y % vsub || src_h % vsub) {
- drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
- src_y, src_h, vsub, str_yes_no(rotated));
- return -EINVAL;
- }
-
- return 0;
-}
-
static void i9xx_plane_linear_gamma(u16 gamma[8])
{
/* The points are not evenly spaced. */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ce55b8f09301..fd0065a46ec5 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -17,7 +17,6 @@
#include "intel_fb.h"
#include "intel_fbc.h"
#include "intel_psr.h"
-#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 9/9] drm/i915: Extract intel_sprite_uapi.c
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (7 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 8/9] drm/i915: Relocate intel_plane_check_src_coordinates() Ville Syrjala
@ 2023-03-14 13:02 ` Ville Syrjala
2023-03-14 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cleanups and extra registers Patchwork
` (3 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjala @ 2023-03-14 13:02 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the sprite colorkey ioctl handler to its own file
so that intel_sprite.c becomes all about the low level
details of pre-skl sprite planes.
And drop a bunch of unnecessary includes while at it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_sprite.c | 125 -----------------
.../gpu/drm/i915/display/intel_sprite_uapi.c | 127 ++++++++++++++++++
.../gpu/drm/i915/display/intel_sprite_uapi.h | 15 +++
4 files changed, 143 insertions(+), 125 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_uapi.c
create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_uapi.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8e46f57e4569..a59937b2b431 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -267,6 +267,7 @@ i915-y += \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
+ display/intel_sprite_uapi.o \
display/intel_tc.o \
display/intel_vblank.o \
display/intel_vga.o \
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 3563fecee838..25034bbf1445 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -32,27 +32,20 @@
#include <linux/string_helpers.h>
-#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_blend.h>
#include <drm/drm_color_mgmt.h>
-#include <drm/drm_crtc.h>
-#include <drm/drm_damage_helper.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_rect.h>
#include "i915_drv.h"
#include "i915_reg.h"
-#include "i915_vgpu.h"
#include "i9xx_plane.h"
#include "intel_atomic_plane.h"
-#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_fb.h"
-#include "intel_frontbuffer.h"
#include "intel_sprite.h"
-#include "intel_vrr.h"
static void i9xx_plane_linear_gamma(u16 gamma[8])
{
@@ -1391,124 +1384,6 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
-static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
-{
- return DISPLAY_VER(dev_priv) >= 9;
-}
-
-static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
- const struct drm_intel_sprite_colorkey *set)
-{
- struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
-
- *key = *set;
-
- /*
- * We want src key enabled on the
- * sprite and not on the primary.
- */
- if (plane->id == PLANE_PRIMARY &&
- set->flags & I915_SET_COLORKEY_SOURCE)
- key->flags = 0;
-
- /*
- * On SKL+ we want dst key enabled on
- * the primary and not on the sprite.
- */
- if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
- set->flags & I915_SET_COLORKEY_DESTINATION)
- key->flags = 0;
-}
-
-int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_intel_sprite_colorkey *set = data;
- struct drm_plane *plane;
- struct drm_plane_state *plane_state;
- struct drm_atomic_state *state;
- struct drm_modeset_acquire_ctx ctx;
- int ret = 0;
-
- /* ignore the pointless "none" flag */
- set->flags &= ~I915_SET_COLORKEY_NONE;
-
- if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
- return -EINVAL;
-
- /* Make sure we don't try to enable both src & dest simultaneously */
- if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
- return -EINVAL;
-
- if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- set->flags & I915_SET_COLORKEY_DESTINATION)
- return -EINVAL;
-
- plane = drm_plane_find(dev, file_priv, set->plane_id);
- if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
- return -ENOENT;
-
- /*
- * SKL+ only plane 2 can do destination keying against plane 1.
- * Also multiple planes can't do destination keying on the same
- * pipe simultaneously.
- */
- if (DISPLAY_VER(dev_priv) >= 9 &&
- to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
- set->flags & I915_SET_COLORKEY_DESTINATION)
- return -EINVAL;
-
- drm_modeset_acquire_init(&ctx, 0);
-
- state = drm_atomic_state_alloc(plane->dev);
- if (!state) {
- ret = -ENOMEM;
- goto out;
- }
- state->acquire_ctx = &ctx;
-
- while (1) {
- plane_state = drm_atomic_get_plane_state(state, plane);
- ret = PTR_ERR_OR_ZERO(plane_state);
- if (!ret)
- intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
-
- /*
- * On some platforms we have to configure
- * the dst colorkey on the primary plane.
- */
- if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
- struct intel_crtc *crtc =
- intel_crtc_for_pipe(dev_priv,
- to_intel_plane(plane)->pipe);
-
- plane_state = drm_atomic_get_plane_state(state,
- crtc->base.primary);
- ret = PTR_ERR_OR_ZERO(plane_state);
- if (!ret)
- intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
- }
-
- if (!ret)
- ret = drm_atomic_commit(state);
-
- if (ret != -EDEADLK)
- break;
-
- drm_atomic_state_clear(state);
- drm_modeset_backoff(&ctx);
- }
-
- drm_atomic_state_put(state);
-out:
- drm_modeset_drop_locks(&ctx);
- drm_modeset_acquire_fini(&ctx);
- return ret;
-}
-
static const u32 g4x_sprite_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_YUYV,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
new file mode 100644
index 000000000000..70a391083751
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_crtc.h"
+#include "intel_display_types.h"
+#include "intel_sprite_uapi.h"
+
+static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
+{
+ return DISPLAY_VER(dev_priv) >= 9;
+}
+
+static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
+ const struct drm_intel_sprite_colorkey *set)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
+
+ *key = *set;
+
+ /*
+ * We want src key enabled on the
+ * sprite and not on the primary.
+ */
+ if (plane->id == PLANE_PRIMARY &&
+ set->flags & I915_SET_COLORKEY_SOURCE)
+ key->flags = 0;
+
+ /*
+ * On SKL+ we want dst key enabled on
+ * the primary and not on the sprite.
+ */
+ if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
+ set->flags & I915_SET_COLORKEY_DESTINATION)
+ key->flags = 0;
+}
+
+int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_intel_sprite_colorkey *set = data;
+ struct drm_plane *plane;
+ struct drm_plane_state *plane_state;
+ struct drm_atomic_state *state;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ /* ignore the pointless "none" flag */
+ set->flags &= ~I915_SET_COLORKEY_NONE;
+
+ if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
+ return -EINVAL;
+
+ /* Make sure we don't try to enable both src & dest simultaneously */
+ if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
+ return -EINVAL;
+
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ set->flags & I915_SET_COLORKEY_DESTINATION)
+ return -EINVAL;
+
+ plane = drm_plane_find(dev, file_priv, set->plane_id);
+ if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
+ return -ENOENT;
+
+ /*
+ * SKL+ only plane 2 can do destination keying against plane 1.
+ * Also multiple planes can't do destination keying on the same
+ * pipe simultaneously.
+ */
+ if (DISPLAY_VER(dev_priv) >= 9 &&
+ to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
+ set->flags & I915_SET_COLORKEY_DESTINATION)
+ return -EINVAL;
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+ state = drm_atomic_state_alloc(plane->dev);
+ if (!state) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ state->acquire_ctx = &ctx;
+
+ while (1) {
+ plane_state = drm_atomic_get_plane_state(state, plane);
+ ret = PTR_ERR_OR_ZERO(plane_state);
+ if (!ret)
+ intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
+
+ /*
+ * On some platforms we have to configure
+ * the dst colorkey on the primary plane.
+ */
+ if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
+ struct intel_crtc *crtc =
+ intel_crtc_for_pipe(dev_priv,
+ to_intel_plane(plane)->pipe);
+
+ plane_state = drm_atomic_get_plane_state(state,
+ crtc->base.primary);
+ ret = PTR_ERR_OR_ZERO(plane_state);
+ if (!ret)
+ intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
+ }
+
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret != -EDEADLK)
+ break;
+
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ }
+
+ drm_atomic_state_put(state);
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.h b/drivers/gpu/drm/i915/display/intel_sprite_uapi.h
new file mode 100644
index 000000000000..3eb50025acaf
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_SPRITE_UAPI_H__
+#define __INTEL_SPRITE_UAPI_H__
+
+struct drm_device;
+struct drm_file;
+
+int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+#endif /* __INTEL_SPRITE_UAPI_H__ */
--
2.39.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cleanups and extra registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (8 preceding siblings ...)
2023-03-14 13:02 ` [Intel-gfx] [PATCH 9/9] drm/i915: Extract intel_sprite_uapi.c Ville Syrjala
@ 2023-03-14 17:10 ` Patchwork
2023-03-14 17:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-03-14 17:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane cleanups and extra registers
URL : https://patchwork.freedesktop.org/series/115127/
State : warning
== Summary ==
Error: dim checkpatch failed
802cf3411ec1 drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
76f7c6ff785e drm/i915: s/PIPEMISC/PIPE_MISC/
4ab5b9c730d4 drm/i915: Define more pipe timestamp registers
-:35: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:3530:
+#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
total: 0 errors, 1 warnings, 0 checks, 32 lines checked
cb266ee1072d drm/i915: Program VLV/CHV PIPE_MSA_MISC register
1feeb0e1ba95 drm/i915: Define skl+ universal plane SURFLIVE registers
-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:4785:
+#define PLANE_SURFLIVE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
717e5e4e9f97 drm/i915: Define vlv/chv sprite plane SURFLIVE registers
-:39: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:4442:
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
total: 0 errors, 1 warnings, 0 checks, 21 lines checked
b130477a1347 drm/i915: Clean up skl+ plane alpha bits
fe9486538cff drm/i915: Relocate intel_plane_check_src_coordinates()
-:79: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#79: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:984:
+ hsub = vsub = max(hsub, vsub);
total: 0 errors, 0 warnings, 1 checks, 177 lines checked
820d0149b732 drm/i915: Extract intel_sprite_uapi.c
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:187: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#187:
new file mode 100644
-:251: WARNING:LONG_LINE: line length of 148 exceeds 100 columns
#251: FILE: drivers/gpu/drm/i915/display/intel_sprite_uapi.c:60:
+ if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
total: 0 errors, 2 warnings, 0 checks, 300 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane cleanups and extra registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (9 preceding siblings ...)
2023-03-14 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cleanups and extra registers Patchwork
@ 2023-03-14 17:30 ` Patchwork
2023-03-15 20:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-17 11:12 ` [Intel-gfx] [PATCH 0/9] " Hogander, Jouni
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-03-14 17:30 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4083 bytes --]
== Series Details ==
Series: drm/i915: Plane cleanups and extra registers
URL : https://patchwork.freedesktop.org/series/115127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12857 -> Patchwork_115127v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/index.html
Participating hosts (36 -> 35)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_115127v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: NOTRUN -> [ABORT][3] ([i915#4983])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-adlp-9: NOTRUN -> [SKIP][4] ([i915#7828])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/bat-adlp-9/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8109u: [DMESG-FAIL][5] ([i915#5334]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][7] ([i915#4983] / [i915#7694] / [i915#7911] / [i915#7981]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/bat-rpls-1/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/bat-rpls-1/igt@i915_selftest@live@requests.html
- bat-adlp-9: [ABORT][9] ([i915#7982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/bat-adlp-9/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/bat-adlp-9/igt@i915_selftest@live@requests.html
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
Build changes
-------------
* Linux: CI_DRM_12857 -> Patchwork_115127v1
CI-20190529: 20190529
CI_DRM_12857: 004fefbbf160569f80946d1e516d538b7ecb04f2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7194: d22d66efd6211a22d301649b63d58c8c293e0817 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115127v1: 004fefbbf160569f80946d1e516d538b7ecb04f2 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f886ede62a8c drm/i915: Extract intel_sprite_uapi.c
7b0463644a1e drm/i915: Relocate intel_plane_check_src_coordinates()
8c9ae51078bb drm/i915: Clean up skl+ plane alpha bits
3b4274d07ab8 drm/i915: Define vlv/chv sprite plane SURFLIVE registers
3da88e6aebe6 drm/i915: Define skl+ universal plane SURFLIVE registers
54a0ec993485 drm/i915: Program VLV/CHV PIPE_MSA_MISC register
3a6d7de044a4 drm/i915: Define more pipe timestamp registers
bb1554ca2a67 drm/i915: s/PIPEMISC/PIPE_MISC/
ca35eacdbc79 drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/index.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane cleanups and extra registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (10 preceding siblings ...)
2023-03-14 17:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-15 20:59 ` Patchwork
2023-03-17 11:12 ` [Intel-gfx] [PATCH 0/9] " Hogander, Jouni
12 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2023-03-15 20:59 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 22591 bytes --]
== Series Details ==
Series: drm/i915: Plane cleanups and extra registers
URL : https://patchwork.freedesktop.org/series/115127/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12857_full -> Patchwork_115127v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-tglu0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_115127v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@basic-s3-without-i915:
- {shard-tglu}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-1/igt@i915_suspend@basic-s3-without-i915.html
Known issues
------------
Here are the changes found in Patchwork_115127v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-apl4/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2346])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][6] -> [ABORT][7] ([i915#180])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][8] -> [DMESG-WARN][9] ([i915#180])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
#### Possible fixes ####
* igt@device_reset@unbind-reset-rebind:
- {shard-rkl}: [FAIL][10] ([i915#4778]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-5/igt@device_reset@unbind-reset-rebind.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-3/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][12] ([i915#7742]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-1/igt@drm_fdinfo@idle@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-2/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}: [FAIL][14] ([i915#6268]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-hang@bcs0:
- {shard-rkl}: [SKIP][16] ([i915#6252]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-3/igt@gem_ctx_persistence@engines-hang@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][18] ([i915#2846]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- {shard-rkl}: [FAIL][20] ([i915#2842]) -> [PASS][21] +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][22] ([i915#2842]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-3/igt@gem_exec_fair@basic-none-share@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][24] ([i915#2842]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-write-read:
- {shard-rkl}: [SKIP][26] ([i915#3281]) -> [PASS][27] +5 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-tglu}: [SKIP][28] ([i915#1850]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-9/igt@gem_mmap_wc@set-cache-level.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-4/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- {shard-rkl}: [SKIP][30] ([i915#3282]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gen9_exec_parse@bb-start-cmd:
- {shard-rkl}: [SKIP][32] ([i915#2527]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-6/igt@gen9_exec_parse@bb-start-cmd.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][34] ([i915#1397]) -> [PASS][35] +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp-stress.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_selftest@live@dmabuf:
- shard-apl: [DMESG-FAIL][36] ([i915#7562]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-apl2/igt@i915_selftest@live@dmabuf.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-apl4/igt@i915_selftest@live@dmabuf.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs:
- {shard-tglu}: [SKIP][38] ([i915#1845] / [i915#7651]) -> [PASS][39] +25 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-9/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-4/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][40] ([i915#4767]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fence_pin_leak:
- {shard-tglu}: [SKIP][42] ([fdo#109274] / [i915#1845]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-9/igt@kms_fence_pin_leak.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-4/igt@kms_fence_pin_leak.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- {shard-tglu}: [SKIP][44] ([i915#1849]) -> [PASS][45] +5 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-9/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- {shard-rkl}: [SKIP][46] ([i915#1849] / [i915#4098]) -> [PASS][47] +8 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-rte.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_psr@cursor_render:
- {shard-rkl}: [SKIP][48] ([i915#1072]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-1/igt@kms_psr@cursor_render.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@kms_rotation_crc@cursor-rotation-180:
- {shard-tglu}: [SKIP][50] ([i915#1845]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-9/igt@kms_rotation_crc@cursor-rotation-180.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-6/igt@kms_rotation_crc@cursor-rotation-180.html
* igt@kms_universal_plane@universal-plane-pipe-d-functional:
- {shard-tglu}: [SKIP][52] ([fdo#109274]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-tglu-9/igt@kms_universal_plane@universal-plane-pipe-d-functional.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-tglu-6/igt@kms_universal_plane@universal-plane-pipe-d-functional.html
* igt@kms_vblank@pipe-a-ts-continuation-idle:
- {shard-rkl}: [SKIP][54] ([i915#1845] / [i915#4098]) -> [PASS][55] +17 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-1/igt@kms_vblank@pipe-a-ts-continuation-idle.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-6/igt@kms_vblank@pipe-a-ts-continuation-idle.html
* igt@prime_self_import@basic-with_one_bo:
- {shard-rkl}: [SKIP][56] ([fdo#109315]) -> [PASS][57] +3 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-5/igt@prime_self_import@basic-with_one_bo.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-3/igt@prime_self_import@basic-with_one_bo.html
* igt@syncobj_timeline@wait-all-for-submit-delayed-submit:
- {shard-rkl}: [SKIP][58] ([i915#2575]) -> [PASS][59] +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12857/shard-rkl-5/igt@syncobj_timeline@wait-all-for-submit-delayed-submit.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/shard-rkl-3/igt@syncobj_timeline@wait-all-for-submit-delayed-submit.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7562]: https://gitlab.freedesktop.org/drm/intel/issues/7562
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8273]: https://gitlab.freedesktop.org/drm/intel/issues/8273
[i915#8282]: https://gitlab.freedesktop.org/drm/intel/issues/8282
Build changes
-------------
* Linux: CI_DRM_12857 -> Patchwork_115127v1
CI-20190529: 20190529
CI_DRM_12857: 004fefbbf160569f80946d1e516d538b7ecb04f2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7194: d22d66efd6211a22d301649b63d58c8c293e0817 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115127v1: 004fefbbf160569f80946d1e516d538b7ecb04f2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115127v1/index.html
[-- Attachment #2: Type: text/html, Size: 16189 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers
2023-03-14 13:02 ` [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers Ville Syrjala
@ 2023-03-16 8:43 ` Hogander, Jouni
2023-03-16 9:44 ` Ville Syrjälä
0 siblings, 1 reply; 20+ messages in thread
From: Hogander, Jouni @ 2023-03-16 8:43 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add definitions for various pipe timestamp registers:
> - frame timestamp (last start of vblank) (g4x+), already had this
> defined
> - flip timestamp (when SURF was last written) (g4x+)
> - flipdone timestamp (when last flipdone was signalled) (tgl+)
>
> Note that on pre-tgl the flip related timestamps are only updated
> for primary plane flips, but on tgl+ we can select which plane
> updates them (via PIPE_MISC2). Let's define those related bits
> as well.
>
> Curiously VLV/CHV do not have the frame/flip timestamp registers,
> despite all the other related registers being inherited from g4x.
> This means we can get rid of the pipe_offsets[] usage for these,
> and thus the implicit dev_priv is gone as well.
According to bspec these exist in VLV (Bspec: 8264, 8261) ?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index a383397ebeca..66b6f451b80a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3526,6 +3526,8 @@
> #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
> #define
> PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE
> _COUNTER_MASK, 80)
> #define
> PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE
> _COUNTER_MASK, 20)
> +#define
> PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /*
> tgl+ */
> +#define
> PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC
> 2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
> #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe,
> _PIPE_MISC2_A, _PIPE_MISC2_B)
>
> /* Skylake+ pipe bottom (background) color */
> @@ -7545,9 +7547,23 @@ enum skl_power_gate {
> #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
> #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf
> << 12)
>
> +/* g4x+, except vlv/chv! */
> #define _PIPE_FRMTMSTMP_A 0x70048
> +#define _PIPE_FRMTMSTMP_B 0x71048
> #define PIPE_FRMTMSTMP(pipe) \
> - _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
> + _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
> +
> +/* g4x+, except vlv/chv! */
> +#define _PIPE_FLIPTMSTMP_A 0x7004C
> +#define _PIPE_FLIPTMSTMP_B 0x7104C
> +#define PIPE_FLIPTMSTMP(pipe) \
> + _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
> +
> +/* tgl+ */
This is mentioned in pre tgl documentation as well? (Bspec: 29591)
> +#define _PIPE_FLIPDONETMSTMP_A 0x70054
> +#define _PIPE_FLIPDONETMSTMP_B 0x71054
> +#define PIPE_FLIPDONETIMSTMP(pipe) \
> + _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> _PIPE_FLIPDONETMSTMP_B)
>
> #define GGC _MMIO(0x108040)
> #define GMS_MASK REG_GENMASK(15, 8)
BR,
Jouni Högander
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register
2023-03-14 13:02 ` [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register Ville Syrjala
@ 2023-03-16 8:55 ` Hogander, Jouni
2023-03-16 9:40 ` Ville Syrjälä
0 siblings, 1 reply; 20+ messages in thread
From: Hogander, Jouni @ 2023-03-16 8:55 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV/CHV have an extra register to configure some stereo3d
> signalling details via DP MSA. Make sure we reset that
> register to zero (since we don't do any stereo3d stuff).
Maybe add Bspec here? It took me a while to find this documentation.
Can you please check also Bspec: 8125 ?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d95817288966..7b371d2746b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2139,6 +2139,8 @@ static void valleyview_crtc_enable(struct
> intel_atomic_state *state,
>
> intel_set_pipe_src_size(new_crtc_state);
>
> + intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
> +
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> intel_de_write(dev_priv, CHV_BLEND(pipe),
> CHV_BLEND_LEGACY);
> intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 66b6f451b80a..8f301bf4e2b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7565,6 +7565,12 @@ enum skl_power_gate {
> #define PIPE_FLIPDONETIMSTMP(pipe) \
> _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> _PIPE_FLIPDONETMSTMP_B)
>
> +#define _VLV_PIPE_MSA_MISC_A 0x70048
> +#define VLV_PIPE_MSA_MISC(pipe) \
> + _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
> +#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
> +#define
> VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA
> MISC1 3:1 */
> +
> #define GGC _MMIO(0x108040)
> #define GMS_MASK REG_GENMASK(15, 8)
> #define GGMS_MASK REG_GENMASK(7, 6)
BR,
Jouni Högander
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite plane SURFLIVE registers
2023-03-14 13:02 ` [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite " Ville Syrjala
@ 2023-03-16 9:12 ` Hogander, Jouni
2023-03-16 9:41 ` Ville Syrjälä
0 siblings, 1 reply; 20+ messages in thread
From: Hogander, Jouni @ 2023-03-16 9:12 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Might as well complete the SURFLIVE register definitions
> for all platforms/plane types. We are only missing the
> VLV/CHV sprite planes.
Can you please point out Bspec you used for these definitions?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index a2b4af711e6d..e908959dba4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4394,6 +4394,7 @@
> #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
> #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> #define
> SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MA
> SK, (alpha))
> +#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
> #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
> #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
> #define
> SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /*
> u3.6 */
> @@ -4417,6 +4418,7 @@
> #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
> #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
> #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
> #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
> #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
> #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
> @@ -4437,6 +4439,7 @@
> #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> (plane_id), _SPATILEOFF, _SPBTILEOFF)
> #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
> #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> (plane_id), _SPACLRC0, _SPBCLRC0)
> #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> (plane_id), _SPACLRC1, _SPBCLRC1)
> #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe),
> (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
BR,
Jouni Högander
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register
2023-03-16 8:55 ` Hogander, Jouni
@ 2023-03-16 9:40 ` Ville Syrjälä
0 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjälä @ 2023-03-16 9:40 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
On Thu, Mar 16, 2023 at 08:55:01AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > VLV/CHV have an extra register to configure some stereo3d
> > signalling details via DP MSA. Make sure we reset that
> > register to zero (since we don't do any stereo3d stuff).
>
> Maybe add Bspec here? It took me a while to find this documentation.
Bpec + vlv/chv is lost cause. I never even bother looking there.
>
> Can you please check also Bspec: 8125 ?
That's the HSW+ MSA register. Different beast.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index d95817288966..7b371d2746b5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -2139,6 +2139,8 @@ static void valleyview_crtc_enable(struct
> > intel_atomic_state *state,
> >
> > intel_set_pipe_src_size(new_crtc_state);
> >
> > + intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
> > +
> > if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> > intel_de_write(dev_priv, CHV_BLEND(pipe),
> > CHV_BLEND_LEGACY);
> > intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 66b6f451b80a..8f301bf4e2b6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7565,6 +7565,12 @@ enum skl_power_gate {
> > #define PIPE_FLIPDONETIMSTMP(pipe) \
> > _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> > _PIPE_FLIPDONETMSTMP_B)
> >
> > +#define _VLV_PIPE_MSA_MISC_A 0x70048
> > +#define VLV_PIPE_MSA_MISC(pipe) \
> > + _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
> > +#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
> > +#define
> > VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA
> > MISC1 3:1 */
> > +
> > #define GGC _MMIO(0x108040)
> > #define GMS_MASK REG_GENMASK(15, 8)
> > #define GGMS_MASK REG_GENMASK(7, 6)
>
> BR,
>
> Jouni Högander
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite plane SURFLIVE registers
2023-03-16 9:12 ` Hogander, Jouni
@ 2023-03-16 9:41 ` Ville Syrjälä
0 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjälä @ 2023-03-16 9:41 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
On Thu, Mar 16, 2023 at 09:12:00AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Might as well complete the SURFLIVE register definitions
> > for all platforms/plane types. We are only missing the
> > VLV/CHV sprite planes.
>
> Can you please point out Bspec you used for these definitions?
For vlv/chv you need magic offline docs.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a2b4af711e6d..e908959dba4a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4394,6 +4394,7 @@
> > #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
> > #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> > #define
> > SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MA
> > SK, (alpha))
> > +#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
> > #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
> > #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
> > #define
> > SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /*
> > u3.6 */
> > @@ -4417,6 +4418,7 @@
> > #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
> > #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
> > #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> > +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
> > #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
> > #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
> > #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
> > @@ -4437,6 +4439,7 @@
> > #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> > (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> > #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> > (plane_id), _SPATILEOFF, _SPBTILEOFF)
> > #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> > (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> > +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> > (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
> > #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> > (plane_id), _SPACLRC0, _SPBCLRC0)
> > #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe),
> > (plane_id), _SPACLRC1, _SPBCLRC1)
> > #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe),
> > (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
>
> BR,
>
> Jouni Högander
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers
2023-03-16 8:43 ` Hogander, Jouni
@ 2023-03-16 9:44 ` Ville Syrjälä
0 siblings, 0 replies; 20+ messages in thread
From: Ville Syrjälä @ 2023-03-16 9:44 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
On Thu, Mar 16, 2023 at 08:43:12AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add definitions for various pipe timestamp registers:
> > - frame timestamp (last start of vblank) (g4x+), already had this
> > defined
> > - flip timestamp (when SURF was last written) (g4x+)
> > - flipdone timestamp (when last flipdone was signalled) (tgl+)
> >
> > Note that on pre-tgl the flip related timestamps are only updated
> > for primary plane flips, but on tgl+ we can select which plane
> > updates them (via PIPE_MISC2). Let's define those related bits
> > as well.
> >
> > Curiously VLV/CHV do not have the frame/flip timestamp registers,
> > despite all the other related registers being inherited from g4x.
> > This means we can get rid of the pipe_offsets[] usage for these,
> > and thus the implicit dev_priv is gone as well.
>
> According to bspec these exist in VLV (Bspec: 8264, 8261) ?
It is lying to you.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++++++++-
> > 1 file changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a383397ebeca..66b6f451b80a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3526,6 +3526,8 @@
> > #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
> > #define
> > PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE
> > _COUNTER_MASK, 80)
> > #define
> > PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE
> > _COUNTER_MASK, 20)
> > +#define
> > PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /*
> > tgl+ */
> > +#define
> > PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC
> > 2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
> > #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe,
> > _PIPE_MISC2_A, _PIPE_MISC2_B)
> >
> > /* Skylake+ pipe bottom (background) color */
> > @@ -7545,9 +7547,23 @@ enum skl_power_gate {
> > #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
> > #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf
> > << 12)
> >
> > +/* g4x+, except vlv/chv! */
> > #define _PIPE_FRMTMSTMP_A 0x70048
> > +#define _PIPE_FRMTMSTMP_B 0x71048
> > #define PIPE_FRMTMSTMP(pipe) \
> > - _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
> > + _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
> > +
> > +/* g4x+, except vlv/chv! */
> > +#define _PIPE_FLIPTMSTMP_A 0x7004C
> > +#define _PIPE_FLIPTMSTMP_B 0x7104C
> > +#define PIPE_FLIPTMSTMP(pipe) \
> > + _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
> > +
> > +/* tgl+ */
>
> This is mentioned in pre tgl documentation as well? (Bspec: 29591)
I think that is only a leftover artifact from before the
gen12+ split. If you set the filter to ICLLP (or earlier)
the register should disappear for you.
>
> > +#define _PIPE_FLIPDONETMSTMP_A 0x70054
> > +#define _PIPE_FLIPDONETMSTMP_B 0x71054
> > +#define PIPE_FLIPDONETIMSTMP(pipe) \
> > + _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A,
> > _PIPE_FLIPDONETMSTMP_B)
> >
> > #define GGC _MMIO(0x108040)
> > #define GMS_MASK REG_GENMASK(15, 8)
>
> BR,
>
> Jouni Högander
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
` (11 preceding siblings ...)
2023-03-15 20:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-03-17 11:12 ` Hogander, Jouni
12 siblings, 0 replies; 20+ messages in thread
From: Hogander, Jouni @ 2023-03-17 11:12 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
As you have checked my comments against documentation you have for
older platforms (obviously better than what I have):
for the whole set:
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
BR,
Jouni Högander
On Tue, 2023-03-14 at 15:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Do a bit of cleanup/reorganization around mostly plane
> relatd stuff, and also add some more plane/pipe registers
> that are useful for development/debugging.
>
> Ville Syrjälä (9):
> drm/i915: Stop using pipe_offsets[] for PIPE_MISC*
> drm/i915: s/PIPEMISC/PIPE_MISC/
> drm/i915: Define more pipe timestamp registers
> drm/i915: Program VLV/CHV PIPE_MSA_MISC register
> drm/i915: Define skl+ universal plane SURFLIVE registers
> drm/i915: Define vlv/chv sprite plane SURFLIVE registers
> drm/i915: Clean up skl+ plane alpha bits
> drm/i915: Relocate intel_plane_check_src_coordinates()
> drm/i915: Extract intel_sprite_uapi.c
>
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> .../gpu/drm/i915/display/intel_atomic_plane.c | 60 +++++-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 1 +
> drivers/gpu/drm/i915/display/intel_cursor.c | 1 -
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
> drivers/gpu/drm/i915/display/intel_display.c | 59 +++---
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 183 ----------------
> --
> .../gpu/drm/i915/display/intel_sprite_uapi.c | 127 ++++++++++++
> .../gpu/drm/i915/display/intel_sprite_uapi.h | 15 ++
> .../drm/i915/display/skl_universal_plane.c | 1 -
> drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 77 ++++++--
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +-
> 15 files changed, 295 insertions(+), 243 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_uapi.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_sprite_uapi.h
>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-03-17 11:12 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-14 13:02 [Intel-gfx] [PATCH 0/9] drm/i915: Plane cleanups and extra registers Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 1/9] drm/i915: Stop using pipe_offsets[] for PIPE_MISC* Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 2/9] drm/i915: s/PIPEMISC/PIPE_MISC/ Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 3/9] drm/i915: Define more pipe timestamp registers Ville Syrjala
2023-03-16 8:43 ` Hogander, Jouni
2023-03-16 9:44 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 4/9] drm/i915: Program VLV/CHV PIPE_MSA_MISC register Ville Syrjala
2023-03-16 8:55 ` Hogander, Jouni
2023-03-16 9:40 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 5/9] drm/i915: Define skl+ universal plane SURFLIVE registers Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 6/9] drm/i915: Define vlv/chv sprite " Ville Syrjala
2023-03-16 9:12 ` Hogander, Jouni
2023-03-16 9:41 ` Ville Syrjälä
2023-03-14 13:02 ` [Intel-gfx] [PATCH 7/9] drm/i915: Clean up skl+ plane alpha bits Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 8/9] drm/i915: Relocate intel_plane_check_src_coordinates() Ville Syrjala
2023-03-14 13:02 ` [Intel-gfx] [PATCH 9/9] drm/i915: Extract intel_sprite_uapi.c Ville Syrjala
2023-03-14 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane cleanups and extra registers Patchwork
2023-03-14 17:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-15 20:59 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-17 11:12 ` [Intel-gfx] [PATCH 0/9] " Hogander, Jouni
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