[PATCH] drm/amdgpu: change gfx8 ib test to use WB

[PATCH] drm/amdgpu: change gfx8 ib test to use WB

[Shirish S]

This patch is extends the usage of WB in
gfx8's ib test which was originally
implemented in the below upstream patch:
"ed9324a drm/amdgpu: change gfx9 ib test to use WB"

Signed-off-by: Shirish S <shirish.s@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 818874b..61452c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_ib ib;
 	struct dma_fence *f = NULL;
-	uint32_t scratch;
-	uint32_t tmp = 0;
+
+	unsigned int index;
+	uint64_t gpu_addr;
+	uint32_t tmp;
 	long r;
 
-	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	r = amdgpu_device_wb_get(adev, &index);
 	if (r) {
-		DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
+		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
-	WREG32(scratch, 0xCAFEDEAD);
+
+	gpu_addr = adev->wb.gpu_addr + (index * 4);
+	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 	memset(&ib, 0, sizeof(ib));
-	r = amdgpu_ib_get(adev, NULL, 256, &ib);
+	r = amdgpu_ib_get(adev, NULL, 16, &ib);
 	if (r) {
 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 		goto err1;
 	}
-	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
-	ib.ptr[2] = 0xDEADBEEF;
-	ib.length_dw = 3;
+	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+	ib.ptr[2] = lower_32_bits(gpu_addr);
+	ib.ptr[3] = upper_32_bits(gpu_addr);
+	ib.ptr[4] = 0xDEADBEEF;
+	ib.length_dw = 5;
 
 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 	if (r)
@@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 		goto err2;
 	}
-	tmp = RREG32(scratch);
+
+	tmp = adev->wb.wb[index];
 	if (tmp == 0xDEADBEEF) {
 		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 		r = 0;
 	} else {
-		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
-			  scratch, tmp);
+		DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 		r = -EINVAL;
 	}
+
 err2:
 	amdgpu_ib_free(adev, &ib, NULL);
 	dma_fence_put(f);
 err1:
-	amdgpu_gfx_scratch_free(adev, scratch);
+	amdgpu_device_wb_free(adev, index);
 	return r;
 }
 
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: change gfx8 ib test to use WB

[zhoucm1]

On 2018年06月08日 12:54, Shirish S wrote:
> This patch is extends the usage of WB in
> gfx8's ib test which was originally
> implemented in the below upstream patch:
> "ed9324a drm/amdgpu: change gfx9 ib test to use WB"
>
> Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35 +++++++++++++++++++++--------------
>   1 file changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 818874b..61452c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>   	struct amdgpu_device *adev = ring->adev;
>   	struct amdgpu_ib ib;
>   	struct dma_fence *f = NULL;
> -	uint32_t scratch;
> -	uint32_t tmp = 0;
> +
> +	unsigned int index;
> +	uint64_t gpu_addr;
> +	uint32_t tmp;
>   	long r;
>   
> -	r = amdgpu_gfx_scratch_get(adev, &scratch);
> +	r = amdgpu_device_wb_get(adev, &index);
>   	if (r) {
> -		DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
> +		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
>   		return r;
>   	}
> -	WREG32(scratch, 0xCAFEDEAD);
> +
> +	gpu_addr = adev->wb.gpu_addr + (index * 4);
> +	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
>   	memset(&ib, 0, sizeof(ib));
> -	r = amdgpu_ib_get(adev, NULL, 256, &ib);
> +	r = amdgpu_ib_get(adev, NULL, 16, &ib);
>   	if (r) {
>   		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
>   		goto err1;
>   	}
> -	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
> -	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
> -	ib.ptr[2] = 0xDEADBEEF;
> -	ib.length_dw = 3;
> +	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
> +	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
> +	ib.ptr[2] = lower_32_bits(gpu_addr);
> +	ib.ptr[3] = upper_32_bits(gpu_addr);
> +	ib.ptr[4] = 0xDEADBEEF;
> +	ib.length_dw = 5;
>   
>   	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
>   	if (r)
> @@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>   		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
>   		goto err2;
>   	}
> -	tmp = RREG32(scratch);
> +
> +	tmp = adev->wb.wb[index];
>   	if (tmp == 0xDEADBEEF) {
>   		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
>   		r = 0;
>   	} else {
> -		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
> -			  scratch, tmp);
> +		DRM_ERROR("ib test on ring %d failed\n", ring->idx);
>   		r = -EINVAL;
>   	}
> +
>   err2:
>   	amdgpu_ib_free(adev, &ib, NULL);
>   	dma_fence_put(f);
>   err1:
> -	amdgpu_gfx_scratch_free(adev, scratch);
> +	amdgpu_device_wb_free(adev, index);
>   	return r;
>   }
>   

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Re: [PATCH] drm/amdgpu: change gfx8 ib test to use WB

[Christian König]

Am 08.06.2018 um 07:23 schrieb zhoucm1:
>
>
> On 2018年06月08日 12:54, Shirish S wrote:
>> This patch is extends the usage of WB in
>> gfx8's ib test which was originally
>> implemented in the below upstream patch:
>> "ed9324a drm/amdgpu: change gfx9 ib test to use WB"

You could copy the commit message from ed9324a to better explain why we 
do it, but that is only nice to have.

>>
>> Signed-off-by: Shirish S <shirish.s@amd.com>
> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35 
>> +++++++++++++++++++++--------------
>>   1 file changed, 21 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index 818874b..61452c7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct 
>> amdgpu_ring *ring, long timeout)
>>       struct amdgpu_device *adev = ring->adev;
>>       struct amdgpu_ib ib;
>>       struct dma_fence *f = NULL;
>> -    uint32_t scratch;
>> -    uint32_t tmp = 0;
>> +
>> +    unsigned int index;
>> +    uint64_t gpu_addr;
>> +    uint32_t tmp;
>>       long r;
>>   -    r = amdgpu_gfx_scratch_get(adev, &scratch);
>> +    r = amdgpu_device_wb_get(adev, &index);
>>       if (r) {
>> -        DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
>> +        dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
>>           return r;
>>       }
>> -    WREG32(scratch, 0xCAFEDEAD);
>> +
>> +    gpu_addr = adev->wb.gpu_addr + (index * 4);
>> +    adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
>>       memset(&ib, 0, sizeof(ib));
>> -    r = amdgpu_ib_get(adev, NULL, 256, &ib);
>> +    r = amdgpu_ib_get(adev, NULL, 16, &ib);
>>       if (r) {
>>           DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
>>           goto err1;
>>       }
>> -    ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
>> -    ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
>> -    ib.ptr[2] = 0xDEADBEEF;
>> -    ib.length_dw = 3;
>> +    ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
>> +    ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
>> +    ib.ptr[2] = lower_32_bits(gpu_addr);
>> +    ib.ptr[3] = upper_32_bits(gpu_addr);
>> +    ib.ptr[4] = 0xDEADBEEF;
>> +    ib.length_dw = 5;
>>         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
>>       if (r)
>> @@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct 
>> amdgpu_ring *ring, long timeout)
>>           DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
>>           goto err2;
>>       }
>> -    tmp = RREG32(scratch);
>> +
>> +    tmp = adev->wb.wb[index];
>>       if (tmp == 0xDEADBEEF) {
>>           DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
>>           r = 0;
>>       } else {
>> -        DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
>> -              scratch, tmp);
>> +        DRM_ERROR("ib test on ring %d failed\n", ring->idx);
>>           r = -EINVAL;
>>       }
>> +
>>   err2:
>>       amdgpu_ib_free(adev, &ib, NULL);
>>       dma_fence_put(f);
>>   err1:
>> -    amdgpu_gfx_scratch_free(adev, scratch);
>> +    amdgpu_device_wb_free(adev, index);
>>       return r;
>>   }
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH] drm/amdgpu: change gfx8 ib test to use WB

[Christian König]

Am 08.06.2018 um 10:37 schrieb S, Shirish:
>
>
> On 6/8/2018 1:08 PM, Christian König wrote:
>> Am 08.06.2018 um 07:23 schrieb zhoucm1:
>>>
>>>
>>> On 2018年06月08日 12:54, Shirish S wrote:
>>>> This patch is extends the usage of WB in
>>>> gfx8's ib test which was originally
>>>> implemented in the below upstream patch:
>>>> "ed9324a drm/amdgpu: change gfx9 ib test to use WB"
>>
>> You could copy the commit message from ed9324a to better explain why 
>> we do it, but that is only nice to have.
>>
>>>>
>>>> Signed-off-by: Shirish S <shirish.s@amd.com>
>>> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
>>
>> Reviewed-by: Christian König <christian.koenig@amd.com>
>>
> Thanks Christian & david, shall re-send with the updated commit 
> message and RB's.

Since you already gathered RB's from two people and haven't made any 
function change (only extended the commit message a bit) you can also go 
ahead and commit it.

Regards,
Christian.

>
> Regards,
> Shirish S
>>>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35 
>>>> +++++++++++++++++++++--------------
>>>>   1 file changed, 21 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>>> index 818874b..61452c7 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>>> @@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct 
>>>> amdgpu_ring *ring, long timeout)
>>>>       struct amdgpu_device *adev = ring->adev;
>>>>       struct amdgpu_ib ib;
>>>>       struct dma_fence *f = NULL;
>>>> -    uint32_t scratch;
>>>> -    uint32_t tmp = 0;
>>>> +
>>>> +    unsigned int index;
>>>> +    uint64_t gpu_addr;
>>>> +    uint32_t tmp;
>>>>       long r;
>>>>   -    r = amdgpu_gfx_scratch_get(adev, &scratch);
>>>> +    r = amdgpu_device_wb_get(adev, &index);
>>>>       if (r) {
>>>> -        DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
>>>> +        dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
>>>>           return r;
>>>>       }
>>>> -    WREG32(scratch, 0xCAFEDEAD);
>>>> +
>>>> +    gpu_addr = adev->wb.gpu_addr + (index * 4);
>>>> +    adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
>>>>       memset(&ib, 0, sizeof(ib));
>>>> -    r = amdgpu_ib_get(adev, NULL, 256, &ib);
>>>> +    r = amdgpu_ib_get(adev, NULL, 16, &ib);
>>>>       if (r) {
>>>>           DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
>>>>           goto err1;
>>>>       }
>>>> -    ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
>>>> -    ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
>>>> -    ib.ptr[2] = 0xDEADBEEF;
>>>> -    ib.length_dw = 3;
>>>> +    ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
>>>> +    ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
>>>> +    ib.ptr[2] = lower_32_bits(gpu_addr);
>>>> +    ib.ptr[3] = upper_32_bits(gpu_addr);
>>>> +    ib.ptr[4] = 0xDEADBEEF;
>>>> +    ib.length_dw = 5;
>>>>         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
>>>>       if (r)
>>>> @@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct 
>>>> amdgpu_ring *ring, long timeout)
>>>>           DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
>>>>           goto err2;
>>>>       }
>>>> -    tmp = RREG32(scratch);
>>>> +
>>>> +    tmp = adev->wb.wb[index];
>>>>       if (tmp == 0xDEADBEEF) {
>>>>           DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
>>>>           r = 0;
>>>>       } else {
>>>> -        DRM_ERROR("amdgpu: ib test failed 
>>>> (scratch(0x%04X)=0x%08X)\n",
>>>> -              scratch, tmp);
>>>> +        DRM_ERROR("ib test on ring %d failed\n", ring->idx);
>>>>           r = -EINVAL;
>>>>       }
>>>> +
>>>>   err2:
>>>>       amdgpu_ib_free(adev, &ib, NULL);
>>>>       dma_fence_put(f);
>>>>   err1:
>>>> -    amdgpu_gfx_scratch_free(adev, scratch);
>>>> +    amdgpu_device_wb_free(adev, index);
>>>>       return r;
>>>>   }
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>

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Re: [PATCH] drm/amdgpu: change gfx8 ib test to use WB

[S, Shirish]

On 6/8/2018 1:08 PM, Christian König wrote:
> Am 08.06.2018 um 07:23 schrieb zhoucm1:
>>
>>
>> On 2018年06月08日 12:54, Shirish S wrote:
>>> This patch is extends the usage of WB in
>>> gfx8's ib test which was originally
>>> implemented in the below upstream patch:
>>> "ed9324a drm/amdgpu: change gfx9 ib test to use WB"
>
> You could copy the commit message from ed9324a to better explain why 
> we do it, but that is only nice to have.
>
>>>
>>> Signed-off-by: Shirish S <shirish.s@amd.com>
>> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
>
> Reviewed-by: Christian König <christian.koenig@amd.com>
>
Thanks Christian & david, shall re-send with the updated commit message 
and RB's.

Regards,
Shirish S
>>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35 
>>> +++++++++++++++++++++--------------
>>>   1 file changed, 21 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> index 818874b..61452c7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> @@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct 
>>> amdgpu_ring *ring, long timeout)
>>>       struct amdgpu_device *adev = ring->adev;
>>>       struct amdgpu_ib ib;
>>>       struct dma_fence *f = NULL;
>>> -    uint32_t scratch;
>>> -    uint32_t tmp = 0;
>>> +
>>> +    unsigned int index;
>>> +    uint64_t gpu_addr;
>>> +    uint32_t tmp;
>>>       long r;
>>>   -    r = amdgpu_gfx_scratch_get(adev, &scratch);
>>> +    r = amdgpu_device_wb_get(adev, &index);
>>>       if (r) {
>>> -        DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
>>> +        dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
>>>           return r;
>>>       }
>>> -    WREG32(scratch, 0xCAFEDEAD);
>>> +
>>> +    gpu_addr = adev->wb.gpu_addr + (index * 4);
>>> +    adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
>>>       memset(&ib, 0, sizeof(ib));
>>> -    r = amdgpu_ib_get(adev, NULL, 256, &ib);
>>> +    r = amdgpu_ib_get(adev, NULL, 16, &ib);
>>>       if (r) {
>>>           DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
>>>           goto err1;
>>>       }
>>> -    ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
>>> -    ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
>>> -    ib.ptr[2] = 0xDEADBEEF;
>>> -    ib.length_dw = 3;
>>> +    ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
>>> +    ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
>>> +    ib.ptr[2] = lower_32_bits(gpu_addr);
>>> +    ib.ptr[3] = upper_32_bits(gpu_addr);
>>> +    ib.ptr[4] = 0xDEADBEEF;
>>> +    ib.length_dw = 5;
>>>         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
>>>       if (r)
>>> @@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct 
>>> amdgpu_ring *ring, long timeout)
>>>           DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
>>>           goto err2;
>>>       }
>>> -    tmp = RREG32(scratch);
>>> +
>>> +    tmp = adev->wb.wb[index];
>>>       if (tmp == 0xDEADBEEF) {
>>>           DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
>>>           r = 0;
>>>       } else {
>>> -        DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
>>> -              scratch, tmp);
>>> +        DRM_ERROR("ib test on ring %d failed\n", ring->idx);
>>>           r = -EINVAL;
>>>       }
>>> +
>>>   err2:
>>>       amdgpu_ib_free(adev, &ib, NULL);
>>>       dma_fence_put(f);
>>>   err1:
>>> -    amdgpu_gfx_scratch_free(adev, scratch);
>>> +    amdgpu_device_wb_free(adev, index);
>>>       return r;
>>>   }
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>

-- 
Regards,
Shirish S

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[PATCH] drm/amdgpu: change gfx8 ib test to use WB

[Shirish S]

This patch is extends the usage of WB in
gfx8's ib test which was originally
implemented in the below upstream patch
"ed9324a drm/amdgpu: change gfx9 ib test to use WB"

For reference below are the reasons for switching
to WB:

1)Because when doing IB test we don't want to involve KIQ health
status affect, and since SCRATCH register access is go through
KIQ that way GFX IB test would failed due to KIQ fail.

2)acccessing SCRATCH register cost much more time than WB method
because SCRATCH register access runs through KIQ which at least could
begin after GPU world switch back to current Guest VF

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 818874b..61452c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_ib ib;
 	struct dma_fence *f = NULL;
-	uint32_t scratch;
-	uint32_t tmp = 0;
+
+	unsigned int index;
+	uint64_t gpu_addr;
+	uint32_t tmp;
 	long r;
 
-	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	r = amdgpu_device_wb_get(adev, &index);
 	if (r) {
-		DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
+		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 		return r;
 	}
-	WREG32(scratch, 0xCAFEDEAD);
+
+	gpu_addr = adev->wb.gpu_addr + (index * 4);
+	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 	memset(&ib, 0, sizeof(ib));
-	r = amdgpu_ib_get(adev, NULL, 256, &ib);
+	r = amdgpu_ib_get(adev, NULL, 16, &ib);
 	if (r) {
 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 		goto err1;
 	}
-	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-	ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
-	ib.ptr[2] = 0xDEADBEEF;
-	ib.length_dw = 3;
+	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+	ib.ptr[2] = lower_32_bits(gpu_addr);
+	ib.ptr[3] = upper_32_bits(gpu_addr);
+	ib.ptr[4] = 0xDEADBEEF;
+	ib.length_dw = 5;
 
 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 	if (r)
@@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 		goto err2;
 	}
-	tmp = RREG32(scratch);
+
+	tmp = adev->wb.wb[index];
 	if (tmp == 0xDEADBEEF) {
 		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 		r = 0;
 	} else {
-		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
-			  scratch, tmp);
+		DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 		r = -EINVAL;
 	}
+
 err2:
 	amdgpu_ib_free(adev, &ib, NULL);
 	dma_fence_put(f);
 err1:
-	amdgpu_gfx_scratch_free(adev, scratch);
+	amdgpu_device_wb_free(adev, index);
 	return r;
 }
 
-- 
2.7.4

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