* [PATCH] sdhci: zynqmp: Setting up clock frequency based on DT
@ 2021-11-18 12:03 Michal Simek
2021-11-19 17:16 ` Sean Anderson
0 siblings, 1 reply; 4+ messages in thread
From: Michal Simek @ 2021-11-18 12:03 UTC (permalink / raw)
To: u-boot, git; +Cc: Jaehoon Chung, Peng Fan
Using clock-frequency property to define desired clock speed for
controllers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/mmc/zynq_sdhci.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 5cea4c695e8d..ee87907939fe 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -58,6 +58,7 @@ struct arasan_sdhci_plat {
struct arasan_sdhci_priv {
struct sdhci_host *host;
struct arasan_sdhci_clk_data clk_data;
+ u32 frequency;
u8 deviceid;
u8 bank;
u8 no_1p8;
@@ -721,6 +722,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
return ret;
}
+ if (priv->frequency) {
+ ret = clk_set_rate(&clk, priv->frequency);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(dev, "failed to set clock rate\n");
+ return ret;
+ }
+ }
+
clock = clk_get_rate(&clk);
if (IS_ERR_VALUE(clock)) {
dev_err(dev, "failed to get rate\n");
@@ -804,6 +813,7 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
if (IS_ERR(priv->host->ioaddr))
return PTR_ERR(priv->host->ioaddr);
+ priv->frequency = dev_read_u32_default(dev, "clock-frequency", 0);
priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
--
2.33.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] sdhci: zynqmp: Setting up clock frequency based on DT
2021-11-18 12:03 [PATCH] sdhci: zynqmp: Setting up clock frequency based on DT Michal Simek
@ 2021-11-19 17:16 ` Sean Anderson
2021-11-22 15:31 ` Michal Simek
0 siblings, 1 reply; 4+ messages in thread
From: Sean Anderson @ 2021-11-19 17:16 UTC (permalink / raw)
To: Michal Simek, u-boot, git; +Cc: Jaehoon Chung, Peng Fan
On 11/18/21 7:03 AM, Michal Simek wrote:
> Using clock-frequency property to define desired clock speed for
> controllers.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> drivers/mmc/zynq_sdhci.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index 5cea4c695e8d..ee87907939fe 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -58,6 +58,7 @@ struct arasan_sdhci_plat {
> struct arasan_sdhci_priv {
> struct sdhci_host *host;
> struct arasan_sdhci_clk_data clk_data;
> + u32 frequency;
> u8 deviceid;
> u8 bank;
> u8 no_1p8;
> @@ -721,6 +722,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
> return ret;
> }
>
> + if (priv->frequency) {
> + ret = clk_set_rate(&clk, priv->frequency);
> + if (IS_ERR_VALUE(ret)) {
> + dev_err(dev, "failed to set clock rate\n");
> + return ret;
> + }
> + }
> +
> clock = clk_get_rate(&clk);
> if (IS_ERR_VALUE(clock)) {
> dev_err(dev, "failed to get rate\n");
> @@ -804,6 +813,7 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
> if (IS_ERR(priv->host->ioaddr))
> return PTR_ERR(priv->host->ioaddr);
>
> + priv->frequency = dev_read_u32_default(dev, "clock-frequency", 0);
> priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
> priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
> priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
>
Why not just assigned-clock-rates? Are there any existing users with just clock-frequency?
--Sean
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] sdhci: zynqmp: Setting up clock frequency based on DT
2021-11-19 17:16 ` Sean Anderson
@ 2021-11-22 15:31 ` Michal Simek
2021-11-29 15:55 ` Michal Simek
0 siblings, 1 reply; 4+ messages in thread
From: Michal Simek @ 2021-11-22 15:31 UTC (permalink / raw)
To: Sean Anderson, Michal Simek, u-boot, git; +Cc: Jaehoon Chung, Peng Fan
Hi,
On 11/19/21 18:16, Sean Anderson wrote:
>
>
> On 11/18/21 7:03 AM, Michal Simek wrote:
>> Using clock-frequency property to define desired clock speed for
>> controllers.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> drivers/mmc/zynq_sdhci.c | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
>> index 5cea4c695e8d..ee87907939fe 100644
>> --- a/drivers/mmc/zynq_sdhci.c
>> +++ b/drivers/mmc/zynq_sdhci.c
>> @@ -58,6 +58,7 @@ struct arasan_sdhci_plat {
>> struct arasan_sdhci_priv {
>> struct sdhci_host *host;
>> struct arasan_sdhci_clk_data clk_data;
>> + u32 frequency;
>> u8 deviceid;
>> u8 bank;
>> u8 no_1p8;
>> @@ -721,6 +722,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
>> return ret;
>> }
>> + if (priv->frequency) {
>> + ret = clk_set_rate(&clk, priv->frequency);
>> + if (IS_ERR_VALUE(ret)) {
>> + dev_err(dev, "failed to set clock rate\n");
>> + return ret;
>> + }
>> + }
>> +
>> clock = clk_get_rate(&clk);
>> if (IS_ERR_VALUE(clock)) {
>> dev_err(dev, "failed to get rate\n");
>> @@ -804,6 +813,7 @@ static int arasan_sdhci_of_to_plat(struct udevice
>> *dev)
>> if (IS_ERR(priv->host->ioaddr))
>> return PTR_ERR(priv->host->ioaddr);
>> + priv->frequency = dev_read_u32_default(dev, "clock-frequency", 0);
>> priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
>> priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
>> priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
>>
>
> Why not just assigned-clock-rates? Are there any existing users with
> just clock-frequency?
There is no user of it now in public domain. I was looking for the right
properly and found only clock-frequency but assigned-clock-rates works
for me. Will test and send v2.
Thanks,
Michal
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] sdhci: zynqmp: Setting up clock frequency based on DT
2021-11-22 15:31 ` Michal Simek
@ 2021-11-29 15:55 ` Michal Simek
0 siblings, 0 replies; 4+ messages in thread
From: Michal Simek @ 2021-11-29 15:55 UTC (permalink / raw)
To: Michal Simek, Sean Anderson, u-boot, git; +Cc: Jaehoon Chung, Peng Fan
On 11/22/21 16:31, Michal Simek wrote:
> Hi,
>
> On 11/19/21 18:16, Sean Anderson wrote:
>>
>>
>> On 11/18/21 7:03 AM, Michal Simek wrote:
>>> Using clock-frequency property to define desired clock speed for
>>> controllers.
>>>
>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>> ---
>>>
>>> drivers/mmc/zynq_sdhci.c | 10 ++++++++++
>>> 1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
>>> index 5cea4c695e8d..ee87907939fe 100644
>>> --- a/drivers/mmc/zynq_sdhci.c
>>> +++ b/drivers/mmc/zynq_sdhci.c
>>> @@ -58,6 +58,7 @@ struct arasan_sdhci_plat {
>>> struct arasan_sdhci_priv {
>>> struct sdhci_host *host;
>>> struct arasan_sdhci_clk_data clk_data;
>>> + u32 frequency;
>>> u8 deviceid;
>>> u8 bank;
>>> u8 no_1p8;
>>> @@ -721,6 +722,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
>>> return ret;
>>> }
>>> + if (priv->frequency) {
>>> + ret = clk_set_rate(&clk, priv->frequency);
>>> + if (IS_ERR_VALUE(ret)) {
>>> + dev_err(dev, "failed to set clock rate\n");
>>> + return ret;
>>> + }
>>> + }
>>> +
>>> clock = clk_get_rate(&clk);
>>> if (IS_ERR_VALUE(clock)) {
>>> dev_err(dev, "failed to get rate\n");
>>> @@ -804,6 +813,7 @@ static int arasan_sdhci_of_to_plat(struct udevice
>>> *dev)
>>> if (IS_ERR(priv->host->ioaddr))
>>> return PTR_ERR(priv->host->ioaddr);
>>> + priv->frequency = dev_read_u32_default(dev, "clock-frequency", 0);
>>> priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
>>> priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
>>> priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
>>>
>>
>> Why not just assigned-clock-rates? Are there any existing users with
>> just clock-frequency?
>
> There is no user of it now in public domain. I was looking for the right
> properly and found only clock-frequency but assigned-clock-rates works
> for me. Will test and send v2.
Just for the record I have tried assigned-clock-rates and there is no
need to do any change in the driver. That's why please ignore this patch.
Thanks,
Michal
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-11-29 15:56 UTC | newest]
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2021-11-18 12:03 [PATCH] sdhci: zynqmp: Setting up clock frequency based on DT Michal Simek
2021-11-19 17:16 ` Sean Anderson
2021-11-22 15:31 ` Michal Simek
2021-11-29 15:55 ` Michal Simek
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