* [RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases
@ 2022-05-13 9:46 Tsukasa OI
2022-05-13 9:46 ` [RFC PATCH 1/1] target/riscv: Make property names lowercase Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
0 siblings, 2 replies; 19+ messages in thread
From: Tsukasa OI @ 2022-05-13 9:46 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis, Frank Chang, Dao Lu; +Cc: qemu-devel, qemu-riscv
Hello,
While I'm reviewing Dao Lu's Zihintpause patch, I noticed something.
c.f. <https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00210.html>
While some CPU configuration properties have capitalized names but others
have lowercase names. See riscv_cpu_properties in target/riscv/cpu.c
for example:
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
...
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
...
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
...
I think this is not good. Property names should have some sort of
consistency (especially when those names are case sensitive). This is
what happens when invalid property is specified:
Invalid: -cpu rv64,counters=off
Valid : -cpu rv64,Counters=off
qemu-system-riscv64: can't apply global rv64-riscv-cpu.counters=off: Property 'rv64-riscv-cpu.counters' not found
But we can't just remove such names for compatibility.
I found a way to make "property aliases" and that way, we can make both
"Counters" and "counters" valid. I chose lowercase names (because of
number of properties implemented) as primary ones and capitalized names
are defined as aliases.
For instance, I'll show how both "counters" and "Counters" are implemented
below. They share three arguments but on alias (the second one),:
- it uses DEFINE_PROP on alias to disable setting default value and
- it defines property type (that is generally set by DEFINE_PROP_BOOL but
must be set manually because the alias uses DEFINE_PROP).
DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP ("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
Tsukasa OI (1):
target/riscv: Make property names lowercase
target/riscv/cpu.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
base-commit: 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RFC PATCH 1/1] target/riscv: Make property names lowercase
2022-05-13 9:46 [RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases Tsukasa OI
@ 2022-05-13 9:46 ` Tsukasa OI
2022-05-23 6:36 ` Alistair Francis
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
1 sibling, 1 reply; 19+ messages in thread
From: Tsukasa OI @ 2022-05-13 9:46 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis, Frank Chang, Dao Lu; +Cc: qemu-devel, qemu-riscv
Many properties for extension names are just in lowercase. On the other
hand, following extension properties and "Counters" are capitalized.
- Zifencei
- Zicsr
- Zfh
- Zfhmin
- Zve32f
- Zve64f
This commit chooses lowercase as primary property names but keeps
capitalized names as aliases for compatibility.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 23 ++++++++++++++++-------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ccacdee215..16227a1ac5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -822,17 +822,26 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
- DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
- DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
- DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
- DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
- DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+ DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
+ DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+ DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
+ DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+ /* Capitalized aliases */
+ DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
+ DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
+ DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
+
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [RFC PATCH 1/1] target/riscv: Make property names lowercase
2022-05-13 9:46 ` [RFC PATCH 1/1] target/riscv: Make property names lowercase Tsukasa OI
@ 2022-05-23 6:36 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2022-05-23 6:36 UTC (permalink / raw)
To: Tsukasa OI
Cc: Frank Chang, Dao Lu, qemu-devel@nongnu.org Developers, open list:RISC-V
On Fri, May 13, 2022 at 7:47 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Many properties for extension names are just in lowercase. On the other
> hand, following extension properties and "Counters" are capitalized.
>
> - Zifencei
> - Zicsr
> - Zfh
> - Zfhmin
> - Zve32f
> - Zve64f
>
> This commit chooses lowercase as primary property names but keeps
> capitalized names as aliases for compatibility.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
> target/riscv/cpu.c | 23 ++++++++++++++++-------
> 1 file changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..16227a1ac5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -822,17 +822,26 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>
> + /* Capitalized aliases */
> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
Cool!
I think we should add a comment here saying not to do this for anything new.
Also, it's probably worth adding a deprecation note about the capital
names, then we can remove them in the future.
Alistair
> +
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases)
2022-05-13 9:46 [RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases Tsukasa OI
2022-05-13 9:46 ` [RFC PATCH 1/1] target/riscv: Make property names lowercase Tsukasa OI
@ 2022-05-25 9:54 ` Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
` (3 more replies)
1 sibling, 4 replies; 19+ messages in thread
From: Tsukasa OI @ 2022-05-25 9:54 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
v1:
<https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00227.html>
Hello,
This is a refined version of the patch to RISC-V CPU property names.
See v1 for background.
[Changes: RFC PATCH (v1) -> PATCH v2]
- Reorganized all properties for clarity and extensibility
(PATCH 1/3, not actually a point of this patchset but worth doing)
- Reworded for correctness and clarity
(it's the first time for me to use Grammarly)
- Added a deprecation note to documentation (PATCH 3/3)
[RFC: PATCH 3/3]
1. Which is a better section to add a deprecation note?
- "System emulator command line arguments" or
- A new section under "Device options" (THIS PATCH)
2. Is it okay to use the word "7.1" (an unreleased version number)?
Tsukasa OI (3):
target/riscv: Reorganize riscv_cpu_properties
target/riscv: Make CPU property names lowercase
target/riscv: Deprecate capitalized property names
docs/about/deprecated.rst | 10 +++++
target/riscv/cpu.c | 79 +++++++++++++++++++++++++--------------
2 files changed, 61 insertions(+), 28 deletions(-)
base-commit: 0cac736e73723850a99e5142e35d14d8f8efb232
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
@ 2022-05-25 9:54 ` Tsukasa OI
2022-06-01 4:05 ` Alistair Francis
2022-05-25 9:54 ` [PATCH v2 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
` (2 subsequent siblings)
3 siblings, 1 reply; 19+ messages in thread
From: Tsukasa OI @ 2022-05-25 9:54 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
This commit reorganizes riscv_cpu_properties for clarity.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 64 +++++++++++++++++++++++++++-------------------
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a91253d4bd..3f21563f2d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -840,7 +840,7 @@ static void riscv_cpu_init(Object *obj)
}
static Property riscv_cpu_properties[] = {
- /* Defaults for standard extensions */
+ /* Base ISA and single-letter standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
@@ -853,29 +853,17 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+
+ /* Standard unprivileged extensions */
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
- DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
- DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
- DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
- DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
- DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
-
- DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
- DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
- DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
- DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-
- DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
- DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
- DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
-
- DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
- DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
- DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
+ DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
@@ -884,6 +872,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+
DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
@@ -895,10 +884,31 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
- DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
- DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
- DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
- DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+ DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
+ DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+
+ /* Standard supervisor-level extensions */
+ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+ DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
+
+ /* Base features */
+ DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+
+ /* ISA specification / extension versions */
+ DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+
+ /* CPU parameters */
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+ DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+ DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+ DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
@@ -909,9 +919,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
-
+ /* Other options */
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
@ 2022-05-25 9:54 ` Tsukasa OI
2022-05-25 12:10 ` Víctor Colombo
2022-05-25 14:32 ` [PATCH v2.1 " Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
3 siblings, 2 replies; 19+ messages in thread
From: Tsukasa OI @ 2022-05-25 9:54 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
Many CPU properties for RISC-V are in lowercase except those with
"capitalized" (or CamelCase) names:
- Counters
- Zifencei
- Zicsr
- Zfh
- Zfhmin
- Zve32f
- Zve64f
This commit makes lowercase names primary but keeps capitalized names
as aliases (for backward comatibility, but with deprecated status).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3f21563f2d..83262586e4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
}
static Property riscv_cpu_properties[] = {
+ /*
+ * Names for ISA extensions and features should be in lowercase.
+ */
+
/* Base ISA and single-letter standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
@@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
/* Standard unprivileged extensions */
- DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
- DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
- DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+ DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
+ DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
@@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
- DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
- DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+ DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
+ DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
/* Standard supervisor-level extensions */
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
@@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
/* Base features */
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
@@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
/* Other options */
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+ /* Capitalized aliases (deprecated and will be removed) */
+ DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
+ DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
+ DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 3/3] target/riscv: Deprecate capitalized property names
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
@ 2022-05-25 9:54 ` Tsukasa OI
2022-06-02 1:20 ` Alistair Francis
2022-06-03 11:36 ` [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
3 siblings, 1 reply; 19+ messages in thread
From: Tsukasa OI @ 2022-05-25 9:54 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
This commit adds a deprecation note of capitalized property names of
RISC-V CPU to documentation.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
docs/about/deprecated.rst | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index a92ae0f162..cfc9adcd4b 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -300,6 +300,16 @@ Options are:
Device options
--------------
+CPU options
+'''''''''''
+
+Capitalized property names on RISC-V ``-cpu`` (since 7.1)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Using capitalized RISC-V CPU property names like ``-cpu rv64,Counters=on`` is
+deprecated. Use lowercase names instead (e.g. ``-cpu rv64,counters=on``).
+
+
Emulated device options
'''''''''''''''''''''''
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
2022-05-25 9:54 ` [PATCH v2 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
@ 2022-05-25 12:10 ` Víctor Colombo
2022-05-25 14:55 ` Tsukasa OI
2022-05-25 14:32 ` [PATCH v2.1 " Tsukasa OI
1 sibling, 1 reply; 19+ messages in thread
From: Víctor Colombo @ 2022-05-25 12:10 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
On 25/05/2022 06:54, Tsukasa OI wrote:
> Many CPU properties for RISC-V are in lowercase except those with
> "capitalized" (or CamelCase) names:
>
> - Counters
> - Zifencei
> - Zicsr
> - Zfh
> - Zfhmin
> - Zve32f
> - Zve64f
>
> This commit makes lowercase names primary but keeps capitalized names
> as aliases (for backward comatibility, but with deprecated status).
'compatibility'
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br>
> ---
> target/riscv/cpu.c | 27 ++++++++++++++++++++-------
> 1 file changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3f21563f2d..83262586e4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
> }
>
> static Property riscv_cpu_properties[] = {
> + /*
> + * Names for ISA extensions and features should be in lowercase.
> + */
> +
> /* Base ISA and single-letter standard extensions */
> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
>
> /* Standard unprivileged extensions */
> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
>
> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
>
> /* Standard supervisor-level extensions */
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> /* Base features */
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
> /* Other options */
> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
>
> + /* Capitalized aliases (deprecated and will be removed) */
> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
> --
> 2.34.1
>
>
Best regards,
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2.1 2/3] target/riscv: Make CPU property names lowercase
2022-05-25 9:54 ` [PATCH v2 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
2022-05-25 12:10 ` Víctor Colombo
@ 2022-05-25 14:32 ` Tsukasa OI
1 sibling, 0 replies; 19+ messages in thread
From: Tsukasa OI @ 2022-05-25 14:32 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
Many CPU properties for RISC-V are in lowercase except those with
"capitalized" (or CamelCase) names:
- Counters
- Zifencei
- Zicsr
- Zfh
- Zfhmin
- Zve32f
- Zve64f
This commit makes lowercase names primary but keeps capitalized names
as aliases (for backward compatibility, but with deprecated status).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3f21563f2d..83262586e4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
}
static Property riscv_cpu_properties[] = {
+ /*
+ * Names for ISA extensions and features should be in lowercase.
+ */
+
/* Base ISA and single-letter standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
@@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
/* Standard unprivileged extensions */
- DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
- DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
- DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+ DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
+ DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
@@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
- DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
- DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+ DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
+ DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
/* Standard supervisor-level extensions */
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
@@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
/* Base features */
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
@@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
/* Other options */
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+ /* Capitalized aliases (deprecated and will be removed) */
+ DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
+ DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
+ DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
2022-05-25 12:10 ` Víctor Colombo
@ 2022-05-25 14:55 ` Tsukasa OI
2022-06-02 1:17 ` Alistair Francis
0 siblings, 1 reply; 19+ messages in thread
From: Tsukasa OI @ 2022-05-25 14:55 UTC (permalink / raw)
To: Víctor Colombo; +Cc: qemu-devel, qemu-riscv
On 2022/05/25 21:10, Víctor Colombo wrote:
> On 25/05/2022 06:54, Tsukasa OI wrote:
>> Many CPU properties for RISC-V are in lowercase except those with
>> "capitalized" (or CamelCase) names:
>>
>> - Counters
>> - Zifencei
>> - Zicsr
>> - Zfh
>> - Zfhmin
>> - Zve32f
>> - Zve64f
>>
>> This commit makes lowercase names primary but keeps capitalized names
>> as aliases (for backward comatibility, but with deprecated status).
>
> 'compatibility'
I think I somehow pressed a backspace while finalizing.
I submitted v2.1 (PATCH 2/3 only) and that should be fine.
https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00417.html
Thanks!
Tsukasa
>
>>
>> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br>
>
>> ---
>> target/riscv/cpu.c | 27 ++++++++++++++++++++-------
>> 1 file changed, 20 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 3f21563f2d..83262586e4 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
>> }
>>
>> static Property riscv_cpu_properties[] = {
>> + /*
>> + * Names for ISA extensions and features should be in lowercase.
>> + */
>> +
>> /* Base ISA and single-letter standard extensions */
>> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
>> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>> @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
>>
>> /* Standard unprivileged extensions */
>> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
>> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
>>
>> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
>> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
>> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
>> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
>> DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
>> DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
>> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
>> @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
>> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>>
>> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
>> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
>> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
>> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
>>
>> /* Standard supervisor-level extensions */
>> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>> @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>>
>> /* Base features */
>> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
>> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
>> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>> @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
>> /* Other options */
>> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU,
>> cfg.short_isa_string, false),
>>
>> + /* Capitalized aliases (deprecated and will be removed) */
>> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters,
>> qdev_prop_bool, bool),
>> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei,
>> qdev_prop_bool, bool),
>> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
>> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
>> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool,
>> bool),
>> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool,
>> bool),
>> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool,
>> bool),
>> +
>> DEFINE_PROP_END_OF_LIST(),
>> };
>>
>> --
>> 2.34.1
>>
>>
>
> Best regards,
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties
2022-05-25 9:54 ` [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
@ 2022-06-01 4:05 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2022-06-01 4:05 UTC (permalink / raw)
To: Tsukasa OI; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Wed, May 25, 2022 at 7:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit reorganizes riscv_cpu_properties for clarity.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 64 +++++++++++++++++++++++++++-------------------
> 1 file changed, 37 insertions(+), 27 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a91253d4bd..3f21563f2d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -840,7 +840,7 @@ static void riscv_cpu_init(Object *obj)
> }
>
> static Property riscv_cpu_properties[] = {
> - /* Defaults for standard extensions */
> + /* Base ISA and single-letter standard extensions */
> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> @@ -853,29 +853,17 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> +
> + /* Standard unprivileged extensions */
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> +
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> -
> - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> -
> - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
> -
> - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> - DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> - DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
>
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> @@ -884,6 +872,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +
> DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> @@ -895,10 +884,31 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
> - DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> - DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> - DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> - DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
> + DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> + DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> +
> + /* Standard supervisor-level extensions */
> + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> +
> + /* Base features */
> + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> +
> + /* ISA specification / extension versions */
> + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> +
> + /* CPU parameters */
> + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
> + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> /* Vendor-specific custom extensions */
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
> @@ -909,9 +919,9 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
>
> - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> -
> + /* Other options */
> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
2022-05-25 14:55 ` Tsukasa OI
@ 2022-06-02 1:17 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2022-06-02 1:17 UTC (permalink / raw)
To: Tsukasa OI
Cc: Víctor Colombo, qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, May 26, 2022 at 1:27 AM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> On 2022/05/25 21:10, Víctor Colombo wrote:
> > On 25/05/2022 06:54, Tsukasa OI wrote:
> >> Many CPU properties for RISC-V are in lowercase except those with
> >> "capitalized" (or CamelCase) names:
> >>
> >> - Counters
> >> - Zifencei
> >> - Zicsr
> >> - Zfh
> >> - Zfhmin
> >> - Zve32f
> >> - Zve64f
> >>
> >> This commit makes lowercase names primary but keeps capitalized names
> >> as aliases (for backward comatibility, but with deprecated status).
> >
> > 'compatibility'
>
> I think I somehow pressed a backspace while finalizing.
> I submitted v2.1 (PATCH 2/3 only) and that should be fine.
>
> https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00417.html
Do you mind re-sending the series, it's difficult to keep track of
single patch increments like this
>
> Thanks!
> Tsukasa
>
> >
> >>
> >> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> >
> > Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> >
> >> ---
> >> target/riscv/cpu.c | 27 ++++++++++++++++++++-------
> >> 1 file changed, 20 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 3f21563f2d..83262586e4 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
> >> }
> >>
> >> static Property riscv_cpu_properties[] = {
> >> + /*
> >> + * Names for ISA extensions and features should be in lowercase.
> >> + */
> >> +
> >> /* Base ISA and single-letter standard extensions */
> >> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> >> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> >> @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
> >> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
> >>
> >> /* Standard unprivileged extensions */
> >> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> >> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> >> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
> >> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
> >>
> >> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> >> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> >> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
> >> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> >> DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> >> DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> >> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> >> @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
> >> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> >> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
> >>
> >> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> >> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> >> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
> >> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
> >>
> >> /* Standard supervisor-level extensions */
> >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> >> @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
> >> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> >>
> >> /* Base features */
> >> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> >> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
> >> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> >> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> >> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> >> @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
> >> /* Other options */
> >> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU,
> >> cfg.short_isa_string, false),
> >>
> >> + /* Capitalized aliases (deprecated and will be removed) */
> >> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters,
> >> qdev_prop_bool, bool),
> >> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei,
> >> qdev_prop_bool, bool),
> >> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
> >> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
> >> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool,
> >> bool),
> >> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool,
> >> bool),
> >> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool,
> >> bool),
> >> +
> >> DEFINE_PROP_END_OF_LIST(),
> >> };
> >>
> >> --
> >> 2.34.1
> >>
> >>
> >
> > Best regards,
> >
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 3/3] target/riscv: Deprecate capitalized property names
2022-05-25 9:54 ` [PATCH v2 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
@ 2022-06-02 1:20 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2022-06-02 1:20 UTC (permalink / raw)
To: Tsukasa OI; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Wed, May 25, 2022 at 7:55 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> This commit adds a deprecation note of capitalized property names of
> RISC-V CPU to documentation.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
> docs/about/deprecated.rst | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> index a92ae0f162..cfc9adcd4b 100644
> --- a/docs/about/deprecated.rst
> +++ b/docs/about/deprecated.rst
> @@ -300,6 +300,16 @@ Options are:
> Device options
> --------------
>
> +CPU options
> +'''''''''''
> +
> +Capitalized property names on RISC-V ``-cpu`` (since 7.1)
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This should probably just be added under `linux-user mode CPUs` and
`System emulator CPUS` to avoid adding new sections
Alistair
> +
> +Using capitalized RISC-V CPU property names like ``-cpu rv64,Counters=on`` is
> +deprecated. Use lowercase names instead (e.g. ``-cpu rv64,counters=on``).
> +
> +
> Emulated device options
> '''''''''''''''''''''''
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases)
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
` (2 preceding siblings ...)
2022-05-25 9:54 ` [PATCH v2 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
@ 2022-06-03 11:36 ` Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
` (2 more replies)
3 siblings, 3 replies; 19+ messages in thread
From: Tsukasa OI @ 2022-06-03 11:36 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
v1: <https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00227.html>
v2: <https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00411.html>
v2.1: <https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00417.html>
Hello,
This is v3 of the patch to RISC-V CPU property names.
See v1 for background.
[Changes: PATCH v2 -> PATCH v3]
- Rebased to newer master
- Fixed a typo
- Clarified intent of PATCH 1/3
Tsukasa OI (3):
target/riscv: Reorganize riscv_cpu_properties
target/riscv: Make CPU property names lowercase
target/riscv: Deprecate capitalized property names
docs/about/deprecated.rst | 10 +++++
target/riscv/cpu.c | 79 +++++++++++++++++++++++++--------------
2 files changed, 61 insertions(+), 28 deletions(-)
base-commit: c9641eb422905cc0804a7e310269abf09543cce8
--
2.34.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties
2022-06-03 11:36 ` [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
@ 2022-06-03 11:36 ` Tsukasa OI
2022-06-06 6:02 ` Alistair Francis
2022-06-03 11:36 ` [PATCH v3 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
2 siblings, 1 reply; 19+ messages in thread
From: Tsukasa OI @ 2022-06-03 11:36 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
Because many developers introduced new properties in various ways, the
entire riscv_cpu_properties block is getting too complex.
This commit reorganizes riscv_cpu_properties for clarity on future.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 64 +++++++++++++++++++++++++++-------------------
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a91253d4bd..3f21563f2d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -840,7 +840,7 @@ static void riscv_cpu_init(Object *obj)
}
static Property riscv_cpu_properties[] = {
- /* Defaults for standard extensions */
+ /* Base ISA and single-letter standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
@@ -853,29 +853,17 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+
+ /* Standard unprivileged extensions */
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
- DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
- DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
- DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
- DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
- DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
-
- DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
- DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
- DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
- DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-
- DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
- DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
- DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
-
- DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
- DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
- DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
+ DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
@@ -884,6 +872,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+
DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
@@ -895,10 +884,31 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
- DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
- DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
- DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
- DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+ DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
+ DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+
+ /* Standard supervisor-level extensions */
+ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
+ DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+ DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
+
+ /* Base features */
+ DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+
+ /* ISA specification / extension versions */
+ DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+
+ /* CPU parameters */
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+ DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+ DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
+ DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
@@ -909,9 +919,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
-
+ /* Other options */
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/3] target/riscv: Make CPU property names lowercase
2022-06-03 11:36 ` [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
@ 2022-06-03 11:36 ` Tsukasa OI
2022-06-06 6:03 ` Alistair Francis
2022-06-03 11:36 ` [PATCH v3 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
2 siblings, 1 reply; 19+ messages in thread
From: Tsukasa OI @ 2022-06-03 11:36 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
Many CPU properties for RISC-V are in lowercase except those with
"capitalized" (or CamelCase) names:
- Counters
- Zifencei
- Zicsr
- Zfh
- Zfhmin
- Zve32f
- Zve64f
This commit makes lowercase names primary but keeps capitalized names
as aliases (for backward compatibility, but with deprecated status).
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3f21563f2d..83262586e4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
}
static Property riscv_cpu_properties[] = {
+ /*
+ * Names for ISA extensions and features should be in lowercase.
+ */
+
/* Base ISA and single-letter standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
@@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
/* Standard unprivileged extensions */
- DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
- DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
- DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
- DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+ DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
+ DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
@@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
- DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
- DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+ DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
+ DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
/* Standard supervisor-level extensions */
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
@@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
/* Base features */
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
@@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
/* Other options */
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
+ /* Capitalized aliases (deprecated and will be removed) */
+ DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
+ DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
+ DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
+ DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
+ DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 3/3] target/riscv: Deprecate capitalized property names
2022-06-03 11:36 ` [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
@ 2022-06-03 11:36 ` Tsukasa OI
2 siblings, 0 replies; 19+ messages in thread
From: Tsukasa OI @ 2022-06-03 11:36 UTC (permalink / raw)
To: Tsukasa OI, Alistair Francis; +Cc: qemu-devel, qemu-riscv
This commit adds a deprecation note of capitalized property names of
RISC-V CPU to documentation.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
docs/about/deprecated.rst | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index a92ae0f162..cfc9adcd4b 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -300,6 +300,16 @@ Options are:
Device options
--------------
+CPU options
+'''''''''''
+
+Capitalized property names on RISC-V ``-cpu`` (since 7.1)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Using capitalized RISC-V CPU property names like ``-cpu rv64,Counters=on`` is
+deprecated. Use lowercase names instead (e.g. ``-cpu rv64,counters=on``).
+
+
Emulated device options
'''''''''''''''''''''''
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties
2022-06-03 11:36 ` [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
@ 2022-06-06 6:02 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2022-06-06 6:02 UTC (permalink / raw)
To: Tsukasa OI; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Fri, Jun 3, 2022 at 9:36 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Because many developers introduced new properties in various ways, the
> entire riscv_cpu_properties block is getting too complex.
>
> This commit reorganizes riscv_cpu_properties for clarity on future.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 64 +++++++++++++++++++++++++++-------------------
> 1 file changed, 37 insertions(+), 27 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a91253d4bd..3f21563f2d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -840,7 +840,7 @@ static void riscv_cpu_init(Object *obj)
> }
>
> static Property riscv_cpu_properties[] = {
> - /* Defaults for standard extensions */
> + /* Base ISA and single-letter standard extensions */
> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> @@ -853,29 +853,17 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> +
> + /* Standard unprivileged extensions */
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> +
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> -
> - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> -
> - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
> -
> - DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> - DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> - DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
>
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> @@ -884,6 +872,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +
> DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> @@ -895,10 +884,31 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
> - DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> - DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> - DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> - DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
> + DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> + DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> +
> + /* Standard supervisor-level extensions */
> + DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> + DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> + DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> +
> + /* Base features */
> + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> +
> + /* ISA specification / extension versions */
> + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> +
> + /* CPU parameters */
> + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
> + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> /* Vendor-specific custom extensions */
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
> @@ -909,9 +919,9 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
>
> - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> -
> + /* Other options */
> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v3 2/3] target/riscv: Make CPU property names lowercase
2022-06-03 11:36 ` [PATCH v3 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
@ 2022-06-06 6:03 ` Alistair Francis
0 siblings, 0 replies; 19+ messages in thread
From: Alistair Francis @ 2022-06-06 6:03 UTC (permalink / raw)
To: Tsukasa OI; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Fri, Jun 3, 2022 at 9:37 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> Many CPU properties for RISC-V are in lowercase except those with
> "capitalized" (or CamelCase) names:
>
> - Counters
> - Zifencei
> - Zicsr
> - Zfh
> - Zfhmin
> - Zve32f
> - Zve64f
>
> This commit makes lowercase names primary but keeps capitalized names
> as aliases (for backward compatibility, but with deprecated status).
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 27 ++++++++++++++++++++-------
> 1 file changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3f21563f2d..83262586e4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj)
> }
>
> static Property riscv_cpu_properties[] = {
> + /*
> + * Names for ISA extensions and features should be in lowercase.
> + */
> +
> /* Base ISA and single-letter standard extensions */
> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
>
> /* Standard unprivileged extensions */
> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true),
>
> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false),
> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
> DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
> @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
>
> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false),
> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false),
>
> /* Standard supervisor-level extensions */
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> /* Base features */
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = {
> /* Other options */
> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
>
> + /* Capitalized aliases (deprecated and will be removed) */
> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool),
> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool),
> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool),
> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool),
> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool),
> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool),
> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool),
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2022-06-06 6:09 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-13 9:46 [RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases Tsukasa OI
2022-05-13 9:46 ` [RFC PATCH 1/1] target/riscv: Make property names lowercase Tsukasa OI
2022-05-23 6:36 ` Alistair Francis
2022-05-25 9:54 ` [PATCH v2 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
2022-06-01 4:05 ` Alistair Francis
2022-05-25 9:54 ` [PATCH v2 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
2022-05-25 12:10 ` Víctor Colombo
2022-05-25 14:55 ` Tsukasa OI
2022-06-02 1:17 ` Alistair Francis
2022-05-25 14:32 ` [PATCH v2.1 " Tsukasa OI
2022-05-25 9:54 ` [PATCH v2 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
2022-06-02 1:20 ` Alistair Francis
2022-06-03 11:36 ` [PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases) Tsukasa OI
2022-06-03 11:36 ` [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties Tsukasa OI
2022-06-06 6:02 ` Alistair Francis
2022-06-03 11:36 ` [PATCH v3 2/3] target/riscv: Make CPU property names lowercase Tsukasa OI
2022-06-06 6:03 ` Alistair Francis
2022-06-03 11:36 ` [PATCH v3 3/3] target/riscv: Deprecate capitalized property names Tsukasa OI
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