* [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch ***
@ 2023-09-26 9:54 xianglai li
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
` (6 more replies)
0 siblings, 7 replies; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Hello everyone, We refer to the implementation of ARM CPU
Hot-Plug to add GED-based CPU Hot-Plug support to Loongarch.
The first 2 patches are changes to the QEMU common code,
including adding GED support for CPU Hot-Plug, updating
the ACPI table creation process.
For the modification of the public part of the code, we refer to the
arm-related patch, and the link address of the corresponding patch is
as follows:
https://lore.kernel.org/all/20200613213629.21984-1-salil.mehta@huawei.com/
We also refer to shentey's patch link as follows:
https://patchew.org/QEMU/20230908084234.17642-1-shentey@gmail.com/
In order to respect the work of "Salil Mehta" and shentey, we will rebase
the first 2 patches in the final patch, which are referenced here to ensure
that the loongarch cpu hotplug can work properly.
The last 5 patches are Loongarch architecture-related,
and the modifications include the definition of the hook
function related to the CPU Hot-(UN)Plug, the allocation
and release of CPU resources when CPU Hot-(UN)Plug,
the creation process of updating the ACPI table,
and finally the custom switch for the CPU Hot-Plug.
V3:
- The call to the function qdev_disconnect_gpio_out_named was removed
- The use of the function cpu_address_space_destroy is necessary,
most architectures also need to be called, we want to call
in the common path, rather than each cpu architecture itself,
because the scheme is not sure we want to solve this problem
in a separate patch, here we do the function rollback processing.
- Referring to shentey's patch, loongarch no longer creates the
TYPE_ACPI_GED_LOONGARCH device class, but instead passes build_madt_cpu_fn
directly as an argument to the build_cpus_aml function
V2:
- Fix formatting and spelling errors
- Split large patches into smaller patches
- Split the original patch
<<Add basic CPU hot-(un)plug support for Loongarch>> into
<<Added CPU topology support for Loongarch>>
<<Optimize loongarch_irq_init function implementation >>
<<Add basic CPU hot-(un)plug support for Loongarch>>.
- Split the original patch
<<Update the ACPI table for the Loongarch CPU>> into
<<Add generic event device for Loongarch>>
<<Update the ACPI table for the Loongarch CPU>>
- Added loongarch cpu topology calculation method.
- Change the position of the cpu topology patch.
- Change unreasonable variable and function names.
xianglai li (7):
Update ACPI GED framework to support vcpu hot-(un)plug
Update CPUs AML with cpu-(ctrl)dev change
Added CPU topology support for Loongarch
Optimize loongarch_irq_init function implementation
Add basic CPU hot-(un)plug support for Loongarch
Add support of *unrealize* for Loongarch cpu
Update the ACPI table for the Loongarch CPU
.../devices/loongarch64-softmmu/default.mak | 1 +
docs/system/loongarch/virt.rst | 31 ++
hw/acpi/acpi-cpu-hotplug-stub.c | 15 +
hw/acpi/cpu.c | 27 +-
hw/acpi/generic_event_device.c | 33 ++
hw/i386/acpi-build.c | 3 +-
hw/loongarch/acpi-build.c | 34 +-
hw/loongarch/virt.c | 409 +++++++++++++++---
include/hw/acpi/cpu.h | 5 +-
include/hw/acpi/cpu_hotplug.h | 10 +
include/hw/acpi/generic_event_device.h | 5 +
include/hw/loongarch/virt.h | 6 +-
target/loongarch/cpu.c | 33 +-
target/loongarch/cpu.h | 13 +-
14 files changed, 542 insertions(+), 83 deletions(-)
--
2.39.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 10:50 ` Salil Mehta via
` (2 more replies)
2023-09-26 9:54 ` [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change xianglai li
` (5 subsequent siblings)
6 siblings, 3 replies; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Salil Mehta, Salil Mehta, Bernhard Beschow, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
ACPI GED shall be used to convey to the guest kernel about any cpu hot-(un)plug
events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced
to support CPU hot-(un)plug state and events.
Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
hw/acpi/acpi-cpu-hotplug-stub.c | 6 +++++
hw/acpi/cpu.c | 7 ------
hw/acpi/generic_event_device.c | 33 ++++++++++++++++++++++++++
include/hw/acpi/cpu_hotplug.h | 10 ++++++++
include/hw/acpi/generic_event_device.h | 5 ++++
5 files changed, 54 insertions(+), 7 deletions(-)
diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c
index 3fc4b14c26..2aec90d968 100644
--- a/hw/acpi/acpi-cpu-hotplug-stub.c
+++ b/hw/acpi/acpi-cpu-hotplug-stub.c
@@ -24,6 +24,12 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list)
return;
}
+void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
+ CPUHotplugState *state, hwaddr base_addr)
+{
+ return;
+}
+
void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev,
CPUHotplugState *cpu_st, DeviceState *dev, Error **errp)
{
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 011d2c6c2d..5bad983928 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -7,13 +7,6 @@
#include "trace.h"
#include "sysemu/numa.h"
-#define ACPI_CPU_HOTPLUG_REG_LEN 12
-#define ACPI_CPU_SELECTOR_OFFSET_WR 0
-#define ACPI_CPU_FLAGS_OFFSET_RW 4
-#define ACPI_CPU_CMD_OFFSET_WR 5
-#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
-#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
-
#define OVMF_CPUHP_SMI_CMD 4
enum {
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
index a3d31631fe..c5a70957b4 100644
--- a/hw/acpi/generic_event_device.c
+++ b/hw/acpi/generic_event_device.c
@@ -12,6 +12,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/acpi/acpi.h"
+#include "hw/acpi/cpu.h"
#include "hw/acpi/generic_event_device.h"
#include "hw/irq.h"
#include "hw/mem/pc-dimm.h"
@@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] = {
ACPI_GED_MEM_HOTPLUG_EVT,
ACPI_GED_PWR_DOWN_EVT,
ACPI_GED_NVDIMM_HOTPLUG_EVT,
+ ACPI_GED_CPU_HOTPLUG_EVT,
};
/*
@@ -117,6 +119,10 @@ void build_ged_aml(Aml *table, const char *name, HotplugHandler *hotplug_dev,
aml_notify(aml_name("\\_SB.NVDR"),
aml_int(0x80)));
break;
+ case ACPI_GED_CPU_HOTPLUG_EVT:
+ aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "."
+ ACPI_CPU_SCAN_METHOD));
+ break;
default:
/*
* Please make sure all the events in ged_supported_events[]
@@ -234,6 +240,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
} else {
acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp);
}
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
+ acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
} else {
error_setg(errp, "virt: device plug request for unsupported device"
" type: %s", object_get_typename(OBJECT(dev)));
@@ -248,6 +256,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
!(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
+ acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
} else {
error_setg(errp, "acpi: device unplug request for unsupported device"
" type: %s", object_get_typename(OBJECT(dev)));
@@ -261,6 +271,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
+ acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
} else {
error_setg(errp, "acpi: device unplug for unsupported device"
" type: %s", object_get_typename(OBJECT(dev)));
@@ -272,6 +284,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
AcpiGedState *s = ACPI_GED(adev);
acpi_memory_ospm_status(&s->memhp_state, list);
+ acpi_cpu_ospm_status(&s->cpuhp_state, list);
}
static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
@@ -286,6 +299,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
sel = ACPI_GED_PWR_DOWN_EVT;
} else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) {
sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
+ } else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
+ sel = ACPI_GED_CPU_HOTPLUG_EVT;
} else {
/* Unknown event. Return without generating interrupt. */
warn_report("GED: Unsupported event %d. No irq injected", ev);
@@ -318,6 +333,16 @@ static const VMStateDescription vmstate_memhp_state = {
}
};
+static const VMStateDescription vmstate_cpuhp_state = {
+ .name = "acpi-ged/cpuhp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_ged_state = {
.name = "acpi-ged-state",
.version_id = 1,
@@ -366,6 +391,7 @@ static const VMStateDescription vmstate_acpi_ged = {
},
.subsections = (const VMStateDescription * []) {
&vmstate_memhp_state,
+ &vmstate_cpuhp_state,
&vmstate_ghes_state,
NULL
}
@@ -400,6 +426,13 @@ static void acpi_ged_initfn(Object *obj)
memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
sysbus_init_mmio(sbd, &ged_st->regs);
+
+ s->cpuhp.device = OBJECT(s);
+ memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp container",
+ ACPI_CPU_HOTPLUG_REG_LEN);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container_cpuhp);
+ cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
+ &s->cpuhp_state, 0);
}
static void acpi_ged_class_init(ObjectClass *class, void *data)
diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
index 3b932abbbb..afee1ab996 100644
--- a/include/hw/acpi/cpu_hotplug.h
+++ b/include/hw/acpi/cpu_hotplug.h
@@ -19,6 +19,16 @@
#include "hw/hotplug.h"
#include "hw/acpi/cpu.h"
+#define ACPI_CPU_HOTPLUG_REG_LEN 12
+#define ACPI_CPU_SELECTOR_OFFSET_WR 0
+#define ACPI_CPU_FLAGS_OFFSET_RW 4
+#define ACPI_CPU_CMD_OFFSET_WR 5
+#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
+#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
+
+#define ACPI_CPU_SCAN_METHOD "CSCN"
+#define ACPI_CPU_CONTAINER "\\_SB.CPUS"
+
typedef struct AcpiCpuHotplug {
Object *device;
MemoryRegion io;
diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
index ba84ce0214..a803ea818e 100644
--- a/include/hw/acpi/generic_event_device.h
+++ b/include/hw/acpi/generic_event_device.h
@@ -60,6 +60,7 @@
#define HW_ACPI_GENERIC_EVENT_DEVICE_H
#include "hw/sysbus.h"
+#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/ghes.h"
#include "qom/object.h"
@@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
#define ACPI_GED_MEM_HOTPLUG_EVT 0x1
#define ACPI_GED_PWR_DOWN_EVT 0x2
#define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
+#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
typedef struct GEDState {
MemoryRegion evt;
@@ -106,6 +108,9 @@ struct AcpiGedState {
SysBusDevice parent_obj;
MemHotplugState memhp_state;
MemoryRegion container_memhp;
+ CPUHotplugState cpuhp_state;
+ MemoryRegion container_cpuhp;
+ AcpiCpuHotplug cpuhp;
GEDState ged_state;
uint32_t ged_event_bitmap;
qemu_irq irq;
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 10:49 ` Salil Mehta via
2023-09-26 9:54 ` [PATCH v3 3/7] Added CPU topology support for Loongarch xianglai li
` (4 subsequent siblings)
6 siblings, 1 reply; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Salil Mehta, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
is based on PCI and is IO port based and hence existing cpus AML code
assumes _CRS objects would evaluate to a system resource which describes
IO Port address.
But on Loongarch arch CPUs control device(\\_SB.PRES) register interface
is memory-mapped hence _CRS object should evaluate to system resource
which describes memory-mapped base address.
This cpus AML code change updates the existing interface of the build cpus AML
function to accept both IO/MEMORY type regions and update the _CRS object
correspondingly.
Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
hw/acpi/cpu.c | 20 +++++++++++++++-----
hw/i386/acpi-build.c | 3 ++-
include/hw/acpi/cpu.h | 5 +++--
3 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 5bad983928..0afa04832e 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -6,6 +6,7 @@
#include "qapi/qapi-events-acpi.h"
#include "trace.h"
#include "sysemu/numa.h"
+#include "hw/acpi/cpu_hotplug.h"
#define OVMF_CPUHP_SMI_CMD 4
@@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
#define CPU_FW_EJECT_EVENT "CEJF"
void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
- build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
+ build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
const char *res_root,
- const char *event_handler_method)
+ const char *event_handler_method,
+ AmlRegionSpace rs)
{
Aml *ifctx;
Aml *field;
@@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
crs = aml_resource_template();
- aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
+ if (rs == AML_SYSTEM_IO) {
+ aml_append(crs, aml_io(AML_DECODE16, mmap_io_base, mmap_io_base, 1,
ACPI_CPU_HOTPLUG_REG_LEN));
+ } else {
+ aml_append(crs, aml_memory32_fixed(mmap_io_base,
+ ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE));
+ }
+
aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
+ g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
/* declare CPU hotplug MMIO region with related access fields */
aml_append(cpu_ctrl_dev,
- aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base),
- ACPI_CPU_HOTPLUG_REG_LEN));
+ aml_operation_region("PRST", rs,
+ aml_int(mmap_io_base),
+ ACPI_CPU_HOTPLUG_REG_LEN));
field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
AML_WRITE_AS_ZEROS);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 863a939210..7016205d15 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
.fw_unplugs_cpu = pm->smi_on_cpu_unplug,
};
build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
- pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02");
+ pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
+ AML_SYSTEM_IO);
}
if (pcms->memhp_io_base && nr_mem) {
diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
index bc901660fb..601f644e57 100644
--- a/include/hw/acpi/cpu.h
+++ b/include/hw/acpi/cpu.h
@@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const CPUArchIdList *apic_ids,
GArray *entry, bool force_enabled);
void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
- build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
+ build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
const char *res_root,
- const char *event_handler_method);
+ const char *event_handler_method,
+ AmlRegionSpace rs);
void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list);
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 3/7] Added CPU topology support for Loongarch
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
2023-09-26 9:54 ` [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 9:54 ` [PATCH v3 4/7] Optimize loongarch_irq_init function implementation xianglai li
` (3 subsequent siblings)
6 siblings, 0 replies; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Salil Mehta, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
1.Add topological relationships for Loongarch VCPU
and initialize topology member variables.
2.Add a description of the calculation method of
the arch_id and the topological relationship of the CPU.
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
docs/system/loongarch/virt.rst | 31 ++++++++++
hw/loongarch/virt.c | 101 ++++++++++++++++++++++++++-------
target/loongarch/cpu.c | 13 ++++-
target/loongarch/cpu.h | 12 +++-
4 files changed, 134 insertions(+), 23 deletions(-)
diff --git a/docs/system/loongarch/virt.rst b/docs/system/loongarch/virt.rst
index c37268b404..eaba9e2fd7 100644
--- a/docs/system/loongarch/virt.rst
+++ b/docs/system/loongarch/virt.rst
@@ -28,6 +28,37 @@ The ``qemu-system-loongarch64`` provides emulation for virt
machine. You can specify the machine type ``virt`` and
cpu type ``la464``.
+CPU Topology
+--------------------
+
+The ``LA464`` type CPUs have the concept of Socket Core and Thread.
+
+For example:
+
+``-smp 1,maxcpus=M,sockets=S,cores=C,threads=T``
+
+The above parameters indicate that the machine has a maximum of ``M`` vCPUs and
+``S`` sockets, each socket has ``C`` cores, each core has ``T`` threads,
+and each thread corresponds to a vCPU.
+
+Then ``M`` ``S`` ``C`` ``T`` has the following relationship:
+
+``M = S * C * T``
+
+In the CPU topology relationship, When we know the ``socket_id`` ``core_id``
+and ``thread_id`` of the CPU, we can calculate its ``arch_id``:
+
+``arch_id = (socket_id * S) + (core_id * C) + (thread_id * T)``
+
+Similarly, when we know the ``arch_id`` of the CPU,
+we can also get its ``socket_id`` ``core_id`` and ``thread_id``:
+
+``socket_id = arch_id / (C * T)``
+
+``core_id = (arch_id / T) % C``
+
+``thread_id = arch_id % T``
+
Boot options
------------
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 2629128aed..b8474e7b94 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -624,11 +624,11 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
1));
/*
- * extioi iocsr memory region
- * only one extioi is added on loongarch virt machine
- * external device interrupt can only be routed to cpu 0-3
- */
- if (cpu < EXTIOI_CPUS)
+ * extioi iocsr memory region
+ * only one extioi is added on loongarch virt machine
+ * external device interrupt can only be routed to cpu 0-3
+ */
+ if (cpu < EXTIOI_CPUS)
memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
cpu));
@@ -789,9 +789,7 @@ static void loongarch_init(MachineState *machine)
NodeInfo *numa_info = machine->numa_state->nodes;
int i;
hwaddr fdt_base;
- const CPUArchIdList *possible_cpus;
MachineClass *mc = MACHINE_GET_CLASS(machine);
- CPUState *cpu;
char *ramName = NULL;
if (!cpu_model) {
@@ -803,16 +801,41 @@ static void loongarch_init(MachineState *machine)
exit(1);
}
create_fdt(lams);
- /* Init CPUs */
- possible_cpus = mc->possible_cpu_arch_ids(machine);
- for (i = 0; i < possible_cpus->len; i++) {
- cpu = cpu_create(machine->cpu_type);
- cpu->cpu_index = i;
- machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
- lacpu = LOONGARCH_CPU(cpu);
- lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
+ /* Init CPUs */
+ mc->possible_cpu_arch_ids(machine);
+ for (i = 0; i < machine->smp.cpus; i++) {
+ Object *cpuobj;
+ cpuobj = object_new(machine->cpu_type);
+ lacpu = LOONGARCH_CPU(cpuobj);
+
+ lacpu->arch_id = machine->possible_cpus->cpus[i].arch_id;
+ object_property_set_int(cpuobj, "socket-id",
+ machine->possible_cpus->cpus[i].props.socket_id,
+ NULL);
+ object_property_set_int(cpuobj, "core-id",
+ machine->possible_cpus->cpus[i].props.core_id,
+ NULL);
+ object_property_set_int(cpuobj, "thread-id",
+ machine->possible_cpus->cpus[i].props.thread_id,
+ NULL);
+ /*
+ * The CPU in place at the time of machine startup will also enter
+ * the CPU hot-plug process when it is created, but at this time,
+ * the GED device has not been created, resulting in exit in the CPU
+ * hot-plug process, which can avoid the incumbent CPU repeatedly
+ * applying for resources.
+ *
+ * The interrupt resource of the in-place CPU will be requested at
+ * the current function call loongarch_irq_init().
+ *
+ * The interrupt resource of the subsequently inserted CPU will be
+ * requested in the CPU hot-plug process.
+ */
+ qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
+ object_unref(cpuobj);
}
+
fdt_add_cpu_nodes(lams);
/* Node0 memory */
@@ -983,6 +1006,37 @@ static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
}
+static int virt_get_arch_id_from_cpu_topo(const MachineState *ms,
+ LoongArchCPUTopo *cpu_topo)
+{
+ int arch_id, sock_vcpu_num, core_vcpu_num;
+
+ /*
+ * calculate total logical cpus across socket/core/thread.
+ * For more information on how to calculate the arch_id,
+ * you can refer to the CPU Topology chapter of the
+ * docs/system/loongarch/virt.rst document.
+ */
+ sock_vcpu_num = cpu_topo->socket_id * (ms->smp.threads * ms->smp.cores);
+ core_vcpu_num = cpu_topo->core_id * ms->smp.threads;
+
+ /* get vcpu-id(logical cpu index) for this vcpu from this topology */
+ arch_id = (sock_vcpu_num + core_vcpu_num) + cpu_topo->thread_id;
+
+ assert(arch_id >= 0 && arch_id < ms->possible_cpus->len);
+
+ return arch_id;
+}
+
+static void virt_get_cpu_topo_by_cpu_index(const MachineState *ms,
+ LoongArchCPUTopo *cpu_topo,
+ int cpu_index)
+{
+ cpu_topo->socket_id = cpu_index / (ms->smp.cores * ms->smp.threads);
+ cpu_topo->core_id = cpu_index / ms->smp.threads % ms->smp.cores;
+ cpu_topo->thread_id = cpu_index % ms->smp.threads;
+}
+
static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
@@ -1069,6 +1123,8 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
{
int n;
unsigned int max_cpus = ms->smp.max_cpus;
+ unsigned int smp_threads = ms->smp.threads;
+ LoongArchCPUTopo cpu_topo;
if (ms->possible_cpus) {
assert(ms->possible_cpus->len == max_cpus);
@@ -1079,17 +1135,20 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
for (n = 0; n < ms->possible_cpus->len; n++) {
+ ms->possible_cpus->cpus[n].vcpus_count = smp_threads;
ms->possible_cpus->cpus[n].type = ms->cpu_type;
- ms->possible_cpus->cpus[n].arch_id = n;
+
+ virt_get_cpu_topo_by_cpu_index(ms, &cpu_topo, n);
ms->possible_cpus->cpus[n].props.has_socket_id = true;
- ms->possible_cpus->cpus[n].props.socket_id =
- n / (ms->smp.cores * ms->smp.threads);
+ ms->possible_cpus->cpus[n].props.socket_id = cpu_topo.socket_id;
ms->possible_cpus->cpus[n].props.has_core_id = true;
- ms->possible_cpus->cpus[n].props.core_id =
- n / ms->smp.threads % ms->smp.cores;
+ ms->possible_cpus->cpus[n].props.core_id = cpu_topo.core_id;
ms->possible_cpus->cpus[n].props.has_thread_id = true;
- ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads;
+ ms->possible_cpus->cpus[n].props.thread_id = cpu_topo.thread_id;
+
+ ms->possible_cpus->cpus[n].arch_id =
+ virt_get_arch_id_from_cpu_topo(ms, &cpu_topo);
}
return ms->possible_cpus;
}
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index fc7f70fbe5..40b856554f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -20,6 +20,7 @@
#include "sysemu/reset.h"
#include "tcg/tcg.h"
#include "vec.h"
+#include "hw/qdev-properties.h"
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -732,10 +733,19 @@ static int64_t loongarch_cpu_get_arch_id(CPUState *cs)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
- return cpu->phy_id;
+ return cpu->arch_id;
}
#endif
+static Property loongarch_cpu_properties[] = {
+ DEFINE_PROP_INT32("socket-id", LoongArchCPU, socket_id, 0),
+ DEFINE_PROP_INT32("core-id", LoongArchCPU, core_id, 0),
+ DEFINE_PROP_INT32("thread-id", LoongArchCPU, thread_id, 0),
+ DEFINE_PROP_INT32("node-id", LoongArchCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
+
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
{
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
@@ -743,6 +753,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
+ device_class_set_props(dc, loongarch_cpu_properties);
device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
&lacc->parent_realize);
resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index f125a8e49b..838492f014 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -364,6 +364,12 @@ typedef struct CPUArchState {
#endif
} CPULoongArchState;
+typedef struct LoongArchCPUTopo {
+ int32_t socket_id; /* socket-id of this VCPU */
+ int32_t core_id; /* core-id of this VCPU */
+ int32_t thread_id; /* thread-id of this VCPU */
+} LoongArchCPUTopo;
+
/**
* LoongArchCPU:
* @env: #CPULoongArchState
@@ -375,10 +381,14 @@ struct ArchCPU {
CPUState parent_obj;
/*< public >*/
+ int32_t socket_id; /* socket-id of this VCPU */
+ int32_t core_id; /* core-id of this VCPU */
+ int32_t thread_id; /* thread-id of this VCPU */
+ int32_t node_id; /* NUMA node this CPU belongs to */
CPUNegativeOffsetState neg;
CPULoongArchState env;
QEMUTimer timer;
- uint32_t phy_id;
+ uint32_t arch_id;
/* 'compatible' string for this CPU for Linux device trees */
const char *dtb_compatible;
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 4/7] Optimize loongarch_irq_init function implementation
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
` (2 preceding siblings ...)
2023-09-26 9:54 ` [PATCH v3 3/7] Added CPU topology support for Loongarch xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 9:54 ` [PATCH v3 5/7] Add basic CPU hot-(un)plug support for Loongarch xianglai li
` (2 subsequent siblings)
6 siblings, 0 replies; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Salil Mehta, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Optimize loongarch_irq_init function implementation
and abstract the function loongarch_cpu_irq_init from it.
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
hw/loongarch/virt.c | 105 ++++++++++++++++++++----------------
include/hw/loongarch/virt.h | 5 +-
2 files changed, 62 insertions(+), 48 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b8474e7b94..fb06b4ab4e 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -46,6 +46,8 @@
#include "hw/block/flash.h"
#include "qemu/error-report.h"
+static LoongArchCPU *loongarch_cpu_irq_init(MachineState *machine,
+ LoongArchCPU *cpu, Error **errp);
static void virt_flash_create(LoongArchMachineState *lams)
{
@@ -573,16 +575,16 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
static void loongarch_irq_init(LoongArchMachineState *lams)
{
MachineState *ms = MACHINE(lams);
- DeviceState *pch_pic, *pch_msi, *cpudev;
- DeviceState *ipi, *extioi;
+ DeviceState *pch_pic, *pch_msi;
+ DeviceState *extioi;
SysBusDevice *d;
LoongArchCPU *lacpu;
- CPULoongArchState *env;
CPUState *cpu_state;
- int cpu, pin, i, start, num;
+ int cpu, i, start, num;
extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
+ lams->extioi = extioi;
/*
* The connection of interrupts:
@@ -607,44 +609,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
*/
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
cpu_state = qemu_get_cpu(cpu);
- cpudev = DEVICE(cpu_state);
lacpu = LOONGARCH_CPU(cpu_state);
- env = &(lacpu->env);
-
- ipi = qdev_new(TYPE_LOONGARCH_IPI);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
-
- /* connect ipi irq to cpu irq */
- qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI));
- /* IPI iocsr memory region */
- memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
- sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
- 0));
- memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
- sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
- 1));
- /*
- * extioi iocsr memory region
- * only one extioi is added on loongarch virt machine
- * external device interrupt can only be routed to cpu 0-3
- */
- if (cpu < EXTIOI_CPUS)
- memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
- sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
- cpu));
- env->ipistate = ipi;
- }
-
- /*
- * connect ext irq to the cpu irq
- * cpu_pin[9:2] <= intc_pin[7:0]
- */
- for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
- cpudev = DEVICE(qemu_get_cpu(cpu));
- for (pin = 0; pin < LS3A_INTC_IP; pin++) {
- qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
- qdev_get_gpio_in(cpudev, pin + 2));
- }
+ loongarch_cpu_irq_init(ms, lacpu, &error_fatal);
}
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
@@ -927,11 +893,7 @@ static void loongarch_init(MachineState *machine)
}
}
fdt_add_flash_node(lams);
- /* register reset function */
- for (i = 0; i < machine->smp.cpus; i++) {
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
- qemu_register_reset(reset_load_elf, lacpu);
- }
+
/* Initialize the IO interrupt subsystem */
loongarch_irq_init(lams);
fdt_add_irqchip_node(lams);
@@ -1091,6 +1053,57 @@ static void virt_mem_plug(HotplugHandler *hotplug_dev,
dev, &error_abort);
}
+static LoongArchCPU *loongarch_cpu_irq_init(MachineState *machine,
+ LoongArchCPU *cpu, Error **errp)
+{
+ LoongArchMachineState *lsms = LOONGARCH_MACHINE(machine);
+ CPUState *cs = CPU(cpu);
+ unsigned int cpu_index = cs->cpu_index;
+ DeviceState *cpudev = DEVICE(cpu);
+ DeviceState *extioi = lsms->extioi;
+ CPULoongArchState *env = &cpu->env;
+ DeviceState *ipi;
+ int pin;
+
+ qemu_register_reset(reset_load_elf, cpu);
+
+ ipi = qdev_new(TYPE_LOONGARCH_IPI);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), errp);
+
+ /* connect ipi irq to cpu irq */
+ qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI));
+ /* IPI iocsr memory region */
+ memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+ 0));
+ memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+ 1));
+ /*
+ * extioi iocsr memory region
+ * only one extioi is added on loongarch virt machine
+ * external device interrupt can only be routed to cpu 0-3
+ */
+ if (cpu_index < EXTIOI_CPUS)
+ memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
+ cpu_index));
+ env->ipistate = ipi;
+
+ /*
+ * connect ext irq to the cpu irq
+ * cpu_pin[9:2] <= intc_pin[7:0]
+ */
+ if (cpu_index < EXTIOI_CPUS) {
+ for (pin = 0; pin < LS3A_INTC_IP; pin++) {
+ qdev_connect_gpio_out(extioi, (cpu_index * 8 + pin),
+ qdev_get_gpio_in(cpudev, pin + 2));
+ }
+ }
+
+ return cpu;
+}
+
static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index f1659655c6..176dc43a93 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -42,7 +42,7 @@ struct LoongArchMachineState {
MemoryRegion bios;
bool bios_loaded;
/* State for other subsystems/APIs: */
- FWCfgState *fw_cfg;
+ FWCfgState *fw_cfg;
Notifier machine_done;
Notifier powerdown_notifier;
OnOffAuto acpi;
@@ -50,9 +50,10 @@ struct LoongArchMachineState {
char *oem_table_id;
DeviceState *acpi_ged;
int fdt_size;
- DeviceState *platform_bus_dev;
+ DeviceState *platform_bus_dev;
PCIBus *pci_bus;
PFlashCFI01 *flash;
+ DeviceState *extioi;
};
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 5/7] Add basic CPU hot-(un)plug support for Loongarch
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
` (3 preceding siblings ...)
2023-09-26 9:54 ` [PATCH v3 4/7] Optimize loongarch_irq_init function implementation xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 9:54 ` [PATCH v3 6/7] Add support of *unrealize* for Loongarch cpu xianglai li
2023-09-26 9:54 ` [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU xianglai li
6 siblings, 0 replies; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Salil Mehta, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Add CPU hot-(un)plug related hook functions and
turn on the CPU hot-(un)plug custom switch.
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
.../devices/loongarch64-softmmu/default.mak | 1 +
hw/loongarch/virt.c | 210 ++++++++++++++++++
2 files changed, 211 insertions(+)
diff --git a/configs/devices/loongarch64-softmmu/default.mak b/configs/devices/loongarch64-softmmu/default.mak
index 928bc117ef..e596706fab 100644
--- a/configs/devices/loongarch64-softmmu/default.mak
+++ b/configs/devices/loongarch64-softmmu/default.mak
@@ -1,3 +1,4 @@
# Default configuration for loongarch64-softmmu
CONFIG_LOONGARCH_VIRT=y
+CONFIG_ACPI_CPU_HOTPLUG=y
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index fb06b4ab4e..c704f3117f 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -999,11 +999,93 @@ static void virt_get_cpu_topo_by_cpu_index(const MachineState *ms,
cpu_topo->thread_id = cpu_index % ms->smp.threads;
}
+/* find cpu slot in machine->possible_cpus by arch_id */
+static CPUArchId *loongarch_find_cpu_slot(MachineState *ms, int arch_id)
+{
+ int n;
+ for (n = 0; n < ms->possible_cpus->len; n++) {
+ if (ms->possible_cpus->cpus[n].arch_id == arch_id) {
+ return &ms->possible_cpus->cpus[n];
+ }
+ }
+
+ return NULL;
+}
+
+static void loongarch_cpu_pre_plug(HotplugHandler *hotplug_dev,
+ DeviceState *dev, Error **errp)
+{
+ MachineState *ms = MACHINE(OBJECT(hotplug_dev));
+ MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
+ LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+ CPUState *cs = CPU(dev);
+ CPUArchId *cpu_slot;
+ Error *local_err = NULL;
+ LoongArchCPUTopo cpu_topo;
+ int arch_id;
+
+ if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
+ error_setg(&local_err, "CPU hotplug not supported for this machine");
+ goto out;
+ }
+
+ /* sanity check the cpu */
+ if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
+ error_setg(&local_err, "Invalid CPU type, expected cpu type: '%s'",
+ ms->cpu_type);
+ goto out;
+ }
+
+ if ((cpu->thread_id < 0) || (cpu->thread_id >= ms->smp.threads)) {
+ error_setg(&local_err,
+ "Invalid thread-id %u specified, must be in range 1:%u",
+ cpu->thread_id, ms->smp.threads - 1);
+ goto out;
+ }
+
+ if ((cpu->core_id < 0) || (cpu->core_id >= ms->smp.cores)) {
+ error_setg(&local_err,
+ "Invalid core-id %u specified, must be in range 1:%u",
+ cpu->core_id, ms->smp.cores);
+ goto out;
+ }
+
+ if ((cpu->socket_id < 0) || (cpu->socket_id >= ms->smp.sockets)) {
+ error_setg(&local_err,
+ "Invalid socket-id %u specified, must be in range 1:%u",
+ cpu->socket_id, ms->smp.sockets - 1);
+ goto out;
+ }
+
+ cpu_topo.socket_id = cpu->socket_id;
+ cpu_topo.core_id = cpu->core_id;
+ cpu_topo.thread_id = cpu->thread_id;
+ arch_id = virt_get_arch_id_from_cpu_topo(ms, &cpu_topo);
+
+ cpu_slot = loongarch_find_cpu_slot(ms, arch_id);
+ if (CPU(cpu_slot->cpu)) {
+ error_setg(&local_err,
+ "cpu(id%d=%d:%d:%d) with arch-id %" PRIu64 " exists",
+ cs->cpu_index, cpu->socket_id, cpu->core_id,
+ cpu->thread_id, cpu_slot->arch_id);
+ goto out;
+ }
+ cpu->arch_id = arch_id;
+
+ numa_cpu_pre_plug(cpu_slot, dev, &local_err);
+
+ return ;
+out:
+ error_propagate(errp, local_err);
+}
+
static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
if (memhp_type_supported(dev)) {
virt_mem_pre_plug(hotplug_dev, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) {
+ loongarch_cpu_pre_plug(hotplug_dev, dev, errp);
}
}
@@ -1017,11 +1099,45 @@ static void virt_mem_unplug_request(HotplugHandler *hotplug_dev,
errp);
}
+static void loongarch_cpu_unplug_request(HotplugHandler *hotplug_dev,
+ DeviceState *dev, Error **errp)
+{
+ MachineState *machine = MACHINE(OBJECT(hotplug_dev));
+ LoongArchMachineState *lsms = LOONGARCH_MACHINE(machine);
+ Error *local_err = NULL;
+ HotplugHandlerClass *hhc;
+ LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+ CPUState *cs = CPU(dev);
+
+ if (!lsms->acpi_ged) {
+ error_setg(&local_err, "CPU hot unplug not supported without ACPI");
+ goto out;
+ }
+
+ if (cs->cpu_index == 0) {
+ error_setg(&local_err,
+ "hot-unplug of boot cpu(id%d=%d:%d:%d) not supported",
+ cs->cpu_index, cpu->socket_id,
+ cpu->core_id, cpu->thread_id);
+ goto out;
+ }
+
+
+ hhc = HOTPLUG_HANDLER_GET_CLASS(lsms->acpi_ged);
+ hhc->unplug_request(HOTPLUG_HANDLER(lsms->acpi_ged), dev, &local_err);
+
+ return;
+ out:
+ error_propagate(errp, local_err);
+}
+
static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
if (memhp_type_supported(dev)) {
virt_mem_unplug_request(hotplug_dev, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) {
+ loongarch_cpu_unplug_request(hotplug_dev, dev, errp);
}
}
@@ -1035,11 +1151,74 @@ static void virt_mem_unplug(HotplugHandler *hotplug_dev,
qdev_unrealize(dev);
}
+static void loongarch_cpu_irq_uninit(MachineState *machine,
+ LoongArchCPU *cpu)
+{
+ LoongArchMachineState *lsms = LOONGARCH_MACHINE(machine);
+ CPULoongArchState *env = &cpu->env;
+ DeviceState *ipi = env->ipistate;
+ CPUState *cs = CPU(cpu);
+ unsigned int cpu_index = cs->cpu_index;
+ DeviceState *extioi = lsms->extioi;
+
+ qemu_unregister_reset(reset_load_elf, DEVICE(cpu));
+
+ /* del IPI iocsr memory region */
+ memory_region_del_subregion(&env->system_iocsr,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+ 0));
+ memory_region_del_subregion(&env->system_iocsr,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+ 1));
+
+ env->ipistate = NULL;
+ object_unparent(OBJECT(ipi));
+
+ /*
+ * del extioi iocsr memory region
+ * only one extioi is added on loongarch virt machine
+ * external device interrupt can only be routed to cpu 0-3
+ */
+ if (cpu_index < EXTIOI_CPUS)
+ memory_region_del_subregion(&env->system_iocsr,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
+ cpu_index));
+}
+
+static void loongarch_cpu_unplug(HotplugHandler *hotplug_dev,
+ DeviceState *dev, Error **errp)
+{
+ CPUArchId *found_cpu;
+ HotplugHandlerClass *hhc;
+ Error *local_err = NULL;
+ LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+ MachineState *machine = MACHINE(OBJECT(hotplug_dev));
+ LoongArchMachineState *lsms = LOONGARCH_MACHINE(machine);
+
+ hhc = HOTPLUG_HANDLER_GET_CLASS(lsms->acpi_ged);
+ hhc->unplug(HOTPLUG_HANDLER(lsms->acpi_ged), dev, &local_err);
+
+ if (local_err) {
+ goto out;
+ }
+
+ loongarch_cpu_irq_uninit(machine, cpu);
+
+ found_cpu = loongarch_find_cpu_slot(MACHINE(lsms), cpu->arch_id);
+ found_cpu->cpu = NULL;
+
+ return;
+out:
+ error_propagate(errp, local_err);
+}
+
static void virt_machine_device_unplug(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
if (memhp_type_supported(dev)) {
virt_mem_unplug(hotplug_dev, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) {
+ loongarch_cpu_unplug(hotplug_dev, dev, errp);
}
}
@@ -1104,6 +1283,33 @@ static LoongArchCPU *loongarch_cpu_irq_init(MachineState *machine,
return cpu;
}
+static void loongarch_cpu_plug(HotplugHandler *hotplug_dev,
+ DeviceState *dev, Error **errp)
+{
+ CPUArchId *found_cpu;
+ HotplugHandlerClass *hhc;
+ Error *local_err = NULL;
+ MachineState *machine = MACHINE(OBJECT(hotplug_dev));
+ LoongArchMachineState *lsms = LOONGARCH_MACHINE(machine);
+ LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+
+ if (lsms->acpi_ged) {
+ loongarch_cpu_irq_init(machine, cpu, errp);
+ hhc = HOTPLUG_HANDLER_GET_CLASS(lsms->acpi_ged);
+ hhc->plug(HOTPLUG_HANDLER(lsms->acpi_ged), dev, &local_err);
+ if (local_err) {
+ goto out;
+ }
+ }
+
+ found_cpu = loongarch_find_cpu_slot(MACHINE(lsms), cpu->arch_id);
+ found_cpu->cpu = OBJECT(dev);
+
+ return;
+out:
+ error_propagate(errp, local_err);
+}
+
static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp)
{
@@ -1117,6 +1323,8 @@ static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev,
}
} else if (memhp_type_supported(dev)) {
virt_mem_plug(hotplug_dev, dev, errp);
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU)) {
+ loongarch_cpu_plug(hotplug_dev, dev, errp);
}
}
@@ -1126,6 +1334,7 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (device_is_dynamic_sysbus(mc, dev) ||
+ object_dynamic_cast(OBJECT(dev), TYPE_LOONGARCH_CPU) ||
memhp_type_supported(dev)) {
return HOTPLUG_HANDLER(machine);
}
@@ -1194,6 +1403,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
+ mc->has_hotpluggable_cpus = true;
mc->desc = "Loongson-3A5000 LS7A1000 machine";
mc->init = loongarch_init;
mc->default_ram_size = 1 * GiB;
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 6/7] Add support of *unrealize* for Loongarch cpu
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
` (4 preceding siblings ...)
2023-09-26 9:54 ` [PATCH v3 5/7] Add basic CPU hot-(un)plug support for Loongarch xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 9:54 ` [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU xianglai li
6 siblings, 0 replies; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Salil Mehta, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Add the unrealize function to the Loongarch CPU for cpu hot-(un)plug
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
target/loongarch/cpu.c | 20 ++++++++++++++++++++
target/loongarch/cpu.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 40b856554f..92fb23704f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -576,6 +576,22 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
lacc->parent_realize(dev, errp);
}
+static void loongarch_cpu_unrealizefn(DeviceState *dev)
+{
+ LoongArchCPUClass *mcc = LOONGARCH_CPU_GET_CLASS(dev);
+
+#ifndef CONFIG_USER_ONLY
+ LoongArchCPU *cpu = LOONGARCH_CPU(dev);
+ CPULoongArchState *env = &cpu->env;
+
+ cpu_remove_sync(CPU(dev));
+ address_space_destroy(&env->address_space_iocsr);
+ memory_region_del_subregion(&env->system_iocsr, &env->iocsr_mem);
+#endif
+
+ mcc->parent_unrealize(dev);
+}
+
#ifndef CONFIG_USER_ONLY
static void loongarch_qemu_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
@@ -756,6 +772,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, loongarch_cpu_properties);
device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
&lacc->parent_realize);
+ device_class_set_parent_unrealize(dc, loongarch_cpu_unrealizefn,
+ &lacc->parent_unrealize);
+
resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
&lacc->parent_phases);
@@ -777,6 +796,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;
#endif
+ dc->user_creatable = true;
}
static gchar *loongarch32_gdb_arch_name(CPUState *cs)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 838492f014..ec4a9ff166 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -414,6 +414,7 @@ struct LoongArchCPUClass {
/*< public >*/
DeviceRealize parent_realize;
+ DeviceUnrealize parent_unrealize;
ResettablePhases parent_phases;
};
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
` (5 preceding siblings ...)
2023-09-26 9:54 ` [PATCH v3 6/7] Add support of *unrealize* for Loongarch cpu xianglai li
@ 2023-09-26 9:54 ` xianglai li
2023-09-26 10:58 ` Salil Mehta via
6 siblings, 1 reply; 32+ messages in thread
From: xianglai li @ 2023-09-26 9:54 UTC (permalink / raw)
To: qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Salil Mehta, Xiaojuan Yang,
Song Gao, Michael S. Tsirkin, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé,
Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Add new types of GED devices for Loongarch machines,
add CPU hot-(un)plug event response and address spaces,
and update the ACPI table.
Cc: "Bernhard Beschow" <shentey@gmail.com>
Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
Cc: "Salil Mehta" <salil.mehta@huawei.com>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: Song Gao <gaosong@loongson.cn>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Eduardo Habkost <eduardo@habkost.net>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Yanan Wang <wangyanan55@huawei.com>
Cc: "Daniel P. Berrangé" <berrange@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Cc: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: xianglai li <lixianglai@loongson.cn>
---
hw/acpi/acpi-cpu-hotplug-stub.c | 9 +++++++++
hw/loongarch/acpi-build.c | 34 ++++++++++++++++++++++++++++++++-
hw/loongarch/virt.c | 3 ++-
include/hw/loongarch/virt.h | 1 +
4 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c
index 2aec90d968..b3ac7a1e31 100644
--- a/hw/acpi/acpi-cpu-hotplug-stub.c
+++ b/hw/acpi/acpi-cpu-hotplug-stub.c
@@ -19,6 +19,15 @@ void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner,
return;
}
+void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
+ build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
+ const char *res_root,
+ const char *event_handler_method,
+ AmlRegionSpace rs)
+{
+ return;
+}
+
void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list)
{
return;
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index ae292fc543..cf89e5c1cb 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -46,6 +46,23 @@
#define ACPI_BUILD_DPRINTF(fmt, ...)
#endif
+static void virt_madt_cpu_entry(int uid,
+ const CPUArchIdList *apic_ids,
+ GArray *entry, bool force_enabled)
+{
+ uint32_t apic_id = apic_ids->cpus[uid].arch_id;
+ /* Flags – Local APIC Flags */
+ uint32_t flags = apic_ids->cpus[uid].cpu != NULL || force_enabled ?
+ 1 /* Enabled */ : 0;
+
+ /* Rev 1.0b, Table 5-13 Processor Local APIC Structure */
+ build_append_int_noprefix(entry, 0, 1); /* Type */
+ build_append_int_noprefix(entry, 8, 1); /* Length */
+ build_append_int_noprefix(entry, uid, 1); /* ACPI Processor ID */
+ build_append_int_noprefix(entry, apic_id, 1); /* APIC ID */
+ build_append_int_noprefix(entry, flags, 4); /* Flags */
+}
+
/* build FADT */
static void init_common_fadt_data(AcpiFadtData *data)
{
@@ -121,15 +138,18 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
for (i = 0; i < arch_ids->len; i++) {
+ uint32_t flags;
+
/* Processor Core Interrupt Controller Structure */
arch_id = arch_ids->cpus[i].arch_id;
+ flags = arch_ids->cpus[i].cpu ? 1 : 0;
build_append_int_noprefix(table_data, 17, 1); /* Type */
build_append_int_noprefix(table_data, 15, 1); /* Length */
build_append_int_noprefix(table_data, 1, 1); /* Version */
build_append_int_noprefix(table_data, i, 4); /* ACPI Processor ID */
build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */
- build_append_int_noprefix(table_data, 1, 4); /* Flags */
+ build_append_int_noprefix(table_data, flags, 4); /* Flags */
}
/* Extend I/O Interrupt Controller Structure */
@@ -292,6 +312,18 @@ build_la_ged_aml(Aml *dsdt, MachineState *machine)
AML_SYSTEM_MEMORY,
VIRT_GED_MEM_ADDR);
}
+
+ if (event & ACPI_GED_CPU_HOTPLUG_EVT) {
+ CPUHotplugFeatures opts = {
+ .acpi_1_compatible = false,
+ .has_legacy_cphp = false
+ };
+
+ build_cpus_aml(dsdt, machine, opts, virt_madt_cpu_entry,
+ VIRT_GED_CPUHP_ADDR, "\\_SB", "\\_GPE._E01",
+ AML_SYSTEM_MEMORY);
+
+ }
acpi_dsdt_add_power_button(dsdt);
}
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index c704f3117f..22b287eb39 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -449,7 +449,7 @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
{
DeviceState *dev;
MachineState *ms = MACHINE(lams);
- uint32_t event = ACPI_GED_PWR_DOWN_EVT;
+ uint32_t event = ACPI_GED_PWR_DOWN_EVT | ACPI_GED_CPU_HOTPLUG_EVT;
if (ms->ram_slots) {
event |= ACPI_GED_MEM_HOTPLUG_EVT;
@@ -463,6 +463,7 @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR);
/* ged regs used for reset and power down */
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 3, VIRT_GED_CPUHP_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE));
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index 176dc43a93..e23a45f9bb 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -31,6 +31,7 @@
#define VIRT_GED_EVT_ADDR 0x100e0000
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
+#define VIRT_GED_CPUHP_ADDR (VIRT_GED_REG_ADDR + ACPI_CPU_HOTPLUG_REG_LEN)
struct LoongArchMachineState {
/*< private >*/
--
2.39.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* RE: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 9:54 ` [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change xianglai li
@ 2023-09-26 10:49 ` Salil Mehta via
2023-09-26 11:12 ` Michael S. Tsirkin
2023-09-26 12:17 ` lixianglai
0 siblings, 2 replies; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 10:49 UTC (permalink / raw)
To: xianglai li, qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Xiaojuan Yang, Song Gao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Xianglai,
FYI. RFC V2 is out and you can now drop the arch agnostic patches from
your patch-set. Please check the details in the cover letter which one
you need to pick and rebase from:
https://lore.kernel.org/qemu-devel/20230926100436.28284-1-salil.mehta@huawei.com/T/#t
I am planning to float the architecture agnostic patch-set within this
week which will have same patches and in same order as mentioned in
the cover letter. This will untie the development across different
architectures.
Many thanks
Salil.
> From: xianglai li <lixianglai@loongson.cn>
> Sent: Tuesday, September 26, 2023 10:54 AM
> To: qemu-devel@nongnu.org
> Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>; Xiaojuan
> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
> <maobibo@loongson.cn>
> Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
> is based on PCI and is IO port based and hence existing cpus AML code
> assumes _CRS objects would evaluate to a system resource which describes
> IO Port address.
> But on Loongarch arch CPUs control device(\\_SB.PRES) register interface
> is memory-mapped hence _CRS object should evaluate to system resource
> which describes memory-mapped base address.
>
> This cpus AML code change updates the existing interface of the build cpus
> AML
> function to accept both IO/MEMORY type regions and update the _CRS object
> correspondingly.
>
> Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Bernhard Beschow" <shentey@gmail.com>
> Cc: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Cc: Song Gao <gaosong@loongson.cn>
> Cc: "Michael S. Tsirkin" <mst@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Ani Sinha <anisinha@redhat.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Eduardo Habkost <eduardo@habkost.net>
> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> Cc: Yanan Wang <wangyanan55@huawei.com>
> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> Cc: Peter Xu <peterx@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Bibo Mao <maobibo@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> ---
> hw/acpi/cpu.c | 20 +++++++++++++++-----
> hw/i386/acpi-build.c | 3 ++-
> include/hw/acpi/cpu.h | 5 +++--
> 3 files changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> index 5bad983928..0afa04832e 100644
> --- a/hw/acpi/cpu.c
> +++ b/hw/acpi/cpu.c
> @@ -6,6 +6,7 @@
> #include "qapi/qapi-events-acpi.h"
> #include "trace.h"
> #include "sysemu/numa.h"
> +#include "hw/acpi/cpu_hotplug.h"
>
> #define OVMF_CPUHP_SMI_CMD 4
>
> @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
> #define CPU_FW_EJECT_EVENT "CEJF"
>
> void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
> opts,
> - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
> const char *res_root,
> - const char *event_handler_method)
> + const char *event_handler_method,
> + AmlRegionSpace rs)
> {
> Aml *ifctx;
> Aml *field;
> @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
> *machine, CPUHotplugFeatures opts,
> aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
>
> crs = aml_resource_template();
> - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
> + if (rs == AML_SYSTEM_IO) {
> + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
> mmap_io_base, 1,
> ACPI_CPU_HOTPLUG_REG_LEN));
> + } else {
> + aml_append(crs, aml_memory32_fixed(mmap_io_base,
> + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE));
> + }
> +
> aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
>
> + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
> /* declare CPU hotplug MMIO region with related access fields */
> aml_append(cpu_ctrl_dev,
> - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base),
> - ACPI_CPU_HOTPLUG_REG_LEN));
> + aml_operation_region("PRST", rs,
> + aml_int(mmap_io_base),
> + ACPI_CPU_HOTPLUG_REG_LEN));
>
> field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
> AML_WRITE_AS_ZEROS);
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 863a939210..7016205d15 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
> };
> build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
> - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02");
> + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
> + AML_SYSTEM_IO);
> }
>
> if (pcms->memhp_io_base && nr_mem) {
> diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
> index bc901660fb..601f644e57 100644
> --- a/include/hw/acpi/cpu.h
> +++ b/include/hw/acpi/cpu.h
> @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
> CPUArchIdList *apic_ids,
> GArray *entry, bool force_enabled);
>
> void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
> opts,
> - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
> const char *res_root,
> - const char *event_handler_method);
> + const char *event_handler_method,
> + AmlRegionSpace rs);
>
> void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> ***list);
>
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
@ 2023-09-26 10:50 ` Salil Mehta via
2023-09-26 12:16 ` lixianglai
2023-09-26 11:02 ` Michael S. Tsirkin
2023-09-26 12:03 ` Michael S. Tsirkin
2 siblings, 1 reply; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 10:50 UTC (permalink / raw)
To: xianglai li, qemu-devel
Cc: Salil Mehta, Bernhard Beschow, Xiaojuan Yang, Song Gao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Same with this patch. It already exists in the architecture agnostic
patches part of below:
https://lore.kernel.org/qemu-devel/20230926100436.28284-1-salil.mehta@huawei.com/T/#t
Thanks
Salil.
> From: xianglai li <lixianglai@loongson.cn>
> Sent: Tuesday, September 26, 2023 10:54 AM
> To: qemu-devel@nongnu.org
> Cc: Salil Mehta <salil.mehta@opnsrc.net>; Salil Mehta
> <salil.mehta@huawei.com>; Bernhard Beschow <shentey@gmail.com>; Xiaojuan
> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
> <maobibo@loongson.cn>
> Subject: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-
> (un)plug
>
> ACPI GED shall be used to convey to the guest kernel about any cpu hot-
> (un)plug
> events. Therefore, existing ACPI GED framework inside QEMU needs to be
> enhanced
> to support CPU hot-(un)plug state and events.
>
> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Bernhard Beschow" <shentey@gmail.com>
> Cc: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Cc: Song Gao <gaosong@loongson.cn>
> Cc: "Michael S. Tsirkin" <mst@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Ani Sinha <anisinha@redhat.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Eduardo Habkost <eduardo@habkost.net>
> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> Cc: Yanan Wang <wangyanan55@huawei.com>
> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> Cc: Peter Xu <peterx@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Bibo Mao <maobibo@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> ---
> hw/acpi/acpi-cpu-hotplug-stub.c | 6 +++++
> hw/acpi/cpu.c | 7 ------
> hw/acpi/generic_event_device.c | 33 ++++++++++++++++++++++++++
> include/hw/acpi/cpu_hotplug.h | 10 ++++++++
> include/hw/acpi/generic_event_device.h | 5 ++++
> 5 files changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-
> stub.c
> index 3fc4b14c26..2aec90d968 100644
> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
> @@ -24,6 +24,12 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st,
> ACPIOSTInfoList ***list)
> return;
> }
>
> +void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
> + CPUHotplugState *state, hwaddr base_addr)
> +{
> + return;
> +}
> +
> void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev,
> CPUHotplugState *cpu_st, DeviceState *dev, Error
> **errp)
> {
> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> index 011d2c6c2d..5bad983928 100644
> --- a/hw/acpi/cpu.c
> +++ b/hw/acpi/cpu.c
> @@ -7,13 +7,6 @@
> #include "trace.h"
> #include "sysemu/numa.h"
>
> -#define ACPI_CPU_HOTPLUG_REG_LEN 12
> -#define ACPI_CPU_SELECTOR_OFFSET_WR 0
> -#define ACPI_CPU_FLAGS_OFFSET_RW 4
> -#define ACPI_CPU_CMD_OFFSET_WR 5
> -#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
> -#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
> -
> #define OVMF_CPUHP_SMI_CMD 4
>
> enum {
> diff --git a/hw/acpi/generic_event_device.c
> b/hw/acpi/generic_event_device.c
> index a3d31631fe..c5a70957b4 100644
> --- a/hw/acpi/generic_event_device.c
> +++ b/hw/acpi/generic_event_device.c
> @@ -12,6 +12,7 @@
> #include "qemu/osdep.h"
> #include "qapi/error.h"
> #include "hw/acpi/acpi.h"
> +#include "hw/acpi/cpu.h"
> #include "hw/acpi/generic_event_device.h"
> #include "hw/irq.h"
> #include "hw/mem/pc-dimm.h"
> @@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] = {
> ACPI_GED_MEM_HOTPLUG_EVT,
> ACPI_GED_PWR_DOWN_EVT,
> ACPI_GED_NVDIMM_HOTPLUG_EVT,
> + ACPI_GED_CPU_HOTPLUG_EVT,
> };
>
> /*
> @@ -117,6 +119,10 @@ void build_ged_aml(Aml *table, const char *name,
> HotplugHandler *hotplug_dev,
> aml_notify(aml_name("\\_SB.NVDR"),
> aml_int(0x80)));
> break;
> + case ACPI_GED_CPU_HOTPLUG_EVT:
> + aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "."
> + ACPI_CPU_SCAN_METHOD));
> + break;
> default:
> /*
> * Please make sure all the events in
> ged_supported_events[]
> @@ -234,6 +240,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler
> *hotplug_dev,
> } else {
> acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp);
> }
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "virt: device plug request for unsupported
> device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -248,6 +256,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler
> *hotplug_dev,
> if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
> !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM))))
> {
> acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev,
> errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev,
> errp);
> } else {
> error_setg(errp, "acpi: device unplug request for unsupported
> device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -261,6 +271,8 @@ static void acpi_ged_unplug_cb(HotplugHandler
> *hotplug_dev,
>
> if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
> acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "acpi: device unplug for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -272,6 +284,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev,
> ACPIOSTInfoList ***list)
> AcpiGedState *s = ACPI_GED(adev);
>
> acpi_memory_ospm_status(&s->memhp_state, list);
> + acpi_cpu_ospm_status(&s->cpuhp_state, list);
> }
>
> static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits
> ev)
> @@ -286,6 +299,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev,
> AcpiEventStatusBits ev)
> sel = ACPI_GED_PWR_DOWN_EVT;
> } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) {
> sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
> + } else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
> + sel = ACPI_GED_CPU_HOTPLUG_EVT;
> } else {
> /* Unknown event. Return without generating interrupt. */
> warn_report("GED: Unsupported event %d. No irq injected", ev);
> @@ -318,6 +333,16 @@ static const VMStateDescription vmstate_memhp_state =
> {
> }
> };
>
> +static const VMStateDescription vmstate_cpuhp_state = {
> + .name = "acpi-ged/cpuhp",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static const VMStateDescription vmstate_ged_state = {
> .name = "acpi-ged-state",
> .version_id = 1,
> @@ -366,6 +391,7 @@ static const VMStateDescription vmstate_acpi_ged = {
> },
> .subsections = (const VMStateDescription * []) {
> &vmstate_memhp_state,
> + &vmstate_cpuhp_state,
> &vmstate_ghes_state,
> NULL
> }
> @@ -400,6 +426,13 @@ static void acpi_ged_initfn(Object *obj)
> memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
> TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
> sysbus_init_mmio(sbd, &ged_st->regs);
> +
> + s->cpuhp.device = OBJECT(s);
> + memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp
> container",
> + ACPI_CPU_HOTPLUG_REG_LEN);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container_cpuhp);
> + cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
> + &s->cpuhp_state, 0);
> }
>
> static void acpi_ged_class_init(ObjectClass *class, void *data)
> diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
> index 3b932abbbb..afee1ab996 100644
> --- a/include/hw/acpi/cpu_hotplug.h
> +++ b/include/hw/acpi/cpu_hotplug.h
> @@ -19,6 +19,16 @@
> #include "hw/hotplug.h"
> #include "hw/acpi/cpu.h"
>
> +#define ACPI_CPU_HOTPLUG_REG_LEN 12
> +#define ACPI_CPU_SELECTOR_OFFSET_WR 0
> +#define ACPI_CPU_FLAGS_OFFSET_RW 4
> +#define ACPI_CPU_CMD_OFFSET_WR 5
> +#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
> +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
> +
> +#define ACPI_CPU_SCAN_METHOD "CSCN"
> +#define ACPI_CPU_CONTAINER "\\_SB.CPUS"
> +
> typedef struct AcpiCpuHotplug {
> Object *device;
> MemoryRegion io;
> diff --git a/include/hw/acpi/generic_event_device.h
> b/include/hw/acpi/generic_event_device.h
> index ba84ce0214..a803ea818e 100644
> --- a/include/hw/acpi/generic_event_device.h
> +++ b/include/hw/acpi/generic_event_device.h
> @@ -60,6 +60,7 @@
> #define HW_ACPI_GENERIC_EVENT_DEVICE_H
>
> #include "hw/sysbus.h"
> +#include "hw/acpi/cpu_hotplug.h"
> #include "hw/acpi/memory_hotplug.h"
> #include "hw/acpi/ghes.h"
> #include "qom/object.h"
> @@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
> #define ACPI_GED_MEM_HOTPLUG_EVT 0x1
> #define ACPI_GED_PWR_DOWN_EVT 0x2
> #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
> +#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
>
> typedef struct GEDState {
> MemoryRegion evt;
> @@ -106,6 +108,9 @@ struct AcpiGedState {
> SysBusDevice parent_obj;
> MemHotplugState memhp_state;
> MemoryRegion container_memhp;
> + CPUHotplugState cpuhp_state;
> + MemoryRegion container_cpuhp;
> + AcpiCpuHotplug cpuhp;
> GEDState ged_state;
> uint32_t ged_event_bitmap;
> qemu_irq irq;
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU
2023-09-26 9:54 ` [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU xianglai li
@ 2023-09-26 10:58 ` Salil Mehta via
2023-09-27 2:26 ` lixianglai
0 siblings, 1 reply; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 10:58 UTC (permalink / raw)
To: xianglai li, qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Xiaojuan Yang, Song Gao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Xianglai,
> From: xianglai li <lixianglai@loongson.cn>
> Sent: Tuesday, September 26, 2023 10:55 AM
> To: qemu-devel@nongnu.org
> Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>; Xiaojuan
> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
> <maobibo@loongson.cn>
> Subject: [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU
>
> Add new types of GED devices for Loongarch machines,
> add CPU hot-(un)plug event response and address spaces,
> and update the ACPI table.
>
> Cc: "Bernhard Beschow" <shentey@gmail.com>
> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> Cc: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Cc: Song Gao <gaosong@loongson.cn>
> Cc: "Michael S. Tsirkin" <mst@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Ani Sinha <anisinha@redhat.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Eduardo Habkost <eduardo@habkost.net>
> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> Cc: Yanan Wang <wangyanan55@huawei.com>
> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> Cc: Peter Xu <peterx@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Bibo Mao <maobibo@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> ---
> hw/acpi/acpi-cpu-hotplug-stub.c | 9 +++++++++
> hw/loongarch/acpi-build.c | 34 ++++++++++++++++++++++++++++++++-
> hw/loongarch/virt.c | 3 ++-
> include/hw/loongarch/virt.h | 1 +
> 4 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-
> stub.c
> index 2aec90d968..b3ac7a1e31 100644
> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
> @@ -19,6 +19,15 @@ void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent,
> Object *owner,
> return;
> }
>
> +void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
> opts,
> + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
> + const char *res_root,
> + const char *event_handler_method,
> + AmlRegionSpace rs)
> +{
> + return;
> +}
> +
> void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> ***list)
> {
> return;
Above change is already part of the architecture agnostic patch-set.
Not required here!
Thanks
Salil.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
2023-09-26 10:50 ` Salil Mehta via
@ 2023-09-26 11:02 ` Michael S. Tsirkin
2023-09-26 11:26 ` lixianglai
2023-09-26 12:03 ` Michael S. Tsirkin
2 siblings, 1 reply; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 11:02 UTC (permalink / raw)
To: xianglai li
Cc: qemu-devel, Salil Mehta, Salil Mehta, Bernhard Beschow,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 05:54:26PM +0800, xianglai li wrote:
> ACPI GED shall be used to convey to the guest kernel about any cpu hot-(un)plug
> events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced
> to support CPU hot-(un)plug state and events.
>
> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
This is not the way to handle multiple emails.
> Cc: "Bernhard Beschow" <shentey@gmail.com>
> Cc: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Cc: Song Gao <gaosong@loongson.cn>
> Cc: "Michael S. Tsirkin" <mst@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Ani Sinha <anisinha@redhat.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Eduardo Habkost <eduardo@habkost.net>
> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> Cc: Yanan Wang <wangyanan55@huawei.com>
> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> Cc: Peter Xu <peterx@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Bibo Mao <maobibo@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
> ---
> hw/acpi/acpi-cpu-hotplug-stub.c | 6 +++++
> hw/acpi/cpu.c | 7 ------
> hw/acpi/generic_event_device.c | 33 ++++++++++++++++++++++++++
> include/hw/acpi/cpu_hotplug.h | 10 ++++++++
> include/hw/acpi/generic_event_device.h | 5 ++++
> 5 files changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c
> index 3fc4b14c26..2aec90d968 100644
> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
> @@ -24,6 +24,12 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list)
> return;
> }
>
> +void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
> + CPUHotplugState *state, hwaddr base_addr)
> +{
> + return;
> +}
> +
> void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev,
> CPUHotplugState *cpu_st, DeviceState *dev, Error **errp)
> {
> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> index 011d2c6c2d..5bad983928 100644
> --- a/hw/acpi/cpu.c
> +++ b/hw/acpi/cpu.c
> @@ -7,13 +7,6 @@
> #include "trace.h"
> #include "sysemu/numa.h"
>
> -#define ACPI_CPU_HOTPLUG_REG_LEN 12
> -#define ACPI_CPU_SELECTOR_OFFSET_WR 0
> -#define ACPI_CPU_FLAGS_OFFSET_RW 4
> -#define ACPI_CPU_CMD_OFFSET_WR 5
> -#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
> -#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
> -
> #define OVMF_CPUHP_SMI_CMD 4
>
> enum {
> diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
> index a3d31631fe..c5a70957b4 100644
> --- a/hw/acpi/generic_event_device.c
> +++ b/hw/acpi/generic_event_device.c
> @@ -12,6 +12,7 @@
> #include "qemu/osdep.h"
> #include "qapi/error.h"
> #include "hw/acpi/acpi.h"
> +#include "hw/acpi/cpu.h"
> #include "hw/acpi/generic_event_device.h"
> #include "hw/irq.h"
> #include "hw/mem/pc-dimm.h"
> @@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] = {
> ACPI_GED_MEM_HOTPLUG_EVT,
> ACPI_GED_PWR_DOWN_EVT,
> ACPI_GED_NVDIMM_HOTPLUG_EVT,
> + ACPI_GED_CPU_HOTPLUG_EVT,
> };
>
> /*
> @@ -117,6 +119,10 @@ void build_ged_aml(Aml *table, const char *name, HotplugHandler *hotplug_dev,
> aml_notify(aml_name("\\_SB.NVDR"),
> aml_int(0x80)));
> break;
> + case ACPI_GED_CPU_HOTPLUG_EVT:
> + aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "."
> + ACPI_CPU_SCAN_METHOD));
> + break;
> default:
> /*
> * Please make sure all the events in ged_supported_events[]
> @@ -234,6 +240,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
> } else {
> acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp);
> }
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "virt: device plug request for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -248,6 +256,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
> if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
> !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
> acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "acpi: device unplug request for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -261,6 +271,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
>
> if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
> acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "acpi: device unplug for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -272,6 +284,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
> AcpiGedState *s = ACPI_GED(adev);
>
> acpi_memory_ospm_status(&s->memhp_state, list);
> + acpi_cpu_ospm_status(&s->cpuhp_state, list);
> }
>
> static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
> @@ -286,6 +299,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
> sel = ACPI_GED_PWR_DOWN_EVT;
> } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) {
> sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
> + } else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
> + sel = ACPI_GED_CPU_HOTPLUG_EVT;
> } else {
> /* Unknown event. Return without generating interrupt. */
> warn_report("GED: Unsupported event %d. No irq injected", ev);
> @@ -318,6 +333,16 @@ static const VMStateDescription vmstate_memhp_state = {
> }
> };
>
> +static const VMStateDescription vmstate_cpuhp_state = {
> + .name = "acpi-ged/cpuhp",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static const VMStateDescription vmstate_ged_state = {
> .name = "acpi-ged-state",
> .version_id = 1,
> @@ -366,6 +391,7 @@ static const VMStateDescription vmstate_acpi_ged = {
> },
> .subsections = (const VMStateDescription * []) {
> &vmstate_memhp_state,
> + &vmstate_cpuhp_state,
> &vmstate_ghes_state,
> NULL
> }
> @@ -400,6 +426,13 @@ static void acpi_ged_initfn(Object *obj)
> memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
> TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
> sysbus_init_mmio(sbd, &ged_st->regs);
> +
> + s->cpuhp.device = OBJECT(s);
> + memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp container",
> + ACPI_CPU_HOTPLUG_REG_LEN);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container_cpuhp);
> + cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
> + &s->cpuhp_state, 0);
> }
>
> static void acpi_ged_class_init(ObjectClass *class, void *data)
> diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
> index 3b932abbbb..afee1ab996 100644
> --- a/include/hw/acpi/cpu_hotplug.h
> +++ b/include/hw/acpi/cpu_hotplug.h
> @@ -19,6 +19,16 @@
> #include "hw/hotplug.h"
> #include "hw/acpi/cpu.h"
>
> +#define ACPI_CPU_HOTPLUG_REG_LEN 12
> +#define ACPI_CPU_SELECTOR_OFFSET_WR 0
> +#define ACPI_CPU_FLAGS_OFFSET_RW 4
> +#define ACPI_CPU_CMD_OFFSET_WR 5
> +#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
> +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
> +
> +#define ACPI_CPU_SCAN_METHOD "CSCN"
> +#define ACPI_CPU_CONTAINER "\\_SB.CPUS"
> +
> typedef struct AcpiCpuHotplug {
> Object *device;
> MemoryRegion io;
> diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
> index ba84ce0214..a803ea818e 100644
> --- a/include/hw/acpi/generic_event_device.h
> +++ b/include/hw/acpi/generic_event_device.h
> @@ -60,6 +60,7 @@
> #define HW_ACPI_GENERIC_EVENT_DEVICE_H
>
> #include "hw/sysbus.h"
> +#include "hw/acpi/cpu_hotplug.h"
> #include "hw/acpi/memory_hotplug.h"
> #include "hw/acpi/ghes.h"
> #include "qom/object.h"
> @@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
> #define ACPI_GED_MEM_HOTPLUG_EVT 0x1
> #define ACPI_GED_PWR_DOWN_EVT 0x2
> #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
> +#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
>
> typedef struct GEDState {
> MemoryRegion evt;
> @@ -106,6 +108,9 @@ struct AcpiGedState {
> SysBusDevice parent_obj;
> MemHotplugState memhp_state;
> MemoryRegion container_memhp;
> + CPUHotplugState cpuhp_state;
> + MemoryRegion container_cpuhp;
> + AcpiCpuHotplug cpuhp;
> GEDState ged_state;
> uint32_t ged_event_bitmap;
> qemu_irq irq;
> --
> 2.39.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 10:49 ` Salil Mehta via
@ 2023-09-26 11:12 ` Michael S. Tsirkin
2023-09-26 11:45 ` Salil Mehta via
2023-09-26 12:17 ` lixianglai
1 sibling, 1 reply; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 11:12 UTC (permalink / raw)
To: Salil Mehta
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> Hi Xianglai,
> FYI. RFC V2 is out and you can now drop the arch agnostic patches from
> your patch-set. Please check the details in the cover letter which one
> you need to pick and rebase from:
>
> https://lore.kernel.org/qemu-devel/20230926100436.28284-1-salil.mehta@huawei.com/T/#t
>
> I am planning to float the architecture agnostic patch-set within this
> week which will have same patches and in same order as mentioned in
> the cover letter. This will untie the development across different
> architectures.
>
> Many thanks
> Salil.
However, please get authorship info right. This claims patch has been
codeveloped by Bernhard Beschow, xianglai li and yourself.
Your patch claims a completely different list of authors
with yourself being the only common author.
Not nice.
> > From: xianglai li <lixianglai@loongson.cn>
> > Sent: Tuesday, September 26, 2023 10:54 AM
> > To: qemu-devel@nongnu.org
> > Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> > <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>; Xiaojuan
> > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
> > Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
> > <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> > Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> > <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
> > Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> > <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
> > Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
> > <maobibo@loongson.cn>
> > Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> >
> > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
> > is based on PCI and is IO port based and hence existing cpus AML code
> > assumes _CRS objects would evaluate to a system resource which describes
> > IO Port address.
> > But on Loongarch arch CPUs control device(\\_SB.PRES) register interface
> > is memory-mapped hence _CRS object should evaluate to system resource
> > which describes memory-mapped base address.
> >
> > This cpus AML code change updates the existing interface of the build cpus
> > AML
> > function to accept both IO/MEMORY type regions and update the _CRS object
> > correspondingly.
> >
> > Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
> > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > Cc: "Bernhard Beschow" <shentey@gmail.com>
> > Cc: "Salil Mehta" <salil.mehta@huawei.com>
> > Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> > Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> > Cc: Song Gao <gaosong@loongson.cn>
> > Cc: "Michael S. Tsirkin" <mst@redhat.com>
> > Cc: Igor Mammedov <imammedo@redhat.com>
> > Cc: Ani Sinha <anisinha@redhat.com>
> > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > Cc: Richard Henderson <richard.henderson@linaro.org>
> > Cc: Eduardo Habkost <eduardo@habkost.net>
> > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> > Cc: Yanan Wang <wangyanan55@huawei.com>
> > Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> > Cc: Peter Xu <peterx@redhat.com>
> > Cc: David Hildenbrand <david@redhat.com>
> > Cc: Bibo Mao <maobibo@loongson.cn>
> > Signed-off-by: xianglai li <lixianglai@loongson.cn>
> > ---
> > hw/acpi/cpu.c | 20 +++++++++++++++-----
> > hw/i386/acpi-build.c | 3 ++-
> > include/hw/acpi/cpu.h | 5 +++--
> > 3 files changed, 20 insertions(+), 8 deletions(-)
> >
> > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> > index 5bad983928..0afa04832e 100644
> > --- a/hw/acpi/cpu.c
> > +++ b/hw/acpi/cpu.c
> > @@ -6,6 +6,7 @@
> > #include "qapi/qapi-events-acpi.h"
> > #include "trace.h"
> > #include "sysemu/numa.h"
> > +#include "hw/acpi/cpu_hotplug.h"
> >
> > #define OVMF_CPUHP_SMI_CMD 4
> >
> > @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
> > #define CPU_FW_EJECT_EVENT "CEJF"
> >
> > void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
> > opts,
> > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> > + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
> > const char *res_root,
> > - const char *event_handler_method)
> > + const char *event_handler_method,
> > + AmlRegionSpace rs)
> > {
> > Aml *ifctx;
> > Aml *field;
> > @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
> > *machine, CPUHotplugFeatures opts,
> > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
> >
> > crs = aml_resource_template();
> > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
> > + if (rs == AML_SYSTEM_IO) {
> > + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
> > mmap_io_base, 1,
> > ACPI_CPU_HOTPLUG_REG_LEN));
> > + } else {
> > + aml_append(crs, aml_memory32_fixed(mmap_io_base,
> > + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE));
> > + }
> > +
> > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
> >
> > + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
> > /* declare CPU hotplug MMIO region with related access fields */
> > aml_append(cpu_ctrl_dev,
> > - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base),
> > - ACPI_CPU_HOTPLUG_REG_LEN));
> > + aml_operation_region("PRST", rs,
> > + aml_int(mmap_io_base),
> > + ACPI_CPU_HOTPLUG_REG_LEN));
> >
> > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
> > AML_WRITE_AS_ZEROS);
> > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > index 863a939210..7016205d15 100644
> > --- a/hw/i386/acpi-build.c
> > +++ b/hw/i386/acpi-build.c
> > @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> > .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
> > };
> > build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
> > - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02");
> > + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
> > + AML_SYSTEM_IO);
> > }
> >
> > if (pcms->memhp_io_base && nr_mem) {
> > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
> > index bc901660fb..601f644e57 100644
> > --- a/include/hw/acpi/cpu.h
> > +++ b/include/hw/acpi/cpu.h
> > @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
> > CPUArchIdList *apic_ids,
> > GArray *entry, bool force_enabled);
> >
> > void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
> > opts,
> > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> > + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
> > const char *res_root,
> > - const char *event_handler_method);
> > + const char *event_handler_method,
> > + AmlRegionSpace rs);
> >
> > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> > ***list);
> >
> > --
> > 2.39.1
> >
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 11:02 ` Michael S. Tsirkin
@ 2023-09-26 11:26 ` lixianglai
2023-09-26 12:08 ` Michael S. Tsirkin
0 siblings, 1 reply; 32+ messages in thread
From: lixianglai @ 2023-09-26 11:26 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: qemu-devel, Salil Mehta, Salil Mehta, Bernhard Beschow,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi, Michael S. Tsirkin :
> On Tue, Sep 26, 2023 at 05:54:26PM +0800, xianglai li wrote:
>> ACPI GED shall be used to convey to the guest kernel about any cpu hot-(un)plug
>> events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced
>> to support CPU hot-(un)plug state and events.
>>
>> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> This is not the way to handle multiple emails.
Oh, sorry, I'll delete the first one.
Thanks,
Xianglai.
>
>> Cc: "Bernhard Beschow" <shentey@gmail.com>
>> Cc: "Salil Mehta" <salil.mehta@huawei.com>
>> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> Cc: Song Gao <gaosong@loongson.cn>
>> Cc: "Michael S. Tsirkin" <mst@redhat.com>
>> Cc: Igor Mammedov <imammedo@redhat.com>
>> Cc: Ani Sinha <anisinha@redhat.com>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Richard Henderson <richard.henderson@linaro.org>
>> Cc: Eduardo Habkost <eduardo@habkost.net>
>> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
>> Cc: Yanan Wang <wangyanan55@huawei.com>
>> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
>> Cc: Peter Xu <peterx@redhat.com>
>> Cc: David Hildenbrand <david@redhat.com>
>> Cc: Bibo Mao <maobibo@loongson.cn>
>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>> ---
>> hw/acpi/acpi-cpu-hotplug-stub.c | 6 +++++
>> hw/acpi/cpu.c | 7 ------
>> hw/acpi/generic_event_device.c | 33 ++++++++++++++++++++++++++
>> include/hw/acpi/cpu_hotplug.h | 10 ++++++++
>> include/hw/acpi/generic_event_device.h | 5 ++++
>> 5 files changed, 54 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c
>> index 3fc4b14c26..2aec90d968 100644
>> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
>> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
>> @@ -24,6 +24,12 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list)
>> return;
>> }
>>
>> +void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
>> + CPUHotplugState *state, hwaddr base_addr)
>> +{
>> + return;
>> +}
>> +
>> void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev,
>> CPUHotplugState *cpu_st, DeviceState *dev, Error **errp)
>> {
>> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
>> index 011d2c6c2d..5bad983928 100644
>> --- a/hw/acpi/cpu.c
>> +++ b/hw/acpi/cpu.c
>> @@ -7,13 +7,6 @@
>> #include "trace.h"
>> #include "sysemu/numa.h"
>>
>> -#define ACPI_CPU_HOTPLUG_REG_LEN 12
>> -#define ACPI_CPU_SELECTOR_OFFSET_WR 0
>> -#define ACPI_CPU_FLAGS_OFFSET_RW 4
>> -#define ACPI_CPU_CMD_OFFSET_WR 5
>> -#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
>> -#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
>> -
>> #define OVMF_CPUHP_SMI_CMD 4
>>
>> enum {
>> diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
>> index a3d31631fe..c5a70957b4 100644
>> --- a/hw/acpi/generic_event_device.c
>> +++ b/hw/acpi/generic_event_device.c
>> @@ -12,6 +12,7 @@
>> #include "qemu/osdep.h"
>> #include "qapi/error.h"
>> #include "hw/acpi/acpi.h"
>> +#include "hw/acpi/cpu.h"
>> #include "hw/acpi/generic_event_device.h"
>> #include "hw/irq.h"
>> #include "hw/mem/pc-dimm.h"
>> @@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] = {
>> ACPI_GED_MEM_HOTPLUG_EVT,
>> ACPI_GED_PWR_DOWN_EVT,
>> ACPI_GED_NVDIMM_HOTPLUG_EVT,
>> + ACPI_GED_CPU_HOTPLUG_EVT,
>> };
>>
>> /*
>> @@ -117,6 +119,10 @@ void build_ged_aml(Aml *table, const char *name, HotplugHandler *hotplug_dev,
>> aml_notify(aml_name("\\_SB.NVDR"),
>> aml_int(0x80)));
>> break;
>> + case ACPI_GED_CPU_HOTPLUG_EVT:
>> + aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "."
>> + ACPI_CPU_SCAN_METHOD));
>> + break;
>> default:
>> /*
>> * Please make sure all the events in ged_supported_events[]
>> @@ -234,6 +240,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
>> } else {
>> acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp);
>> }
>> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
>> + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
>> } else {
>> error_setg(errp, "virt: device plug request for unsupported device"
>> " type: %s", object_get_typename(OBJECT(dev)));
>> @@ -248,6 +256,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
>> if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
>> !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
>> acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
>> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
>> + acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
>> } else {
>> error_setg(errp, "acpi: device unplug request for unsupported device"
>> " type: %s", object_get_typename(OBJECT(dev)));
>> @@ -261,6 +271,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
>>
>> if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
>> acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
>> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
>> + acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
>> } else {
>> error_setg(errp, "acpi: device unplug for unsupported device"
>> " type: %s", object_get_typename(OBJECT(dev)));
>> @@ -272,6 +284,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
>> AcpiGedState *s = ACPI_GED(adev);
>>
>> acpi_memory_ospm_status(&s->memhp_state, list);
>> + acpi_cpu_ospm_status(&s->cpuhp_state, list);
>> }
>>
>> static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
>> @@ -286,6 +299,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
>> sel = ACPI_GED_PWR_DOWN_EVT;
>> } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) {
>> sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
>> + } else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
>> + sel = ACPI_GED_CPU_HOTPLUG_EVT;
>> } else {
>> /* Unknown event. Return without generating interrupt. */
>> warn_report("GED: Unsupported event %d. No irq injected", ev);
>> @@ -318,6 +333,16 @@ static const VMStateDescription vmstate_memhp_state = {
>> }
>> };
>>
>> +static const VMStateDescription vmstate_cpuhp_state = {
>> + .name = "acpi-ged/cpuhp",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> static const VMStateDescription vmstate_ged_state = {
>> .name = "acpi-ged-state",
>> .version_id = 1,
>> @@ -366,6 +391,7 @@ static const VMStateDescription vmstate_acpi_ged = {
>> },
>> .subsections = (const VMStateDescription * []) {
>> &vmstate_memhp_state,
>> + &vmstate_cpuhp_state,
>> &vmstate_ghes_state,
>> NULL
>> }
>> @@ -400,6 +426,13 @@ static void acpi_ged_initfn(Object *obj)
>> memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
>> TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
>> sysbus_init_mmio(sbd, &ged_st->regs);
>> +
>> + s->cpuhp.device = OBJECT(s);
>> + memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp container",
>> + ACPI_CPU_HOTPLUG_REG_LEN);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container_cpuhp);
>> + cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
>> + &s->cpuhp_state, 0);
>> }
>>
>> static void acpi_ged_class_init(ObjectClass *class, void *data)
>> diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
>> index 3b932abbbb..afee1ab996 100644
>> --- a/include/hw/acpi/cpu_hotplug.h
>> +++ b/include/hw/acpi/cpu_hotplug.h
>> @@ -19,6 +19,16 @@
>> #include "hw/hotplug.h"
>> #include "hw/acpi/cpu.h"
>>
>> +#define ACPI_CPU_HOTPLUG_REG_LEN 12
>> +#define ACPI_CPU_SELECTOR_OFFSET_WR 0
>> +#define ACPI_CPU_FLAGS_OFFSET_RW 4
>> +#define ACPI_CPU_CMD_OFFSET_WR 5
>> +#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
>> +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
>> +
>> +#define ACPI_CPU_SCAN_METHOD "CSCN"
>> +#define ACPI_CPU_CONTAINER "\\_SB.CPUS"
>> +
>> typedef struct AcpiCpuHotplug {
>> Object *device;
>> MemoryRegion io;
>> diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
>> index ba84ce0214..a803ea818e 100644
>> --- a/include/hw/acpi/generic_event_device.h
>> +++ b/include/hw/acpi/generic_event_device.h
>> @@ -60,6 +60,7 @@
>> #define HW_ACPI_GENERIC_EVENT_DEVICE_H
>>
>> #include "hw/sysbus.h"
>> +#include "hw/acpi/cpu_hotplug.h"
>> #include "hw/acpi/memory_hotplug.h"
>> #include "hw/acpi/ghes.h"
>> #include "qom/object.h"
>> @@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
>> #define ACPI_GED_MEM_HOTPLUG_EVT 0x1
>> #define ACPI_GED_PWR_DOWN_EVT 0x2
>> #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
>> +#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
>>
>> typedef struct GEDState {
>> MemoryRegion evt;
>> @@ -106,6 +108,9 @@ struct AcpiGedState {
>> SysBusDevice parent_obj;
>> MemHotplugState memhp_state;
>> MemoryRegion container_memhp;
>> + CPUHotplugState cpuhp_state;
>> + MemoryRegion container_cpuhp;
>> + AcpiCpuHotplug cpuhp;
>> GEDState ged_state;
>> uint32_t ged_event_bitmap;
>> qemu_irq irq;
>> --
>> 2.39.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 11:12 ` Michael S. Tsirkin
@ 2023-09-26 11:45 ` Salil Mehta via
2023-09-26 11:54 ` Michael S. Tsirkin
0 siblings, 1 reply; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 11:45 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Tuesday, September 26, 2023 12:12 PM
> To: Salil Mehta <salil.mehta@huawei.com>
> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> Bonzini <pbonzini@redhat.com>; Richard Henderson
> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>
> On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> > Hi Xianglai,
> > FYI. RFC V2 is out and you can now drop the arch agnostic patches from
> > your patch-set. Please check the details in the cover letter which one
> > you need to pick and rebase from:
> >
> > https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
> salil.mehta@huawei.com/T/#t
> >
> > I am planning to float the architecture agnostic patch-set within this
> > week which will have same patches and in same order as mentioned in
> > the cover letter. This will untie the development across different
> > architectures.
> >
> > Many thanks
> > Salil.
>
> However, please get authorship info right. This claims patch has been
> codeveloped by Bernhard Beschow, xianglai li and yourself.
> Your patch claims a completely different list of authors
Yes, because those are the people who have developed the patches.
> with yourself being the only common author.
> Not nice.
I have already replied in the other thread. This patch has been
taken from the ARM patch-set sent in the year 2020.
I am not sure who is the other author and how he has contributed.
Co-developed-by usually points at main authors.
> > > From: xianglai li <lixianglai@loongson.cn>
> > > Sent: Tuesday, September 26, 2023 10:54 AM
> > > To: qemu-devel@nongnu.org
> > > Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> > > <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>;
> Xiaojuan
> > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>;
> Michael S.
> > > Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani
> Sinha
> > > <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> > > Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> > > <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
> > > Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> > > <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>;
> Peter
> > > Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
> > > <maobibo@loongson.cn>
> > > Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > >
> > > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
> > > is based on PCI and is IO port based and hence existing cpus AML code
> > > assumes _CRS objects would evaluate to a system resource which
> describes
> > > IO Port address.
> > > But on Loongarch arch CPUs control device(\\_SB.PRES) register
> interface
> > > is memory-mapped hence _CRS object should evaluate to system resource
> > > which describes memory-mapped base address.
> > >
> > > This cpus AML code change updates the existing interface of the build
> cpus
> > > AML
> > > function to accept both IO/MEMORY type regions and update the _CRS
> object
> > > correspondingly.
> > >
> > > Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
> > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > > Cc: "Bernhard Beschow" <shentey@gmail.com>
> > > Cc: "Salil Mehta" <salil.mehta@huawei.com>
> > > Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> > > Cc: Song Gao <gaosong@loongson.cn>
> > > Cc: "Michael S. Tsirkin" <mst@redhat.com>
> > > Cc: Igor Mammedov <imammedo@redhat.com>
> > > Cc: Ani Sinha <anisinha@redhat.com>
> > > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > > Cc: Richard Henderson <richard.henderson@linaro.org>
> > > Cc: Eduardo Habkost <eduardo@habkost.net>
> > > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > > Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> > > Cc: Yanan Wang <wangyanan55@huawei.com>
> > > Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> > > Cc: Peter Xu <peterx@redhat.com>
> > > Cc: David Hildenbrand <david@redhat.com>
> > > Cc: Bibo Mao <maobibo@loongson.cn>
> > > Signed-off-by: xianglai li <lixianglai@loongson.cn>
> > > ---
> > > hw/acpi/cpu.c | 20 +++++++++++++++-----
> > > hw/i386/acpi-build.c | 3 ++-
> > > include/hw/acpi/cpu.h | 5 +++--
> > > 3 files changed, 20 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> > > index 5bad983928..0afa04832e 100644
> > > --- a/hw/acpi/cpu.c
> > > +++ b/hw/acpi/cpu.c
> > > @@ -6,6 +6,7 @@
> > > #include "qapi/qapi-events-acpi.h"
> > > #include "trace.h"
> > > #include "sysemu/numa.h"
> > > +#include "hw/acpi/cpu_hotplug.h"
> > >
> > > #define OVMF_CPUHP_SMI_CMD 4
> > >
> > > @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
> > > #define CPU_FW_EJECT_EVENT "CEJF"
> > >
> > > void build_cpus_aml(Aml *table, MachineState *machine,
> CPUHotplugFeatures
> > > opts,
> > > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> mmap_io_base,
> > > const char *res_root,
> > > - const char *event_handler_method)
> > > + const char *event_handler_method,
> > > + AmlRegionSpace rs)
> > > {
> > > Aml *ifctx;
> > > Aml *field;
> > > @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
> > > *machine, CPUHotplugFeatures opts,
> > > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
> > >
> > > crs = aml_resource_template();
> > > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
> > > + if (rs == AML_SYSTEM_IO) {
> > > + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
> > > mmap_io_base, 1,
> > > ACPI_CPU_HOTPLUG_REG_LEN));
> > > + } else {
> > > + aml_append(crs, aml_memory32_fixed(mmap_io_base,
> > > + ACPI_CPU_HOTPLUG_REG_LEN,
> AML_READ_WRITE));
> > > + }
> > > +
> > > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
> > >
> > > + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
> > > /* declare CPU hotplug MMIO region with related access fields
> */
> > > aml_append(cpu_ctrl_dev,
> > > - aml_operation_region("PRST", AML_SYSTEM_IO,
> aml_int(io_base),
> > > - ACPI_CPU_HOTPLUG_REG_LEN));
> > > + aml_operation_region("PRST", rs,
> > > + aml_int(mmap_io_base),
> > > + ACPI_CPU_HOTPLUG_REG_LEN));
> > >
> > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
> > > AML_WRITE_AS_ZEROS);
> > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > index 863a939210..7016205d15 100644
> > > --- a/hw/i386/acpi-build.c
> > > +++ b/hw/i386/acpi-build.c
> > > @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker
> *linker,
> > > .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
> > > };
> > > build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
> > > - pm->cpu_hp_io_base, "\\_SB.PCI0",
> "\\_GPE._E02");
> > > + pm->cpu_hp_io_base, "\\_SB.PCI0",
> "\\_GPE._E02",
> > > + AML_SYSTEM_IO);
> > > }
> > >
> > > if (pcms->memhp_io_base && nr_mem) {
> > > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
> > > index bc901660fb..601f644e57 100644
> > > --- a/include/hw/acpi/cpu.h
> > > +++ b/include/hw/acpi/cpu.h
> > > @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
> > > CPUArchIdList *apic_ids,
> > > GArray *entry, bool force_enabled);
> > >
> > > void build_cpus_aml(Aml *table, MachineState *machine,
> CPUHotplugFeatures
> > > opts,
> > > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> mmap_io_base,
> > > const char *res_root,
> > > - const char *event_handler_method);
> > > + const char *event_handler_method,
> > > + AmlRegionSpace rs);
> > >
> > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> > > ***list);
> > >
> > > --
> > > 2.39.1
> > >
> >
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 11:45 ` Salil Mehta via
@ 2023-09-26 11:54 ` Michael S. Tsirkin
2023-09-26 12:03 ` Salil Mehta via
2023-09-26 12:30 ` Daniel P. Berrangé
0 siblings, 2 replies; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 11:54 UTC (permalink / raw)
To: Salil Mehta
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
>
> > From: Michael S. Tsirkin <mst@redhat.com>
> > Sent: Tuesday, September 26, 2023 12:12 PM
> > To: Salil Mehta <salil.mehta@huawei.com>
> > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> >
> > On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> > > Hi Xianglai,
> > > FYI. RFC V2 is out and you can now drop the arch agnostic patches from
> > > your patch-set. Please check the details in the cover letter which one
> > > you need to pick and rebase from:
> > >
> > > https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
> > salil.mehta@huawei.com/T/#t
> > >
> > > I am planning to float the architecture agnostic patch-set within this
> > > week which will have same patches and in same order as mentioned in
> > > the cover letter. This will untie the development across different
> > > architectures.
> > >
> > > Many thanks
> > > Salil.
> >
> > However, please get authorship info right. This claims patch has been
> > codeveloped by Bernhard Beschow, xianglai li and yourself.
> > Your patch claims a completely different list of authors
>
> Yes, because those are the people who have developed the patches.
>
> > with yourself being the only common author.
> > Not nice.
>
> I have already replied in the other thread. This patch has been
> taken from the ARM patch-set sent in the year 2020.
>
> I am not sure who is the other author and how he has contributed.
>
> Co-developed-by usually points at main authors.
>
If you are not sure then find out please.
And to help you stop guessing at the rules:
Documentation/process/submitting-patches.rst
Co-developed-by: states that the patch was co-created by multiple developers;
it is used to give attribution to co-authors (in addition to the author
attributed by the From: tag) when several people work on a single patch. Since
Co-developed-by: denotes authorship, every Co-developed-by: must be immediately
followed by a Signed-off-by: of the associated co-author. Standard sign-off
procedure applies, i.e. the ordering of Signed-off-by: tags should reflect the
chronological history of the patch insofar as possible, regardless of whether
the author is attributed via From: or Co-developed-by:. Notably, the last
Signed-off-by: must always be that of the developer submitting the patch.
>
>
>
> > > > From: xianglai li <lixianglai@loongson.cn>
> > > > Sent: Tuesday, September 26, 2023 10:54 AM
> > > > To: qemu-devel@nongnu.org
> > > > Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> > > > <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>;
> > Xiaojuan
> > > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>;
> > Michael S.
> > > > Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani
> > Sinha
> > > > <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> > > > Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> > > > <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
> > > > Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> > > > <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>;
> > Peter
> > > > Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
> > > > <maobibo@loongson.cn>
> > > > Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > > >
> > > > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
> > > > is based on PCI and is IO port based and hence existing cpus AML code
> > > > assumes _CRS objects would evaluate to a system resource which
> > describes
> > > > IO Port address.
> > > > But on Loongarch arch CPUs control device(\\_SB.PRES) register
> > interface
> > > > is memory-mapped hence _CRS object should evaluate to system resource
> > > > which describes memory-mapped base address.
> > > >
> > > > This cpus AML code change updates the existing interface of the build
> > cpus
> > > > AML
> > > > function to accept both IO/MEMORY type regions and update the _CRS
> > object
> > > > correspondingly.
> > > >
> > > > Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
> > > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > > > Cc: "Bernhard Beschow" <shentey@gmail.com>
> > > > Cc: "Salil Mehta" <salil.mehta@huawei.com>
> > > > Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> > > > Cc: Song Gao <gaosong@loongson.cn>
> > > > Cc: "Michael S. Tsirkin" <mst@redhat.com>
> > > > Cc: Igor Mammedov <imammedo@redhat.com>
> > > > Cc: Ani Sinha <anisinha@redhat.com>
> > > > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > > > Cc: Richard Henderson <richard.henderson@linaro.org>
> > > > Cc: Eduardo Habkost <eduardo@habkost.net>
> > > > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > > > Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> > > > Cc: Yanan Wang <wangyanan55@huawei.com>
> > > > Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> > > > Cc: Peter Xu <peterx@redhat.com>
> > > > Cc: David Hildenbrand <david@redhat.com>
> > > > Cc: Bibo Mao <maobibo@loongson.cn>
> > > > Signed-off-by: xianglai li <lixianglai@loongson.cn>
> > > > ---
> > > > hw/acpi/cpu.c | 20 +++++++++++++++-----
> > > > hw/i386/acpi-build.c | 3 ++-
> > > > include/hw/acpi/cpu.h | 5 +++--
> > > > 3 files changed, 20 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> > > > index 5bad983928..0afa04832e 100644
> > > > --- a/hw/acpi/cpu.c
> > > > +++ b/hw/acpi/cpu.c
> > > > @@ -6,6 +6,7 @@
> > > > #include "qapi/qapi-events-acpi.h"
> > > > #include "trace.h"
> > > > #include "sysemu/numa.h"
> > > > +#include "hw/acpi/cpu_hotplug.h"
> > > >
> > > > #define OVMF_CPUHP_SMI_CMD 4
> > > >
> > > > @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
> > > > #define CPU_FW_EJECT_EVENT "CEJF"
> > > >
> > > > void build_cpus_aml(Aml *table, MachineState *machine,
> > CPUHotplugFeatures
> > > > opts,
> > > > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> > > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> > mmap_io_base,
> > > > const char *res_root,
> > > > - const char *event_handler_method)
> > > > + const char *event_handler_method,
> > > > + AmlRegionSpace rs)
> > > > {
> > > > Aml *ifctx;
> > > > Aml *field;
> > > > @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
> > > > *machine, CPUHotplugFeatures opts,
> > > > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
> > > >
> > > > crs = aml_resource_template();
> > > > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
> > > > + if (rs == AML_SYSTEM_IO) {
> > > > + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
> > > > mmap_io_base, 1,
> > > > ACPI_CPU_HOTPLUG_REG_LEN));
> > > > + } else {
> > > > + aml_append(crs, aml_memory32_fixed(mmap_io_base,
> > > > + ACPI_CPU_HOTPLUG_REG_LEN,
> > AML_READ_WRITE));
> > > > + }
> > > > +
> > > > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
> > > >
> > > > + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
> > > > /* declare CPU hotplug MMIO region with related access fields
> > */
> > > > aml_append(cpu_ctrl_dev,
> > > > - aml_operation_region("PRST", AML_SYSTEM_IO,
> > aml_int(io_base),
> > > > - ACPI_CPU_HOTPLUG_REG_LEN));
> > > > + aml_operation_region("PRST", rs,
> > > > + aml_int(mmap_io_base),
> > > > + ACPI_CPU_HOTPLUG_REG_LEN));
> > > >
> > > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
> > > > AML_WRITE_AS_ZEROS);
> > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > > index 863a939210..7016205d15 100644
> > > > --- a/hw/i386/acpi-build.c
> > > > +++ b/hw/i386/acpi-build.c
> > > > @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker
> > *linker,
> > > > .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
> > > > };
> > > > build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
> > > > - pm->cpu_hp_io_base, "\\_SB.PCI0",
> > "\\_GPE._E02");
> > > > + pm->cpu_hp_io_base, "\\_SB.PCI0",
> > "\\_GPE._E02",
> > > > + AML_SYSTEM_IO);
> > > > }
> > > >
> > > > if (pcms->memhp_io_base && nr_mem) {
> > > > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
> > > > index bc901660fb..601f644e57 100644
> > > > --- a/include/hw/acpi/cpu.h
> > > > +++ b/include/hw/acpi/cpu.h
> > > > @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
> > > > CPUArchIdList *apic_ids,
> > > > GArray *entry, bool force_enabled);
> > > >
> > > > void build_cpus_aml(Aml *table, MachineState *machine,
> > CPUHotplugFeatures
> > > > opts,
> > > > - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
> > > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> > mmap_io_base,
> > > > const char *res_root,
> > > > - const char *event_handler_method);
> > > > + const char *event_handler_method,
> > > > + AmlRegionSpace rs);
> > > >
> > > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> > > > ***list);
> > > >
> > > > --
> > > > 2.39.1
> > > >
> > >
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 11:54 ` Michael S. Tsirkin
@ 2023-09-26 12:03 ` Salil Mehta via
2023-09-26 12:07 ` Michael S. Tsirkin
2023-09-26 12:49 ` lixianglai
2023-09-26 12:30 ` Daniel P. Berrangé
1 sibling, 2 replies; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 12:03 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Tuesday, September 26, 2023 12:54 PM
> To: Salil Mehta <salil.mehta@huawei.com>
> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> Bonzini <pbonzini@redhat.com>; Richard Henderson
> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>
> On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
> >
> > > From: Michael S. Tsirkin <mst@redhat.com>
> > > Sent: Tuesday, September 26, 2023 12:12 PM
> > > To: Salil Mehta <salil.mehta@huawei.com>
> > > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org;
> Bernhard
> > > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>;
> Xiaojuan
> > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > >
> > > On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> > > > Hi Xianglai,
> > > > FYI. RFC V2 is out and you can now drop the arch agnostic patches
> from
> > > > your patch-set. Please check the details in the cover letter which
> one
> > > > you need to pick and rebase from:
> > > >
> > > > https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
> > > salil.mehta@huawei.com/T/#t
> > > >
> > > > I am planning to float the architecture agnostic patch-set within
> this
> > > > week which will have same patches and in same order as mentioned in
> > > > the cover letter. This will untie the development across different
> > > > architectures.
> > > >
> > > > Many thanks
> > > > Salil.
> > >
> > > However, please get authorship info right. This claims patch has been
> > > codeveloped by Bernhard Beschow, xianglai li and yourself.
> > > Your patch claims a completely different list of authors
> >
> > Yes, because those are the people who have developed the patches.
> >
> > > with yourself being the only common author.
> > > Not nice.
> >
> > I have already replied in the other thread. This patch has been
> > taken from the ARM patch-set sent in the year 2020.
> >
> > I am not sure who is the other author and how he has contributed.
> >
> > Co-developed-by usually points at main authors.
> >
>
>
> If you are not sure then find out please.
We really have not collaborated on anything as part of
this entire development of virtual CPU hotplug since the
year 2020?
I would leave it to Xianglai to answer about the person.
> And to help you stop guessing at the rules:
>
> Documentation/process/submitting-patches.rst
>
> Co-developed-by: states that the patch was co-created by multiple
> developers;
> it is used to give attribution to co-authors (in addition to the
> author
> attributed by the From: tag) when several people work on a single
> patch. Since
> Co-developed-by: denotes authorship, every Co-developed-by: must be
> immediately
> followed by a Signed-off-by: of the associated co-author. Standard
> sign-off
> procedure applies, i.e. the ordering of Signed-off-by: tags should
> reflect the
> chronological history of the patch insofar as possible, regardless of
> whether
> the author is attributed via From: or Co-developed-by:. Notably, the
> last
> Signed-off-by: must always be that of the developer submitting the
> patch.
Sure, ARM patch-set follows exactly above rules.
> > > > > From: xianglai li <lixianglai@loongson.cn>
> > > > > Sent: Tuesday, September 26, 2023 10:54 AM
> > > > > To: qemu-devel@nongnu.org
> > > > > Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> > > > > <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>;
> > > Xiaojuan
> > > > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>;
> > > Michael S.
> > > > > Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani
> > > Sinha
> > > > > <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> > > > > Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> > > > > <eduardo@habkost.net>; Marcel Apfelbaum
> <marcel.apfelbaum@gmail.com>;
> > > > > Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> > > > > <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>;
> > > Peter
> > > > > Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo
> Mao
> > > > > <maobibo@loongson.cn>
> > > > > Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > > > >
> > > > > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
> > > > > is based on PCI and is IO port based and hence existing cpus AML
> code
> > > > > assumes _CRS objects would evaluate to a system resource which
> > > describes
> > > > > IO Port address.
> > > > > But on Loongarch arch CPUs control device(\\_SB.PRES) register
> > > interface
> > > > > is memory-mapped hence _CRS object should evaluate to system
> resource
> > > > > which describes memory-mapped base address.
> > > > >
> > > > > This cpus AML code change updates the existing interface of the
> build
> > > cpus
> > > > > AML
> > > > > function to accept both IO/MEMORY type regions and update the _CRS
> > > object
> > > > > correspondingly.
> > > > >
> > > > > Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
> > > > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > > > > Cc: "Bernhard Beschow" <shentey@gmail.com>
> > > > > Cc: "Salil Mehta" <salil.mehta@huawei.com>
> > > > > Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > > Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> > > > > Cc: Song Gao <gaosong@loongson.cn>
> > > > > Cc: "Michael S. Tsirkin" <mst@redhat.com>
> > > > > Cc: Igor Mammedov <imammedo@redhat.com>
> > > > > Cc: Ani Sinha <anisinha@redhat.com>
> > > > > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > > > > Cc: Richard Henderson <richard.henderson@linaro.org>
> > > > > Cc: Eduardo Habkost <eduardo@habkost.net>
> > > > > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > > > > Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> > > > > Cc: Yanan Wang <wangyanan55@huawei.com>
> > > > > Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> > > > > Cc: Peter Xu <peterx@redhat.com>
> > > > > Cc: David Hildenbrand <david@redhat.com>
> > > > > Cc: Bibo Mao <maobibo@loongson.cn>
> > > > > Signed-off-by: xianglai li <lixianglai@loongson.cn>
> > > > > ---
> > > > > hw/acpi/cpu.c | 20 +++++++++++++++-----
> > > > > hw/i386/acpi-build.c | 3 ++-
> > > > > include/hw/acpi/cpu.h | 5 +++--
> > > > > 3 files changed, 20 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> > > > > index 5bad983928..0afa04832e 100644
> > > > > --- a/hw/acpi/cpu.c
> > > > > +++ b/hw/acpi/cpu.c
> > > > > @@ -6,6 +6,7 @@
> > > > > #include "qapi/qapi-events-acpi.h"
> > > > > #include "trace.h"
> > > > > #include "sysemu/numa.h"
> > > > > +#include "hw/acpi/cpu_hotplug.h"
> > > > >
> > > > > #define OVMF_CPUHP_SMI_CMD 4
> > > > >
> > > > > @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug =
> {
> > > > > #define CPU_FW_EJECT_EVENT "CEJF"
> > > > >
> > > > > void build_cpus_aml(Aml *table, MachineState *machine,
> > > CPUHotplugFeatures
> > > > > opts,
> > > > > - build_madt_cpu_fn build_madt_cpu, hwaddr
> io_base,
> > > > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> > > mmap_io_base,
> > > > > const char *res_root,
> > > > > - const char *event_handler_method)
> > > > > + const char *event_handler_method,
> > > > > + AmlRegionSpace rs)
> > > > > {
> > > > > Aml *ifctx;
> > > > > Aml *field;
> > > > > @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
> > > > > *machine, CPUHotplugFeatures opts,
> > > > > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
> > > > >
> > > > > crs = aml_resource_template();
> > > > > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
> > > > > + if (rs == AML_SYSTEM_IO) {
> > > > > + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
> > > > > mmap_io_base, 1,
> > > > > ACPI_CPU_HOTPLUG_REG_LEN));
> > > > > + } else {
> > > > > + aml_append(crs, aml_memory32_fixed(mmap_io_base,
> > > > > + ACPI_CPU_HOTPLUG_REG_LEN,
> > > AML_READ_WRITE));
> > > > > + }
> > > > > +
> > > > > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
> > > > >
> > > > > + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
> > > > > /* declare CPU hotplug MMIO region with related access
> fields
> > > */
> > > > > aml_append(cpu_ctrl_dev,
> > > > > - aml_operation_region("PRST", AML_SYSTEM_IO,
> > > aml_int(io_base),
> > > > > - ACPI_CPU_HOTPLUG_REG_LEN));
> > > > > + aml_operation_region("PRST", rs,
> > > > > + aml_int(mmap_io_base),
> > > > > +
> ACPI_CPU_HOTPLUG_REG_LEN));
> > > > >
> > > > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
> > > > > AML_WRITE_AS_ZEROS);
> > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > > > index 863a939210..7016205d15 100644
> > > > > --- a/hw/i386/acpi-build.c
> > > > > +++ b/hw/i386/acpi-build.c
> > > > > @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker
> > > *linker,
> > > > > .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
> > > > > };
> > > > > build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
> > > > > - pm->cpu_hp_io_base, "\\_SB.PCI0",
> > > "\\_GPE._E02");
> > > > > + pm->cpu_hp_io_base, "\\_SB.PCI0",
> > > "\\_GPE._E02",
> > > > > + AML_SYSTEM_IO);
> > > > > }
> > > > >
> > > > > if (pcms->memhp_io_base && nr_mem) {
> > > > > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
> > > > > index bc901660fb..601f644e57 100644
> > > > > --- a/include/hw/acpi/cpu.h
> > > > > +++ b/include/hw/acpi/cpu.h
> > > > > @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
> > > > > CPUArchIdList *apic_ids,
> > > > > GArray *entry, bool
> force_enabled);
> > > > >
> > > > > void build_cpus_aml(Aml *table, MachineState *machine,
> > > CPUHotplugFeatures
> > > > > opts,
> > > > > - build_madt_cpu_fn build_madt_cpu, hwaddr
> io_base,
> > > > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> > > mmap_io_base,
> > > > > const char *res_root,
> > > > > - const char *event_handler_method);
> > > > > + const char *event_handler_method,
> > > > > + AmlRegionSpace rs);
> > > > >
> > > > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> > > > > ***list);
> > > > >
> > > > > --
> > > > > 2.39.1
> > > > >
> > > >
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
2023-09-26 10:50 ` Salil Mehta via
2023-09-26 11:02 ` Michael S. Tsirkin
@ 2023-09-26 12:03 ` Michael S. Tsirkin
2 siblings, 0 replies; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 12:03 UTC (permalink / raw)
To: xianglai li
Cc: qemu-devel, Salil Mehta, Salil Mehta, Bernhard Beschow,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 05:54:26PM +0800, xianglai li wrote:
> ACPI GED shall be used to convey to the guest kernel about any cpu hot-(un)plug
> events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced
> to support CPU hot-(un)plug state and events.
>
> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Bernhard Beschow" <shentey@gmail.com>
> Cc: "Salil Mehta" <salil.mehta@huawei.com>
> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> Cc: Song Gao <gaosong@loongson.cn>
> Cc: "Michael S. Tsirkin" <mst@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Ani Sinha <anisinha@redhat.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Cc: Eduardo Habkost <eduardo@habkost.net>
> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> Cc: Yanan Wang <wangyanan55@huawei.com>
> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> Cc: Peter Xu <peterx@redhat.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Bibo Mao <maobibo@loongson.cn>
> Signed-off-by: xianglai li <lixianglai@loongson.cn>
Same question as I sent on Salil Mehta's patchset.
Is this based on this patchset:
https://lore.kernel.org/qemu-devel/20200613213629.21984-11-salil.mehta@huawei.com/
?
If yes then it looks like you dropped Keqian Zhu.
And the rules for Co-developed-by are:
Co-developed-by: states that the patch was co-created by multiple developers;
it is used to give attribution to co-authors (in addition to the author
attributed by the From: tag) when several people work on a single patch. Since
Co-developed-by: denotes authorship, every Co-developed-by: must be immediately
followed by a Signed-off-by: of the associated co-author. Standard sign-off
procedure applies, i.e. the ordering of Signed-off-by: tags should reflect the
chronological history of the patch insofar as possible, regardless of whether
the author is attributed via From: or Co-developed-by:. Notably, the last
Signed-off-by: must always be that of the developer submitting the patch.
but it looks like Keqian Zhu did not sign off on his original patch so
you need to go and get his sign off.
> ---
> hw/acpi/acpi-cpu-hotplug-stub.c | 6 +++++
> hw/acpi/cpu.c | 7 ------
> hw/acpi/generic_event_device.c | 33 ++++++++++++++++++++++++++
> include/hw/acpi/cpu_hotplug.h | 10 ++++++++
> include/hw/acpi/generic_event_device.h | 5 ++++
> 5 files changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-stub.c
> index 3fc4b14c26..2aec90d968 100644
> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
> @@ -24,6 +24,12 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list)
> return;
> }
>
> +void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
> + CPUHotplugState *state, hwaddr base_addr)
> +{
> + return;
> +}
> +
> void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev,
> CPUHotplugState *cpu_st, DeviceState *dev, Error **errp)
> {
> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> index 011d2c6c2d..5bad983928 100644
> --- a/hw/acpi/cpu.c
> +++ b/hw/acpi/cpu.c
> @@ -7,13 +7,6 @@
> #include "trace.h"
> #include "sysemu/numa.h"
>
> -#define ACPI_CPU_HOTPLUG_REG_LEN 12
> -#define ACPI_CPU_SELECTOR_OFFSET_WR 0
> -#define ACPI_CPU_FLAGS_OFFSET_RW 4
> -#define ACPI_CPU_CMD_OFFSET_WR 5
> -#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
> -#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
> -
> #define OVMF_CPUHP_SMI_CMD 4
>
> enum {
> diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c
> index a3d31631fe..c5a70957b4 100644
> --- a/hw/acpi/generic_event_device.c
> +++ b/hw/acpi/generic_event_device.c
> @@ -12,6 +12,7 @@
> #include "qemu/osdep.h"
> #include "qapi/error.h"
> #include "hw/acpi/acpi.h"
> +#include "hw/acpi/cpu.h"
> #include "hw/acpi/generic_event_device.h"
> #include "hw/irq.h"
> #include "hw/mem/pc-dimm.h"
> @@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] = {
> ACPI_GED_MEM_HOTPLUG_EVT,
> ACPI_GED_PWR_DOWN_EVT,
> ACPI_GED_NVDIMM_HOTPLUG_EVT,
> + ACPI_GED_CPU_HOTPLUG_EVT,
> };
>
> /*
> @@ -117,6 +119,10 @@ void build_ged_aml(Aml *table, const char *name, HotplugHandler *hotplug_dev,
> aml_notify(aml_name("\\_SB.NVDR"),
> aml_int(0x80)));
> break;
> + case ACPI_GED_CPU_HOTPLUG_EVT:
> + aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "."
> + ACPI_CPU_SCAN_METHOD));
> + break;
> default:
> /*
> * Please make sure all the events in ged_supported_events[]
> @@ -234,6 +240,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev,
> } else {
> acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp);
> }
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "virt: device plug request for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -248,6 +256,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev,
> if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
> !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) {
> acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "acpi: device unplug request for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -261,6 +271,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev,
>
> if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
> acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> + acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
> } else {
> error_setg(errp, "acpi: device unplug for unsupported device"
> " type: %s", object_get_typename(OBJECT(dev)));
> @@ -272,6 +284,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
> AcpiGedState *s = ACPI_GED(adev);
>
> acpi_memory_ospm_status(&s->memhp_state, list);
> + acpi_cpu_ospm_status(&s->cpuhp_state, list);
> }
>
> static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
> @@ -286,6 +299,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
> sel = ACPI_GED_PWR_DOWN_EVT;
> } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) {
> sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
> + } else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
> + sel = ACPI_GED_CPU_HOTPLUG_EVT;
> } else {
> /* Unknown event. Return without generating interrupt. */
> warn_report("GED: Unsupported event %d. No irq injected", ev);
> @@ -318,6 +333,16 @@ static const VMStateDescription vmstate_memhp_state = {
> }
> };
>
> +static const VMStateDescription vmstate_cpuhp_state = {
> + .name = "acpi-ged/cpuhp",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static const VMStateDescription vmstate_ged_state = {
> .name = "acpi-ged-state",
> .version_id = 1,
> @@ -366,6 +391,7 @@ static const VMStateDescription vmstate_acpi_ged = {
> },
> .subsections = (const VMStateDescription * []) {
> &vmstate_memhp_state,
> + &vmstate_cpuhp_state,
> &vmstate_ghes_state,
> NULL
> }
> @@ -400,6 +426,13 @@ static void acpi_ged_initfn(Object *obj)
> memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
> TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
> sysbus_init_mmio(sbd, &ged_st->regs);
> +
> + s->cpuhp.device = OBJECT(s);
> + memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp container",
> + ACPI_CPU_HOTPLUG_REG_LEN);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container_cpuhp);
> + cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
> + &s->cpuhp_state, 0);
> }
>
> static void acpi_ged_class_init(ObjectClass *class, void *data)
> diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
> index 3b932abbbb..afee1ab996 100644
> --- a/include/hw/acpi/cpu_hotplug.h
> +++ b/include/hw/acpi/cpu_hotplug.h
> @@ -19,6 +19,16 @@
> #include "hw/hotplug.h"
> #include "hw/acpi/cpu.h"
>
> +#define ACPI_CPU_HOTPLUG_REG_LEN 12
> +#define ACPI_CPU_SELECTOR_OFFSET_WR 0
> +#define ACPI_CPU_FLAGS_OFFSET_RW 4
> +#define ACPI_CPU_CMD_OFFSET_WR 5
> +#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
> +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
> +
> +#define ACPI_CPU_SCAN_METHOD "CSCN"
> +#define ACPI_CPU_CONTAINER "\\_SB.CPUS"
> +
> typedef struct AcpiCpuHotplug {
> Object *device;
> MemoryRegion io;
> diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h
> index ba84ce0214..a803ea818e 100644
> --- a/include/hw/acpi/generic_event_device.h
> +++ b/include/hw/acpi/generic_event_device.h
> @@ -60,6 +60,7 @@
> #define HW_ACPI_GENERIC_EVENT_DEVICE_H
>
> #include "hw/sysbus.h"
> +#include "hw/acpi/cpu_hotplug.h"
> #include "hw/acpi/memory_hotplug.h"
> #include "hw/acpi/ghes.h"
> #include "qom/object.h"
> @@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
> #define ACPI_GED_MEM_HOTPLUG_EVT 0x1
> #define ACPI_GED_PWR_DOWN_EVT 0x2
> #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
> +#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
>
> typedef struct GEDState {
> MemoryRegion evt;
> @@ -106,6 +108,9 @@ struct AcpiGedState {
> SysBusDevice parent_obj;
> MemHotplugState memhp_state;
> MemoryRegion container_memhp;
> + CPUHotplugState cpuhp_state;
> + MemoryRegion container_cpuhp;
> + AcpiCpuHotplug cpuhp;
> GEDState ged_state;
> uint32_t ged_event_bitmap;
> qemu_irq irq;
> --
> 2.39.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 12:03 ` Salil Mehta via
@ 2023-09-26 12:07 ` Michael S. Tsirkin
2023-09-26 15:52 ` Salil Mehta via
2023-09-26 12:49 ` lixianglai
1 sibling, 1 reply; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 12:07 UTC (permalink / raw)
To: Salil Mehta
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 12:03:46PM +0000, Salil Mehta wrote:
> Sure, ARM patch-set follows exactly above rules.
>
Almost.
Co-developed-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
You should drop your own Co-developed-by as well as multiple Signed-off-by.
--
MST
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 11:26 ` lixianglai
@ 2023-09-26 12:08 ` Michael S. Tsirkin
2023-09-26 12:38 ` Salil Mehta via
0 siblings, 1 reply; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 12:08 UTC (permalink / raw)
To: lixianglai
Cc: qemu-devel, Salil Mehta, Salil Mehta, Bernhard Beschow,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, Yanan Wang, Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 07:26:40PM +0800, lixianglai wrote:
>
> Hi, Michael S. Tsirkin :
> > On Tue, Sep 26, 2023 at 05:54:26PM +0800, xianglai li wrote:
> > > ACPI GED shall be used to convey to the guest kernel about any cpu hot-(un)plug
> > > events. Therefore, existing ACPI GED framework inside QEMU needs to be enhanced
> > > to support CPU hot-(un)plug state and events.
> > >
> > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > This is not the way to handle multiple emails.
>
> Oh, sorry, I'll delete the first one.
>
> Thanks,
>
> Xianglai.
Can you guys figure out together with Salil Mehta what's the
correct order to merge this? I can't figure out with dueling patches.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 10:50 ` Salil Mehta via
@ 2023-09-26 12:16 ` lixianglai
0 siblings, 0 replies; 32+ messages in thread
From: lixianglai @ 2023-09-26 12:16 UTC (permalink / raw)
To: Salil Mehta, qemu-devel
Cc: Salil Mehta, Bernhard Beschow, Xiaojuan Yang, Song Gao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Salil Mehta via:
> Same with this patch. It already exists in the architecture agnostic
> patches part of below:
>
> https://lore.kernel.org/qemu-devel/20230926100436.28284-1-salil.mehta@huawei.com/T/#t
OK, I will remove the first two patches in the next version.
Thanks,
Xianglai.
>
> Thanks
> Salil.
>
>> From: xianglai li <lixianglai@loongson.cn>
>> Sent: Tuesday, September 26, 2023 10:54 AM
>> To: qemu-devel@nongnu.org
>> Cc: Salil Mehta <salil.mehta@opnsrc.net>; Salil Mehta
>> <salil.mehta@huawei.com>; Bernhard Beschow <shentey@gmail.com>; Xiaojuan
>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
>> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
>> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
>> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
>> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
>> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
>> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
>> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
>> <maobibo@loongson.cn>
>> Subject: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-
>> (un)plug
>>
>> ACPI GED shall be used to convey to the guest kernel about any cpu hot-
>> (un)plug
>> events. Therefore, existing ACPI GED framework inside QEMU needs to be
>> enhanced
>> to support CPU hot-(un)plug state and events.
>>
>> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
>> Cc: "Bernhard Beschow" <shentey@gmail.com>
>> Cc: "Salil Mehta" <salil.mehta@huawei.com>
>> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> Cc: Song Gao <gaosong@loongson.cn>
>> Cc: "Michael S. Tsirkin" <mst@redhat.com>
>> Cc: Igor Mammedov <imammedo@redhat.com>
>> Cc: Ani Sinha <anisinha@redhat.com>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Richard Henderson <richard.henderson@linaro.org>
>> Cc: Eduardo Habkost <eduardo@habkost.net>
>> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
>> Cc: Yanan Wang <wangyanan55@huawei.com>
>> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
>> Cc: Peter Xu <peterx@redhat.com>
>> Cc: David Hildenbrand <david@redhat.com>
>> Cc: Bibo Mao <maobibo@loongson.cn>
>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>> ---
>> hw/acpi/acpi-cpu-hotplug-stub.c | 6 +++++
>> hw/acpi/cpu.c | 7 ------
>> hw/acpi/generic_event_device.c | 33 ++++++++++++++++++++++++++
>> include/hw/acpi/cpu_hotplug.h | 10 ++++++++
>> include/hw/acpi/generic_event_device.h | 5 ++++
>> 5 files changed, 54 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-
>> stub.c
>> index 3fc4b14c26..2aec90d968 100644
>> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
>> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
>> @@ -24,6 +24,12 @@ void acpi_cpu_ospm_status(CPUHotplugState *cpu_st,
>> ACPIOSTInfoList ***list)
>> return;
>> }
>>
>> +void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
>> + CPUHotplugState *state, hwaddr base_addr)
>> +{
>> + return;
>> +}
>> +
>> void acpi_cpu_plug_cb(HotplugHandler *hotplug_dev,
>> CPUHotplugState *cpu_st, DeviceState *dev, Error
>> **errp)
>> {
>> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
>> index 011d2c6c2d..5bad983928 100644
>> --- a/hw/acpi/cpu.c
>> +++ b/hw/acpi/cpu.c
>> @@ -7,13 +7,6 @@
>> #include "trace.h"
>> #include "sysemu/numa.h"
>>
>> -#define ACPI_CPU_HOTPLUG_REG_LEN 12
>> -#define ACPI_CPU_SELECTOR_OFFSET_WR 0
>> -#define ACPI_CPU_FLAGS_OFFSET_RW 4
>> -#define ACPI_CPU_CMD_OFFSET_WR 5
>> -#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
>> -#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
>> -
>> #define OVMF_CPUHP_SMI_CMD 4
>>
>> enum {
>> diff --git a/hw/acpi/generic_event_device.c
>> b/hw/acpi/generic_event_device.c
>> index a3d31631fe..c5a70957b4 100644
>> --- a/hw/acpi/generic_event_device.c
>> +++ b/hw/acpi/generic_event_device.c
>> @@ -12,6 +12,7 @@
>> #include "qemu/osdep.h"
>> #include "qapi/error.h"
>> #include "hw/acpi/acpi.h"
>> +#include "hw/acpi/cpu.h"
>> #include "hw/acpi/generic_event_device.h"
>> #include "hw/irq.h"
>> #include "hw/mem/pc-dimm.h"
>> @@ -25,6 +26,7 @@ static const uint32_t ged_supported_events[] = {
>> ACPI_GED_MEM_HOTPLUG_EVT,
>> ACPI_GED_PWR_DOWN_EVT,
>> ACPI_GED_NVDIMM_HOTPLUG_EVT,
>> + ACPI_GED_CPU_HOTPLUG_EVT,
>> };
>>
>> /*
>> @@ -117,6 +119,10 @@ void build_ged_aml(Aml *table, const char *name,
>> HotplugHandler *hotplug_dev,
>> aml_notify(aml_name("\\_SB.NVDR"),
>> aml_int(0x80)));
>> break;
>> + case ACPI_GED_CPU_HOTPLUG_EVT:
>> + aml_append(if_ctx, aml_call0(ACPI_CPU_CONTAINER "."
>> + ACPI_CPU_SCAN_METHOD));
>> + break;
>> default:
>> /*
>> * Please make sure all the events in
>> ged_supported_events[]
>> @@ -234,6 +240,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler
>> *hotplug_dev,
>> } else {
>> acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp);
>> }
>> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
>> + acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
>> } else {
>> error_setg(errp, "virt: device plug request for unsupported
>> device"
>> " type: %s", object_get_typename(OBJECT(dev)));
>> @@ -248,6 +256,8 @@ static void acpi_ged_unplug_request_cb(HotplugHandler
>> *hotplug_dev,
>> if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) &&
>> !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM))))
>> {
>> acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev,
>> errp);
>> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
>> + acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev,
>> errp);
>> } else {
>> error_setg(errp, "acpi: device unplug request for unsupported
>> device"
>> " type: %s", object_get_typename(OBJECT(dev)));
>> @@ -261,6 +271,8 @@ static void acpi_ged_unplug_cb(HotplugHandler
>> *hotplug_dev,
>>
>> if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
>> acpi_memory_unplug_cb(&s->memhp_state, dev, errp);
>> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
>> + acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
>> } else {
>> error_setg(errp, "acpi: device unplug for unsupported device"
>> " type: %s", object_get_typename(OBJECT(dev)));
>> @@ -272,6 +284,7 @@ static void acpi_ged_ospm_status(AcpiDeviceIf *adev,
>> ACPIOSTInfoList ***list)
>> AcpiGedState *s = ACPI_GED(adev);
>>
>> acpi_memory_ospm_status(&s->memhp_state, list);
>> + acpi_cpu_ospm_status(&s->cpuhp_state, list);
>> }
>>
>> static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits
>> ev)
>> @@ -286,6 +299,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev,
>> AcpiEventStatusBits ev)
>> sel = ACPI_GED_PWR_DOWN_EVT;
>> } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) {
>> sel = ACPI_GED_NVDIMM_HOTPLUG_EVT;
>> + } else if (ev & ACPI_CPU_HOTPLUG_STATUS) {
>> + sel = ACPI_GED_CPU_HOTPLUG_EVT;
>> } else {
>> /* Unknown event. Return without generating interrupt. */
>> warn_report("GED: Unsupported event %d. No irq injected", ev);
>> @@ -318,6 +333,16 @@ static const VMStateDescription vmstate_memhp_state =
>> {
>> }
>> };
>>
>> +static const VMStateDescription vmstate_cpuhp_state = {
>> + .name = "acpi-ged/cpuhp",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_CPU_HOTPLUG(cpuhp_state, AcpiGedState),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> static const VMStateDescription vmstate_ged_state = {
>> .name = "acpi-ged-state",
>> .version_id = 1,
>> @@ -366,6 +391,7 @@ static const VMStateDescription vmstate_acpi_ged = {
>> },
>> .subsections = (const VMStateDescription * []) {
>> &vmstate_memhp_state,
>> + &vmstate_cpuhp_state,
>> &vmstate_ghes_state,
>> NULL
>> }
>> @@ -400,6 +426,13 @@ static void acpi_ged_initfn(Object *obj)
>> memory_region_init_io(&ged_st->regs, obj, &ged_regs_ops, ged_st,
>> TYPE_ACPI_GED "-regs", ACPI_GED_REG_COUNT);
>> sysbus_init_mmio(sbd, &ged_st->regs);
>> +
>> + s->cpuhp.device = OBJECT(s);
>> + memory_region_init(&s->container_cpuhp, OBJECT(dev), "cpuhp
>> container",
>> + ACPI_CPU_HOTPLUG_REG_LEN);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container_cpuhp);
>> + cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev),
>> + &s->cpuhp_state, 0);
>> }
>>
>> static void acpi_ged_class_init(ObjectClass *class, void *data)
>> diff --git a/include/hw/acpi/cpu_hotplug.h b/include/hw/acpi/cpu_hotplug.h
>> index 3b932abbbb..afee1ab996 100644
>> --- a/include/hw/acpi/cpu_hotplug.h
>> +++ b/include/hw/acpi/cpu_hotplug.h
>> @@ -19,6 +19,16 @@
>> #include "hw/hotplug.h"
>> #include "hw/acpi/cpu.h"
>>
>> +#define ACPI_CPU_HOTPLUG_REG_LEN 12
>> +#define ACPI_CPU_SELECTOR_OFFSET_WR 0
>> +#define ACPI_CPU_FLAGS_OFFSET_RW 4
>> +#define ACPI_CPU_CMD_OFFSET_WR 5
>> +#define ACPI_CPU_CMD_DATA_OFFSET_RW 8
>> +#define ACPI_CPU_CMD_DATA2_OFFSET_R 0
>> +
>> +#define ACPI_CPU_SCAN_METHOD "CSCN"
>> +#define ACPI_CPU_CONTAINER "\\_SB.CPUS"
>> +
>> typedef struct AcpiCpuHotplug {
>> Object *device;
>> MemoryRegion io;
>> diff --git a/include/hw/acpi/generic_event_device.h
>> b/include/hw/acpi/generic_event_device.h
>> index ba84ce0214..a803ea818e 100644
>> --- a/include/hw/acpi/generic_event_device.h
>> +++ b/include/hw/acpi/generic_event_device.h
>> @@ -60,6 +60,7 @@
>> #define HW_ACPI_GENERIC_EVENT_DEVICE_H
>>
>> #include "hw/sysbus.h"
>> +#include "hw/acpi/cpu_hotplug.h"
>> #include "hw/acpi/memory_hotplug.h"
>> #include "hw/acpi/ghes.h"
>> #include "qom/object.h"
>> @@ -95,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
>> #define ACPI_GED_MEM_HOTPLUG_EVT 0x1
>> #define ACPI_GED_PWR_DOWN_EVT 0x2
>> #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4
>> +#define ACPI_GED_CPU_HOTPLUG_EVT 0x8
>>
>> typedef struct GEDState {
>> MemoryRegion evt;
>> @@ -106,6 +108,9 @@ struct AcpiGedState {
>> SysBusDevice parent_obj;
>> MemHotplugState memhp_state;
>> MemoryRegion container_memhp;
>> + CPUHotplugState cpuhp_state;
>> + MemoryRegion container_cpuhp;
>> + AcpiCpuHotplug cpuhp;
>> GEDState ged_state;
>> uint32_t ged_event_bitmap;
>> qemu_irq irq;
>> --
>> 2.39.1
>>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 10:49 ` Salil Mehta via
2023-09-26 11:12 ` Michael S. Tsirkin
@ 2023-09-26 12:17 ` lixianglai
1 sibling, 0 replies; 32+ messages in thread
From: lixianglai @ 2023-09-26 12:17 UTC (permalink / raw)
To: Salil Mehta, qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Xiaojuan Yang, Song Gao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Salil Mehta via :
> Hi Xianglai,
> FYI. RFC V2 is out and you can now drop the arch agnostic patches from
> your patch-set. Please check the details in the cover letter which one
> you need to pick and rebase from:
>
> https://lore.kernel.org/qemu-devel/20230926100436.28284-1-salil.mehta@huawei.com/T/#t
>
> I am planning to float the architecture agnostic patch-set within this
> week which will have same patches and in same order as mentioned in
> the cover letter. This will untie the development across different
> architectures.
Very Good!
Looking forward to the release of your architecture-independent patches.
I will remove the first two patches in the next version.
Thanks,
Xianglai.
>
> Many thanks
> Salil.
>
>> From: xianglai li <lixianglai@loongson.cn>
>> Sent: Tuesday, September 26, 2023 10:54 AM
>> To: qemu-devel@nongnu.org
>> Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
>> <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>; Xiaojuan
>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
>> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
>> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
>> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
>> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
>> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
>> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
>> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
>> <maobibo@loongson.cn>
>> Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>
>> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
>> is based on PCI and is IO port based and hence existing cpus AML code
>> assumes _CRS objects would evaluate to a system resource which describes
>> IO Port address.
>> But on Loongarch arch CPUs control device(\\_SB.PRES) register interface
>> is memory-mapped hence _CRS object should evaluate to system resource
>> which describes memory-mapped base address.
>>
>> This cpus AML code change updates the existing interface of the build cpus
>> AML
>> function to accept both IO/MEMORY type regions and update the _CRS object
>> correspondingly.
>>
>> Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
>> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
>> Cc: "Bernhard Beschow" <shentey@gmail.com>
>> Cc: "Salil Mehta" <salil.mehta@huawei.com>
>> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> Cc: Song Gao <gaosong@loongson.cn>
>> Cc: "Michael S. Tsirkin" <mst@redhat.com>
>> Cc: Igor Mammedov <imammedo@redhat.com>
>> Cc: Ani Sinha <anisinha@redhat.com>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Richard Henderson <richard.henderson@linaro.org>
>> Cc: Eduardo Habkost <eduardo@habkost.net>
>> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
>> Cc: Yanan Wang <wangyanan55@huawei.com>
>> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
>> Cc: Peter Xu <peterx@redhat.com>
>> Cc: David Hildenbrand <david@redhat.com>
>> Cc: Bibo Mao <maobibo@loongson.cn>
>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>> ---
>> hw/acpi/cpu.c | 20 +++++++++++++++-----
>> hw/i386/acpi-build.c | 3 ++-
>> include/hw/acpi/cpu.h | 5 +++--
>> 3 files changed, 20 insertions(+), 8 deletions(-)
>>
>> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
>> index 5bad983928..0afa04832e 100644
>> --- a/hw/acpi/cpu.c
>> +++ b/hw/acpi/cpu.c
>> @@ -6,6 +6,7 @@
>> #include "qapi/qapi-events-acpi.h"
>> #include "trace.h"
>> #include "sysemu/numa.h"
>> +#include "hw/acpi/cpu_hotplug.h"
>>
>> #define OVMF_CPUHP_SMI_CMD 4
>>
>> @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
>> #define CPU_FW_EJECT_EVENT "CEJF"
>>
>> void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
>> opts,
>> - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
>> + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
>> const char *res_root,
>> - const char *event_handler_method)
>> + const char *event_handler_method,
>> + AmlRegionSpace rs)
>> {
>> Aml *ifctx;
>> Aml *field;
>> @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
>> *machine, CPUHotplugFeatures opts,
>> aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
>>
>> crs = aml_resource_template();
>> - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
>> + if (rs == AML_SYSTEM_IO) {
>> + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
>> mmap_io_base, 1,
>> ACPI_CPU_HOTPLUG_REG_LEN));
>> + } else {
>> + aml_append(crs, aml_memory32_fixed(mmap_io_base,
>> + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE));
>> + }
>> +
>> aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
>>
>> + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
>> /* declare CPU hotplug MMIO region with related access fields */
>> aml_append(cpu_ctrl_dev,
>> - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base),
>> - ACPI_CPU_HOTPLUG_REG_LEN));
>> + aml_operation_region("PRST", rs,
>> + aml_int(mmap_io_base),
>> + ACPI_CPU_HOTPLUG_REG_LEN));
>>
>> field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
>> AML_WRITE_AS_ZEROS);
>> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
>> index 863a939210..7016205d15 100644
>> --- a/hw/i386/acpi-build.c
>> +++ b/hw/i386/acpi-build.c
>> @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
>> .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
>> };
>> build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
>> - pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02");
>> + pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
>> + AML_SYSTEM_IO);
>> }
>>
>> if (pcms->memhp_io_base && nr_mem) {
>> diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
>> index bc901660fb..601f644e57 100644
>> --- a/include/hw/acpi/cpu.h
>> +++ b/include/hw/acpi/cpu.h
>> @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
>> CPUArchIdList *apic_ids,
>> GArray *entry, bool force_enabled);
>>
>> void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
>> opts,
>> - build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
>> + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
>> const char *res_root,
>> - const char *event_handler_method);
>> + const char *event_handler_method,
>> + AmlRegionSpace rs);
>>
>> void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
>> ***list);
>>
>> --
>> 2.39.1
>>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 11:54 ` Michael S. Tsirkin
2023-09-26 12:03 ` Salil Mehta via
@ 2023-09-26 12:30 ` Daniel P. Berrangé
2023-09-27 15:16 ` Michael S. Tsirkin
1 sibling, 1 reply; 32+ messages in thread
From: Daniel P. Berrangé @ 2023-09-26 12:30 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Salil Mehta, xianglai li, qemu-devel, Bernhard Beschow,
Salil Mehta, Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, wangyanan (Y),
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 07:54:04AM -0400, Michael S. Tsirkin wrote:
> On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
> >
> > > From: Michael S. Tsirkin <mst@redhat.com>
> > > Sent: Tuesday, September 26, 2023 12:12 PM
> > > To: Salil Mehta <salil.mehta@huawei.com>
> > > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> > > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > >
> > > On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> > > > Hi Xianglai,
> > > > FYI. RFC V2 is out and you can now drop the arch agnostic patches from
> > > > your patch-set. Please check the details in the cover letter which one
> > > > you need to pick and rebase from:
> > > >
> > > > https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
> > > salil.mehta@huawei.com/T/#t
> > > >
> > > > I am planning to float the architecture agnostic patch-set within this
> > > > week which will have same patches and in same order as mentioned in
> > > > the cover letter. This will untie the development across different
> > > > architectures.
> > > >
> > > > Many thanks
> > > > Salil.
> > >
> > > However, please get authorship info right. This claims patch has been
> > > codeveloped by Bernhard Beschow, xianglai li and yourself.
> > > Your patch claims a completely different list of authors
> >
> > Yes, because those are the people who have developed the patches.
> >
> > > with yourself being the only common author.
> > > Not nice.
> >
> > I have already replied in the other thread. This patch has been
> > taken from the ARM patch-set sent in the year 2020.
> >
> > I am not sure who is the other author and how he has contributed.
> >
> > Co-developed-by usually points at main authors.
> >
>
>
> If you are not sure then find out please.
> And to help you stop guessing at the rules:
>
> Documentation/process/submitting-patches.rst
>
> Co-developed-by: states that the patch was co-created by multiple developers;
> it is used to give attribution to co-authors (in addition to the author
> attributed by the From: tag) when several people work on a single patch. Since
> Co-developed-by: denotes authorship, every Co-developed-by: must be immediately
> followed by a Signed-off-by: of the associated co-author. Standard sign-off
> procedure applies, i.e. the ordering of Signed-off-by: tags should reflect the
> chronological history of the patch insofar as possible, regardless of whether
> the author is attributed via From: or Co-developed-by:. Notably, the last
> Signed-off-by: must always be that of the developer submitting the patch.
Note, that's a linux.git docs requirement you're pointing to,
not a QEMU one.
I don't think QEMU has historically gone about this level
of precise detail/strictness.
Nothing in the DCO requires every co-developer to add a S-o-B.
The person adding a S-o-B is attesting that they are confident
they have the rights to submit this. One way they can attain
this confidence is if the people they worked with add their own
S-o-B but that's not a hard requirement. *If* some co-developers
were working inside the same company and copyright is owned by
the company, it is reasonable to only have one S-o-B for the
person who finally submits it. That's a judgement call the person
submitting can make.
With regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 12:08 ` Michael S. Tsirkin
@ 2023-09-26 12:38 ` Salil Mehta via
2023-09-27 15:18 ` Michael S. Tsirkin
0 siblings, 1 reply; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 12:38 UTC (permalink / raw)
To: Michael S. Tsirkin, lixianglai
Cc: qemu-devel, Salil Mehta, Bernhard Beschow, Xiaojuan Yang,
Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Michael,
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Tuesday, September 26, 2023 1:08 PM
>
> On Tue, Sep 26, 2023 at 07:26:40PM +0800, lixianglai wrote:
> >
> > Hi, Michael S. Tsirkin :
> > > On Tue, Sep 26, 2023 at 05:54:26PM +0800, xianglai li wrote:
> > > > ACPI GED shall be used to convey to the guest kernel about any cpu
> hot-(un)plug
> > > > events. Therefore, existing ACPI GED framework inside QEMU needs to
> be enhanced
> > > > to support CPU hot-(un)plug state and events.
> > > >
> > > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > > This is not the way to handle multiple emails.
> >
> > Oh, sorry, I'll delete the first one.
> >
> > Thanks,
> >
> > Xianglai.
>
> Can you guys figure out together with Salil Mehta what's the
> correct order to merge this? I can't figure out with dueling patches.
We already have an agreed approach and Loongson folks will
rebase from the common patch-set. There is no contention.
Thanks
Salil.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 12:03 ` Salil Mehta via
2023-09-26 12:07 ` Michael S. Tsirkin
@ 2023-09-26 12:49 ` lixianglai
2023-09-27 15:17 ` Michael S. Tsirkin
1 sibling, 1 reply; 32+ messages in thread
From: lixianglai @ 2023-09-26 12:49 UTC (permalink / raw)
To: Salil Mehta, Michael S. Tsirkin
Cc: qemu-devel, Bernhard Beschow, Salil Mehta, Xiaojuan Yang,
Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Salil Mehta via And Michael S. Tsirkin:
>> From: Michael S. Tsirkin <mst@redhat.com>
>> Sent: Tuesday, September 26, 2023 12:54 PM
>> To: Salil Mehta <salil.mehta@huawei.com>
>> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
>> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
>> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
>> Bonzini <pbonzini@redhat.com>; Richard Henderson
>> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
>> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
>> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
>> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
>> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
>> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>
>> On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
>>>> From: Michael S. Tsirkin <mst@redhat.com>
>>>> Sent: Tuesday, September 26, 2023 12:12 PM
>>>> To: Salil Mehta <salil.mehta@huawei.com>
>>>> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org;
>> Bernhard
>>>> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>;
>> Xiaojuan
>>>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
>>>> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
>>>> Bonzini <pbonzini@redhat.com>; Richard Henderson
>>>> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
>>>> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
>>>> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
>>>> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
>>>> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
>>>> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>>>
>>>> On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
>>>>> Hi Xianglai,
>>>>> FYI. RFC V2 is out and you can now drop the arch agnostic patches
>> from
>>>>> your patch-set. Please check the details in the cover letter which
>> one
>>>>> you need to pick and rebase from:
>>>>>
>>>>> https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
>>>> salil.mehta@huawei.com/T/#t
>>>>> I am planning to float the architecture agnostic patch-set within
>> this
>>>>> week which will have same patches and in same order as mentioned in
>>>>> the cover letter. This will untie the development across different
>>>>> architectures.
>>>>>
>>>>> Many thanks
>>>>> Salil.
>>>> However, please get authorship info right. This claims patch has been
>>>> codeveloped by Bernhard Beschow, xianglai li and yourself.
>>>> Your patch claims a completely different list of authors
>>> Yes, because those are the people who have developed the patches.
>>>
>>>> with yourself being the only common author.
>>>> Not nice.
>>> I have already replied in the other thread. This patch has been
>>> taken from the ARM patch-set sent in the year 2020.
>>>
>>> I am not sure who is the other author and how he has contributed.
>>>
>>> Co-developed-by usually points at main authors.
>>>
>>
>> If you are not sure then find out please.
>
> We really have not collaborated on anything as part of
> this entire development of virtual CPU hotplug since the
> year 2020?
>
> I would leave it to Xianglai to answer about the person.
>
I did not participate in the hot swap of arm virtualized cpu.
I just referred to the patch sent by Salil Mehta to the community.
Since his patch has not been integrated into qemu's code repository,
I referred to Salil Mehta's patch to ensure that my code could run.
I added Co-developed-by in order to show respect for the achievements of
his labor,
which is all my fault. I wrongly used Co-developed-by, and I apologize
for that.
I will delete the first two patches until the unrelated patches in Salil
Mehta's architecture are combined,
and then submit my own patch.
Thanks,
Xianglai.
>
>> And to help you stop guessing at the rules:
>>
>> Documentation/process/submitting-patches.rst
>>
>> Co-developed-by: states that the patch was co-created by multiple
>> developers;
>> it is used to give attribution to co-authors (in addition to the
>> author
>> attributed by the From: tag) when several people work on a single
>> patch. Since
>> Co-developed-by: denotes authorship, every Co-developed-by: must be
>> immediately
>> followed by a Signed-off-by: of the associated co-author. Standard
>> sign-off
>> procedure applies, i.e. the ordering of Signed-off-by: tags should
>> reflect the
>> chronological history of the patch insofar as possible, regardless of
>> whether
>> the author is attributed via From: or Co-developed-by:. Notably, the
>> last
>> Signed-off-by: must always be that of the developer submitting the
>> patch.
>
> Sure, ARM patch-set follows exactly above rules.
>
>
>
>>>>>> From: xianglai li <lixianglai@loongson.cn>
>>>>>> Sent: Tuesday, September 26, 2023 10:54 AM
>>>>>> To: qemu-devel@nongnu.org
>>>>>> Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
>>>>>> <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>;
>>>> Xiaojuan
>>>>>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>;
>>>> Michael S.
>>>>>> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani
>>>> Sinha
>>>>>> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
>>>>>> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
>>>>>> <eduardo@habkost.net>; Marcel Apfelbaum
>> <marcel.apfelbaum@gmail.com>;
>>>>>> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
>>>>>> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>;
>>>> Peter
>>>>>> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo
>> Mao
>>>>>> <maobibo@loongson.cn>
>>>>>> Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>>>>>
>>>>>> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
>>>>>> is based on PCI and is IO port based and hence existing cpus AML
>> code
>>>>>> assumes _CRS objects would evaluate to a system resource which
>>>> describes
>>>>>> IO Port address.
>>>>>> But on Loongarch arch CPUs control device(\\_SB.PRES) register
>>>> interface
>>>>>> is memory-mapped hence _CRS object should evaluate to system
>> resource
>>>>>> which describes memory-mapped base address.
>>>>>>
>>>>>> This cpus AML code change updates the existing interface of the
>> build
>>>> cpus
>>>>>> AML
>>>>>> function to accept both IO/MEMORY type regions and update the _CRS
>>>> object
>>>>>> correspondingly.
>>>>>>
>>>>>> Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
>>>>>> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
>>>>>> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
>>>>>> Cc: "Bernhard Beschow" <shentey@gmail.com>
>>>>>> Cc: "Salil Mehta" <salil.mehta@huawei.com>
>>>>>> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
>>>>>> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>>>>>> Cc: Song Gao <gaosong@loongson.cn>
>>>>>> Cc: "Michael S. Tsirkin" <mst@redhat.com>
>>>>>> Cc: Igor Mammedov <imammedo@redhat.com>
>>>>>> Cc: Ani Sinha <anisinha@redhat.com>
>>>>>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>>>>>> Cc: Richard Henderson <richard.henderson@linaro.org>
>>>>>> Cc: Eduardo Habkost <eduardo@habkost.net>
>>>>>> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>>>>>> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
>>>>>> Cc: Yanan Wang <wangyanan55@huawei.com>
>>>>>> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
>>>>>> Cc: Peter Xu <peterx@redhat.com>
>>>>>> Cc: David Hildenbrand <david@redhat.com>
>>>>>> Cc: Bibo Mao <maobibo@loongson.cn>
>>>>>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>>>>>> ---
>>>>>> hw/acpi/cpu.c | 20 +++++++++++++++-----
>>>>>> hw/i386/acpi-build.c | 3 ++-
>>>>>> include/hw/acpi/cpu.h | 5 +++--
>>>>>> 3 files changed, 20 insertions(+), 8 deletions(-)
>>>>>>
>>>>>> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
>>>>>> index 5bad983928..0afa04832e 100644
>>>>>> --- a/hw/acpi/cpu.c
>>>>>> +++ b/hw/acpi/cpu.c
>>>>>> @@ -6,6 +6,7 @@
>>>>>> #include "qapi/qapi-events-acpi.h"
>>>>>> #include "trace.h"
>>>>>> #include "sysemu/numa.h"
>>>>>> +#include "hw/acpi/cpu_hotplug.h"
>>>>>>
>>>>>> #define OVMF_CPUHP_SMI_CMD 4
>>>>>>
>>>>>> @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug =
>> {
>>>>>> #define CPU_FW_EJECT_EVENT "CEJF"
>>>>>>
>>>>>> void build_cpus_aml(Aml *table, MachineState *machine,
>>>> CPUHotplugFeatures
>>>>>> opts,
>>>>>> - build_madt_cpu_fn build_madt_cpu, hwaddr
>> io_base,
>>>>>> + build_madt_cpu_fn build_madt_cpu, hwaddr
>>>> mmap_io_base,
>>>>>> const char *res_root,
>>>>>> - const char *event_handler_method)
>>>>>> + const char *event_handler_method,
>>>>>> + AmlRegionSpace rs)
>>>>>> {
>>>>>> Aml *ifctx;
>>>>>> Aml *field;
>>>>>> @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
>>>>>> *machine, CPUHotplugFeatures opts,
>>>>>> aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
>>>>>>
>>>>>> crs = aml_resource_template();
>>>>>> - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
>>>>>> + if (rs == AML_SYSTEM_IO) {
>>>>>> + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
>>>>>> mmap_io_base, 1,
>>>>>> ACPI_CPU_HOTPLUG_REG_LEN));
>>>>>> + } else {
>>>>>> + aml_append(crs, aml_memory32_fixed(mmap_io_base,
>>>>>> + ACPI_CPU_HOTPLUG_REG_LEN,
>>>> AML_READ_WRITE));
>>>>>> + }
>>>>>> +
>>>>>> aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
>>>>>>
>>>>>> + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
>>>>>> /* declare CPU hotplug MMIO region with related access
>> fields
>>>> */
>>>>>> aml_append(cpu_ctrl_dev,
>>>>>> - aml_operation_region("PRST", AML_SYSTEM_IO,
>>>> aml_int(io_base),
>>>>>> - ACPI_CPU_HOTPLUG_REG_LEN));
>>>>>> + aml_operation_region("PRST", rs,
>>>>>> + aml_int(mmap_io_base),
>>>>>> +
>> ACPI_CPU_HOTPLUG_REG_LEN));
>>>>>> field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
>>>>>> AML_WRITE_AS_ZEROS);
>>>>>> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
>>>>>> index 863a939210..7016205d15 100644
>>>>>> --- a/hw/i386/acpi-build.c
>>>>>> +++ b/hw/i386/acpi-build.c
>>>>>> @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker
>>>> *linker,
>>>>>> .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
>>>>>> };
>>>>>> build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
>>>>>> - pm->cpu_hp_io_base, "\\_SB.PCI0",
>>>> "\\_GPE._E02");
>>>>>> + pm->cpu_hp_io_base, "\\_SB.PCI0",
>>>> "\\_GPE._E02",
>>>>>> + AML_SYSTEM_IO);
>>>>>> }
>>>>>>
>>>>>> if (pcms->memhp_io_base && nr_mem) {
>>>>>> diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
>>>>>> index bc901660fb..601f644e57 100644
>>>>>> --- a/include/hw/acpi/cpu.h
>>>>>> +++ b/include/hw/acpi/cpu.h
>>>>>> @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
>>>>>> CPUArchIdList *apic_ids,
>>>>>> GArray *entry, bool
>> force_enabled);
>>>>>> void build_cpus_aml(Aml *table, MachineState *machine,
>>>> CPUHotplugFeatures
>>>>>> opts,
>>>>>> - build_madt_cpu_fn build_madt_cpu, hwaddr
>> io_base,
>>>>>> + build_madt_cpu_fn build_madt_cpu, hwaddr
>>>> mmap_io_base,
>>>>>> const char *res_root,
>>>>>> - const char *event_handler_method);
>>>>>> + const char *event_handler_method,
>>>>>> + AmlRegionSpace rs);
>>>>>>
>>>>>> void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
>>>>>> ***list);
>>>>>>
>>>>>> --
>>>>>> 2.39.1
>>>>>>
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 12:07 ` Michael S. Tsirkin
@ 2023-09-26 15:52 ` Salil Mehta via
2023-09-26 17:38 ` Michael S. Tsirkin
0 siblings, 1 reply; 32+ messages in thread
From: Salil Mehta via @ 2023-09-26 15:52 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Tuesday, September 26, 2023 1:07 PM
> To: Salil Mehta <salil.mehta@huawei.com>
> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> Bonzini <pbonzini@redhat.com>; Richard Henderson
> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>
> On Tue, Sep 26, 2023 at 12:03:46PM +0000, Salil Mehta wrote:
> > Sure, ARM patch-set follows exactly above rules.
> >
>
>
> Almost.
>
> Co-developed-by: Salil Mehta <salil.mehta@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
>
> You should drop your own Co-developed-by as well as multiple Signed-off-by.
https://docs.kernel.org/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by
Reference: Co-developed-by: Pasting excerpt from above link:
"1. Standard sign-off procedure applies, i.e. the ordering of
Signed-off-by: tags should reflect the chronological history
of the patch insofar as possible, regardless of whether the
author is attributed via From: or Co-developed-by:.
2.Notably, the last Signed-off-by: must always be that of the
developer submitting the patch."
To be able to achieve 1. I have to put Co-developed-by: of
mine at the top as I am the main author of the patch-set
historically and have been continually driving the work.
(It is a common rule even within the kernel to keep first
SOB that of the main author)
Reference: Signed-off-by: Excerpt from above link:
" Any further SoBs (Signed-off-by:'s) following the author's
SoB are from people handling and transporting the patch, but
were not involved in its development. SoB chains should
reflect the real route a patch took as it was propagated to
the maintainers and ultimately to Linus, with the first SoB
entry signalling primary authorship of a single author."
And since I am the person who is submitting the patches
(which might or not be the same in future) I need to put
my SOB in any case to be able to achieve 2.
This is to ensure primary author remains the first SOD/CDY.
Thanks
Salil.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 15:52 ` Salil Mehta via
@ 2023-09-26 17:38 ` Michael S. Tsirkin
0 siblings, 0 replies; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-26 17:38 UTC (permalink / raw)
To: Salil Mehta
Cc: xianglai li, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 03:52:48PM +0000, Salil Mehta wrote:
> > From: Michael S. Tsirkin <mst@redhat.com>
> > Sent: Tuesday, September 26, 2023 1:07 PM
> > To: Salil Mehta <salil.mehta@huawei.com>
> > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> >
> > On Tue, Sep 26, 2023 at 12:03:46PM +0000, Salil Mehta wrote:
> > > Sure, ARM patch-set follows exactly above rules.
> > >
> >
> >
> > Almost.
> >
> > Co-developed-by: Salil Mehta <salil.mehta@huawei.com>
> > Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> > Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> > Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> > Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> >
> > You should drop your own Co-developed-by as well as multiple Signed-off-by.
>
>
> https://docs.kernel.org/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by
>
> Reference: Co-developed-by: Pasting excerpt from above link:
>
> "1. Standard sign-off procedure applies, i.e. the ordering of
> Signed-off-by: tags should reflect the chronological history
> of the patch insofar as possible, regardless of whether the
> author is attributed via From: or Co-developed-by:.
> 2.Notably, the last Signed-off-by: must always be that of the
> developer submitting the patch."
>
> To be able to achieve 1. I have to put Co-developed-by: of
> mine at the top as I am the main author of the patch-set
> historically and have been continually driving the work.
> (It is a common rule even within the kernel to keep first
> SOB that of the main author)
yes that is fine.
> Reference: Signed-off-by: Excerpt from above link:
>
> " Any further SoBs (Signed-off-by:'s) following the author's
> SoB are from people handling and transporting the patch, but
> were not involved in its development. SoB chains should
> reflect the real route a patch took as it was propagated to
> the maintainers and ultimately to Linus, with the first SoB
> entry signalling primary authorship of a single author."
>
>
> And since I am the person who is submitting the patches
> (which might or not be the same in future) I need to put
> my SOB in any case to be able to achieve 2.
>
> This is to ensure primary author remains the first SOD/CDY.
>
>
> Thanks
> Salil.
I think you misunderstand what it says -
you don't need to repeat signatures many times.
you took the patches that were signed off by people A,B,C
and sent to me. Thus you do:
S.o.b: A
S.o.b: B
S.o.b: C
S.o.b: Salil Mehta
and I add:
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
and send to Linus.
--
MST`
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU
2023-09-26 10:58 ` Salil Mehta via
@ 2023-09-27 2:26 ` lixianglai
0 siblings, 0 replies; 32+ messages in thread
From: lixianglai @ 2023-09-27 2:26 UTC (permalink / raw)
To: Salil Mehta, qemu-devel
Cc: Bernhard Beschow, Salil Mehta, Xiaojuan Yang, Song Gao,
Michael S. Tsirkin, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Salil Mehta:
> Hi Xianglai,
>
>> From: xianglai li <lixianglai@loongson.cn>
>> Sent: Tuesday, September 26, 2023 10:55 AM
>> To: qemu-devel@nongnu.org
>> Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
>> <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>; Xiaojuan
>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Michael S.
>> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani Sinha
>> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
>> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
>> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>;
>> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
>> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>; Peter
>> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo Mao
>> <maobibo@loongson.cn>
>> Subject: [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU
>>
>> Add new types of GED devices for Loongarch machines,
>> add CPU hot-(un)plug event response and address spaces,
>> and update the ACPI table.
>>
>> Cc: "Bernhard Beschow" <shentey@gmail.com>
>> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
>> Cc: "Salil Mehta" <salil.mehta@huawei.com>
>> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>> Cc: Song Gao <gaosong@loongson.cn>
>> Cc: "Michael S. Tsirkin" <mst@redhat.com>
>> Cc: Igor Mammedov <imammedo@redhat.com>
>> Cc: Ani Sinha <anisinha@redhat.com>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Richard Henderson <richard.henderson@linaro.org>
>> Cc: Eduardo Habkost <eduardo@habkost.net>
>> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
>> Cc: Yanan Wang <wangyanan55@huawei.com>
>> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
>> Cc: Peter Xu <peterx@redhat.com>
>> Cc: David Hildenbrand <david@redhat.com>
>> Cc: Bibo Mao <maobibo@loongson.cn>
>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>> ---
>> hw/acpi/acpi-cpu-hotplug-stub.c | 9 +++++++++
>> hw/loongarch/acpi-build.c | 34 ++++++++++++++++++++++++++++++++-
>> hw/loongarch/virt.c | 3 ++-
>> include/hw/loongarch/virt.h | 1 +
>> 4 files changed, 45 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/acpi/acpi-cpu-hotplug-stub.c b/hw/acpi/acpi-cpu-hotplug-
>> stub.c
>> index 2aec90d968..b3ac7a1e31 100644
>> --- a/hw/acpi/acpi-cpu-hotplug-stub.c
>> +++ b/hw/acpi/acpi-cpu-hotplug-stub.c
>> @@ -19,6 +19,15 @@ void legacy_acpi_cpu_hotplug_init(MemoryRegion *parent,
>> Object *owner,
>> return;
>> }
>>
>> +void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures
>> opts,
>> + build_madt_cpu_fn build_madt_cpu, hwaddr mmap_io_base,
>> + const char *res_root,
>> + const char *event_handler_method,
>> + AmlRegionSpace rs)
>> +{
>> + return;
>> +}
>> +
>> void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
>> ***list)
>> {
>> return;
Ok, I'll take care of that.
Thanks,
Xianglai.
>
> Above change is already part of the architecture agnostic patch-set.
> Not required here!
>
> Thanks
> Salil.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 12:30 ` Daniel P. Berrangé
@ 2023-09-27 15:16 ` Michael S. Tsirkin
0 siblings, 0 replies; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-27 15:16 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: Salil Mehta, xianglai li, qemu-devel, Bernhard Beschow,
Salil Mehta, Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha,
Paolo Bonzini, Richard Henderson, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, wangyanan (Y),
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 01:30:30PM +0100, Daniel P. Berrangé wrote:
> On Tue, Sep 26, 2023 at 07:54:04AM -0400, Michael S. Tsirkin wrote:
> > On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
> > >
> > > > From: Michael S. Tsirkin <mst@redhat.com>
> > > > Sent: Tuesday, September 26, 2023 12:12 PM
> > > > To: Salil Mehta <salil.mehta@huawei.com>
> > > > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> > > > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> > > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > > > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > > > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > > > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > > > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > > > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > > > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > > > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > > > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > > >
> > > > On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> > > > > Hi Xianglai,
> > > > > FYI. RFC V2 is out and you can now drop the arch agnostic patches from
> > > > > your patch-set. Please check the details in the cover letter which one
> > > > > you need to pick and rebase from:
> > > > >
> > > > > https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
> > > > salil.mehta@huawei.com/T/#t
> > > > >
> > > > > I am planning to float the architecture agnostic patch-set within this
> > > > > week which will have same patches and in same order as mentioned in
> > > > > the cover letter. This will untie the development across different
> > > > > architectures.
> > > > >
> > > > > Many thanks
> > > > > Salil.
> > > >
> > > > However, please get authorship info right. This claims patch has been
> > > > codeveloped by Bernhard Beschow, xianglai li and yourself.
> > > > Your patch claims a completely different list of authors
> > >
> > > Yes, because those are the people who have developed the patches.
> > >
> > > > with yourself being the only common author.
> > > > Not nice.
> > >
> > > I have already replied in the other thread. This patch has been
> > > taken from the ARM patch-set sent in the year 2020.
> > >
> > > I am not sure who is the other author and how he has contributed.
> > >
> > > Co-developed-by usually points at main authors.
> > >
> >
> >
> > If you are not sure then find out please.
> > And to help you stop guessing at the rules:
> >
> > Documentation/process/submitting-patches.rst
> >
> > Co-developed-by: states that the patch was co-created by multiple developers;
> > it is used to give attribution to co-authors (in addition to the author
> > attributed by the From: tag) when several people work on a single patch. Since
> > Co-developed-by: denotes authorship, every Co-developed-by: must be immediately
> > followed by a Signed-off-by: of the associated co-author. Standard sign-off
> > procedure applies, i.e. the ordering of Signed-off-by: tags should reflect the
> > chronological history of the patch insofar as possible, regardless of whether
> > the author is attributed via From: or Co-developed-by:. Notably, the last
> > Signed-off-by: must always be that of the developer submitting the patch.
>
> Note, that's a linux.git docs requirement you're pointing to,
> not a QEMU one.
>
> I don't think QEMU has historically gone about this level
> of precise detail/strictness.
>
> Nothing in the DCO requires every co-developer to add a S-o-B.
> The person adding a S-o-B is attesting that they are confident
> they have the rights to submit this. One way they can attain
> this confidence is if the people they worked with add their own
> S-o-B but that's not a hard requirement. *If* some co-developers
> were working inside the same company and copyright is owned by
> the company, it is reasonable to only have one S-o-B for the
> person who finally submits it. That's a judgement call the person
> submitting can make.
>
> With regards,
> Daniel
We really should write the rules up btw.
And, I think it would be a really bad idea to use exactly
the same tag as linux with a slightly different set of rules.
> --
> |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
> |: https://libvirt.org -o- https://fstop138.berrange.com :|
> |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-26 12:49 ` lixianglai
@ 2023-09-27 15:17 ` Michael S. Tsirkin
2023-09-28 1:36 ` lixianglai
0 siblings, 1 reply; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-27 15:17 UTC (permalink / raw)
To: lixianglai
Cc: Salil Mehta, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 08:49:27PM +0800, lixianglai wrote:
>
> Hi Salil Mehta via And Michael S. Tsirkin:
> > > From: Michael S. Tsirkin <mst@redhat.com>
> > > Sent: Tuesday, September 26, 2023 12:54 PM
> > > To: Salil Mehta <salil.mehta@huawei.com>
> > > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
> > > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
> > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > >
> > > On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
> > > > > From: Michael S. Tsirkin <mst@redhat.com>
> > > > > Sent: Tuesday, September 26, 2023 12:12 PM
> > > > > To: Salil Mehta <salil.mehta@huawei.com>
> > > > > Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org;
> > > Bernhard
> > > > > Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>;
> > > Xiaojuan
> > > > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
> > > > > Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
> > > > > Bonzini <pbonzini@redhat.com>; Richard Henderson
> > > > > <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
> > > > > Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> > > > > <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
> > > > > Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
> > > > > Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
> > > > > Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > > > >
> > > > > On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
> > > > > > Hi Xianglai,
> > > > > > FYI. RFC V2 is out and you can now drop the arch agnostic patches
> > > from
> > > > > > your patch-set. Please check the details in the cover letter which
> > > one
> > > > > > you need to pick and rebase from:
> > > > > >
> > > > > > https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
> > > > > salil.mehta@huawei.com/T/#t
> > > > > > I am planning to float the architecture agnostic patch-set within
> > > this
> > > > > > week which will have same patches and in same order as mentioned in
> > > > > > the cover letter. This will untie the development across different
> > > > > > architectures.
> > > > > >
> > > > > > Many thanks
> > > > > > Salil.
> > > > > However, please get authorship info right. This claims patch has been
> > > > > codeveloped by Bernhard Beschow, xianglai li and yourself.
> > > > > Your patch claims a completely different list of authors
> > > > Yes, because those are the people who have developed the patches.
> > > >
> > > > > with yourself being the only common author.
> > > > > Not nice.
> > > > I have already replied in the other thread. This patch has been
> > > > taken from the ARM patch-set sent in the year 2020.
> > > >
> > > > I am not sure who is the other author and how he has contributed.
> > > >
> > > > Co-developed-by usually points at main authors.
> > > >
> > >
> > > If you are not sure then find out please.
> >
> > We really have not collaborated on anything as part of
> > this entire development of virtual CPU hotplug since the
> > year 2020?
> >
> > I would leave it to Xianglai to answer about the person.
> >
>
> I did not participate in the hot swap of arm virtualized cpu.
>
> I just referred to the patch sent by Salil Mehta to the community.
>
> Since his patch has not been integrated into qemu's code repository,
>
> I referred to Salil Mehta's patch to ensure that my code could run.
>
> I added Co-developed-by in order to show respect for the achievements of his
> labor,
>
> which is all my fault. I wrongly used Co-developed-by, and I apologize for
> that.
>
> I will delete the first two patches until the unrelated patches in Salil
> Mehta's architecture are combined,
>
> and then submit my own patch.
>
>
> Thanks,
>
> Xianglai.
I see. The correct way is to simply keep the original author.
I don't know what you used to apply the patch but e.g. git am
will do exactly that for you.
Add your own S.O.B at the bottom and you are all set.
>
> >
> > > And to help you stop guessing at the rules:
> > >
> > > Documentation/process/submitting-patches.rst
> > >
> > > Co-developed-by: states that the patch was co-created by multiple
> > > developers;
> > > it is used to give attribution to co-authors (in addition to the
> > > author
> > > attributed by the From: tag) when several people work on a single
> > > patch. Since
> > > Co-developed-by: denotes authorship, every Co-developed-by: must be
> > > immediately
> > > followed by a Signed-off-by: of the associated co-author. Standard
> > > sign-off
> > > procedure applies, i.e. the ordering of Signed-off-by: tags should
> > > reflect the
> > > chronological history of the patch insofar as possible, regardless of
> > > whether
> > > the author is attributed via From: or Co-developed-by:. Notably, the
> > > last
> > > Signed-off-by: must always be that of the developer submitting the
> > > patch.
> >
> > Sure, ARM patch-set follows exactly above rules.
> >
> >
> >
> > > > > > > From: xianglai li <lixianglai@loongson.cn>
> > > > > > > Sent: Tuesday, September 26, 2023 10:54 AM
> > > > > > > To: qemu-devel@nongnu.org
> > > > > > > Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
> > > > > > > <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>;
> > > > > Xiaojuan
> > > > > > > Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>;
> > > > > Michael S.
> > > > > > > Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani
> > > > > Sinha
> > > > > > > <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
> > > > > > > Henderson <richard.henderson@linaro.org>; Eduardo Habkost
> > > > > > > <eduardo@habkost.net>; Marcel Apfelbaum
> > > <marcel.apfelbaum@gmail.com>;
> > > > > > > Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
> > > > > > > <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>;
> > > > > Peter
> > > > > > > Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo
> > > Mao
> > > > > > > <maobibo@loongson.cn>
> > > > > > > Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
> > > > > > >
> > > > > > > CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
> > > > > > > is based on PCI and is IO port based and hence existing cpus AML
> > > code
> > > > > > > assumes _CRS objects would evaluate to a system resource which
> > > > > describes
> > > > > > > IO Port address.
> > > > > > > But on Loongarch arch CPUs control device(\\_SB.PRES) register
> > > > > interface
> > > > > > > is memory-mapped hence _CRS object should evaluate to system
> > > resource
> > > > > > > which describes memory-mapped base address.
> > > > > > >
> > > > > > > This cpus AML code change updates the existing interface of the
> > > build
> > > > > cpus
> > > > > > > AML
> > > > > > > function to accept both IO/MEMORY type regions and update the _CRS
> > > > > object
> > > > > > > correspondingly.
> > > > > > >
> > > > > > > Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
> > > > > > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > > > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > > > > > > Cc: "Bernhard Beschow" <shentey@gmail.com>
> > > > > > > Cc: "Salil Mehta" <salil.mehta@huawei.com>
> > > > > > > Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > > > > Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> > > > > > > Cc: Song Gao <gaosong@loongson.cn>
> > > > > > > Cc: "Michael S. Tsirkin" <mst@redhat.com>
> > > > > > > Cc: Igor Mammedov <imammedo@redhat.com>
> > > > > > > Cc: Ani Sinha <anisinha@redhat.com>
> > > > > > > Cc: Paolo Bonzini <pbonzini@redhat.com>
> > > > > > > Cc: Richard Henderson <richard.henderson@linaro.org>
> > > > > > > Cc: Eduardo Habkost <eduardo@habkost.net>
> > > > > > > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > > > > > > Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
> > > > > > > Cc: Yanan Wang <wangyanan55@huawei.com>
> > > > > > > Cc: "Daniel P. Berrangé" <berrange@redhat.com>
> > > > > > > Cc: Peter Xu <peterx@redhat.com>
> > > > > > > Cc: David Hildenbrand <david@redhat.com>
> > > > > > > Cc: Bibo Mao <maobibo@loongson.cn>
> > > > > > > Signed-off-by: xianglai li <lixianglai@loongson.cn>
> > > > > > > ---
> > > > > > > hw/acpi/cpu.c | 20 +++++++++++++++-----
> > > > > > > hw/i386/acpi-build.c | 3 ++-
> > > > > > > include/hw/acpi/cpu.h | 5 +++--
> > > > > > > 3 files changed, 20 insertions(+), 8 deletions(-)
> > > > > > >
> > > > > > > diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
> > > > > > > index 5bad983928..0afa04832e 100644
> > > > > > > --- a/hw/acpi/cpu.c
> > > > > > > +++ b/hw/acpi/cpu.c
> > > > > > > @@ -6,6 +6,7 @@
> > > > > > > #include "qapi/qapi-events-acpi.h"
> > > > > > > #include "trace.h"
> > > > > > > #include "sysemu/numa.h"
> > > > > > > +#include "hw/acpi/cpu_hotplug.h"
> > > > > > >
> > > > > > > #define OVMF_CPUHP_SMI_CMD 4
> > > > > > >
> > > > > > > @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug =
> > > {
> > > > > > > #define CPU_FW_EJECT_EVENT "CEJF"
> > > > > > >
> > > > > > > void build_cpus_aml(Aml *table, MachineState *machine,
> > > > > CPUHotplugFeatures
> > > > > > > opts,
> > > > > > > - build_madt_cpu_fn build_madt_cpu, hwaddr
> > > io_base,
> > > > > > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> > > > > mmap_io_base,
> > > > > > > const char *res_root,
> > > > > > > - const char *event_handler_method)
> > > > > > > + const char *event_handler_method,
> > > > > > > + AmlRegionSpace rs)
> > > > > > > {
> > > > > > > Aml *ifctx;
> > > > > > > Aml *field;
> > > > > > > @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
> > > > > > > *machine, CPUHotplugFeatures opts,
> > > > > > > aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
> > > > > > >
> > > > > > > crs = aml_resource_template();
> > > > > > > - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
> > > > > > > + if (rs == AML_SYSTEM_IO) {
> > > > > > > + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
> > > > > > > mmap_io_base, 1,
> > > > > > > ACPI_CPU_HOTPLUG_REG_LEN));
> > > > > > > + } else {
> > > > > > > + aml_append(crs, aml_memory32_fixed(mmap_io_base,
> > > > > > > + ACPI_CPU_HOTPLUG_REG_LEN,
> > > > > AML_READ_WRITE));
> > > > > > > + }
> > > > > > > +
> > > > > > > aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
> > > > > > >
> > > > > > > + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
> > > > > > > /* declare CPU hotplug MMIO region with related access
> > > fields
> > > > > */
> > > > > > > aml_append(cpu_ctrl_dev,
> > > > > > > - aml_operation_region("PRST", AML_SYSTEM_IO,
> > > > > aml_int(io_base),
> > > > > > > - ACPI_CPU_HOTPLUG_REG_LEN));
> > > > > > > + aml_operation_region("PRST", rs,
> > > > > > > + aml_int(mmap_io_base),
> > > > > > > +
> > > ACPI_CPU_HOTPLUG_REG_LEN));
> > > > > > > field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
> > > > > > > AML_WRITE_AS_ZEROS);
> > > > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> > > > > > > index 863a939210..7016205d15 100644
> > > > > > > --- a/hw/i386/acpi-build.c
> > > > > > > +++ b/hw/i386/acpi-build.c
> > > > > > > @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker
> > > > > *linker,
> > > > > > > .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
> > > > > > > };
> > > > > > > build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
> > > > > > > - pm->cpu_hp_io_base, "\\_SB.PCI0",
> > > > > "\\_GPE._E02");
> > > > > > > + pm->cpu_hp_io_base, "\\_SB.PCI0",
> > > > > "\\_GPE._E02",
> > > > > > > + AML_SYSTEM_IO);
> > > > > > > }
> > > > > > >
> > > > > > > if (pcms->memhp_io_base && nr_mem) {
> > > > > > > diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
> > > > > > > index bc901660fb..601f644e57 100644
> > > > > > > --- a/include/hw/acpi/cpu.h
> > > > > > > +++ b/include/hw/acpi/cpu.h
> > > > > > > @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
> > > > > > > CPUArchIdList *apic_ids,
> > > > > > > GArray *entry, bool
> > > force_enabled);
> > > > > > > void build_cpus_aml(Aml *table, MachineState *machine,
> > > > > CPUHotplugFeatures
> > > > > > > opts,
> > > > > > > - build_madt_cpu_fn build_madt_cpu, hwaddr
> > > io_base,
> > > > > > > + build_madt_cpu_fn build_madt_cpu, hwaddr
> > > > > mmap_io_base,
> > > > > > > const char *res_root,
> > > > > > > - const char *event_handler_method);
> > > > > > > + const char *event_handler_method,
> > > > > > > + AmlRegionSpace rs);
> > > > > > >
> > > > > > > void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
> > > > > > > ***list);
> > > > > > >
> > > > > > > --
> > > > > > > 2.39.1
> > > > > > >
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug
2023-09-26 12:38 ` Salil Mehta via
@ 2023-09-27 15:18 ` Michael S. Tsirkin
0 siblings, 0 replies; 32+ messages in thread
From: Michael S. Tsirkin @ 2023-09-27 15:18 UTC (permalink / raw)
To: Salil Mehta
Cc: lixianglai, qemu-devel, Salil Mehta, Bernhard Beschow,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
On Tue, Sep 26, 2023 at 12:38:44PM +0000, Salil Mehta wrote:
> Hi Michael,
>
> > From: Michael S. Tsirkin <mst@redhat.com>
> > Sent: Tuesday, September 26, 2023 1:08 PM
> >
> > On Tue, Sep 26, 2023 at 07:26:40PM +0800, lixianglai wrote:
> > >
> > > Hi, Michael S. Tsirkin :
> > > > On Tue, Sep 26, 2023 at 05:54:26PM +0800, xianglai li wrote:
> > > > > ACPI GED shall be used to convey to the guest kernel about any cpu
> > hot-(un)plug
> > > > > events. Therefore, existing ACPI GED framework inside QEMU needs to
> > be enhanced
> > > > > to support CPU hot-(un)plug state and events.
> > > > >
> > > > > Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
> > > > > Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
> > > > This is not the way to handle multiple emails.
> > >
> > > Oh, sorry, I'll delete the first one.
> > >
> > > Thanks,
> > >
> > > Xianglai.
> >
> > Can you guys figure out together with Salil Mehta what's the
> > correct order to merge this? I can't figure out with dueling patches.
>
> We already have an agreed approach and Loongson folks will
> rebase from the common patch-set. There is no contention.
>
> Thanks
> Salil.
>
>
Great, thanks a lot!
--
MST
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
2023-09-27 15:17 ` Michael S. Tsirkin
@ 2023-09-28 1:36 ` lixianglai
0 siblings, 0 replies; 32+ messages in thread
From: lixianglai @ 2023-09-28 1:36 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Salil Mehta, qemu-devel, Bernhard Beschow, Salil Mehta,
Xiaojuan Yang, Song Gao, Igor Mammedov, Ani Sinha, Paolo Bonzini,
Richard Henderson, Eduardo Habkost, Marcel Apfelbaum,
Philippe Mathieu-Daudé, wangyanan (Y),
Daniel P. Berrangé,
Peter Xu, David Hildenbrand, Bibo Mao
Hi Michael S. Tsirkin:
> On Tue, Sep 26, 2023 at 08:49:27PM +0800, lixianglai wrote:
>> Hi Salil Mehta via And Michael S. Tsirkin:
>>>> From: Michael S. Tsirkin <mst@redhat.com>
>>>> Sent: Tuesday, September 26, 2023 12:54 PM
>>>> To: Salil Mehta <salil.mehta@huawei.com>
>>>> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org; Bernhard
>>>> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>; Xiaojuan
>>>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
>>>> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
>>>> Bonzini <pbonzini@redhat.com>; Richard Henderson
>>>> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
>>>> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
>>>> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
>>>> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
>>>> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
>>>> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>>>
>>>> On Tue, Sep 26, 2023 at 11:45:19AM +0000, Salil Mehta wrote:
>>>>>> From: Michael S. Tsirkin <mst@redhat.com>
>>>>>> Sent: Tuesday, September 26, 2023 12:12 PM
>>>>>> To: Salil Mehta <salil.mehta@huawei.com>
>>>>>> Cc: xianglai li <lixianglai@loongson.cn>; qemu-devel@nongnu.org;
>>>> Bernhard
>>>>>> Beschow <shentey@gmail.com>; Salil Mehta <salil.mehta@opnsrc.net>;
>>>> Xiaojuan
>>>>>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>; Igor
>>>>>> Mammedov <imammedo@redhat.com>; Ani Sinha <anisinha@redhat.com>; Paolo
>>>>>> Bonzini <pbonzini@redhat.com>; Richard Henderson
>>>>>> <richard.henderson@linaro.org>; Eduardo Habkost <eduardo@habkost.net>;
>>>>>> Marcel Apfelbaum <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
>>>>>> <philmd@linaro.org>; wangyanan (Y) <wangyanan55@huawei.com>; Daniel P.
>>>>>> Berrangé <berrange@redhat.com>; Peter Xu <peterx@redhat.com>; David
>>>>>> Hildenbrand <david@redhat.com>; Bibo Mao <maobibo@loongson.cn>
>>>>>> Subject: Re: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>>>>>
>>>>>> On Tue, Sep 26, 2023 at 10:49:08AM +0000, Salil Mehta wrote:
>>>>>>> Hi Xianglai,
>>>>>>> FYI. RFC V2 is out and you can now drop the arch agnostic patches
>>>> from
>>>>>>> your patch-set. Please check the details in the cover letter which
>>>> one
>>>>>>> you need to pick and rebase from:
>>>>>>>
>>>>>>> https://lore.kernel.org/qemu-devel/20230926100436.28284-1-
>>>>>> salil.mehta@huawei.com/T/#t
>>>>>>> I am planning to float the architecture agnostic patch-set within
>>>> this
>>>>>>> week which will have same patches and in same order as mentioned in
>>>>>>> the cover letter. This will untie the development across different
>>>>>>> architectures.
>>>>>>>
>>>>>>> Many thanks
>>>>>>> Salil.
>>>>>> However, please get authorship info right. This claims patch has been
>>>>>> codeveloped by Bernhard Beschow, xianglai li and yourself.
>>>>>> Your patch claims a completely different list of authors
>>>>> Yes, because those are the people who have developed the patches.
>>>>>
>>>>>> with yourself being the only common author.
>>>>>> Not nice.
>>>>> I have already replied in the other thread. This patch has been
>>>>> taken from the ARM patch-set sent in the year 2020.
>>>>>
>>>>> I am not sure who is the other author and how he has contributed.
>>>>>
>>>>> Co-developed-by usually points at main authors.
>>>>>
>>>> If you are not sure then find out please.
>>> We really have not collaborated on anything as part of
>>> this entire development of virtual CPU hotplug since the
>>> year 2020?
>>>
>>> I would leave it to Xianglai to answer about the person.
>>>
>> I did not participate in the hot swap of arm virtualized cpu.
>>
>> I just referred to the patch sent by Salil Mehta to the community.
>>
>> Since his patch has not been integrated into qemu's code repository,
>>
>> I referred to Salil Mehta's patch to ensure that my code could run.
>>
>> I added Co-developed-by in order to show respect for the achievements of his
>> labor,
>>
>> which is all my fault. I wrongly used Co-developed-by, and I apologize for
>> that.
>>
>> I will delete the first two patches until the unrelated patches in Salil
>> Mehta's architecture are combined,
>>
>> and then submit my own patch.
>>
>>
>> Thanks,
>>
>> Xianglai.
> I see. The correct way is to simply keep the original author.
> I don't know what you used to apply the patch but e.g. git am
> will do exactly that for you.
> Add your own S.O.B at the bottom and you are all set.
Oh, I see.
Thank you very much,
Xianglai.
>
>>>> And to help you stop guessing at the rules:
>>>>
>>>> Documentation/process/submitting-patches.rst
>>>>
>>>> Co-developed-by: states that the patch was co-created by multiple
>>>> developers;
>>>> it is used to give attribution to co-authors (in addition to the
>>>> author
>>>> attributed by the From: tag) when several people work on a single
>>>> patch. Since
>>>> Co-developed-by: denotes authorship, every Co-developed-by: must be
>>>> immediately
>>>> followed by a Signed-off-by: of the associated co-author. Standard
>>>> sign-off
>>>> procedure applies, i.e. the ordering of Signed-off-by: tags should
>>>> reflect the
>>>> chronological history of the patch insofar as possible, regardless of
>>>> whether
>>>> the author is attributed via From: or Co-developed-by:. Notably, the
>>>> last
>>>> Signed-off-by: must always be that of the developer submitting the
>>>> patch.
>>> Sure, ARM patch-set follows exactly above rules.
>>>
>>>
>>>
>>>>>>>> From: xianglai li <lixianglai@loongson.cn>
>>>>>>>> Sent: Tuesday, September 26, 2023 10:54 AM
>>>>>>>> To: qemu-devel@nongnu.org
>>>>>>>> Cc: Bernhard Beschow <shentey@gmail.com>; Salil Mehta
>>>>>>>> <salil.mehta@opnsrc.net>; Salil Mehta <salil.mehta@huawei.com>;
>>>>>> Xiaojuan
>>>>>>>> Yang <yangxiaojuan@loongson.cn>; Song Gao <gaosong@loongson.cn>;
>>>>>> Michael S.
>>>>>>>> Tsirkin <mst@redhat.com>; Igor Mammedov <imammedo@redhat.com>; Ani
>>>>>> Sinha
>>>>>>>> <anisinha@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
>>>>>>>> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
>>>>>>>> <eduardo@habkost.net>; Marcel Apfelbaum
>>>> <marcel.apfelbaum@gmail.com>;
>>>>>>>> Philippe Mathieu-Daudé <philmd@linaro.org>; wangyanan (Y)
>>>>>>>> <wangyanan55@huawei.com>; Daniel P. Berrangé <berrange@redhat.com>;
>>>>>> Peter
>>>>>>>> Xu <peterx@redhat.com>; David Hildenbrand <david@redhat.com>; Bibo
>>>> Mao
>>>>>>>> <maobibo@loongson.cn>
>>>>>>>> Subject: [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change
>>>>>>>>
>>>>>>>> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch
>>>>>>>> is based on PCI and is IO port based and hence existing cpus AML
>>>> code
>>>>>>>> assumes _CRS objects would evaluate to a system resource which
>>>>>> describes
>>>>>>>> IO Port address.
>>>>>>>> But on Loongarch arch CPUs control device(\\_SB.PRES) register
>>>>>> interface
>>>>>>>> is memory-mapped hence _CRS object should evaluate to system
>>>> resource
>>>>>>>> which describes memory-mapped base address.
>>>>>>>>
>>>>>>>> This cpus AML code change updates the existing interface of the
>>>> build
>>>>>> cpus
>>>>>>>> AML
>>>>>>>> function to accept both IO/MEMORY type regions and update the _CRS
>>>>>> object
>>>>>>>> correspondingly.
>>>>>>>>
>>>>>>>> Co-authored-by: "Bernhard Beschow" <shentey@gmail.com>
>>>>>>>> Co-authored-by: "Salil Mehta" <salil.mehta@opnsrc.net>
>>>>>>>> Co-authored-by: "Salil Mehta" <salil.mehta@huawei.com>
>>>>>>>> Cc: "Bernhard Beschow" <shentey@gmail.com>
>>>>>>>> Cc: "Salil Mehta" <salil.mehta@huawei.com>
>>>>>>>> Cc: "Salil Mehta" <salil.mehta@opnsrc.net>
>>>>>>>> Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
>>>>>>>> Cc: Song Gao <gaosong@loongson.cn>
>>>>>>>> Cc: "Michael S. Tsirkin" <mst@redhat.com>
>>>>>>>> Cc: Igor Mammedov <imammedo@redhat.com>
>>>>>>>> Cc: Ani Sinha <anisinha@redhat.com>
>>>>>>>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>>>>>>>> Cc: Richard Henderson <richard.henderson@linaro.org>
>>>>>>>> Cc: Eduardo Habkost <eduardo@habkost.net>
>>>>>>>> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>>>>>>>> Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
>>>>>>>> Cc: Yanan Wang <wangyanan55@huawei.com>
>>>>>>>> Cc: "Daniel P. Berrangé" <berrange@redhat.com>
>>>>>>>> Cc: Peter Xu <peterx@redhat.com>
>>>>>>>> Cc: David Hildenbrand <david@redhat.com>
>>>>>>>> Cc: Bibo Mao <maobibo@loongson.cn>
>>>>>>>> Signed-off-by: xianglai li <lixianglai@loongson.cn>
>>>>>>>> ---
>>>>>>>> hw/acpi/cpu.c | 20 +++++++++++++++-----
>>>>>>>> hw/i386/acpi-build.c | 3 ++-
>>>>>>>> include/hw/acpi/cpu.h | 5 +++--
>>>>>>>> 3 files changed, 20 insertions(+), 8 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
>>>>>>>> index 5bad983928..0afa04832e 100644
>>>>>>>> --- a/hw/acpi/cpu.c
>>>>>>>> +++ b/hw/acpi/cpu.c
>>>>>>>> @@ -6,6 +6,7 @@
>>>>>>>> #include "qapi/qapi-events-acpi.h"
>>>>>>>> #include "trace.h"
>>>>>>>> #include "sysemu/numa.h"
>>>>>>>> +#include "hw/acpi/cpu_hotplug.h"
>>>>>>>>
>>>>>>>> #define OVMF_CPUHP_SMI_CMD 4
>>>>>>>>
>>>>>>>> @@ -332,9 +333,10 @@ const VMStateDescription vmstate_cpu_hotplug =
>>>> {
>>>>>>>> #define CPU_FW_EJECT_EVENT "CEJF"
>>>>>>>>
>>>>>>>> void build_cpus_aml(Aml *table, MachineState *machine,
>>>>>> CPUHotplugFeatures
>>>>>>>> opts,
>>>>>>>> - build_madt_cpu_fn build_madt_cpu, hwaddr
>>>> io_base,
>>>>>>>> + build_madt_cpu_fn build_madt_cpu, hwaddr
>>>>>> mmap_io_base,
>>>>>>>> const char *res_root,
>>>>>>>> - const char *event_handler_method)
>>>>>>>> + const char *event_handler_method,
>>>>>>>> + AmlRegionSpace rs)
>>>>>>>> {
>>>>>>>> Aml *ifctx;
>>>>>>>> Aml *field;
>>>>>>>> @@ -359,14 +361,22 @@ void build_cpus_aml(Aml *table, MachineState
>>>>>>>> *machine, CPUHotplugFeatures opts,
>>>>>>>> aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
>>>>>>>>
>>>>>>>> crs = aml_resource_template();
>>>>>>>> - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
>>>>>>>> + if (rs == AML_SYSTEM_IO) {
>>>>>>>> + aml_append(crs, aml_io(AML_DECODE16, mmap_io_base,
>>>>>>>> mmap_io_base, 1,
>>>>>>>> ACPI_CPU_HOTPLUG_REG_LEN));
>>>>>>>> + } else {
>>>>>>>> + aml_append(crs, aml_memory32_fixed(mmap_io_base,
>>>>>>>> + ACPI_CPU_HOTPLUG_REG_LEN,
>>>>>> AML_READ_WRITE));
>>>>>>>> + }
>>>>>>>> +
>>>>>>>> aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
>>>>>>>>
>>>>>>>> + g_assert(rs == AML_SYSTEM_IO || rs == AML_SYSTEM_MEMORY);
>>>>>>>> /* declare CPU hotplug MMIO region with related access
>>>> fields
>>>>>> */
>>>>>>>> aml_append(cpu_ctrl_dev,
>>>>>>>> - aml_operation_region("PRST", AML_SYSTEM_IO,
>>>>>> aml_int(io_base),
>>>>>>>> - ACPI_CPU_HOTPLUG_REG_LEN));
>>>>>>>> + aml_operation_region("PRST", rs,
>>>>>>>> + aml_int(mmap_io_base),
>>>>>>>> +
>>>> ACPI_CPU_HOTPLUG_REG_LEN));
>>>>>>>> field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
>>>>>>>> AML_WRITE_AS_ZEROS);
>>>>>>>> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
>>>>>>>> index 863a939210..7016205d15 100644
>>>>>>>> --- a/hw/i386/acpi-build.c
>>>>>>>> +++ b/hw/i386/acpi-build.c
>>>>>>>> @@ -1550,7 +1550,8 @@ build_dsdt(GArray *table_data, BIOSLinker
>>>>>> *linker,
>>>>>>>> .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
>>>>>>>> };
>>>>>>>> build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
>>>>>>>> - pm->cpu_hp_io_base, "\\_SB.PCI0",
>>>>>> "\\_GPE._E02");
>>>>>>>> + pm->cpu_hp_io_base, "\\_SB.PCI0",
>>>>>> "\\_GPE._E02",
>>>>>>>> + AML_SYSTEM_IO);
>>>>>>>> }
>>>>>>>>
>>>>>>>> if (pcms->memhp_io_base && nr_mem) {
>>>>>>>> diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
>>>>>>>> index bc901660fb..601f644e57 100644
>>>>>>>> --- a/include/hw/acpi/cpu.h
>>>>>>>> +++ b/include/hw/acpi/cpu.h
>>>>>>>> @@ -60,9 +60,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const
>>>>>>>> CPUArchIdList *apic_ids,
>>>>>>>> GArray *entry, bool
>>>> force_enabled);
>>>>>>>> void build_cpus_aml(Aml *table, MachineState *machine,
>>>>>> CPUHotplugFeatures
>>>>>>>> opts,
>>>>>>>> - build_madt_cpu_fn build_madt_cpu, hwaddr
>>>> io_base,
>>>>>>>> + build_madt_cpu_fn build_madt_cpu, hwaddr
>>>>>> mmap_io_base,
>>>>>>>> const char *res_root,
>>>>>>>> - const char *event_handler_method);
>>>>>>>> + const char *event_handler_method,
>>>>>>>> + AmlRegionSpace rs);
>>>>>>>>
>>>>>>>> void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList
>>>>>>>> ***list);
>>>>>>>>
>>>>>>>> --
>>>>>>>> 2.39.1
>>>>>>>>
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2023-09-28 1:37 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-26 9:54 [PATCH v3 0/7] *** Adds CPU hot-plug support to Loongarch *** xianglai li
2023-09-26 9:54 ` [PATCH v3 1/7] Update ACPI GED framework to support vcpu hot-(un)plug xianglai li
2023-09-26 10:50 ` Salil Mehta via
2023-09-26 12:16 ` lixianglai
2023-09-26 11:02 ` Michael S. Tsirkin
2023-09-26 11:26 ` lixianglai
2023-09-26 12:08 ` Michael S. Tsirkin
2023-09-26 12:38 ` Salil Mehta via
2023-09-27 15:18 ` Michael S. Tsirkin
2023-09-26 12:03 ` Michael S. Tsirkin
2023-09-26 9:54 ` [PATCH v3 2/7] Update CPUs AML with cpu-(ctrl)dev change xianglai li
2023-09-26 10:49 ` Salil Mehta via
2023-09-26 11:12 ` Michael S. Tsirkin
2023-09-26 11:45 ` Salil Mehta via
2023-09-26 11:54 ` Michael S. Tsirkin
2023-09-26 12:03 ` Salil Mehta via
2023-09-26 12:07 ` Michael S. Tsirkin
2023-09-26 15:52 ` Salil Mehta via
2023-09-26 17:38 ` Michael S. Tsirkin
2023-09-26 12:49 ` lixianglai
2023-09-27 15:17 ` Michael S. Tsirkin
2023-09-28 1:36 ` lixianglai
2023-09-26 12:30 ` Daniel P. Berrangé
2023-09-27 15:16 ` Michael S. Tsirkin
2023-09-26 12:17 ` lixianglai
2023-09-26 9:54 ` [PATCH v3 3/7] Added CPU topology support for Loongarch xianglai li
2023-09-26 9:54 ` [PATCH v3 4/7] Optimize loongarch_irq_init function implementation xianglai li
2023-09-26 9:54 ` [PATCH v3 5/7] Add basic CPU hot-(un)plug support for Loongarch xianglai li
2023-09-26 9:54 ` [PATCH v3 6/7] Add support of *unrealize* for Loongarch cpu xianglai li
2023-09-26 9:54 ` [PATCH v3 7/7] Update the ACPI table for the Loongarch CPU xianglai li
2023-09-26 10:58 ` Salil Mehta via
2023-09-27 2:26 ` lixianglai
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.