* [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface
@ 2020-04-18 15:04 Richard Henderson
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
` (6 more replies)
0 siblings, 7 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
Replace 4 separate routines with a single routine taking a vece
parameter. This avoids several targets needing to create this
interface internally.
I noticed this in particular reviewing the riscv code; I'm not
sure why it took three targets to notice. ;-)
r~
Richard Henderson (7):
tcg: Add tcg_gen_gvec_dup_imm
target/s390x: Use tcg_gen_gvec_dup_imm
target/ppc: Use tcg_gen_gvec_dup_imm
target/arm: Use tcg_gen_gvec_dup_imm
tcg: Use tcg_gen_gvec_dup_imm in logical simplifications
tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i
tcg: Add tcg_gen_gvec_dup_tl
include/tcg/tcg-op-gvec.h | 11 +++++---
target/arm/translate-a64.c | 10 +++----
target/arm/translate-sve.c | 12 ++++-----
target/arm/translate.c | 9 ++++---
target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++----------
target/ppc/translate/vsx-impl.inc.c | 2 +-
target/s390x/translate_vx.inc.c | 41 ++++++-----------------------
tcg/tcg-op-gvec.c | 35 +++++-------------------
8 files changed, 57 insertions(+), 95 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 3:17 ` LIU Zhiwei
` (2 more replies)
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
` (5 subsequent siblings)
6 siblings, 3 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
Add a version of tcg_gen_dup_* that takes both immediate and
a vector element size operand. This will replace the set of
tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element
size within the function name.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 2 ++
tcg/tcg-op-gvec.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index 74534e2480..eb0d47a42b 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -313,6 +313,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t s, uint32_t m);
+void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, uint64_t imm);
void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
uint32_t m, TCGv_i32);
void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 327d9588e0..593bb4542e 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1569,6 +1569,13 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
}
+void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint64_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x);
+}
+
void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 7:29 ` David Hildenbrand
` (2 more replies)
2020-04-18 15:04 ` [PATCH 3/7] target/ppc: " Richard Henderson
` (4 subsequent siblings)
6 siblings, 3 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
The gen_gvec_dupi switch is unnecessarily with the new function.
Replace it with a local gen_gvec_dup_imm that takes care of the
register to offset conversion and length arguments.
Drop zero_vec and use use gen_gvec_dup_imm with 0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/translate_vx.inc.c | 41 +++++++--------------------------
1 file changed, 8 insertions(+), 33 deletions(-)
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 24558cce80..12347f8a03 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -231,8 +231,8 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_mov(v1, v2) \
tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
16)
-#define gen_gvec_dup64i(v1, c) \
- tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+#define gen_gvec_dup_imm(es, v1, c) \
+ tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
#define gen_gvec_fn_2(fn, es, v1, v2) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16)
@@ -316,31 +316,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
tcg_temp_free_i64(cl);
}
-static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
-{
- switch (es) {
- case ES_8:
- tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
- break;
- case ES_16:
- tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
- break;
- case ES_32:
- tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
- break;
- case ES_64:
- gen_gvec_dup64i(reg, c);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
-static void zero_vec(uint8_t reg)
-{
- tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
-}
-
static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
uint64_t b)
{
@@ -396,8 +371,8 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
* Masks for both 64 bit elements of the vector are the same.
* Trust tcg to produce a good constant loading.
*/
- gen_gvec_dup64i(get_field(s, v1),
- generate_byte_mask(i2 & 0xff));
+ gen_gvec_dup_imm(ES_64, get_field(s, v1),
+ generate_byte_mask(i2 & 0xff));
} else {
TCGv_i64 t = tcg_temp_new_i64();
@@ -432,7 +407,7 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
}
}
- gen_gvec_dupi(es, get_field(s, v1), mask);
+ gen_gvec_dup_imm(es, get_field(s, v1), mask);
return DISAS_NEXT;
}
@@ -585,7 +560,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
t = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
- zero_vec(get_field(s, v1));
+ gen_gvec_dup_imm(es, get_field(s, v1), 0);
write_vec_element_i64(t, get_field(s, v1), enr, es);
tcg_temp_free_i64(t);
return DISAS_NEXT;
@@ -892,7 +867,7 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
return DISAS_NORETURN;
}
- gen_gvec_dupi(es, get_field(s, v1), data);
+ gen_gvec_dup_imm(es, get_field(s, v1), data);
return DISAS_NEXT;
}
@@ -1372,7 +1347,7 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
}
- zero_vec(get_field(s, v1));
+ gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
tcg_temp_free_i32(tmp);
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 3/7] target/ppc: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 3:41 ` David Gibson
2020-04-20 10:34 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 4/7] target/arm: " Richard Henderson
` (3 subsequent siblings)
6 siblings, 2 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
We can now unify the implementation of the 3 VSPLTI instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++++-------------
target/ppc/translate/vsx-impl.inc.c | 2 +-
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 81d5a7a341..403ed3a01c 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1035,21 +1035,25 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
-#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- int simm; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- simm = SIMM5(ctx->opcode); \
- tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
+static void gen_vsplti(DisasContext *ctx, int vece)
+{
+ int simm;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
}
-GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
-GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
-GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
+ simm = SIMM5(ctx->opcode);
+ tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
+}
+
+#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
+
+GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
+GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
+GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
#define GEN_VXFORM_NOA(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -1559,7 +1563,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
#undef GEN_VXRFORM_DUAL
#undef GEN_VXRFORM1
#undef GEN_VXRFORM
-#undef GEN_VXFORM_DUPI
+#undef GEN_VXFORM_VSPLTI
#undef GEN_VXFORM_NOA
#undef GEN_VXFORM_UIMM
#undef GEN_VAFORM_PAIRED
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 8287e272f5..b518de46db 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1579,7 +1579,7 @@ static void gen_xxspltib(DisasContext *ctx)
return;
}
}
- tcg_gen_gvec_dup8i(vsr_full_offset(rt), 16, 16, uim8);
+ tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
}
static void gen_xxsldwi(DisasContext *ctx)
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 4/7] target/arm: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
` (2 preceding siblings ...)
2020-04-18 15:04 ` [PATCH 3/7] target/ppc: " Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 13:24 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
` (2 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
In a few cases, we're able to remove some manual replication.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 10 +++++-----
target/arm/translate-sve.c | 12 +++++-------
target/arm/translate.c | 9 ++++++---
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7580e46367..095638e09a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -519,7 +519,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
tcg_temp_free_i64(tcg_zero);
}
if (vsz > 16) {
- tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);
+ tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
}
}
@@ -7794,8 +7794,8 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
/* MOVI or MVNI, with MVNI negation handled above. */
- tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
- vec_full_reg_size(s), imm);
+ tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
+ vec_full_reg_size(s), imm);
} else {
/* ORR or BIC, with BIC negation to AND handled above. */
if (is_neg) {
@@ -10223,8 +10223,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
if (is_u) {
if (shift == 8 << size) {
/* Shift count the same size as element size produces zero. */
- tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),
- is_q ? 16 : 8, vec_full_reg_size(s), 0);
+ tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd),
+ is_q ? 16 : 8, vec_full_reg_size(s), 0);
} else {
gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);
}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b35bad245e..6c8bda4e4c 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -177,7 +177,7 @@ static bool do_mov_z(DisasContext *s, int rd, int rn)
static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
{
unsigned vsz = vec_full_reg_size(s);
- tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), vsz, vsz, word);
+ tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
}
/* Invoke a vector expander on two Pregs. */
@@ -1453,7 +1453,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
unsigned oprsz = size_for_gvec(setsz / 8);
if (oprsz * 8 == setsz) {
- tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
+ tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word);
goto done;
}
}
@@ -2044,7 +2044,7 @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
} else {
- tcg_gen_gvec_dup64i(dofs, vsz, vsz, 0);
+ tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
}
}
return true;
@@ -3260,9 +3260,7 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
/* Decode the VFP immediate. */
imm = vfp_expand_imm(a->esz, a->imm);
- imm = dup_const(a->esz, imm);
-
- tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm);
+ tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm);
}
return true;
}
@@ -3276,7 +3274,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
unsigned vsz = vec_full_reg_size(s);
int dofs = vec_full_reg_offset(s, a->rd);
- tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm));
+ tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
}
return true;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9f9f4e19e0..af4d3ff4c9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5386,7 +5386,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
MIN(shift, (8 << size) - 1),
vec_size, vec_size);
} else if (shift >= 8 << size) {
- tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
+ tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
+ vec_size, 0);
} else {
tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
@@ -5437,7 +5438,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
* architecturally valid and results in zero.
*/
if (shift >= 8 << size) {
- tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
+ tcg_gen_gvec_dup_imm(size, rd_ofs,
+ vec_size, vec_size, 0);
} else {
tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
@@ -5783,7 +5785,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
tcg_temp_free_i64(t64);
} else {
- tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm);
+ tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
+ vec_size, imm);
}
}
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
` (3 preceding siblings ...)
2020-04-18 15:04 ` [PATCH 4/7] target/arm: " Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 4:30 ` LIU Zhiwei
2020-04-20 13:32 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
6 siblings, 2 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
Replace the outgoing interface.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op-gvec.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 593bb4542e..de16c027b3 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -2326,7 +2326,7 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
};
if (aofs == bofs) {
- tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
+ tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
@@ -2343,7 +2343,7 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
};
if (aofs == bofs) {
- tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
+ tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
@@ -2360,7 +2360,7 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
};
if (aofs == bofs) {
- tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
+ tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
@@ -2411,7 +2411,7 @@ void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
};
if (aofs == bofs) {
- tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
+ tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
} else {
tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
` (4 preceding siblings ...)
2020-04-18 15:04 ` [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 4:33 ` LIU Zhiwei
` (2 more replies)
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
6 siblings, 3 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
These interfaces are now unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 5 -----
tcg/tcg-op-gvec.c | 28 ----------------------------
2 files changed, 33 deletions(-)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index eb0d47a42b..fa8a0c8d03 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -320,11 +320,6 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
uint32_t m, TCGv_i64);
-void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
-void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
-void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
-void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
-
void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index de16c027b3..5a6cc19812 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1541,34 +1541,6 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
}
}
-void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
- uint32_t maxsz, uint64_t x)
-{
- check_size_align(oprsz, maxsz, dofs);
- do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
-}
-
-void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
- uint32_t maxsz, uint32_t x)
-{
- check_size_align(oprsz, maxsz, dofs);
- do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
-}
-
-void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
- uint32_t maxsz, uint16_t x)
-{
- check_size_align(oprsz, maxsz, dofs);
- do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
-}
-
-void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
- uint32_t maxsz, uint8_t x)
-{
- check_size_align(oprsz, maxsz, dofs);
- do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
-}
-
void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
uint32_t maxsz, uint64_t x)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
` (5 preceding siblings ...)
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
@ 2020-04-18 15:04 ` Richard Henderson
2020-04-20 4:42 ` LIU Zhiwei
` (2 more replies)
6 siblings, 3 replies; 29+ messages in thread
From: Richard Henderson @ 2020-04-18 15:04 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, david, zhiwei_liu, david
For use when a target needs to pass a configure-specific
target_ulong value to duplicate.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index fa8a0c8d03..d89f91f40e 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -320,6 +320,12 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
uint32_t m, TCGv_i64);
+#if TARGET_LONG_BITS == 64
+# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
+#else
+# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
+#endif
+
void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
--
2.20.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
@ 2020-04-20 3:17 ` LIU Zhiwei
2020-04-20 7:29 ` David Hildenbrand
2020-04-20 9:43 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: LIU Zhiwei @ 2020-04-20 3:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, david, david
On 2020/4/18 23:04, Richard Henderson wrote:
> Add a version of tcg_gen_dup_* that takes both immediate and
> a vector element size operand. This will replace the set of
> tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element
> size within the function name.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Zhiwei
> ---
> include/tcg/tcg-op-gvec.h | 2 ++
> tcg/tcg-op-gvec.c | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index 74534e2480..eb0d47a42b 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -313,6 +313,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
>
> void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t s, uint32_t m);
> +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s,
> + uint32_t m, uint64_t imm);
> void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i32);
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 327d9588e0..593bb4542e 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1569,6 +1569,13 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
> }
>
> +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint64_t x)
> +{
> + check_size_align(oprsz, maxsz, dofs);
> + do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x);
> +}
> +
> void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t oprsz, uint32_t maxsz)
> {
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/7] target/ppc: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 3/7] target/ppc: " Richard Henderson
@ 2020-04-20 3:41 ` David Gibson
2020-04-20 10:34 ` Alex Bennée
1 sibling, 0 replies; 29+ messages in thread
From: David Gibson @ 2020-04-20 3:41 UTC (permalink / raw)
To: Richard Henderson; +Cc: peter.maydell, zhiwei_liu, qemu-devel, david
[-- Attachment #1: Type: text/plain, Size: 3625 bytes --]
On Sat, Apr 18, 2020 at 08:04:07AM -0700, Richard Henderson wrote:
> We can now unify the implementation of the 3 VSPLTI instructions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++++-------------
> target/ppc/translate/vsx-impl.inc.c | 2 +-
> 2 files changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
> index 81d5a7a341..403ed3a01c 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -1035,21 +1035,25 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
> GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
> vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
>
> -#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> - { \
> - int simm; \
> - if (unlikely(!ctx->altivec_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_VPU); \
> - return; \
> - } \
> - simm = SIMM5(ctx->opcode); \
> - tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
> +static void gen_vsplti(DisasContext *ctx, int vece)
> +{
> + int simm;
> +
> + if (unlikely(!ctx->altivec_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VPU);
> + return;
> }
>
> -GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
> -GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
> -GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
> + simm = SIMM5(ctx->opcode);
> + tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
> +}
> +
> +#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
> +static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
> +
> +GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
> +GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
> +GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
>
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
> static void glue(gen_, name)(DisasContext *ctx) \
> @@ -1559,7 +1563,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
> #undef GEN_VXRFORM_DUAL
> #undef GEN_VXRFORM1
> #undef GEN_VXRFORM
> -#undef GEN_VXFORM_DUPI
> +#undef GEN_VXFORM_VSPLTI
> #undef GEN_VXFORM_NOA
> #undef GEN_VXFORM_UIMM
> #undef GEN_VAFORM_PAIRED
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 8287e272f5..b518de46db 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1579,7 +1579,7 @@ static void gen_xxspltib(DisasContext *ctx)
> return;
> }
> }
> - tcg_gen_gvec_dup8i(vsr_full_offset(rt), 16, 16, uim8);
> + tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
> }
>
> static void gen_xxsldwi(DisasContext *ctx)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications
2020-04-18 15:04 ` [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
@ 2020-04-20 4:30 ` LIU Zhiwei
2020-04-20 13:32 ` Alex Bennée
1 sibling, 0 replies; 29+ messages in thread
From: LIU Zhiwei @ 2020-04-20 4:30 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, david, david
On 2020/4/18 23:04, Richard Henderson wrote:
> Replace the outgoing interface.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Zhiwei
> ---
> tcg/tcg-op-gvec.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 593bb4542e..de16c027b3 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -2326,7 +2326,7 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
> @@ -2343,7 +2343,7 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
> @@ -2360,7 +2360,7 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
> @@ -2411,7 +2411,7 @@ void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
@ 2020-04-20 4:33 ` LIU Zhiwei
2020-04-20 7:29 ` David Hildenbrand
2020-04-20 13:32 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: LIU Zhiwei @ 2020-04-20 4:33 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, david, david
On 2020/4/18 23:04, Richard Henderson wrote:
> These interfaces are now unused.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Zhiwei
> ---
> include/tcg/tcg-op-gvec.h | 5 -----
> tcg/tcg-op-gvec.c | 28 ----------------------------
> 2 files changed, 33 deletions(-)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index eb0d47a42b..fa8a0c8d03 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -320,11 +320,6 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i64);
>
> -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
> -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
> -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
> -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
> -
> void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
> int64_t shift, uint32_t oprsz, uint32_t maxsz);
> void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index de16c027b3..5a6cc19812 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1541,34 +1541,6 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> }
> }
>
> -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint64_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint32_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint16_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint8_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
> uint32_t maxsz, uint64_t x)
> {
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
@ 2020-04-20 4:42 ` LIU Zhiwei
2020-04-20 7:30 ` David Hildenbrand
2020-04-20 13:32 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: LIU Zhiwei @ 2020-04-20 4:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, david, david
On 2020/4/18 23:04, Richard Henderson wrote:
> For use when a target needs to pass a configure-specific
> target_ulong value to duplicate.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Zhiwei
> ---
> include/tcg/tcg-op-gvec.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index fa8a0c8d03..d89f91f40e 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -320,6 +320,12 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i64);
>
> +#if TARGET_LONG_BITS == 64
> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
> +#else
> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
> +#endif
> +
> void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
> int64_t shift, uint32_t oprsz, uint32_t maxsz);
> void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
@ 2020-04-20 7:29 ` David Hildenbrand
2020-04-20 9:46 ` Alex Bennée
2020-04-20 10:06 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: David Hildenbrand @ 2020-04-20 7:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, zhiwei_liu, david
On 18.04.20 17:04, Richard Henderson wrote:
> The gen_gvec_dupi switch is unnecessarily with the new function.
> Replace it with a local gen_gvec_dup_imm that takes care of the
> register to offset conversion and length arguments.
>
> Drop zero_vec and use use gen_gvec_dup_imm with 0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Nice cleanup, thanks!
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20 3:17 ` LIU Zhiwei
@ 2020-04-20 7:29 ` David Hildenbrand
2020-04-20 9:43 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: David Hildenbrand @ 2020-04-20 7:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, zhiwei_liu, david
On 18.04.20 17:04, Richard Henderson wrote:
> Add a version of tcg_gen_dup_* that takes both immediate and
> a vector element size operand. This will replace the set of
> tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element
> size within the function name.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 2 ++
> tcg/tcg-op-gvec.c | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index 74534e2480..eb0d47a42b 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -313,6 +313,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
>
> void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t s, uint32_t m);
> +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s,
> + uint32_t m, uint64_t imm);
> void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i32);
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 327d9588e0..593bb4542e 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1569,6 +1569,13 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
> }
>
> +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint64_t x)
> +{
> + check_size_align(oprsz, maxsz, dofs);
> + do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x);
> +}
> +
> void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t oprsz, uint32_t maxsz)
> {
>
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
2020-04-20 4:33 ` LIU Zhiwei
@ 2020-04-20 7:29 ` David Hildenbrand
2020-04-20 13:32 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: David Hildenbrand @ 2020-04-20 7:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, zhiwei_liu, david
On 18.04.20 17:04, Richard Henderson wrote:
> These interfaces are now unused.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 5 -----
> tcg/tcg-op-gvec.c | 28 ----------------------------
> 2 files changed, 33 deletions(-)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index eb0d47a42b..fa8a0c8d03 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -320,11 +320,6 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i64);
>
> -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
> -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
> -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
> -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
> -
> void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
> int64_t shift, uint32_t oprsz, uint32_t maxsz);
> void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index de16c027b3..5a6cc19812 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1541,34 +1541,6 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> }
> }
>
> -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint64_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint32_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint16_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint8_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
> uint32_t maxsz, uint64_t x)
> {
>
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
2020-04-20 4:42 ` LIU Zhiwei
@ 2020-04-20 7:30 ` David Hildenbrand
2020-04-20 14:52 ` Richard Henderson
2020-04-20 13:32 ` Alex Bennée
2 siblings, 1 reply; 29+ messages in thread
From: David Hildenbrand @ 2020-04-20 7:30 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, zhiwei_liu, david
On 18.04.20 17:04, Richard Henderson wrote:
> For use when a target needs to pass a configure-specific
> target_ulong value to duplicate.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index fa8a0c8d03..d89f91f40e 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -320,6 +320,12 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i64);
>
> +#if TARGET_LONG_BITS == 64
> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
> +#else
> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
> +#endif
> +
Any user in mind?
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20 3:17 ` LIU Zhiwei
2020-04-20 7:29 ` David Hildenbrand
@ 2020-04-20 9:43 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 9:43 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> Add a version of tcg_gen_dup_* that takes both immediate and
> a vector element size operand. This will replace the set of
> tcg_gen_gvec_dup{8,16,32,64}i functions that encode the element
> size within the function name.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 2 ++
> tcg/tcg-op-gvec.c | 7 +++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index 74534e2480..eb0d47a42b 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -313,6 +313,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
>
> void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t s, uint32_t m);
> +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s,
> + uint32_t m, uint64_t imm);
> void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i32);
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 327d9588e0..593bb4542e 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1569,6 +1569,13 @@ void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
> }
>
> +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint64_t x)
> +{
> + check_size_align(oprsz, maxsz, dofs);
> + do_dup(vece, dofs, oprsz, maxsz, NULL, NULL, x);
> +}
> +
> void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t oprsz, uint32_t maxsz)
> {
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20 7:29 ` David Hildenbrand
@ 2020-04-20 9:46 ` Alex Bennée
2020-04-20 10:06 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 9:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> The gen_gvec_dupi switch is unnecessarily with the new function.
> Replace it with a local gen_gvec_dup_imm that takes care of the
> register to offset conversion and length arguments.
>
> Drop zero_vec and use use gen_gvec_dup_imm with 0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/s390x/translate_vx.inc.c | 41 +++++++--------------------------
> 1 file changed, 8 insertions(+), 33 deletions(-)
>
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 24558cce80..12347f8a03 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -231,8 +231,8 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
> #define gen_gvec_mov(v1, v2) \
> tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
> 16)
> -#define gen_gvec_dup64i(v1, c) \
> - tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
> +#define gen_gvec_dup_imm(es, v1, c) \
> + tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
> #define gen_gvec_fn_2(fn, es, v1, v2) \
> tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> 16, 16)
> @@ -316,31 +316,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
> tcg_temp_free_i64(cl);
> }
>
> -static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
> -{
> - switch (es) {
> - case ES_8:
> - tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
> - break;
> - case ES_16:
> - tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
> - break;
> - case ES_32:
> - tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
> - break;
> - case ES_64:
> - gen_gvec_dup64i(reg, c);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> -}
> -
> -static void zero_vec(uint8_t reg)
> -{
> - tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
> -}
> -
> static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
> uint64_t b)
> {
> @@ -396,8 +371,8 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
> * Masks for both 64 bit elements of the vector are the same.
> * Trust tcg to produce a good constant loading.
> */
> - gen_gvec_dup64i(get_field(s, v1),
> - generate_byte_mask(i2 & 0xff));
> + gen_gvec_dup_imm(ES_64, get_field(s, v1),
> + generate_byte_mask(i2 & 0xff));
> } else {
> TCGv_i64 t = tcg_temp_new_i64();
>
> @@ -432,7 +407,7 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
> }
> }
>
> - gen_gvec_dupi(es, get_field(s, v1), mask);
> + gen_gvec_dup_imm(es, get_field(s, v1), mask);
> return DISAS_NEXT;
> }
>
> @@ -585,7 +560,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
>
> t = tcg_temp_new_i64();
> tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
> - zero_vec(get_field(s, v1));
> + gen_gvec_dup_imm(es, get_field(s, v1), 0);
> write_vec_element_i64(t, get_field(s, v1), enr, es);
> tcg_temp_free_i64(t);
> return DISAS_NEXT;
> @@ -892,7 +867,7 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
> return DISAS_NORETURN;
> }
>
> - gen_gvec_dupi(es, get_field(s, v1), data);
> + gen_gvec_dup_imm(es, get_field(s, v1), data);
> return DISAS_NEXT;
> }
>
> @@ -1372,7 +1347,7 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
> read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
> tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
> }
> - zero_vec(get_field(s, v1));
> + gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
> write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
>
> tcg_temp_free_i32(tmp);
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20 7:29 ` David Hildenbrand
2020-04-20 9:46 ` Alex Bennée
@ 2020-04-20 10:06 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 10:06 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> The gen_gvec_dupi switch is unnecessarily with the new function.
> Replace it with a local gen_gvec_dup_imm that takes care of the
> register to offset conversion and length arguments.
>
> Drop zero_vec and use use gen_gvec_dup_imm with 0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/s390x/translate_vx.inc.c | 41 +++++++--------------------------
> 1 file changed, 8 insertions(+), 33 deletions(-)
>
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 24558cce80..12347f8a03 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -231,8 +231,8 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
> #define gen_gvec_mov(v1, v2) \
> tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
> 16)
> -#define gen_gvec_dup64i(v1, c) \
> - tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
> +#define gen_gvec_dup_imm(es, v1, c) \
> + tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
> #define gen_gvec_fn_2(fn, es, v1, v2) \
> tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> 16, 16)
> @@ -316,31 +316,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
> tcg_temp_free_i64(cl);
> }
>
> -static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
> -{
> - switch (es) {
> - case ES_8:
> - tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
> - break;
> - case ES_16:
> - tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
> - break;
> - case ES_32:
> - tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
> - break;
> - case ES_64:
> - gen_gvec_dup64i(reg, c);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> -}
> -
> -static void zero_vec(uint8_t reg)
> -{
> - tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
> -}
> -
> static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
> uint64_t b)
> {
> @@ -396,8 +371,8 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
> * Masks for both 64 bit elements of the vector are the same.
> * Trust tcg to produce a good constant loading.
> */
> - gen_gvec_dup64i(get_field(s, v1),
> - generate_byte_mask(i2 & 0xff));
> + gen_gvec_dup_imm(ES_64, get_field(s, v1),
> + generate_byte_mask(i2 & 0xff));
> } else {
> TCGv_i64 t = tcg_temp_new_i64();
>
> @@ -432,7 +407,7 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
> }
> }
>
> - gen_gvec_dupi(es, get_field(s, v1), mask);
> + gen_gvec_dup_imm(es, get_field(s, v1), mask);
> return DISAS_NEXT;
> }
>
> @@ -585,7 +560,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
>
> t = tcg_temp_new_i64();
> tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
> - zero_vec(get_field(s, v1));
> + gen_gvec_dup_imm(es, get_field(s, v1), 0);
> write_vec_element_i64(t, get_field(s, v1), enr, es);
> tcg_temp_free_i64(t);
> return DISAS_NEXT;
> @@ -892,7 +867,7 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
> return DISAS_NORETURN;
> }
>
> - gen_gvec_dupi(es, get_field(s, v1), data);
> + gen_gvec_dup_imm(es, get_field(s, v1), data);
> return DISAS_NEXT;
> }
>
> @@ -1372,7 +1347,7 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
> read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
> tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
> }
> - zero_vec(get_field(s, v1));
> + gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
> write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
>
> tcg_temp_free_i32(tmp);
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/7] target/ppc: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 3/7] target/ppc: " Richard Henderson
2020-04-20 3:41 ` David Gibson
@ 2020-04-20 10:34 ` Alex Bennée
2020-04-21 17:50 ` Richard Henderson
1 sibling, 1 reply; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 10:34 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> We can now unify the implementation of the 3 VSPLTI instructions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++++-------------
> target/ppc/translate/vsx-impl.inc.c | 2 +-
> 2 files changed, 19 insertions(+), 15 deletions(-)
>
> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
> index 81d5a7a341..403ed3a01c 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -1035,21 +1035,25 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
> GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
> vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
>
> -#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
> -static void glue(gen_, name)(DisasContext *ctx) \
> - { \
> - int simm; \
> - if (unlikely(!ctx->altivec_enabled)) { \
> - gen_exception(ctx, POWERPC_EXCP_VPU); \
> - return; \
> - } \
> - simm = SIMM5(ctx->opcode); \
> - tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
> +static void gen_vsplti(DisasContext *ctx, int vece)
> +{
> + int simm;
> +
> + if (unlikely(!ctx->altivec_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VPU);
> + return;
> }
>
> -GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
> -GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
> -GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
> + simm = SIMM5(ctx->opcode);
> + tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
> +}
> +
> +#define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
> +static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
> +
> +GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
> +GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
> +GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
There are unused parameters opc2/opc3 parameters here. Given that is it
really worth the glue obfuscation:
static void gen_vspltisb(DisasContext *ctx)
{
gen_vsplti(ctx, MO_8);
}
static void gen_vspltish(DisasContext *ctx)
{
gen_vsplti(ctx, MO_8);
}
static void gen_vspltisw(DisasContext *ctx)
{
gen_vsplti(ctx, MO_8);
}
Of course I tried grepping for their use and couldn't find them until I
realised the call to them was hidden inside another glue operation.
With the removed extra unused macro params:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
> static void glue(gen_, name)(DisasContext *ctx) \
> @@ -1559,7 +1563,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
> #undef GEN_VXRFORM_DUAL
> #undef GEN_VXRFORM1
> #undef GEN_VXRFORM
> -#undef GEN_VXFORM_DUPI
> +#undef GEN_VXFORM_VSPLTI
> #undef GEN_VXFORM_NOA
> #undef GEN_VXFORM_UIMM
> #undef GEN_VAFORM_PAIRED
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 8287e272f5..b518de46db 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1579,7 +1579,7 @@ static void gen_xxspltib(DisasContext *ctx)
> return;
> }
> }
> - tcg_gen_gvec_dup8i(vsr_full_offset(rt), 16, 16, uim8);
> + tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8);
> }
>
> static void gen_xxsldwi(DisasContext *ctx)
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 4/7] target/arm: Use tcg_gen_gvec_dup_imm
2020-04-18 15:04 ` [PATCH 4/7] target/arm: " Richard Henderson
@ 2020-04-20 13:24 ` Alex Bennée
0 siblings, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 13:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> In a few cases, we're able to remove some manual replication.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/arm/translate-a64.c | 10 +++++-----
> target/arm/translate-sve.c | 12 +++++-------
> target/arm/translate.c | 9 ++++++---
> 3 files changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 7580e46367..095638e09a 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -519,7 +519,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
> tcg_temp_free_i64(tcg_zero);
> }
> if (vsz > 16) {
> - tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);
> + tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
> }
> }
>
> @@ -7794,8 +7794,8 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
>
> if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
> /* MOVI or MVNI, with MVNI negation handled above. */
> - tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
> - vec_full_reg_size(s), imm);
> + tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
> + vec_full_reg_size(s), imm);
> } else {
> /* ORR or BIC, with BIC negation to AND handled above. */
> if (is_neg) {
> @@ -10223,8 +10223,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
> if (is_u) {
> if (shift == 8 << size) {
> /* Shift count the same size as element size produces zero. */
> - tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),
> - is_q ? 16 : 8, vec_full_reg_size(s), 0);
> + tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd),
> + is_q ? 16 : 8, vec_full_reg_size(s), 0);
> } else {
> gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);
> }
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index b35bad245e..6c8bda4e4c 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -177,7 +177,7 @@ static bool do_mov_z(DisasContext *s, int rd, int rn)
> static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
> {
> unsigned vsz = vec_full_reg_size(s);
> - tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), vsz, vsz, word);
> + tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
> }
>
> /* Invoke a vector expander on two Pregs. */
> @@ -1453,7 +1453,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
> unsigned oprsz = size_for_gvec(setsz / 8);
>
> if (oprsz * 8 == setsz) {
> - tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
> + tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word);
> goto done;
> }
> }
> @@ -2044,7 +2044,7 @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
> unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
> tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
> } else {
> - tcg_gen_gvec_dup64i(dofs, vsz, vsz, 0);
> + tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
> }
> }
> return true;
> @@ -3260,9 +3260,7 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
>
> /* Decode the VFP immediate. */
> imm = vfp_expand_imm(a->esz, a->imm);
> - imm = dup_const(a->esz, imm);
> -
> - tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm);
> + tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm);
> }
> return true;
> }
> @@ -3276,7 +3274,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
> unsigned vsz = vec_full_reg_size(s);
> int dofs = vec_full_reg_offset(s, a->rd);
>
> - tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm));
> + tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
> }
> return true;
> }
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 9f9f4e19e0..af4d3ff4c9 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -5386,7 +5386,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
> MIN(shift, (8 << size) - 1),
> vec_size, vec_size);
> } else if (shift >= 8 << size) {
> - tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
> + tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
> + vec_size, 0);
> } else {
> tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
> vec_size, vec_size);
> @@ -5437,7 +5438,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
> * architecturally valid and results in zero.
> */
> if (shift >= 8 << size) {
> - tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
> + tcg_gen_gvec_dup_imm(size, rd_ofs,
> + vec_size, vec_size, 0);
> } else {
> tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
> vec_size, vec_size);
> @@ -5783,7 +5785,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
> }
> tcg_temp_free_i64(t64);
> } else {
> - tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm);
> + tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
> + vec_size, imm);
> }
> }
> }
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications
2020-04-18 15:04 ` [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
2020-04-20 4:30 ` LIU Zhiwei
@ 2020-04-20 13:32 ` Alex Bennée
1 sibling, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 13:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> Replace the outgoing interface.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> tcg/tcg-op-gvec.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 593bb4542e..de16c027b3 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -2326,7 +2326,7 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
> @@ -2343,7 +2343,7 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, 0);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
> @@ -2360,7 +2360,7 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
> @@ -2411,7 +2411,7 @@ void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs,
> };
>
> if (aofs == bofs) {
> - tcg_gen_gvec_dup8i(dofs, oprsz, maxsz, -1);
> + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1);
> } else {
> tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g);
> }
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
2020-04-20 4:33 ` LIU Zhiwei
2020-04-20 7:29 ` David Hildenbrand
@ 2020-04-20 13:32 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 13:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> These interfaces are now unused.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 5 -----
> tcg/tcg-op-gvec.c | 28 ----------------------------
> 2 files changed, 33 deletions(-)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index eb0d47a42b..fa8a0c8d03 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -320,11 +320,6 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i64);
>
> -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
> -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
> -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
> -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
> -
> void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
> int64_t shift, uint32_t oprsz, uint32_t maxsz);
> void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index de16c027b3..5a6cc19812 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -1541,34 +1541,6 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> }
> }
>
> -void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint64_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_64, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint32_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_32, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint16_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_16, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> -void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> - uint32_t maxsz, uint8_t x)
> -{
> - check_size_align(oprsz, maxsz, dofs);
> - do_dup(MO_8, dofs, oprsz, maxsz, NULL, NULL, x);
> -}
> -
> void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t oprsz,
> uint32_t maxsz, uint64_t x)
> {
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
2020-04-20 4:42 ` LIU Zhiwei
2020-04-20 7:30 ` David Hildenbrand
@ 2020-04-20 13:32 ` Alex Bennée
2 siblings, 0 replies; 29+ messages in thread
From: Alex Bennée @ 2020-04-20 13:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
Richard Henderson <richard.henderson@linaro.org> writes:
> For use when a target needs to pass a configure-specific
> target_ulong value to duplicate.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index fa8a0c8d03..d89f91f40e 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -320,6 +320,12 @@ void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
> void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
> uint32_t m, TCGv_i64);
>
> +#if TARGET_LONG_BITS == 64
> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
> +#else
> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
> +#endif
> +
> void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
> int64_t shift, uint32_t oprsz, uint32_t maxsz);
> void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
--
Alex Bennée
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl
2020-04-20 7:30 ` David Hildenbrand
@ 2020-04-20 14:52 ` Richard Henderson
2020-04-20 14:55 ` David Hildenbrand
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-04-20 14:52 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel; +Cc: peter.maydell, zhiwei_liu, david
On 4/20/20 12:30 AM, David Hildenbrand wrote:
>> +#if TARGET_LONG_BITS == 64
>> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
>> +#else
>> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
>> +#endif
>> +
>
> Any user in mind?
riscv -- the in-progress patches have some ifdefs that could be avoided.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl
2020-04-20 14:52 ` Richard Henderson
@ 2020-04-20 14:55 ` David Hildenbrand
0 siblings, 0 replies; 29+ messages in thread
From: David Hildenbrand @ 2020-04-20 14:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, zhiwei_liu, david
On 20.04.20 16:52, Richard Henderson wrote:
> On 4/20/20 12:30 AM, David Hildenbrand wrote:
>>> +#if TARGET_LONG_BITS == 64
>>> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64
>>> +#else
>>> +# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32
>>> +#endif
>>> +
>>
>> Any user in mind?
>
> riscv -- the in-progress patches have some ifdefs that could be avoided.
>
Perfect
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/7] target/ppc: Use tcg_gen_gvec_dup_imm
2020-04-20 10:34 ` Alex Bennée
@ 2020-04-21 17:50 ` Richard Henderson
2020-04-22 7:58 ` David Gibson
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-04-21 17:50 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, peter.maydell, david, zhiwei_liu, david
On 4/20/20 3:34 AM, Alex Bennée wrote:
>> +GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
>> +GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
>> +GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
>
> There are unused parameters opc2/opc3 parameters here.
Yes, but all of the other GEN_* macros retain them as well.
Without looking at the actual history, I'd say once upon a time they were
actually used, but we've now split opcode from implementation.
> With the removed extra unused macro params:
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
I wouldn't do that without David's approval. And possibly stripping out the
opcodes everywhere else.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 3/7] target/ppc: Use tcg_gen_gvec_dup_imm
2020-04-21 17:50 ` Richard Henderson
@ 2020-04-22 7:58 ` David Gibson
0 siblings, 0 replies; 29+ messages in thread
From: David Gibson @ 2020-04-22 7:58 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, peter.maydell, Alex Bennée, zhiwei_liu, david
[-- Attachment #1: Type: text/plain, Size: 1093 bytes --]
On Tue, Apr 21, 2020 at 10:50:25AM -0700, Richard Henderson wrote:
> On 4/20/20 3:34 AM, Alex Bennée wrote:
> >> +GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
> >> +GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
> >> +GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
> >
> > There are unused parameters opc2/opc3 parameters here.
>
> Yes, but all of the other GEN_* macros retain them as well.
> Without looking at the actual history, I'd say once upon a time they were
> actually used, but we've now split opcode from implementation.
>
> > With the removed extra unused macro params:
> >
> > Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>
> I wouldn't do that without David's approval. And possibly stripping out the
> opcodes everywhere else.
Yeah. Sounds like one of a nearly infinite number of global cleanups
that the target-ppc tcg code could do with. Patches welcome.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2020-04-22 8:01 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20 3:17 ` LIU Zhiwei
2020-04-20 7:29 ` David Hildenbrand
2020-04-20 9:43 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20 7:29 ` David Hildenbrand
2020-04-20 9:46 ` Alex Bennée
2020-04-20 10:06 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 3/7] target/ppc: " Richard Henderson
2020-04-20 3:41 ` David Gibson
2020-04-20 10:34 ` Alex Bennée
2020-04-21 17:50 ` Richard Henderson
2020-04-22 7:58 ` David Gibson
2020-04-18 15:04 ` [PATCH 4/7] target/arm: " Richard Henderson
2020-04-20 13:24 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
2020-04-20 4:30 ` LIU Zhiwei
2020-04-20 13:32 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
2020-04-20 4:33 ` LIU Zhiwei
2020-04-20 7:29 ` David Hildenbrand
2020-04-20 13:32 ` Alex Bennée
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
2020-04-20 4:42 ` LIU Zhiwei
2020-04-20 7:30 ` David Hildenbrand
2020-04-20 14:52 ` Richard Henderson
2020-04-20 14:55 ` David Hildenbrand
2020-04-20 13:32 ` Alex Bennée
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