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From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	iommu@lists.linux-foundation.org, mingo@redhat.com,
	joro@8bytes.org, Jon.Grimm@amd.com, amonakov@ispras.ru,
	David Coe <david.coe@live.co.uk>
Subject: Re: [PATCH] x86/events/amd/iommu: Fix invalid Perf result due to IOMMU PMC power-gating
Date: Tue, 4 May 2021 18:58:29 +0700	[thread overview]
Message-ID: <e9769da5-3d2a-6e86-8ebd-feb00b567bba@amd.com> (raw)
In-Reply-To: <YJEWWbEeDm0rUyC+@hirez.programming.kicks-ass.net>

Peter,

On 5/4/2021 4:39 PM, Peter Zijlstra wrote:
> On Tue, May 04, 2021 at 01:52:36AM -0500, Suravee Suthikulpanit wrote:
> 
>> 2. Since AMD IOMMU PMU does not support interrupt mode, the logic
>>     can be simplified to always start counting with value zero,
>>     and accumulate the counter value when stopping without the need
>>     to keep track and reprogram the counter with the previously read
>>     counter value.
> 
> This relies on the hardware counter being the full 64bit wide, is it?
> 

The HW counter value is 48-bit. Not sure why it needs to be 64-bit?
I might be missing some points here? Could you please describe?

Thanks,
Suravee



WARNING: multiple messages have this Message-ID (diff)
From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: David Coe <david.coe@live.co.uk>,
	amonakov@ispras.ru, Jon.Grimm@amd.com,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	iommu@lists.linux-foundation.org, mingo@redhat.com
Subject: Re: [PATCH] x86/events/amd/iommu: Fix invalid Perf result due to IOMMU PMC power-gating
Date: Tue, 4 May 2021 18:58:29 +0700	[thread overview]
Message-ID: <e9769da5-3d2a-6e86-8ebd-feb00b567bba@amd.com> (raw)
In-Reply-To: <YJEWWbEeDm0rUyC+@hirez.programming.kicks-ass.net>

Peter,

On 5/4/2021 4:39 PM, Peter Zijlstra wrote:
> On Tue, May 04, 2021 at 01:52:36AM -0500, Suravee Suthikulpanit wrote:
> 
>> 2. Since AMD IOMMU PMU does not support interrupt mode, the logic
>>     can be simplified to always start counting with value zero,
>>     and accumulate the counter value when stopping without the need
>>     to keep track and reprogram the counter with the previously read
>>     counter value.
> 
> This relies on the hardware counter being the full 64bit wide, is it?
> 

The HW counter value is 48-bit. Not sure why it needs to be 64-bit?
I might be missing some points here? Could you please describe?

Thanks,
Suravee


_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply	other threads:[~2021-05-04 11:58 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04  6:52 [PATCH] x86/events/amd/iommu: Fix invalid Perf result due to IOMMU PMC power-gating Suravee Suthikulpanit
2021-05-04  6:52 ` Suravee Suthikulpanit
2021-05-04  9:39 ` Peter Zijlstra
2021-05-04  9:39   ` Peter Zijlstra
2021-05-04 11:58   ` Suthikulpanit, Suravee [this message]
2021-05-04 11:58     ` Suthikulpanit, Suravee
2021-05-04 12:13     ` Peter Zijlstra
2021-05-04 12:13       ` Peter Zijlstra
2021-05-05 12:39       ` Suthikulpanit, Suravee
2021-05-05 12:39         ` Suthikulpanit, Suravee
2021-05-05 13:05         ` Peter Zijlstra
2021-05-05 13:05           ` Peter Zijlstra
2021-05-10  2:08           ` Suthikulpanit, Suravee
2021-05-10  2:08             ` Suthikulpanit, Suravee
2021-05-04 17:04 ` David Coe
2021-05-04 17:04   ` David Coe
2021-05-05 10:24 ` David Coe
2021-05-05 10:24   ` David Coe
2021-05-06 13:48 ` [tip: perf/urgent] " tip-bot2 for Suravee Suthikulpanit
2021-05-14 10:48 ` [PATCH] " David Coe
2021-05-14 10:48   ` David Coe

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