* [PATCH 1/5] drm/amdkfd: Improve doorbell variable names
@ 2019-02-05 20:31 Zhao, Yong
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Zhao, Yong @ 2019-02-05 20:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhao, Yong
Indicate that the doorbell offset and range is in dwords.
Change-Id: Ib0f2564ffa7b1940ffb8725cdc03f662184f5436
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 6 +++++-
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 6 +++++-
9 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d67f8b1dfe80..6230425f3f3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -642,7 +642,7 @@ struct amdgpu_nbio_funcs {
void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
u32 (*get_memsize)(struct amdgpu_device *adev);
void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index, int doorbell_size);
+ bool use_doorbell, int index_in_dw, int range_dw_size);
void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
bool enable);
void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 1cfec06f81d4..5c8d04c353d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -39,6 +39,7 @@ struct amdgpu_doorbell {
* can be 64-bit, so the index defined is in qword.
*/
struct amdgpu_doorbell_index {
+ uint32_t entry_dw_size;
uint32_t kiq;
uint32_t mec_ring0;
uint32_t mec_ring1;
@@ -73,7 +74,7 @@ struct amdgpu_doorbell_index {
};
uint32_t max_assignment;
/* Per engine SDMA doorbell size in dword */
- uint32_t sdma_doorbell_range;
+ uint32_t dw_range_per_sdma_eng;
};
typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index cc967dbfd631..64bc41afd71e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -68,7 +68,7 @@ static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
}
static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index, int doorbell_size)
+ bool use_doorbell, int index_in_dw, int range_dw_size)
{
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
@@ -76,8 +76,8 @@ static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instan
u32 doorbell_range = RREG32(reg);
if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 1cdb98ad2db3..28cc96b7a292 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -67,7 +67,7 @@ static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
}
static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index, int doorbell_size)
+ bool use_doorbell, int index_in_dw, int range_dw_size)
{
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
@@ -75,8 +75,8 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
u32 doorbell_range = RREG32(reg);
if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 221f26e50322..9ae8cd4dc702 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -65,7 +65,7 @@ static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
}
static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
- bool use_doorbell, int doorbell_index, int doorbell_size)
+ bool use_doorbell, int index_in_dw, int range_dw_size)
{
u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
@@ -73,8 +73,8 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
u32 doorbell_range = RREG32(reg);
if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
} else
doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 127b85983e8f..e65e9bc52bd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1520,7 +1520,8 @@ static int sdma_v4_0_sw_init(void *handle)
ring->use_doorbell?"true":"false");
/* doorbell size is 2 dwords, get DWORD offset */
- ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
+ ring->doorbell_index = adev->doorbell_index.sdma_engine[i]
+ * adev->doorbell_index.entry_dw_size;
sprintf(ring->name, "sdma%d", i);
r = amdgpu_ring_init(adev, ring, 1024,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 99ebcf29dcb0..aad72ac80361 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -980,7 +980,7 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
ring = &adev->sdma.instance[i].ring;
adev->nbio_funcs->sdma_doorbell_range(adev, i,
ring->use_doorbell, ring->doorbell_index,
- adev->doorbell_index.sdma_doorbell_range);
+ adev->doorbell_index.dw_range_per_sdma_eng);
}
adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 4b5d60ea3e78..d2409df2dde9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -58,6 +58,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
void vega10_doorbell_index_init(struct amdgpu_device *adev)
{
+ adev->doorbell_index.entry_dw_size = 2;
adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
@@ -83,6 +84,9 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
/* In unit of dword doorbell */
adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
- adev->doorbell_index.sdma_doorbell_range = 4;
+ adev->doorbell_index.dw_range_per_sdma_eng =
+ (adev->doorbell_index.sdma_engine[1]
+ - adev->doorbell_index.sdma_engine[0])
+ * adev->doorbell_index.entry_dw_size;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index 53716c593b2b..b28c5999d8f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -56,6 +56,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
void vega20_doorbell_index_init(struct amdgpu_device *adev)
{
+ adev->doorbell_index.entry_dw_size = 2;
adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ;
adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0;
adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1;
@@ -86,6 +87,9 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
- adev->doorbell_index.sdma_doorbell_range = 20;
+ adev->doorbell_index.dw_range_per_sdma_eng =
+ (adev->doorbell_index.sdma_engine[1]
+ - adev->doorbell_index.sdma_engine[0])
+ * adev->doorbell_index.entry_dw_size;
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-05 20:31 ` [PATCH 3/5] drm/amdgpu: Delete user queue doorbell variables Zhao, Yong
@ 2019-02-05 20:31 ` Zhao, Yong
[not found] ` <20190205203047.22586-2-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-05 20:31 ` [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask " Zhao, Yong
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Zhao, Yong @ 2019-02-05 20:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhao, Yong
Because CP can use all doorbells outside the ones reserved for SDMA, IH,
and VCN, so the value set to CP_MEC_DOORBELL_RANGE_UPPER should be the
maximal index possible in a page.
Change-Id: I402a56ce9a80e6c2ed2f96be431ae71ca88e73a4
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
4 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 5c8d04c353d0..90eca63605ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -73,6 +73,7 @@ struct amdgpu_doorbell_index {
} uvd_vce;
};
uint32_t max_assignment;
+ uint32_t last_idx;
/* Per engine SDMA doorbell size in dword */
uint32_t dw_range_per_sdma_eng;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 262ee3cf6f1c..0278e3ab6b94 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2998,7 +2998,7 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
(adev->doorbell_index.kiq * 2) << 2);
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
- (adev->doorbell_index.userqueue_end * 2) << 2);
+ (adev->doorbell_index.last_idx * 2) << 2);
}
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index d2409df2dde9..9eb8c9209231 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -88,5 +88,8 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
(adev->doorbell_index.sdma_engine[1]
- adev->doorbell_index.sdma_engine[0])
* adev->doorbell_index.entry_dw_size;
+
+ adev->doorbell_index.last_idx = PAGE_SIZE
+ / (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index b28c5999d8f0..aa8c7699c689 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -91,5 +91,8 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
(adev->doorbell_index.sdma_engine[1]
- adev->doorbell_index.sdma_engine[0])
* adev->doorbell_index.entry_dw_size;
+
+ adev->doorbell_index.last_idx = PAGE_SIZE
+ / (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/5] drm/amdgpu: Delete user queue doorbell variables
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-05 20:31 ` Zhao, Yong
2019-02-05 20:31 ` [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15 Zhao, Yong
` (3 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Zhao, Yong @ 2019-02-05 20:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhao, Yong
They are no longer used, so delete them to avoid confusion.
Change-Id: I3cf23fe7110ff88f53c0c279b2b4ec8d1a53b87c
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 8 --------
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 2 --
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 2 --
3 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 90eca63605ea..59c41841cbce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -49,8 +49,6 @@ struct amdgpu_doorbell_index {
uint32_t mec_ring5;
uint32_t mec_ring6;
uint32_t mec_ring7;
- uint32_t userqueue_start;
- uint32_t userqueue_end;
uint32_t gfx_ring0;
uint32_t sdma_engine[8];
uint32_t ih;
@@ -113,8 +111,6 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
- AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
- AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
/* SDMA:256~335*/
AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
@@ -178,10 +174,6 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
- /* User queue doorbell range (128 doorbells) */
- AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
- AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
-
/* Graphics engine */
AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 9eb8c9209231..65214c7b0b20 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -68,8 +68,6 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
- adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START;
- adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL64_sDMA_ENGINE0;
adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL64_sDMA_ENGINE1;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index aa8c7699c689..a388d306391a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -66,8 +66,6 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.mec_ring5 = AMDGPU_VEGA20_DOORBELL_MEC_RING5;
adev->doorbell_index.mec_ring6 = AMDGPU_VEGA20_DOORBELL_MEC_RING6;
adev->doorbell_index.mec_ring7 = AMDGPU_VEGA20_DOORBELL_MEC_RING7;
- adev->doorbell_index.userqueue_start = AMDGPU_VEGA20_DOORBELL_USERQUEUE_START;
- adev->doorbell_index.userqueue_end = AMDGPU_VEGA20_DOORBELL_USERQUEUE_END;
adev->doorbell_index.gfx_ring0 = AMDGPU_VEGA20_DOORBELL_GFX_RING0;
adev->doorbell_index.sdma_engine[0] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0;
adev->doorbell_index.sdma_engine[1] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1;
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask on SOC15
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-05 20:31 ` [PATCH 3/5] drm/amdgpu: Delete user queue doorbell variables Zhao, Yong
2019-02-05 20:31 ` [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15 Zhao, Yong
@ 2019-02-05 20:31 ` Zhao, Yong
[not found] ` <20190205203047.22586-4-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-05 20:31 ` [PATCH 5/5] drm/amdkfd: Optimize out sdma doorbell array in kgd2kfd_shared_resources Zhao, Yong
2019-02-05 21:43 ` [PATCH 1/5] drm/amdkfd: Improve doorbell variable names Kuehling, Felix
4 siblings, 1 reply; 12+ messages in thread
From: Zhao, Yong @ 2019-02-05 20:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhao, Yong
Reserved doorbells for SDMA IH and VCN were not properly masked out
when allocating doorbells for CP user queues. This patch fixed that.
Change-Id: I670adfc3fd7725d2ed0bd9665cb7f69f8b9023c2
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 17 +++++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 4 ++++
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 ++++++++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 ++++++++++++++-----
.../gpu/drm/amd/include/kgd_kfd_interface.h | 19 ++++++-----------
7 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index e957e42c539a..ee8527701731 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -196,11 +196,20 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
gpu_resources.sdma_doorbell[1][i+1] =
adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
}
- /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
- * SDMA, IH and VCN. So don't use them for the CP.
+
+ /* Because of the setting in registers like
+ * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
+ * lower 12 bits of doorbell address for routing. In
+ * order to route the CP queue doorbells to CP engine,
+ * the doorbells allocated to CP queues have to be
+ * outside the range set for SDMA, VCN, and IH blocks
+ * Prior to SOC15, all queues use queue ID to
+ * determine doorbells.
*/
- gpu_resources.reserved_doorbell_mask = 0x1e0;
- gpu_resources.reserved_doorbell_val = 0x0e0;
+ gpu_resources.reserved_doorbells_start =
+ adev->doorbell_index.sdma_engine[0];
+ gpu_resources.reserved_doorbells_end =
+ adev->doorbell_index.last_non_cp;
kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 59c41841cbce..74b8e2bfabd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -70,6 +70,7 @@ struct amdgpu_doorbell_index {
uint32_t vce_ring6_7;
} uvd_vce;
};
+ uint32_t last_non_cp;
uint32_t max_assignment;
uint32_t last_idx;
/* Per engine SDMA doorbell size in dword */
@@ -141,6 +142,7 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
+ AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
@@ -216,6 +218,8 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
+ AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
+
AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
AMDGPU_DOORBELL64_INVALID = 0xFFFF
} AMDGPU_DOORBELL64_ASSIGNMENT;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 65214c7b0b20..76166c0ec509 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -80,6 +80,9 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
+
+ adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
+
/* In unit of dword doorbell */
adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
adev->doorbell_index.dw_range_per_sdma_eng =
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index a388d306391a..10df2fed5a99 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -84,6 +84,9 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
+
+ adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP;
+
adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
adev->doorbell_index.dw_range_per_sdma_eng =
(adev->doorbell_index.sdma_engine[1]
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index e5ebcca7f031..6b8459f852cc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -103,6 +103,15 @@
#define KFD_KERNEL_QUEUE_SIZE 2048
+/* 512 = 0x200
+ * On SOC15, the doorbell index distance for SDMA RLC i and (i + 1) in the
+ * same SDMA engine, where i is a even number.
+ * For 8-bytes doorbells, it ensures that the mirror doorbell range (in terms
+ * of low 12 bit address for each HW engine) on the second doorbell page is
+ * the same as the range of the first doorbell page.*/
+#define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
+
+
/*
* Kernel module parameter to specify maximum number of supported queues per
* device
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 80b36e860a0a..e904d6036b3d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -607,13 +607,24 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
if (!qpd->doorbell_bitmap)
return -ENOMEM;
- /* Mask out any reserved doorbells */
- for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS; i++)
- if ((dev->shared_resources.reserved_doorbell_mask & i) ==
- dev->shared_resources.reserved_doorbell_val) {
+ /* Mask out all reserved doorbells for SDMA, IH, and VCN on SOC15.
+ * Because of the setting in registers like SDMA0_DOORBELL_RANGE etc.,
+ * BIF statically uses the lower 12 bits of doorbell address for
+ * routing. In order to route the CP queue doorbells to CP engine,
+ * the doorbells allocated to CP queues have to be outside the range
+ * set for SDMA, VCN, and IH blocks.
+ * Prior to SOC15, all queues use queue ID to
+ * determine doorbells. */
+ for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS / 2; i++) {
+ if (i >= dev->shared_resources.reserved_doorbells_start
+ && i <= dev->shared_resources.reserved_doorbells_end) {
set_bit(i, qpd->doorbell_bitmap);
- pr_debug("reserved doorbell 0x%03x\n", i);
+ set_bit(i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
+ qpd->doorbell_bitmap);
+ pr_debug("reserved doorbell 0x%03x and 0x%03x\n", i,
+ i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET);
}
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 83d960110d23..b1bf45419d93 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -137,20 +137,13 @@ struct kgd2kfd_shared_resources {
/* Bit n == 1 means Queue n is available for KFD */
DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
- /* Doorbell assignments (SOC15 and later chips only). Only
- * specific doorbells are routed to each SDMA engine. Others
- * are routed to IH and VCN. They are not usable by the CP.
- *
- * Any doorbell number D that satisfies the following condition
- * is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val
- *
- * KFD currently uses 1024 (= 0x3ff) doorbells per process. If
- * doorbells 0x0e0-0x0ff and 0x2e0-0x2ff are reserved, that means
- * mask would be set to 0x1e0 and val set to 0x0e0.
- */
unsigned int sdma_doorbell[2][8];
- unsigned int reserved_doorbell_mask;
- unsigned int reserved_doorbell_val;
+
+ /* From SOC15 onwards, the doorbell indexes reserved for SDMA, IH,
+ * and VCN
+ */
+ unsigned int reserved_doorbells_start;
+ unsigned int reserved_doorbells_end;
/* Base address of doorbell aperture. */
phys_addr_t doorbell_physical_address;
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/5] drm/amdkfd: Optimize out sdma doorbell array in kgd2kfd_shared_resources
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-02-05 20:31 ` [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask " Zhao, Yong
@ 2019-02-05 20:31 ` Zhao, Yong
[not found] ` <20190205203047.22586-5-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-05 21:43 ` [PATCH 1/5] drm/amdkfd: Improve doorbell variable names Kuehling, Felix
4 siblings, 1 reply; 12+ messages in thread
From: Zhao, Yong @ 2019-02-05 20:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhao, Yong
We can directly calculate the sdma doorbell index in the process doorbell
pages through the doorbell_index structure in amdgpu_device, so no need
to cache them in kgd2kfd_shared_resources any more, resulting in more
portable code.
Change-Id: Ic657799856ed0256f36b01e502ef0cab263b1f49
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 55 ++++++-------------
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 18 ++++--
.../gpu/drm/amd/include/kgd_kfd_interface.h | 2 +-
3 files changed, 31 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index ee8527701731..e62c3703169a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -131,7 +131,7 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
{
- int i, n;
+ int i;
int last_valid_bit;
if (adev->kfd.dev) {
@@ -142,7 +142,9 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
.gpuvm_size = min(adev->vm_manager.max_pfn
<< AMDGPU_GPU_PAGE_SHIFT,
AMDGPU_GMC_HOLE_START),
- .drm_render_minor = adev->ddev->render->index
+ .drm_render_minor = adev->ddev->render->index,
+ .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
+
};
/* this is going to have a few of the MSBs set that we need to
@@ -172,45 +174,22 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
&gpu_resources.doorbell_aperture_size,
&gpu_resources.doorbell_start_offset);
- if (adev->asic_type < CHIP_VEGA10) {
- kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
- return;
- }
-
- n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
-
- for (i = 0; i < n; i += 2) {
- /* On SOC15 the BIF is involved in routing
- * doorbells using the low 12 bits of the
- * address. Communicate the assignments to
- * KFD. KFD uses two doorbell pages per
- * process in case of 64-bit doorbells so we
- * can use each doorbell assignment twice.
+ if (adev->asic_type >= CHIP_VEGA10) {
+ /* Because of the setting in registers like
+ * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
+ * lower 12 bits of doorbell address for routing. In
+ * order to route the CP queue doorbells to CP engine,
+ * the doorbells allocated to CP queues have to be
+ * outside the range set for SDMA, VCN, and IH blocks
+ * Prior to SOC15, all queues use queue ID to
+ * determine doorbells.
*/
- gpu_resources.sdma_doorbell[0][i] =
- adev->doorbell_index.sdma_engine[0] + (i >> 1);
- gpu_resources.sdma_doorbell[0][i+1] =
- adev->doorbell_index.sdma_engine[0] + 0x200 + (i >> 1);
- gpu_resources.sdma_doorbell[1][i] =
- adev->doorbell_index.sdma_engine[1] + (i >> 1);
- gpu_resources.sdma_doorbell[1][i+1] =
- adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
+ gpu_resources.reserved_doorbells_start =
+ adev->doorbell_index.sdma_engine[0];
+ gpu_resources.reserved_doorbells_end =
+ adev->doorbell_index.last_non_cp;
}
- /* Because of the setting in registers like
- * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
- * lower 12 bits of doorbell address for routing. In
- * order to route the CP queue doorbells to CP engine,
- * the doorbells allocated to CP queues have to be
- * outside the range set for SDMA, VCN, and IH blocks
- * Prior to SOC15, all queues use queue ID to
- * determine doorbells.
- */
- gpu_resources.reserved_doorbells_start =
- adev->doorbell_index.sdma_engine[0];
- gpu_resources.reserved_doorbells_end =
- adev->doorbell_index.last_non_cp;
-
kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
}
}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 8372556b52eb..81280ce5aa27 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -134,12 +134,20 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
*/
q->doorbell_id = q->properties.queue_id;
} else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
- /* For SDMA queues on SOC15, use static doorbell
- * assignments based on the engine and queue.
+ /* For SDMA queues on SOC15 with 8-byte doorbell, use static
+ * doorbell assignments based on the engine and queue id.
+ * The doobell index distance between RLC (2*i) and (2*i+1)
+ * for a SDMA engine is 512.
+ * 512 8-byte doorbell distance (i.e. one page away) ensures
+ * that SDMA RLC (2*i+1) doorbell lies exactly in the doorbell
+ * OFFSET and SIZE set in register BIF_SDMA0_DOORBELL_RANGE.
*/
- q->doorbell_id = dev->shared_resources.sdma_doorbell
- [q->properties.sdma_engine_id]
- [q->properties.sdma_queue_id];
+ unsigned int *idx_offset =
+ dev->shared_resources.sdma_doorbell_idx;
+ q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
+ + (q->properties.sdma_queue_id >> 1)
+ + (q->properties.sdma_queue_id % 2)
+ * KFD_QUEUE_DOORBELL_MIRROR_OFFSET;
} else {
/* For CP queues on SOC15 reserve a free doorbell ID */
unsigned int found;
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index b1bf45419d93..3559170f6fb3 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -137,7 +137,7 @@ struct kgd2kfd_shared_resources {
/* Bit n == 1 means Queue n is available for KFD */
DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
- unsigned int sdma_doorbell[2][8];
+ unsigned int *sdma_doorbell_idx;
/* From SOC15 onwards, the doorbell indexes reserved for SDMA, IH,
* and VCN
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdkfd: Improve doorbell variable names
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-02-05 20:31 ` [PATCH 5/5] drm/amdkfd: Optimize out sdma doorbell array in kgd2kfd_shared_resources Zhao, Yong
@ 2019-02-05 21:43 ` Kuehling, Felix
[not found] ` <911744ff-f4e5-b165-123e-a574b2310746-5C7GfCeVMHo@public.gmane.org>
4 siblings, 1 reply; 12+ messages in thread
From: Kuehling, Felix @ 2019-02-05 21:43 UTC (permalink / raw)
To: Zhao, Yong, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
The headline should start with "drm/amdgpu". This change is not KFD
specific.
I think Alex should review this change.
Regards,
Felix
On 2019-02-05 3:31 p.m., Zhao, Yong wrote:
> Indicate that the doorbell offset and range is in dwords.
>
> Change-Id: Ib0f2564ffa7b1940ffb8725cdc03f662184f5436
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 3 ++-
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 6 +++++-
> drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 6 +++++-
> 9 files changed, 25 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index d67f8b1dfe80..6230425f3f3d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -642,7 +642,7 @@ struct amdgpu_nbio_funcs {
> void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
> u32 (*get_memsize)(struct amdgpu_device *adev);
> void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
> - bool use_doorbell, int doorbell_index, int doorbell_size);
> + bool use_doorbell, int index_in_dw, int range_dw_size);
> void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
> bool enable);
> void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> index 1cfec06f81d4..5c8d04c353d0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> @@ -39,6 +39,7 @@ struct amdgpu_doorbell {
> * can be 64-bit, so the index defined is in qword.
> */
> struct amdgpu_doorbell_index {
> + uint32_t entry_dw_size;
> uint32_t kiq;
> uint32_t mec_ring0;
> uint32_t mec_ring1;
> @@ -73,7 +74,7 @@ struct amdgpu_doorbell_index {
> };
> uint32_t max_assignment;
> /* Per engine SDMA doorbell size in dword */
> - uint32_t sdma_doorbell_range;
> + uint32_t dw_range_per_sdma_eng;
> };
>
> typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index cc967dbfd631..64bc41afd71e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -68,7 +68,7 @@ static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
> }
>
> static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> - bool use_doorbell, int doorbell_index, int doorbell_size)
> + bool use_doorbell, int index_in_dw, int range_dw_size)
> {
> u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
> SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
> @@ -76,8 +76,8 @@ static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instan
> u32 doorbell_range = RREG32(reg);
>
> if (use_doorbell) {
> - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
> + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
> + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
> } else
> doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index 1cdb98ad2db3..28cc96b7a292 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -67,7 +67,7 @@ static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> }
>
> static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> - bool use_doorbell, int doorbell_index, int doorbell_size)
> + bool use_doorbell, int index_in_dw, int range_dw_size)
> {
> u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
> SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
> @@ -75,8 +75,8 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
> u32 doorbell_range = RREG32(reg);
>
> if (use_doorbell) {
> - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
> + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
> + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
> } else
> doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index 221f26e50322..9ae8cd4dc702 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -65,7 +65,7 @@ static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
> }
>
> static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> - bool use_doorbell, int doorbell_index, int doorbell_size)
> + bool use_doorbell, int index_in_dw, int range_dw_size)
> {
> u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
> SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
> @@ -73,8 +73,8 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
> u32 doorbell_range = RREG32(reg);
>
> if (use_doorbell) {
> - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
> + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
> + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
> } else
> doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 127b85983e8f..e65e9bc52bd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1520,7 +1520,8 @@ static int sdma_v4_0_sw_init(void *handle)
> ring->use_doorbell?"true":"false");
>
> /* doorbell size is 2 dwords, get DWORD offset */
> - ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
> + ring->doorbell_index = adev->doorbell_index.sdma_engine[i]
> + * adev->doorbell_index.entry_dw_size;
>
> sprintf(ring->name, "sdma%d", i);
> r = amdgpu_ring_init(adev, ring, 1024,
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 99ebcf29dcb0..aad72ac80361 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -980,7 +980,7 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
> ring = &adev->sdma.instance[i].ring;
> adev->nbio_funcs->sdma_doorbell_range(adev, i,
> ring->use_doorbell, ring->doorbell_index,
> - adev->doorbell_index.sdma_doorbell_range);
> + adev->doorbell_index.dw_range_per_sdma_eng);
> }
>
> adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> index 4b5d60ea3e78..d2409df2dde9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> @@ -58,6 +58,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
>
> void vega10_doorbell_index_init(struct amdgpu_device *adev)
> {
> + adev->doorbell_index.entry_dw_size = 2;
> adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
> adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
> adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
> @@ -83,6 +84,9 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
> adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
> /* In unit of dword doorbell */
> adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
> - adev->doorbell_index.sdma_doorbell_range = 4;
> + adev->doorbell_index.dw_range_per_sdma_eng =
> + (adev->doorbell_index.sdma_engine[1]
> + - adev->doorbell_index.sdma_engine[0])
> + * adev->doorbell_index.entry_dw_size;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> index 53716c593b2b..b28c5999d8f0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> @@ -56,6 +56,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
>
> void vega20_doorbell_index_init(struct amdgpu_device *adev)
> {
> + adev->doorbell_index.entry_dw_size = 2;
> adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ;
> adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0;
> adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1;
> @@ -86,6 +87,9 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
> adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
> adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
> adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
> - adev->doorbell_index.sdma_doorbell_range = 20;
> + adev->doorbell_index.dw_range_per_sdma_eng =
> + (adev->doorbell_index.sdma_engine[1]
> + - adev->doorbell_index.sdma_engine[0])
> + * adev->doorbell_index.entry_dw_size;
> }
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] drm/amdkfd: Improve doorbell variable names
[not found] ` <911744ff-f4e5-b165-123e-a574b2310746-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-06 1:18 ` Alex Deucher
0 siblings, 0 replies; 12+ messages in thread
From: Alex Deucher @ 2019-02-06 1:18 UTC (permalink / raw)
To: Kuehling, Felix; +Cc: Zhao, Yong, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Tue, Feb 5, 2019 at 4:43 PM Kuehling, Felix <Felix.Kuehling@amd.com> wrote:
>
> The headline should start with "drm/amdgpu". This change is not KFD
> specific.
>
> I think Alex should review this change.
If we are going to change it, let's be consistent for all IPs (e.g.,
gfx, vcn, etc.).
Alex
>
> Regards,
> Felix
>
> On 2019-02-05 3:31 p.m., Zhao, Yong wrote:
> > Indicate that the doorbell offset and range is in dwords.
> >
> > Change-Id: Ib0f2564ffa7b1940ffb8725cdc03f662184f5436
> > Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 6 +++---
> > drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 6 +++---
> > drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +++---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 ++-
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 6 +++++-
> > drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 6 +++++-
> > 9 files changed, 25 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index d67f8b1dfe80..6230425f3f3d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -642,7 +642,7 @@ struct amdgpu_nbio_funcs {
> > void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
> > u32 (*get_memsize)(struct amdgpu_device *adev);
> > void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
> > - bool use_doorbell, int doorbell_index, int doorbell_size);
> > + bool use_doorbell, int index_in_dw, int range_dw_size);
> > void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
> > bool enable);
> > void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> > index 1cfec06f81d4..5c8d04c353d0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> > @@ -39,6 +39,7 @@ struct amdgpu_doorbell {
> > * can be 64-bit, so the index defined is in qword.
> > */
> > struct amdgpu_doorbell_index {
> > + uint32_t entry_dw_size;
> > uint32_t kiq;
> > uint32_t mec_ring0;
> > uint32_t mec_ring1;
> > @@ -73,7 +74,7 @@ struct amdgpu_doorbell_index {
> > };
> > uint32_t max_assignment;
> > /* Per engine SDMA doorbell size in dword */
> > - uint32_t sdma_doorbell_range;
> > + uint32_t dw_range_per_sdma_eng;
> > };
> >
> > typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> > index cc967dbfd631..64bc41afd71e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> > @@ -68,7 +68,7 @@ static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
> > }
> >
> > static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> > - bool use_doorbell, int doorbell_index, int doorbell_size)
> > + bool use_doorbell, int index_in_dw, int range_dw_size)
> > {
> > u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
> > SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
> > @@ -76,8 +76,8 @@ static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instan
> > u32 doorbell_range = RREG32(reg);
> >
> > if (use_doorbell) {
> > - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> > - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
> > + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
> > + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
> > } else
> > doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> > index 1cdb98ad2db3..28cc96b7a292 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> > @@ -67,7 +67,7 @@ static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
> > }
> >
> > static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> > - bool use_doorbell, int doorbell_index, int doorbell_size)
> > + bool use_doorbell, int index_in_dw, int range_dw_size)
> > {
> > u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
> > SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
> > @@ -75,8 +75,8 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
> > u32 doorbell_range = RREG32(reg);
> >
> > if (use_doorbell) {
> > - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> > - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
> > + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
> > + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
> > } else
> > doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> > index 221f26e50322..9ae8cd4dc702 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> > @@ -65,7 +65,7 @@ static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
> > }
> >
> > static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> > - bool use_doorbell, int doorbell_index, int doorbell_size)
> > + bool use_doorbell, int index_in_dw, int range_dw_size)
> > {
> > u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
> > SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
> > @@ -73,8 +73,8 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
> > u32 doorbell_range = RREG32(reg);
> >
> > if (use_doorbell) {
> > - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
> > - doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
> > + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, index_in_dw);
> > + doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range_dw_size);
> > } else
> > doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 127b85983e8f..e65e9bc52bd4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -1520,7 +1520,8 @@ static int sdma_v4_0_sw_init(void *handle)
> > ring->use_doorbell?"true":"false");
> >
> > /* doorbell size is 2 dwords, get DWORD offset */
> > - ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
> > + ring->doorbell_index = adev->doorbell_index.sdma_engine[i]
> > + * adev->doorbell_index.entry_dw_size;
> >
> > sprintf(ring->name, "sdma%d", i);
> > r = amdgpu_ring_init(adev, ring, 1024,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 99ebcf29dcb0..aad72ac80361 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -980,7 +980,7 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev)
> > ring = &adev->sdma.instance[i].ring;
> > adev->nbio_funcs->sdma_doorbell_range(adev, i,
> > ring->use_doorbell, ring->doorbell_index,
> > - adev->doorbell_index.sdma_doorbell_range);
> > + adev->doorbell_index.dw_range_per_sdma_eng);
> > }
> >
> > adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> > index 4b5d60ea3e78..d2409df2dde9 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> > @@ -58,6 +58,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
> >
> > void vega10_doorbell_index_init(struct amdgpu_device *adev)
> > {
> > + adev->doorbell_index.entry_dw_size = 2;
> > adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
> > adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
> > adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
> > @@ -83,6 +84,9 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
> > adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
> > /* In unit of dword doorbell */
> > adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
> > - adev->doorbell_index.sdma_doorbell_range = 4;
> > + adev->doorbell_index.dw_range_per_sdma_eng =
> > + (adev->doorbell_index.sdma_engine[1]
> > + - adev->doorbell_index.sdma_engine[0])
> > + * adev->doorbell_index.entry_dw_size;
> > }
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> > index 53716c593b2b..b28c5999d8f0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> > @@ -56,6 +56,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
> >
> > void vega20_doorbell_index_init(struct amdgpu_device *adev)
> > {
> > + adev->doorbell_index.entry_dw_size = 2;
> > adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ;
> > adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0;
> > adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1;
> > @@ -86,6 +87,9 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
> > adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
> > adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
> > adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
> > - adev->doorbell_index.sdma_doorbell_range = 20;
> > + adev->doorbell_index.dw_range_per_sdma_eng =
> > + (adev->doorbell_index.sdma_engine[1]
> > + - adev->doorbell_index.sdma_engine[0])
> > + * adev->doorbell_index.entry_dw_size;
> > }
> >
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15
[not found] ` <20190205203047.22586-2-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-06 15:23 ` Zeng, Oak
[not found] ` <BL0PR12MB258079D4BB56B65F60C55C06806F0-b4cIHhjg/p/XzH18dTCKOgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Zeng, Oak @ 2019-02-06 15:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Knott, William, Yang,
Alice (SRDC 3D)
Cc: Zhao, Yong
+ Clint/Alice
Hi Clint,
We think CP_MEC_DOORBELL_RANGE_LOWER/UPPER registers are used by MEC to check whether a doorbell routed to MEC belongs to MEC, is this understanding correct?
From the register spec, those registers are 27 bits. Does this mean MEC use all 27 bits to determine? For example, if we set lower/upper to [0, 4k], will a doorbell ring at 6K address be ignored by MEC?
Thanks,
Oak
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhao, Yong
Sent: Tuesday, February 5, 2019 3:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong <Yong.Zhao@amd.com>
Subject: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15
Because CP can use all doorbells outside the ones reserved for SDMA, IH, and VCN, so the value set to CP_MEC_DOORBELL_RANGE_UPPER should be the maximal index possible in a page.
Change-Id: I402a56ce9a80e6c2ed2f96be431ae71ca88e73a4
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++ drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
4 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 5c8d04c353d0..90eca63605ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -73,6 +73,7 @@ struct amdgpu_doorbell_index {
} uvd_vce;
};
uint32_t max_assignment;
+ uint32_t last_idx;
/* Per engine SDMA doorbell size in dword */
uint32_t dw_range_per_sdma_eng;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 262ee3cf6f1c..0278e3ab6b94 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2998,7 +2998,7 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
(adev->doorbell_index.kiq * 2) << 2);
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
- (adev->doorbell_index.userqueue_end * 2) << 2);
+ (adev->doorbell_index.last_idx * 2) << 2);
}
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index d2409df2dde9..9eb8c9209231 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -88,5 +88,8 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
(adev->doorbell_index.sdma_engine[1]
- adev->doorbell_index.sdma_engine[0])
* adev->doorbell_index.entry_dw_size;
+
+ adev->doorbell_index.last_idx = PAGE_SIZE
+ / (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index b28c5999d8f0..aa8c7699c689 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -91,5 +91,8 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
(adev->doorbell_index.sdma_engine[1]
- adev->doorbell_index.sdma_engine[0])
* adev->doorbell_index.entry_dw_size;
+
+ adev->doorbell_index.last_idx = PAGE_SIZE
+ / (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15
[not found] ` <BL0PR12MB258079D4BB56B65F60C55C06806F0-b4cIHhjg/p/XzH18dTCKOgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-02-06 19:35 ` Knott, William
0 siblings, 0 replies; 12+ messages in thread
From: Knott, William @ 2019-02-06 19:35 UTC (permalink / raw)
To: Zeng, Oak, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Yang,
Alice (SRDC 3D)
Cc: Zhao, Yong
Hey Oak,
Interesting you should ask since this has been discussed a lot here recently. So I didn't know until recently that the nbif routes doorbells only using 11:2. So in each 4k page there is an area for the various doorbell recipients including cp gfx and compute.
The doorbell upper/lower in the CP only control the setting of a doorbell updated bit and currently uses the full 27:2. The CP also uses the full 27:2 to match the doorbell to a queue slot and initiate work.
So for your example if you set the ranges to 4k then the CP would not consider a 6k address to match the MEC range and would not actually trigger this doorbell updated logic. This logic is only needed for waking up an idle scheduler and for power gating support.
We are changing the hardware in the doorbell range check to only look at 11:2 to match the nbif routing logic. With the current hardware I am not even sure how you configure the range registers if you are using PASID in bits 27:12 of the doorbell. The default for those registers says that compute gets everything from gfx (0x12) up to 3fffff.
How do you actually configure these currently, do you leave these defaults? That seems like the only way to have it pseudo work without the coming hardware change.
Thanks
Clint
-----Original Message-----
From: Zeng, Oak
Sent: Wednesday, February 06, 2019 10:23 AM
To: Zhao, Yong <Yong.Zhao@amd.com>; amd-gfx@lists.freedesktop.org; Knott, William <William.Knott@amd.com>; Yang, Alice (SRDC 3D) <Alice1.Yang@amd.com>
Cc: Zhao, Yong <Yong.Zhao@amd.com>
Subject: RE: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15
+ Clint/Alice
Hi Clint,
We think CP_MEC_DOORBELL_RANGE_LOWER/UPPER registers are used by MEC to check whether a doorbell routed to MEC belongs to MEC, is this understanding correct?
From the register spec, those registers are 27 bits. Does this mean MEC use all 27 bits to determine? For example, if we set lower/upper to [0, 4k], will a doorbell ring at 6K address be ignored by MEC?
Thanks,
Oak
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhao, Yong
Sent: Tuesday, February 5, 2019 3:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong <Yong.Zhao@amd.com>
Subject: [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15
Because CP can use all doorbells outside the ones reserved for SDMA, IH, and VCN, so the value set to CP_MEC_DOORBELL_RANGE_UPPER should be the maximal index possible in a page.
Change-Id: I402a56ce9a80e6c2ed2f96be431ae71ca88e73a4
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++ drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
4 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 5c8d04c353d0..90eca63605ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -73,6 +73,7 @@ struct amdgpu_doorbell_index {
} uvd_vce;
};
uint32_t max_assignment;
+ uint32_t last_idx;
/* Per engine SDMA doorbell size in dword */
uint32_t dw_range_per_sdma_eng;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 262ee3cf6f1c..0278e3ab6b94 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2998,7 +2998,7 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
(adev->doorbell_index.kiq * 2) << 2);
WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
- (adev->doorbell_index.userqueue_end * 2) << 2);
+ (adev->doorbell_index.last_idx * 2) << 2);
}
WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index d2409df2dde9..9eb8c9209231 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -88,5 +88,8 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
(adev->doorbell_index.sdma_engine[1]
- adev->doorbell_index.sdma_engine[0])
* adev->doorbell_index.entry_dw_size;
+
+ adev->doorbell_index.last_idx = PAGE_SIZE
+ / (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index b28c5999d8f0..aa8c7699c689 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -91,5 +91,8 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
(adev->doorbell_index.sdma_engine[1]
- adev->doorbell_index.sdma_engine[0])
* adev->doorbell_index.entry_dw_size;
+
+ adev->doorbell_index.last_idx = PAGE_SIZE
+ / (sizeof(uint32_t) * adev->doorbell_index.entry_dw_size) - 1;
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask on SOC15
[not found] ` <20190205203047.22586-4-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-07 22:28 ` Zhao, Yong
2019-02-08 21:43 ` Kuehling, Felix
1 sibling, 0 replies; 12+ messages in thread
From: Zhao, Yong @ 2019-02-07 22:28 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 10183 bytes --]
Felix,
Can you review the 4th and 5th patch? They were kept unchanged.
Regards,
Yong
________________________________
From: Zhao, Yong
Sent: Tuesday, February 5, 2019 3:31 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhao, Yong
Subject: [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask on SOC15
Reserved doorbells for SDMA IH and VCN were not properly masked out
when allocating doorbells for CP user queues. This patch fixed that.
Change-Id: I670adfc3fd7725d2ed0bd9665cb7f69f8b9023c2
Signed-off-by: Yong Zhao <Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 17 +++++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 4 ++++
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 ++++++++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 ++++++++++++++-----
.../gpu/drm/amd/include/kgd_kfd_interface.h | 19 ++++++-----------
7 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index e957e42c539a..ee8527701731 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -196,11 +196,20 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
gpu_resources.sdma_doorbell[1][i+1] =
adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
}
- /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
- * SDMA, IH and VCN. So don't use them for the CP.
+
+ /* Because of the setting in registers like
+ * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
+ * lower 12 bits of doorbell address for routing. In
+ * order to route the CP queue doorbells to CP engine,
+ * the doorbells allocated to CP queues have to be
+ * outside the range set for SDMA, VCN, and IH blocks
+ * Prior to SOC15, all queues use queue ID to
+ * determine doorbells.
*/
- gpu_resources.reserved_doorbell_mask = 0x1e0;
- gpu_resources.reserved_doorbell_val = 0x0e0;
+ gpu_resources.reserved_doorbells_start =
+ adev->doorbell_index.sdma_engine[0];
+ gpu_resources.reserved_doorbells_end =
+ adev->doorbell_index.last_non_cp;
kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index 59c41841cbce..74b8e2bfabd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -70,6 +70,7 @@ struct amdgpu_doorbell_index {
uint32_t vce_ring6_7;
} uvd_vce;
};
+ uint32_t last_non_cp;
uint32_t max_assignment;
uint32_t last_idx;
/* Per engine SDMA doorbell size in dword */
@@ -141,6 +142,7 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
+ AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
@@ -216,6 +218,8 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
+ AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
+
AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
AMDGPU_DOORBELL64_INVALID = 0xFFFF
} AMDGPU_DOORBELL64_ASSIGNMENT;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 65214c7b0b20..76166c0ec509 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -80,6 +80,9 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
+
+ adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
+
/* In unit of dword doorbell */
adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
adev->doorbell_index.dw_range_per_sdma_eng =
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index a388d306391a..10df2fed5a99 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -84,6 +84,9 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
+
+ adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP;
+
adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
adev->doorbell_index.dw_range_per_sdma_eng =
(adev->doorbell_index.sdma_engine[1]
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index e5ebcca7f031..6b8459f852cc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -103,6 +103,15 @@
#define KFD_KERNEL_QUEUE_SIZE 2048
+/* 512 = 0x200
+ * On SOC15, the doorbell index distance for SDMA RLC i and (i + 1) in the
+ * same SDMA engine, where i is a even number.
+ * For 8-bytes doorbells, it ensures that the mirror doorbell range (in terms
+ * of low 12 bit address for each HW engine) on the second doorbell page is
+ * the same as the range of the first doorbell page.*/
+#define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
+
+
/*
* Kernel module parameter to specify maximum number of supported queues per
* device
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 80b36e860a0a..e904d6036b3d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -607,13 +607,24 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
if (!qpd->doorbell_bitmap)
return -ENOMEM;
- /* Mask out any reserved doorbells */
- for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS; i++)
- if ((dev->shared_resources.reserved_doorbell_mask & i) ==
- dev->shared_resources.reserved_doorbell_val) {
+ /* Mask out all reserved doorbells for SDMA, IH, and VCN on SOC15.
+ * Because of the setting in registers like SDMA0_DOORBELL_RANGE etc.,
+ * BIF statically uses the lower 12 bits of doorbell address for
+ * routing. In order to route the CP queue doorbells to CP engine,
+ * the doorbells allocated to CP queues have to be outside the range
+ * set for SDMA, VCN, and IH blocks.
+ * Prior to SOC15, all queues use queue ID to
+ * determine doorbells. */
+ for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS / 2; i++) {
+ if (i >= dev->shared_resources.reserved_doorbells_start
+ && i <= dev->shared_resources.reserved_doorbells_end) {
set_bit(i, qpd->doorbell_bitmap);
- pr_debug("reserved doorbell 0x%03x\n", i);
+ set_bit(i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
+ qpd->doorbell_bitmap);
+ pr_debug("reserved doorbell 0x%03x and 0x%03x\n", i,
+ i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET);
}
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 83d960110d23..b1bf45419d93 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -137,20 +137,13 @@ struct kgd2kfd_shared_resources {
/* Bit n == 1 means Queue n is available for KFD */
DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
- /* Doorbell assignments (SOC15 and later chips only). Only
- * specific doorbells are routed to each SDMA engine. Others
- * are routed to IH and VCN. They are not usable by the CP.
- *
- * Any doorbell number D that satisfies the following condition
- * is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val
- *
- * KFD currently uses 1024 (= 0x3ff) doorbells per process. If
- * doorbells 0x0e0-0x0ff and 0x2e0-0x2ff are reserved, that means
- * mask would be set to 0x1e0 and val set to 0x0e0.
- */
unsigned int sdma_doorbell[2][8];
- unsigned int reserved_doorbell_mask;
- unsigned int reserved_doorbell_val;
+
+ /* From SOC15 onwards, the doorbell indexes reserved for SDMA, IH,
+ * and VCN
+ */
+ unsigned int reserved_doorbells_start;
+ unsigned int reserved_doorbells_end;
/* Base address of doorbell aperture. */
phys_addr_t doorbell_physical_address;
--
2.17.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask on SOC15
[not found] ` <20190205203047.22586-4-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-07 22:28 ` Zhao, Yong
@ 2019-02-08 21:43 ` Kuehling, Felix
1 sibling, 0 replies; 12+ messages in thread
From: Kuehling, Felix @ 2019-02-08 21:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhao, Yong
The code is fine. Some comments about your comment changes inline to
help clarify things a bit.
On 2019-02-05 3:31 p.m., Zhao, Yong wrote:
> Reserved doorbells for SDMA IH and VCN were not properly masked out
> when allocating doorbells for CP user queues. This patch fixed that.
>
> Change-Id: I670adfc3fd7725d2ed0bd9665cb7f69f8b9023c2
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 17 +++++++++++----
> drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 4 ++++
> drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 3 +++
> drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 3 +++
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 ++++++++
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 ++++++++++++++-----
> .../gpu/drm/amd/include/kgd_kfd_interface.h | 19 ++++++-----------
> 7 files changed, 54 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index e957e42c539a..ee8527701731 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -196,11 +196,20 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
> gpu_resources.sdma_doorbell[1][i+1] =
> adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
> }
> - /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
> - * SDMA, IH and VCN. So don't use them for the CP.
> +
> + /* Because of the setting in registers like
> + * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
> + * lower 12 bits of doorbell address for routing. In
> + * order to route the CP queue doorbells to CP engine,
> + * the doorbells allocated to CP queues have to be
> + * outside the range set for SDMA, VCN, and IH blocks
> + * Prior to SOC15, all queues use queue ID to
> + * determine doorbells.
This comment mixes up cause and effect:
1. Doorbell routing by the BIF (cause)
2. Changes to doorbell assignment for user mode queues (effect)
The first is a HW change (cause). The second is a consequence from that
(effect). Amdgpu doesn't know anything about KFD queue IDs. I'd just
drop that sentence.
In this context, what distinguishes SOC15 from older chips is, that on
older chips the BIF does not route doorbells. All doorbells can be used
by all engines. Only on SOC15 and newer, KFD needs to know about how
doorbells are routed by the BIF in order to correctly assign doorbells
to queues. Therefore the reserved_doorbell_... and sdma_doorbell fields
are only used on SOC15.
> */
> - gpu_resources.reserved_doorbell_mask = 0x1e0;
> - gpu_resources.reserved_doorbell_val = 0x0e0;
> + gpu_resources.reserved_doorbells_start =
> + adev->doorbell_index.sdma_engine[0];
> + gpu_resources.reserved_doorbells_end =
> + adev->doorbell_index.last_non_cp;
>
> kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> index 59c41841cbce..74b8e2bfabd3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
> @@ -70,6 +70,7 @@ struct amdgpu_doorbell_index {
> uint32_t vce_ring6_7;
> } uvd_vce;
> };
> + uint32_t last_non_cp;
> uint32_t max_assignment;
> uint32_t last_idx;
> /* Per engine SDMA doorbell size in dword */
> @@ -141,6 +142,7 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
> AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
> AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
> AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
> + AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
> AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
> AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
> } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
> @@ -216,6 +218,8 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
> AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
> AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
>
> + AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
> +
> AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
> AMDGPU_DOORBELL64_INVALID = 0xFFFF
> } AMDGPU_DOORBELL64_ASSIGNMENT;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> index 65214c7b0b20..76166c0ec509 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
> @@ -80,6 +80,9 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
> adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
> adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
> adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
> +
> + adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
> +
> /* In unit of dword doorbell */
> adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
> adev->doorbell_index.dw_range_per_sdma_eng =
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> index a388d306391a..10df2fed5a99 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> @@ -84,6 +84,9 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
> adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
> adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
> adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
> +
> + adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP;
> +
> adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
> adev->doorbell_index.dw_range_per_sdma_eng =
> (adev->doorbell_index.sdma_engine[1]
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index e5ebcca7f031..6b8459f852cc 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -103,6 +103,15 @@
>
> #define KFD_KERNEL_QUEUE_SIZE 2048
>
> +/* 512 = 0x200
> + * On SOC15, the doorbell index distance for SDMA RLC i and (i + 1) in the
> + * same SDMA engine, where i is a even number.
> + * For 8-bytes doorbells, it ensures that the mirror doorbell range (in terms
> + * of low 12 bit address for each HW engine) on the second doorbell page is
> + * the same as the range of the first doorbell page.*/
> +#define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
> +
> +
> /*
> * Kernel module parameter to specify maximum number of supported queues per
> * device
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index 80b36e860a0a..e904d6036b3d 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -607,13 +607,24 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
> if (!qpd->doorbell_bitmap)
> return -ENOMEM;
>
> - /* Mask out any reserved doorbells */
> - for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS; i++)
> - if ((dev->shared_resources.reserved_doorbell_mask & i) ==
> - dev->shared_resources.reserved_doorbell_val) {
> + /* Mask out all reserved doorbells for SDMA, IH, and VCN on SOC15.
> + * Because of the setting in registers like SDMA0_DOORBELL_RANGE etc.,
> + * BIF statically uses the lower 12 bits of doorbell address for
> + * routing. In order to route the CP queue doorbells to CP engine,
> + * the doorbells allocated to CP queues have to be outside the range
> + * set for SDMA, VCN, and IH blocks.
> + * Prior to SOC15, all queues use queue ID to
> + * determine doorbells. */
> + for (i = 0; i < KFD_MAX_NUM_OF_QUEUES_PER_PROCESS / 2; i++) {
> + if (i >= dev->shared_resources.reserved_doorbells_start
> + && i <= dev->shared_resources.reserved_doorbells_end) {
> set_bit(i, qpd->doorbell_bitmap);
> - pr_debug("reserved doorbell 0x%03x\n", i);
> + set_bit(i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET,
> + qpd->doorbell_bitmap);
> + pr_debug("reserved doorbell 0x%03x and 0x%03x\n", i,
> + i + KFD_QUEUE_DOORBELL_MIRROR_OFFSET);
> }
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> index 83d960110d23..b1bf45419d93 100644
> --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> @@ -137,20 +137,13 @@ struct kgd2kfd_shared_resources {
> /* Bit n == 1 means Queue n is available for KFD */
> DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
>
> - /* Doorbell assignments (SOC15 and later chips only). Only
> - * specific doorbells are routed to each SDMA engine. Others
> - * are routed to IH and VCN. They are not usable by the CP.
This first paragraph is still applicable and explains why we need the
sdma_doorbell array on SOC15 to assign doorbells for SDMA queues.
> - *
> - * Any doorbell number D that satisfies the following condition
> - * is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val
> - *
> - * KFD currently uses 1024 (= 0x3ff) doorbells per process. If
> - * doorbells 0x0e0-0x0ff and 0x2e0-0x2ff are reserved, that means
> - * mask would be set to 0x1e0 and val set to 0x0e0.
> - */
> unsigned int sdma_doorbell[2][8];
> - unsigned int reserved_doorbell_mask;
> - unsigned int reserved_doorbell_val;
> +
> + /* From SOC15 onwards, the doorbell indexes reserved for SDMA, IH,
> + * and VCN
The important bit that you should not forget to mention, is that these
doorbells are not routed to the CP, so they're reserved (unusable) for
CP queues.
Regards,
Felix
> + */
> + unsigned int reserved_doorbells_start;
> + unsigned int reserved_doorbells_end;
>
> /* Base address of doorbell aperture. */
> phys_addr_t doorbell_physical_address;
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 5/5] drm/amdkfd: Optimize out sdma doorbell array in kgd2kfd_shared_resources
[not found] ` <20190205203047.22586-5-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-08 22:06 ` Kuehling, Felix
0 siblings, 0 replies; 12+ messages in thread
From: Kuehling, Felix @ 2019-02-08 22:06 UTC (permalink / raw)
To: Zhao, Yong, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Some nit-picks inline. Looks good otherwise.
On 2019-02-05 3:31 p.m., Zhao, Yong wrote:
> We can directly calculate the sdma doorbell index in the process doorbell
> pages through the doorbell_index structure in amdgpu_device, so no need
> to cache them in kgd2kfd_shared_resources any more, resulting in more
> portable code.
What do you mean by "portable" here? Portable to what? Other
architectures? Kernels? GPUs?
>
> Change-Id: Ic657799856ed0256f36b01e502ef0cab263b1f49
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 55 ++++++-------------
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 18 ++++--
> .../gpu/drm/amd/include/kgd_kfd_interface.h | 2 +-
> 3 files changed, 31 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index ee8527701731..e62c3703169a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -131,7 +131,7 @@ static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
>
> void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
> {
> - int i, n;
> + int i;
> int last_valid_bit;
>
> if (adev->kfd.dev) {
> @@ -142,7 +142,9 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
> .gpuvm_size = min(adev->vm_manager.max_pfn
> << AMDGPU_GPU_PAGE_SHIFT,
> AMDGPU_GMC_HOLE_START),
> - .drm_render_minor = adev->ddev->render->index
> + .drm_render_minor = adev->ddev->render->index,
> + .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
> +
> };
>
> /* this is going to have a few of the MSBs set that we need to
> @@ -172,45 +174,22 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
> &gpu_resources.doorbell_aperture_size,
> &gpu_resources.doorbell_start_offset);
>
> - if (adev->asic_type < CHIP_VEGA10) {
> - kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
> - return;
> - }
> -
> - n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
> -
> - for (i = 0; i < n; i += 2) {
> - /* On SOC15 the BIF is involved in routing
> - * doorbells using the low 12 bits of the
> - * address. Communicate the assignments to
> - * KFD. KFD uses two doorbell pages per
> - * process in case of 64-bit doorbells so we
> - * can use each doorbell assignment twice.
> + if (adev->asic_type >= CHIP_VEGA10) {
> + /* Because of the setting in registers like
> + * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
> + * lower 12 bits of doorbell address for routing. In
> + * order to route the CP queue doorbells to CP engine,
> + * the doorbells allocated to CP queues have to be
> + * outside the range set for SDMA, VCN, and IH blocks
> + * Prior to SOC15, all queues use queue ID to
> + * determine doorbells.
> */
> - gpu_resources.sdma_doorbell[0][i] =
> - adev->doorbell_index.sdma_engine[0] + (i >> 1);
> - gpu_resources.sdma_doorbell[0][i+1] =
> - adev->doorbell_index.sdma_engine[0] + 0x200 + (i >> 1);
> - gpu_resources.sdma_doorbell[1][i] =
> - adev->doorbell_index.sdma_engine[1] + (i >> 1);
> - gpu_resources.sdma_doorbell[1][i+1] =
> - adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
> + gpu_resources.reserved_doorbells_start =
> + adev->doorbell_index.sdma_engine[0];
> + gpu_resources.reserved_doorbells_end =
> + adev->doorbell_index.last_non_cp;
> }
>
> - /* Because of the setting in registers like
> - * SDMA0_DOORBELL_RANGE etc., BIF statically uses the
> - * lower 12 bits of doorbell address for routing. In
> - * order to route the CP queue doorbells to CP engine,
> - * the doorbells allocated to CP queues have to be
> - * outside the range set for SDMA, VCN, and IH blocks
> - * Prior to SOC15, all queues use queue ID to
> - * determine doorbells.
> - */
> - gpu_resources.reserved_doorbells_start =
> - adev->doorbell_index.sdma_engine[0];
> - gpu_resources.reserved_doorbells_end =
> - adev->doorbell_index.last_non_cp;
> -
> kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
> }
> }
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 8372556b52eb..81280ce5aa27 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -134,12 +134,20 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
> */
> q->doorbell_id = q->properties.queue_id;
> } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
> - /* For SDMA queues on SOC15, use static doorbell
> - * assignments based on the engine and queue.
> + /* For SDMA queues on SOC15 with 8-byte doorbell, use static
> + * doorbell assignments based on the engine and queue id.
> + * The doobell index distance between RLC (2*i) and (2*i+1)
> + * for a SDMA engine is 512.
> + * 512 8-byte doorbell distance (i.e. one page away) ensures
> + * that SDMA RLC (2*i+1) doorbell lies exactly in the doorbell
> + * OFFSET and SIZE set in register BIF_SDMA0_DOORBELL_RANGE.
> */
> - q->doorbell_id = dev->shared_resources.sdma_doorbell
> - [q->properties.sdma_engine_id]
> - [q->properties.sdma_queue_id];
> + unsigned int *idx_offset =
> + dev->shared_resources.sdma_doorbell_idx;
The type in struct amdgpu_doorbell_index is uint32_t. I'd prefer
matching the type of the pointer here.
> + q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
> + + (q->properties.sdma_queue_id >> 1)
> + + (q->properties.sdma_queue_id % 2)
Be consistent with the use of bit-wise operations (x >> 1 and x & 1) or
division (x / 2 and x %2). Here you're mixing them. I prefer the
bit-wise operations for division and modulo with powers of two.
> + * KFD_QUEUE_DOORBELL_MIRROR_OFFSET;
> } else {
> /* For CP queues on SOC15 reserve a free doorbell ID */
> unsigned int found;
> diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> index b1bf45419d93..3559170f6fb3 100644
> --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> @@ -137,7 +137,7 @@ struct kgd2kfd_shared_resources {
> /* Bit n == 1 means Queue n is available for KFD */
> DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
>
> - unsigned int sdma_doorbell[2][8];
> + unsigned int *sdma_doorbell_idx;
The type in struct amdgpu_doorbell_index is uint32_t. I'd prefer
matching the type of the pointer here.
Regards,
Felix
>
> /* From SOC15 onwards, the doorbell indexes reserved for SDMA, IH,
> * and VCN
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-02-08 22:06 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-05 20:31 [PATCH 1/5] drm/amdkfd: Improve doorbell variable names Zhao, Yong
[not found] ` <20190205203047.22586-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-05 20:31 ` [PATCH 3/5] drm/amdgpu: Delete user queue doorbell variables Zhao, Yong
2019-02-05 20:31 ` [PATCH 2/5] drm/amdgpu: Fix a bug in setting CP_MEC_DOORBELL_RANGE_UPPER on SOC15 Zhao, Yong
[not found] ` <20190205203047.22586-2-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-06 15:23 ` Zeng, Oak
[not found] ` <BL0PR12MB258079D4BB56B65F60C55C06806F0-b4cIHhjg/p/XzH18dTCKOgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-02-06 19:35 ` Knott, William
2019-02-05 20:31 ` [PATCH 4/5] drm/amdkfd: Fix bugs regarding CP user queue doorbells mask " Zhao, Yong
[not found] ` <20190205203047.22586-4-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-07 22:28 ` Zhao, Yong
2019-02-08 21:43 ` Kuehling, Felix
2019-02-05 20:31 ` [PATCH 5/5] drm/amdkfd: Optimize out sdma doorbell array in kgd2kfd_shared_resources Zhao, Yong
[not found] ` <20190205203047.22586-5-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-08 22:06 ` Kuehling, Felix
2019-02-05 21:43 ` [PATCH 1/5] drm/amdkfd: Improve doorbell variable names Kuehling, Felix
[not found] ` <911744ff-f4e5-b165-123e-a574b2310746-5C7GfCeVMHo@public.gmane.org>
2019-02-06 1:18 ` Alex Deucher
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