* [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver
@ 2022-06-19 21:27 Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Dmitry Baryshkov
` (7 more replies)
0 siblings, 8 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
Please excuse me for the spam, I've erroneously sent v2 without the
requested change.
Update gcc-msm8916 driver and bindings to use DT-specified clocks
rather than fetching the clocks from the global clocks list.
Changes since v2:
- Use xo-board for the XO rather than RPM clock. This will be sorted
out separately (requested by Stephan Gerhold).
Changes since v1:
- None.
Dmitry Baryshkov (7):
dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml
dt-bindings: clock: separate bindings for MSM8916 GCC device
clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying
num_parents
clk: qcom: gcc-msm8916: move clock parent tables down
clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down
clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names
arm64: dts: qcom: msm8916: add clocks to the GCC device node
.../bindings/clock/qcom,gcc-msm8916.yaml | 61 +
.../bindings/clock/qcom,gcc-msm8976.yaml | 21 +-
.../bindings/clock/qcom,gcc-msm8994.yaml | 21 +-
.../bindings/clock/qcom,gcc-msm8996.yaml | 25 +-
.../bindings/clock/qcom,gcc-msm8998.yaml | 25 +-
.../bindings/clock/qcom,gcc-other.yaml | 1 -
.../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +-
.../bindings/clock/qcom,gcc-sc7180.yaml | 25 +-
.../bindings/clock/qcom,gcc-sc7280.yaml | 21 +-
.../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +-
.../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +-
.../bindings/clock/qcom,gcc-sdm845.yaml | 25 +-
.../bindings/clock/qcom,gcc-sdx55.yaml | 21 +-
.../bindings/clock/qcom,gcc-sdx65.yaml | 21 +-
.../bindings/clock/qcom,gcc-sm6115.yaml | 25 +-
.../bindings/clock/qcom,gcc-sm6125.yaml | 25 +-
.../bindings/clock/qcom,gcc-sm6350.yaml | 25 +-
.../bindings/clock/qcom,gcc-sm8150.yaml | 25 +-
.../bindings/clock/qcom,gcc-sm8250.yaml | 25 +-
.../bindings/clock/qcom,gcc-sm8350.yaml | 21 +-
.../bindings/clock/qcom,gcc-sm8450.yaml | 21 +-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 +
drivers/clk/qcom/gcc-msm8916.c | 1020 +++++++++--------
23 files changed, 669 insertions(+), 870 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
--
2.35.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-20 12:05 ` Dmitry Baryshkov
2022-06-27 21:11 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device Dmitry Baryshkov
` (6 subsequent siblings)
7 siblings, 2 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
Use qcom,gcc.yaml which contains a set of properties common to most
Qualcomm GCC bindings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,gcc-msm8976.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-msm8994.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-msm8996.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-msm8998.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sc7180.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sc7280.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-sdm845.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sdx55.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-sdx65.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-sm6115.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sm6125.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sm6350.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sm8150.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sm8250.yaml | 25 +++----------------
.../bindings/clock/qcom,gcc-sm8350.yaml | 21 +++-------------
.../bindings/clock/qcom,gcc-sm8450.yaml | 21 +++-------------
19 files changed, 76 insertions(+), 367 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
index f3430b159caa..4b7d69518371 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
@@ -45,29 +45,16 @@ properties:
description:
Phandle to voltage regulator providing power to the GX domain.
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- vdd_gfx-supply
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
index 22e67b238bb6..7b9fef6d9b23 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
@@ -32,28 +32,15 @@ properties:
- const: xo
- const: sleep
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
index 5a5b2214f0ca..70f7d3101bd3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
@@ -33,30 +33,13 @@ properties:
- const: cxo2
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
index 8151c0a05649..544a2335cf05 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
@@ -37,32 +37,15 @@ properties:
- const: core_bi_pll_test_se # Optional clock
minItems: 2
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
index 5de9c8263138..aec37e3f5e30 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
@@ -30,32 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
index a404c8fbee67..e4d490e65d14 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
@@ -33,32 +33,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
index 5693b8997570..ea61367e5abc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
@@ -44,28 +44,15 @@ properties:
- const: ufs_phy_tx_symbol_0_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
index f03ef96e57fa..30b5d1215fa8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
@@ -32,32 +32,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
index 0bcdc69c6f89..e33dea86fb9e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
@@ -56,30 +56,17 @@ properties:
- description: First EMAC controller reference clock
- description: Second EMAC controller reference clock
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
protected-clocks:
maxItems: 389
required:
- compatible
- clocks
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
index d902f137ab17..2b8a35d8739e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
@@ -37,30 +37,13 @@ properties:
- const: pcie_0_pipe_clk
- const: pcie_1_pipe_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
# Example for GCC for SDM845:
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
index b0d1c65aa354..13ffa16e0833 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
@@ -35,28 +35,15 @@ properties:
- const: core_bi_pll_test_se # Optional clock
minItems: 2
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
index 16c4cdc7b4d6..8a1419c4d465 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
@@ -20,9 +20,6 @@ properties:
compatible:
const: qcom,gcc-sdx65
- reg:
- maxItems: 1
-
clocks:
items:
- description: Board XO source
@@ -43,25 +40,15 @@ properties:
- const: core_bi_pll_test_se # Optional clock
minItems: 5
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
index 26050da844d5..bb81a27a1b16 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
@@ -30,32 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
index ab12b391effc..03e84e15815c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
@@ -30,32 +30,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
index 20926cd8293e..cbe98c01c085 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
@@ -32,32 +32,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
index 12766a866625..0333ccb07d8d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
@@ -31,32 +31,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
index 80bd6caf5bc9..4e2a9cac0a91 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
@@ -31,32 +31,15 @@ properties:
- const: bi_tcxo
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
index 1122700dcc2b..3edbeca70a9c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
@@ -54,28 +54,15 @@ properties:
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- clocks
- clock-names
- - reg
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
index 58d98a766de6..102ce6862e24 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
@@ -46,28 +46,15 @@ properties:
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
minItems: 2
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-20 12:06 ` Dmitry Baryshkov
2022-06-27 21:09 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
` (5 subsequent siblings)
7 siblings, 2 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
Separate bindings for GCC on Qualcomm MSM8916 platforms. This adds new
clocks/clock-names properties to be used for clock links.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,gcc-msm8916.yaml | 61 +++++++++++++++++++
.../bindings/clock/qcom,gcc-other.yaml | 1 -
2 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
new file mode 100644
index 000000000000..564aa764b17b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for MSM8916
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on MSM8916.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-msm8916.h
+
+properties:
+ compatible:
+ const: qcom,gcc-msm8916
+
+ clocks:
+ items:
+ - description: XO source
+ - description: Sleep clock source
+ - description: DSI phy instance 0 dsi clock
+ - description: DSI phy instance 0 byte clock
+ - description: External MCLK clock
+ - description: External Primary I2S clock
+ - description: External Secondary I2S clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+ - const: dsi0pll
+ - const: dsi0pllbyte
+ - const: ext_mclk
+ - const: ext_pri_i2s
+ - const: ext_sec_i2s
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@300000 {
+ compatible = "qcom,gcc-msm8916";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0x300000 0x90000>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 6c78df0c46a9..61b90e836b5b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -41,7 +41,6 @@ properties:
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8660
- - qcom,gcc-msm8916
- qcom,gcc-msm8939
- qcom,gcc-msm8953
- qcom,gcc-msm8974
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-27 21:03 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 4/7] clk: qcom: gcc-msm8916: move clock parent tables down Dmitry Baryshkov
` (4 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8916.c | 108 ++++++++++++++++-----------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 17e4a5a2a9fd..40c27ba6286f 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -371,7 +371,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.parent_names = gcc_xo_gpll0_bimc,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
};
@@ -383,7 +383,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.parent_names = gcc_xo_gpll0_bimc,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
};
@@ -403,7 +403,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -424,7 +424,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -443,7 +443,7 @@ static struct clk_rcg2 csi0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -456,7 +456,7 @@ static struct clk_rcg2 csi1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -484,7 +484,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
.ops = &clk_rcg2_ops,
},
};
@@ -511,7 +511,7 @@ static struct clk_rcg2 vfe0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
.parent_names = gcc_xo_gpll0_gpll2,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
@@ -530,7 +530,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -559,7 +559,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -572,7 +572,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -586,7 +586,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -599,7 +599,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -613,7 +613,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -626,7 +626,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -640,7 +640,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -653,7 +653,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -667,7 +667,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -680,7 +680,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -694,7 +694,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -727,7 +727,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -741,7 +741,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -760,7 +760,7 @@ static struct clk_rcg2 cci_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
.parent_names = gcc_xo_gpll0a,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
.ops = &clk_rcg2_ops,
},
};
@@ -780,7 +780,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -794,7 +794,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -814,7 +814,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -835,7 +835,7 @@ static struct clk_rcg2 mclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -849,7 +849,7 @@ static struct clk_rcg2 mclk1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -868,7 +868,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
.ops = &clk_rcg2_ops,
},
};
@@ -881,7 +881,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
.ops = &clk_rcg2_ops,
},
};
@@ -901,7 +901,7 @@ static struct clk_rcg2 cpp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
.parent_names = gcc_xo_gpll0_gpll2,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
@@ -922,7 +922,7 @@ static struct clk_rcg2 crypto_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -941,7 +941,7 @@ static struct clk_rcg2 gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -955,7 +955,7 @@ static struct clk_rcg2 gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -969,7 +969,7 @@ static struct clk_rcg2 gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_names = gcc_xo_gpll0_gpll1a_sleep,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -981,7 +981,7 @@ static struct clk_rcg2 byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_names = gcc_xo_gpll0a_dsibyte,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1000,7 +1000,7 @@ static struct clk_rcg2 esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_names = gcc_xo_dsibyte,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
};
@@ -1025,7 +1025,7 @@ static struct clk_rcg2 mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_names = gcc_xo_gpll0_dsiphy,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
.ops = &clk_rcg2_ops,
},
};
@@ -1038,7 +1038,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_names = gcc_xo_gpll0a_dsiphy,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1057,7 +1057,7 @@ static struct clk_rcg2 vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_names = gcc_xo_gpll0a,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
.ops = &clk_rcg2_ops,
},
};
@@ -1075,7 +1075,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1100,7 +1100,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1125,7 +1125,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1145,7 +1145,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
.parent_names = gcc_xo_gpll0a_gpll1_gpll2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
.ops = &clk_rcg2_ops,
},
};
@@ -1168,7 +1168,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_gpu_clk_src",
.parent_names = gcc_xo_gpll0_bimc,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
},
@@ -1187,7 +1187,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1213,7 +1213,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_ahbfabric_clk_src",
.parent_names = gcc_xo_gpll0_gpll1_sleep,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -1292,7 +1292,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_pri_i2s_clk_src",
.parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -1323,7 +1323,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_sec_i2s_clk_src",
.parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -1354,7 +1354,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_aux_i2s_clk_src",
.parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -1389,7 +1389,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_xo_clk_src",
.parent_names = gcc_xo_sleep,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -1445,7 +1445,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "codec_digcodec_clk_src",
.parent_names = gcc_xo_gpll1_emclk_sleep,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
.ops = &clk_rcg2_ops,
},
};
@@ -1515,7 +1515,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
.parent_names = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -2771,7 +2771,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
.parent_names = gcc_xo_gpll0_bimc,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
},
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 4/7] clk: qcom: gcc-msm8916: move clock parent tables down
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
` (2 preceding siblings ...)
2022-06-19 21:27 ` [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down Dmitry Baryshkov
` (3 subsequent siblings)
7 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
Move clock parent tables down, after the GPLL declrataions, so that we
can use gpll hw clock fields in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8916.c | 216 ++++++++++++++++-----------------
1 file changed, 108 insertions(+), 108 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 40c27ba6286f..7962edbdbcf6 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -42,6 +42,114 @@ enum {
P_EXT_MCLK,
};
+static struct clk_pll gpll0 = {
+ .l_reg = 0x21004,
+ .m_reg = 0x21008,
+ .n_reg = 0x2100c,
+ .config_reg = 0x21010,
+ .mode_reg = 0x21000,
+ .status_reg = 0x2101c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll0_vote = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_vote",
+ .parent_names = (const char *[]){ "gpll0" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll gpll1 = {
+ .l_reg = 0x20004,
+ .m_reg = 0x20008,
+ .n_reg = 0x2000c,
+ .config_reg = 0x20010,
+ .mode_reg = 0x20000,
+ .status_reg = 0x2001c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll1_vote = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_vote",
+ .parent_names = (const char *[]){ "gpll1" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll gpll2 = {
+ .l_reg = 0x4a004,
+ .m_reg = 0x4a008,
+ .n_reg = 0x4a00c,
+ .config_reg = 0x4a010,
+ .mode_reg = 0x4a000,
+ .status_reg = 0x4a01c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll2",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll2_vote = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll2_vote",
+ .parent_names = (const char *[]){ "gpll2" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll bimc_pll = {
+ .l_reg = 0x23004,
+ .m_reg = 0x23008,
+ .n_reg = 0x2300c,
+ .config_reg = 0x23010,
+ .mode_reg = 0x23000,
+ .status_reg = 0x2301c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "bimc_pll",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap bimc_pll_vote = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "bimc_pll_vote",
+ .parent_names = (const char *[]){ "bimc_pll" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 },
@@ -256,114 +364,6 @@ static const char * const gcc_xo_gpll1_emclk_sleep[] = {
"sleep_clk",
};
-static struct clk_pll gpll0 = {
- .l_reg = 0x21004,
- .m_reg = 0x21008,
- .n_reg = 0x2100c,
- .config_reg = 0x21010,
- .mode_reg = 0x21000,
- .status_reg = 0x2101c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll0_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_vote",
- .parent_names = (const char *[]){ "gpll0" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll gpll1 = {
- .l_reg = 0x20004,
- .m_reg = 0x20008,
- .n_reg = 0x2000c,
- .config_reg = 0x20010,
- .mode_reg = 0x20000,
- .status_reg = 0x2001c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll1",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll1_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gpll1_vote",
- .parent_names = (const char *[]){ "gpll1" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll gpll2 = {
- .l_reg = 0x4a004,
- .m_reg = 0x4a008,
- .n_reg = 0x4a00c,
- .config_reg = 0x4a010,
- .mode_reg = 0x4a000,
- .status_reg = 0x4a01c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll2",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll2_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gpll2_vote",
- .parent_names = (const char *[]){ "gpll2" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll bimc_pll = {
- .l_reg = 0x23004,
- .m_reg = 0x23008,
- .n_reg = 0x2300c,
- .config_reg = 0x23010,
- .mode_reg = 0x23000,
- .status_reg = 0x2301c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "bimc_pll",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap bimc_pll_vote = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(3),
- .hw.init = &(struct clk_init_data){
- .name = "bimc_pll_vote",
- .parent_names = (const char *[]){ "bimc_pll" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.hid_width = 5,
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
` (3 preceding siblings ...)
2022-06-19 21:27 ` [PATCH v3 4/7] clk: qcom: gcc-msm8916: move clock parent tables down Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-27 21:18 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 6/7] clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names Dmitry Baryshkov
` (2 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
The gcc_mss_q6_bimc_axi_clk clock depends on the bimc_ddr_clk_src clock.
Move it down in the file to come after the source clock.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8916.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 7962edbdbcf6..4d726ca4b0da 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -2594,23 +2594,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
},
};
-static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
- .halt_reg = 0x49004,
- .clkr = {
- .enable_reg = 0x49004,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mss_q6_bimc_axi_clk",
- .parent_names = (const char *[]){
- "bimc_ddr_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_oxili_ahb_clk = {
.halt_reg = 0x59028,
.clkr = {
@@ -2860,6 +2843,23 @@ static struct clk_branch gcc_bimc_gpu_clk = {
},
};
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+ .halt_reg = 0x49004,
+ .clkr = {
+ .enable_reg = 0x49004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_q6_bimc_axi_clk",
+ .parent_names = (const char *[]){
+ "bimc_ddr_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.clkr = {
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 6/7] clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
` (4 preceding siblings ...)
2022-06-19 21:27 ` [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-27 21:28 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node Dmitry Baryshkov
2022-06-20 12:12 ` [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Konrad Dybcio
7 siblings, 1 reply; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-msm8916.c | 682 +++++++++++++++++----------------
1 file changed, 349 insertions(+), 333 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 4d726ca4b0da..148dbbf7cecc 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -52,7 +52,9 @@ static struct clk_pll gpll0 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -63,7 +65,9 @@ static struct clk_regmap gpll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_vote",
- .parent_names = (const char *[]){ "gpll0" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll0.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -79,7 +83,9 @@ static struct clk_pll gpll1 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll1",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -90,7 +96,9 @@ static struct clk_regmap gpll1_vote = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_vote",
- .parent_names = (const char *[]){ "gpll1" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll1.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -106,7 +114,9 @@ static struct clk_pll gpll2 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -117,7 +127,9 @@ static struct clk_regmap gpll2_vote = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_vote",
- .parent_names = (const char *[]){ "gpll2" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gpll2.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -133,7 +145,9 @@ static struct clk_pll bimc_pll = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_pll",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo", .name = "xo_board",
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -144,7 +158,9 @@ static struct clk_regmap bimc_pll_vote = {
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "bimc_pll_vote",
- .parent_names = (const char *[]){ "bimc_pll" },
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_pll.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -155,9 +171,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_GPLL0, 1 },
};
-static const char * const gcc_xo_gpll0[] = {
- "xo",
- "gpll0_vote",
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
@@ -166,10 +182,10 @@ static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
{ P_BIMC, 2 },
};
-static const char * const gcc_xo_gpll0_bimc[] = {
- "xo",
- "gpll0_vote",
- "bimc_pll_vote",
+static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &bimc_pll_vote.hw },
};
static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
@@ -179,11 +195,11 @@ static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
{ P_GPLL2_AUX, 2 },
};
-static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
- "xo",
- "gpll0_vote",
- "gpll1_vote",
- "gpll2_vote",
+static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2a[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll1_vote.hw },
+ { .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
@@ -192,10 +208,10 @@ static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
{ P_GPLL2, 2 },
};
-static const char * const gcc_xo_gpll0_gpll2[] = {
- "xo",
- "gpll0_vote",
- "gpll2_vote",
+static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0a_map[] = {
@@ -203,9 +219,9 @@ static const struct parent_map gcc_xo_gpll0a_map[] = {
{ P_GPLL0_AUX, 2 },
};
-static const char * const gcc_xo_gpll0a[] = {
- "xo",
- "gpll0_vote",
+static const struct clk_parent_data gcc_xo_gpll0a[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
@@ -215,11 +231,11 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
{ P_SLEEP_CLK, 6 },
};
-static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
- "xo",
- "gpll0_vote",
- "gpll1_vote",
- "sleep_clk",
+static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll1_vote.hw },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
@@ -228,10 +244,10 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
{ P_GPLL1_AUX, 2 },
};
-static const char * const gcc_xo_gpll0_gpll1a[] = {
- "xo",
- "gpll0_vote",
- "gpll1_vote",
+static const struct clk_parent_data gcc_xo_gpll0_gpll1a[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll1_vote.hw },
};
static const struct parent_map gcc_xo_dsibyte_map[] = {
@@ -239,9 +255,9 @@ static const struct parent_map gcc_xo_dsibyte_map[] = {
{ P_DSI0_PHYPLL_BYTE, 2 },
};
-static const char * const gcc_xo_dsibyte[] = {
- "xo",
- "dsi0pllbyte",
+static const struct clk_parent_data gcc_xo_dsibyte[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
@@ -250,10 +266,10 @@ static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
{ P_DSI0_PHYPLL_BYTE, 1 },
};
-static const char * const gcc_xo_gpll0a_dsibyte[] = {
- "xo",
- "gpll0_vote",
- "dsi0pllbyte",
+static const struct clk_parent_data gcc_xo_gpll0a_dsibyte[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
@@ -262,10 +278,10 @@ static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
{ P_DSI0_PHYPLL_DSI, 2 },
};
-static const char * const gcc_xo_gpll0_dsiphy[] = {
- "xo",
- "gpll0_vote",
- "dsi0pll",
+static const struct clk_parent_data gcc_xo_gpll0_dsiphy[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
};
static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
@@ -274,10 +290,10 @@ static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
{ P_DSI0_PHYPLL_DSI, 1 },
};
-static const char * const gcc_xo_gpll0a_dsiphy[] = {
- "xo",
- "gpll0_vote",
- "dsi0pll",
+static const struct clk_parent_data gcc_xo_gpll0a_dsiphy[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .fw_name = "dsi0pll", .name = "dsi0pll" },
};
static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
@@ -287,11 +303,11 @@ static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
{ P_GPLL2, 2 },
};
-static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
- "xo",
- "gpll0_vote",
- "gpll1_vote",
- "gpll2_vote",
+static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll1_vote.hw },
+ { .hw = &gpll2_vote.hw },
};
static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
@@ -301,11 +317,11 @@ static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
{ P_SLEEP_CLK, 6 }
};
-static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
- "xo",
- "gpll0_vote",
- "gpll1_vote",
- "sleep_clk",
+static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll0_vote.hw },
+ { .hw = &gpll1_vote.hw },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
@@ -316,12 +332,12 @@ static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
{ P_SLEEP_CLK, 6 }
};
-static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
- "xo",
- "gpll1_vote",
- "ext_pri_i2s",
- "ext_mclk",
- "sleep_clk",
+static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll1_vote.hw },
+ { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
+ { .fw_name = "ext_mclk", .name = "ext_mclk" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
@@ -332,12 +348,12 @@ static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
{ P_SLEEP_CLK, 6 }
};
-static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
- "xo",
- "gpll1_vote",
- "ext_sec_i2s",
- "ext_mclk",
- "sleep_clk",
+static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll1_vote.hw },
+ { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
+ { .fw_name = "ext_mclk", .name = "ext_mclk" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_sleep_map[] = {
@@ -345,9 +361,9 @@ static const struct parent_map gcc_xo_sleep_map[] = {
{ P_SLEEP_CLK, 6 }
};
-static const char * const gcc_xo_sleep[] = {
- "xo",
- "sleep_clk",
+static const struct clk_parent_data gcc_xo_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
@@ -357,11 +373,11 @@ static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
{ P_SLEEP_CLK, 6 }
};
-static const char * const gcc_xo_gpll1_emclk_sleep[] = {
- "xo",
- "gpll1_vote",
- "ext_mclk",
- "sleep_clk",
+static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep[] = {
+ { .fw_name = "xo", .name = "xo_board" },
+ { .hw = &gpll1_vote.hw },
+ { .fw_name = "ext_mclk", .name = "ext_mclk" },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
@@ -370,7 +386,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
- .parent_names = gcc_xo_gpll0_bimc,
+ .parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
@@ -382,7 +398,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
- .parent_names = gcc_xo_gpll0_bimc,
+ .parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
},
@@ -402,7 +418,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
.freq_tbl = ftbl_gcc_camss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_ahb_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -423,7 +439,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.freq_tbl = ftbl_apss_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -442,7 +458,7 @@ static struct clk_rcg2 csi0_clk_src = {
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -455,7 +471,7 @@ static struct clk_rcg2 csi1_clk_src = {
.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -483,7 +499,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
- .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
+ .parent_data = gcc_xo_gpll0a_gpll1_gpll2a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
.ops = &clk_rcg2_ops,
},
@@ -510,7 +526,7 @@ static struct clk_rcg2 vfe0_clk_src = {
.freq_tbl = ftbl_gcc_camss_vfe0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vfe0_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2,
+ .parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
@@ -529,7 +545,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -558,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -571,7 +587,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -585,7 +601,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -598,7 +614,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -612,7 +628,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -625,7 +641,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -639,7 +655,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -652,7 +668,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -666,7 +682,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -679,7 +695,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -693,7 +709,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -726,7 +742,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -740,7 +756,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -759,7 +775,7 @@ static struct clk_rcg2 cci_clk_src = {
.freq_tbl = ftbl_gcc_camss_cci_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cci_clk_src",
- .parent_names = gcc_xo_gpll0a,
+ .parent_data = gcc_xo_gpll0a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
.ops = &clk_rcg2_ops,
},
@@ -779,7 +795,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp0_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -793,7 +809,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "camss_gp1_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -813,7 +829,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
.freq_tbl = ftbl_gcc_camss_jpeg0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "jpeg0_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -834,7 +850,7 @@ static struct clk_rcg2 mclk0_clk_src = {
.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk0_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -848,7 +864,7 @@ static struct clk_rcg2 mclk1_clk_src = {
.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mclk1_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -867,7 +883,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi0phytimer_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a,
+ .parent_data = gcc_xo_gpll0_gpll1a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
.ops = &clk_rcg2_ops,
},
@@ -880,7 +896,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "csi1phytimer_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a,
+ .parent_data = gcc_xo_gpll0_gpll1a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
.ops = &clk_rcg2_ops,
},
@@ -900,7 +916,7 @@ static struct clk_rcg2 cpp_clk_src = {
.freq_tbl = ftbl_gcc_camss_cpp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "cpp_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2,
+ .parent_data = gcc_xo_gpll0_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
@@ -921,7 +937,7 @@ static struct clk_rcg2 crypto_clk_src = {
.freq_tbl = ftbl_gcc_crypto_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -940,7 +956,7 @@ static struct clk_rcg2 gp1_clk_src = {
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -954,7 +970,7 @@ static struct clk_rcg2 gp2_clk_src = {
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -968,7 +984,7 @@ static struct clk_rcg2 gp3_clk_src = {
.freq_tbl = ftbl_gcc_gp1_3_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1a_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1a_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
.ops = &clk_rcg2_ops,
},
@@ -980,7 +996,7 @@ static struct clk_rcg2 byte0_clk_src = {
.parent_map = gcc_xo_gpll0a_dsibyte_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
- .parent_names = gcc_xo_gpll0a_dsibyte,
+ .parent_data = gcc_xo_gpll0a_dsibyte,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
.ops = &clk_byte2_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -999,7 +1015,7 @@ static struct clk_rcg2 esc0_clk_src = {
.freq_tbl = ftbl_gcc_mdss_esc0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
- .parent_names = gcc_xo_dsibyte,
+ .parent_data = gcc_xo_dsibyte,
.num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
.ops = &clk_rcg2_ops,
},
@@ -1024,7 +1040,7 @@ static struct clk_rcg2 mdp_clk_src = {
.freq_tbl = ftbl_gcc_mdss_mdp_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
- .parent_names = gcc_xo_gpll0_dsiphy,
+ .parent_data = gcc_xo_gpll0_dsiphy,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
.ops = &clk_rcg2_ops,
},
@@ -1037,7 +1053,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.parent_map = gcc_xo_gpll0a_dsiphy_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
- .parent_names = gcc_xo_gpll0a_dsiphy,
+ .parent_data = gcc_xo_gpll0a_dsiphy,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
.ops = &clk_pixel_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1056,7 +1072,7 @@ static struct clk_rcg2 vsync_clk_src = {
.freq_tbl = ftbl_gcc_mdss_vsync_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
- .parent_names = gcc_xo_gpll0a,
+ .parent_data = gcc_xo_gpll0a,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
.ops = &clk_rcg2_ops,
},
@@ -1074,7 +1090,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.freq_tbl = ftbl_gcc_pdm2_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1099,7 +1115,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
@@ -1124,7 +1140,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.freq_tbl = ftbl_gcc_sdcc2_apps_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_floor_ops,
},
@@ -1144,7 +1160,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
.freq_tbl = ftbl_gcc_apss_tcu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_tcu_clk_src",
- .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
+ .parent_data = gcc_xo_gpll0a_gpll1_gpll2,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
.ops = &clk_rcg2_ops,
},
@@ -1167,7 +1183,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
.freq_tbl = ftbl_gcc_bimc_gpu_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_gpu_clk_src",
- .parent_names = gcc_xo_gpll0_bimc,
+ .parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
@@ -1186,7 +1202,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.freq_tbl = ftbl_gcc_usb_hs_system_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1212,7 +1228,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
.freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_ahbfabric_clk_src",
- .parent_names = gcc_xo_gpll0_gpll1_sleep,
+ .parent_data = gcc_xo_gpll0_gpll1_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
.ops = &clk_rcg2_ops,
},
@@ -1225,8 +1241,8 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
- .parent_names = (const char *[]){
- "ultaudio_ahbfabric_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1242,8 +1258,8 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
- .parent_names = (const char *[]){
- "ultaudio_ahbfabric_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_ahbfabric_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1291,7 +1307,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_pri_i2s_clk_src",
- .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
+ .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
@@ -1304,8 +1320,8 @@ static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
- .parent_names = (const char *[]){
- "ultaudio_lpaif_pri_i2s_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1322,7 +1338,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_sec_i2s_clk_src",
- .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
+ .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
@@ -1335,8 +1351,8 @@ static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
- .parent_names = (const char *[]){
- "ultaudio_lpaif_sec_i2s_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1353,7 +1369,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_lpaif_aux_i2s_clk_src",
- .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
+ .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
.ops = &clk_rcg2_ops,
},
@@ -1366,8 +1382,8 @@ static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
- .parent_names = (const char *[]){
- "ultaudio_lpaif_aux_i2s_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1388,7 +1404,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
.freq_tbl = ftbl_gcc_ultaudio_xo_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "ultaudio_xo_clk_src",
- .parent_names = gcc_xo_sleep,
+ .parent_data = gcc_xo_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_sleep),
.ops = &clk_rcg2_ops,
},
@@ -1401,8 +1417,8 @@ static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_avsync_xo_clk",
- .parent_names = (const char *[]){
- "ultaudio_xo_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1418,8 +1434,8 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_stc_xo_clk",
- .parent_names = (const char *[]){
- "ultaudio_xo_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &ultaudio_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1444,7 +1460,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
.freq_tbl = ftbl_codec_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "codec_digcodec_clk_src",
- .parent_names = gcc_xo_gpll1_emclk_sleep,
+ .parent_data = gcc_xo_gpll1_emclk_sleep,
.num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
.ops = &clk_rcg2_ops,
},
@@ -1457,8 +1473,8 @@ static struct clk_branch gcc_codec_digcodec_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_codec_digcodec_clk",
- .parent_names = (const char *[]){
- "codec_digcodec_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &codec_digcodec_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1474,8 +1490,8 @@ static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_mport_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1490,8 +1506,8 @@ static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ultaudio_pcnoc_sway_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1514,7 +1530,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
.freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
.clkr.hw.init = &(struct clk_init_data){
.name = "vcodec0_clk_src",
- .parent_names = gcc_xo_gpll0,
+ .parent_data = gcc_xo_gpll0,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
@@ -1528,8 +1544,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1544,8 +1560,8 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1561,8 +1577,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1578,8 +1594,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1595,8 +1611,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1612,8 +1628,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1629,8 +1645,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1646,8 +1662,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1663,8 +1679,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1680,8 +1696,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1697,8 +1713,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup5_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1714,8 +1730,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup5_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup5_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1731,8 +1747,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup6_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1748,8 +1764,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup6_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_qup6_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1765,8 +1781,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1782,8 +1798,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1800,8 +1816,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gcc_boot_rom_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -1816,8 +1832,8 @@ static struct clk_branch gcc_camss_cci_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1833,8 +1849,8 @@ static struct clk_branch gcc_camss_cci_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_clk",
- .parent_names = (const char *[]){
- "cci_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cci_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1850,8 +1866,8 @@ static struct clk_branch gcc_camss_csi0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1867,8 +1883,8 @@ static struct clk_branch gcc_camss_csi0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1884,8 +1900,8 @@ static struct clk_branch gcc_camss_csi0phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phy_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1901,8 +1917,8 @@ static struct clk_branch gcc_camss_csi0pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0pix_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1918,8 +1934,8 @@ static struct clk_branch gcc_camss_csi0rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0rdi_clk",
- .parent_names = (const char *[]){
- "csi0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1935,8 +1951,8 @@ static struct clk_branch gcc_camss_csi1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1952,8 +1968,8 @@ static struct clk_branch gcc_camss_csi1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1969,8 +1985,8 @@ static struct clk_branch gcc_camss_csi1phy_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phy_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1986,8 +2002,8 @@ static struct clk_branch gcc_camss_csi1pix_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1pix_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2003,8 +2019,8 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1rdi_clk",
- .parent_names = (const char *[]){
- "csi1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2020,8 +2036,8 @@ static struct clk_branch gcc_camss_csi_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi_vfe0_clk",
- .parent_names = (const char *[]){
- "vfe0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2037,8 +2053,8 @@ static struct clk_branch gcc_camss_gp0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp0_clk",
- .parent_names = (const char *[]){
- "camss_gp0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2054,8 +2070,8 @@ static struct clk_branch gcc_camss_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_gp1_clk",
- .parent_names = (const char *[]){
- "camss_gp1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2071,8 +2087,8 @@ static struct clk_branch gcc_camss_ispif_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ispif_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2088,8 +2104,8 @@ static struct clk_branch gcc_camss_jpeg0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg0_clk",
- .parent_names = (const char *[]){
- "jpeg0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &jpeg0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2105,8 +2121,8 @@ static struct clk_branch gcc_camss_jpeg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2122,8 +2138,8 @@ static struct clk_branch gcc_camss_jpeg_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_jpeg_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2139,8 +2155,8 @@ static struct clk_branch gcc_camss_mclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
- .parent_names = (const char *[]){
- "mclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2156,8 +2172,8 @@ static struct clk_branch gcc_camss_mclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
- .parent_names = (const char *[]){
- "mclk1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2173,8 +2189,8 @@ static struct clk_branch gcc_camss_micro_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_micro_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2190,8 +2206,8 @@ static struct clk_branch gcc_camss_csi0phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
- .parent_names = (const char *[]){
- "csi0phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2207,8 +2223,8 @@ static struct clk_branch gcc_camss_csi1phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
- .parent_names = (const char *[]){
- "csi1phytimer_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2224,8 +2240,8 @@ static struct clk_branch gcc_camss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2241,8 +2257,8 @@ static struct clk_branch gcc_camss_top_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2258,8 +2274,8 @@ static struct clk_branch gcc_camss_cpp_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2275,8 +2291,8 @@ static struct clk_branch gcc_camss_cpp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cpp_clk",
- .parent_names = (const char *[]){
- "cpp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cpp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2292,8 +2308,8 @@ static struct clk_branch gcc_camss_vfe0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe0_clk",
- .parent_names = (const char *[]){
- "vfe0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vfe0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2309,8 +2325,8 @@ static struct clk_branch gcc_camss_vfe_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_ahb_clk",
- .parent_names = (const char *[]){
- "camss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &camss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2326,8 +2342,8 @@ static struct clk_branch gcc_camss_vfe_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_vfe_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2344,8 +2360,8 @@ static struct clk_branch gcc_crypto_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2362,8 +2378,8 @@ static struct clk_branch gcc_crypto_axi_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2380,8 +2396,8 @@ static struct clk_branch gcc_crypto_clk = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
- .parent_names = (const char *[]){
- "crypto_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &crypto_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2397,8 +2413,8 @@ static struct clk_branch gcc_oxili_gmem_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gmem_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2414,8 +2430,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_names = (const char *[]){
- "gp1_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2431,8 +2447,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_names = (const char *[]){
- "gp2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2448,8 +2464,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_names = (const char *[]){
- "gp3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2465,8 +2481,8 @@ static struct clk_branch gcc_mdss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2482,8 +2498,8 @@ static struct clk_branch gcc_mdss_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2499,8 +2515,8 @@ static struct clk_branch gcc_mdss_byte0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte0_clk",
- .parent_names = (const char *[]){
- "byte0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2516,8 +2532,8 @@ static struct clk_branch gcc_mdss_esc0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc0_clk",
- .parent_names = (const char *[]){
- "esc0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2533,8 +2549,8 @@ static struct clk_branch gcc_mdss_mdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_mdp_clk",
- .parent_names = (const char *[]){
- "mdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2550,8 +2566,8 @@ static struct clk_branch gcc_mdss_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk0_clk",
- .parent_names = (const char *[]){
- "pclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2567,8 +2583,8 @@ static struct clk_branch gcc_mdss_vsync_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_vsync_clk",
- .parent_names = (const char *[]){
- "vsync_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2584,8 +2600,8 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2601,8 +2617,8 @@ static struct clk_branch gcc_oxili_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2618,8 +2634,8 @@ static struct clk_branch gcc_oxili_gfx3d_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gfx3d_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2635,8 +2651,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
- .parent_names = (const char *[]){
- "pdm2_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2652,8 +2668,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2670,8 +2686,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2686,8 +2702,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2703,8 +2719,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_names = (const char *[]){
- "sdcc1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2720,8 +2736,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2737,8 +2753,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_names = (const char *[]){
- "sdcc2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2753,7 +2769,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
.parent_map = gcc_xo_gpll0_bimc_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "bimc_ddr_clk_src",
- .parent_names = gcc_xo_gpll0_bimc,
+ .parent_data = gcc_xo_gpll0_bimc,
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
.ops = &clk_rcg2_ops,
.flags = CLK_GET_RATE_NOCACHE,
@@ -2767,8 +2783,8 @@ static struct clk_branch gcc_apss_tcu_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_tcu_clk",
- .parent_names = (const char *[]){
- "bimc_ddr_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2783,8 +2799,8 @@ static struct clk_branch gcc_gfx_tcu_clk = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_gfx_tcu_clk",
- .parent_names = (const char *[]){
- "bimc_ddr_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2799,8 +2815,8 @@ static struct clk_branch gcc_gtcu_ahb_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_gtcu_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2816,8 +2832,8 @@ static struct clk_branch gcc_bimc_gfx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
- .parent_names = (const char *[]){
- "bimc_gpu_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2833,8 +2849,8 @@ static struct clk_branch gcc_bimc_gpu_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gpu_clk",
- .parent_names = (const char *[]){
- "bimc_gpu_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_gpu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2850,8 +2866,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
- .parent_names = (const char *[]){
- "bimc_ddr_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &bimc_ddr_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2867,8 +2883,8 @@ static struct clk_branch gcc_jpeg_tbu_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_jpeg_tbu_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2884,8 +2900,8 @@ static struct clk_branch gcc_mdp_tbu_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdp_tbu_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2901,8 +2917,8 @@ static struct clk_branch gcc_smmu_cfg_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_smmu_cfg_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2918,8 +2934,8 @@ static struct clk_branch gcc_venus_tbu_clk = {
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus_tbu_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2935,8 +2951,8 @@ static struct clk_branch gcc_vfe_tbu_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gcc_vfe_tbu_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2952,8 +2968,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb2a_phy_sleep_clk",
- .parent_names = (const char *[]){
- "sleep_clk_src",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk", .name = "sleep_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2969,8 +2985,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2986,8 +3002,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
- .parent_names = (const char *[]){
- "usb_hs_system_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3003,8 +3019,8 @@ static struct clk_branch gcc_venus0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3020,8 +3036,8 @@ static struct clk_branch gcc_venus0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_axi_clk",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &system_noc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -3037,8 +3053,8 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_venus0_vcodec0_clk",
- .parent_names = (const char *[]){
- "vcodec0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &vcodec0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
` (5 preceding siblings ...)
2022-06-19 21:27 ` [PATCH v3 6/7] clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-06-19 21:27 ` Dmitry Baryshkov
2022-06-20 12:13 ` Konrad Dybcio
2022-06-27 21:29 ` Marijn Suijten
2022-06-20 12:12 ` [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Konrad Dybcio
7 siblings, 2 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-19 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
As we are converting this platform to use DT clock bindings, add clocks
and clock-names properties to the MMCC device tree node.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 05472510e29d..562c42ce2c5c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -934,6 +934,20 @@ gcc: clock-controller@1800000 {
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x01800000 0x80000>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&dsi_phy0 1>,
+ <&dsi_phy0 0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "xo",
+ "sleep_clk",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "ext_mclk",
+ "ext_pri_i2s",
+ "ext_sec_i2s";
};
tcsr_mutex: hwlock@1905000 {
--
2.35.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml
2022-06-19 21:27 ` [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Dmitry Baryshkov
@ 2022-06-20 12:05 ` Dmitry Baryshkov
2022-06-27 21:11 ` Marijn Suijten
1 sibling, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-20 12:05 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
On 20/06/2022 00:27, Dmitry Baryshkov wrote:
> Use qcom,gcc.yaml which contains a set of properties common to most
> Qualcomm GCC bindings.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Forgot to carry over from v1:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/clock/qcom,gcc-msm8976.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-msm8994.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-msm8996.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-msm8998.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sc7180.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sc7280.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sdm845.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sdx55.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sdx65.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sm6115.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm6125.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm6350.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm8150.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm8250.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm8350.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sm8450.yaml | 21 +++-------------
> 19 files changed, 76 insertions(+), 367 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
> index f3430b159caa..4b7d69518371 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
> @@ -45,29 +45,16 @@ properties:
> description:
> Phandle to voltage regulator providing power to the GX domain.
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - - reg
> - clocks
> - clock-names
> - vdd_gfx-supply
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> index 22e67b238bb6..7b9fef6d9b23 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> @@ -32,28 +32,15 @@ properties:
> - const: xo
> - const: sleep
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
> index 5a5b2214f0ca..70f7d3101bd3 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
> @@ -33,30 +33,13 @@ properties:
> - const: cxo2
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
> index 8151c0a05649..544a2335cf05 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
> @@ -37,32 +37,15 @@ properties:
> - const: core_bi_pll_test_se # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
> index 5de9c8263138..aec37e3f5e30 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
> @@ -30,32 +30,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
> index a404c8fbee67..e4d490e65d14 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
> @@ -33,32 +33,15 @@ properties:
> - const: bi_tcxo_ao
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> index 5693b8997570..ea61367e5abc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> @@ -44,28 +44,15 @@ properties:
> - const: ufs_phy_tx_symbol_0_clk
> - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
> index f03ef96e57fa..30b5d1215fa8 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
> @@ -32,32 +32,15 @@ properties:
> - const: bi_tcxo_ao
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> index 0bcdc69c6f89..e33dea86fb9e 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> @@ -56,30 +56,17 @@ properties:
> - description: First EMAC controller reference clock
> - description: Second EMAC controller reference clock
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> protected-clocks:
> maxItems: 389
>
> required:
> - compatible
> - clocks
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> index d902f137ab17..2b8a35d8739e 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> @@ -37,30 +37,13 @@ properties:
> - const: pcie_0_pipe_clk
> - const: pcie_1_pipe_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> # Example for GCC for SDM845:
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
> index b0d1c65aa354..13ffa16e0833 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
> @@ -35,28 +35,15 @@ properties:
> - const: core_bi_pll_test_se # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
> index 16c4cdc7b4d6..8a1419c4d465 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
> @@ -20,9 +20,6 @@ properties:
> compatible:
> const: qcom,gcc-sdx65
>
> - reg:
> - maxItems: 1
> -
> clocks:
> items:
> - description: Board XO source
> @@ -43,25 +40,15 @@ properties:
> - const: core_bi_pll_test_se # Optional clock
> minItems: 5
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> required:
> - compatible
> - - reg
> - clocks
> - clock-names
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
> index 26050da844d5..bb81a27a1b16 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
> @@ -30,32 +30,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> index ab12b391effc..03e84e15815c 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> @@ -30,32 +30,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
> index 20926cd8293e..cbe98c01c085 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
> @@ -32,32 +32,15 @@ properties:
> - const: bi_tcxo_ao
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
> index 12766a866625..0333ccb07d8d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
> @@ -31,32 +31,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> index 80bd6caf5bc9..4e2a9cac0a91 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> @@ -31,32 +31,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> index 1122700dcc2b..3edbeca70a9c 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> @@ -54,28 +54,15 @@ properties:
> - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> index 58d98a766de6..102ce6862e24 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> @@ -46,28 +46,15 @@ properties:
> - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - - reg
> - clocks
> - clock-names
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device
2022-06-19 21:27 ` [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device Dmitry Baryshkov
@ 2022-06-20 12:06 ` Dmitry Baryshkov
2022-06-27 21:09 ` Marijn Suijten
1 sibling, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-20 12:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten, Konrad Dybcio
On 20/06/2022 00:27, Dmitry Baryshkov wrote:
> Separate bindings for GCC on Qualcomm MSM8916 platforms. This adds new
> clocks/clock-names properties to be used for clock links.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Forgot to carry over from v1:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/clock/qcom,gcc-msm8916.yaml | 61 +++++++++++++++++++
> .../bindings/clock/qcom,gcc-other.yaml | 1 -
> 2 files changed, 61 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
> new file mode 100644
> index 000000000000..564aa764b17b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for MSM8916
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> + - Taniya Das <quic_tdas@quicinc.com>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on MSM8916.
> +
> + See also:
> + - dt-bindings/clock/qcom,gcc-msm8916.h
> +
> +properties:
> + compatible:
> + const: qcom,gcc-msm8916
> +
> + clocks:
> + items:
> + - description: XO source
> + - description: Sleep clock source
> + - description: DSI phy instance 0 dsi clock
> + - description: DSI phy instance 0 byte clock
> + - description: External MCLK clock
> + - description: External Primary I2S clock
> + - description: External Secondary I2S clock
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: sleep_clk
> + - const: dsi0pll
> + - const: dsi0pllbyte
> + - const: ext_mclk
> + - const: ext_pri_i2s
> + - const: ext_sec_i2s
> +
> +required:
> + - compatible
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + clock-controller@300000 {
> + compatible = "qcom,gcc-msm8916";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0x300000 0x90000>;
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> index 6c78df0c46a9..61b90e836b5b 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> @@ -41,7 +41,6 @@ properties:
> - qcom,gcc-mdm9607
> - qcom,gcc-msm8226
> - qcom,gcc-msm8660
> - - qcom,gcc-msm8916
> - qcom,gcc-msm8939
> - qcom,gcc-msm8953
> - qcom,gcc-msm8974
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
` (6 preceding siblings ...)
2022-06-19 21:27 ` [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node Dmitry Baryshkov
@ 2022-06-20 12:12 ` Konrad Dybcio
2022-07-04 16:24 ` Dmitry Baryshkov
7 siblings, 1 reply; 21+ messages in thread
From: Konrad Dybcio @ 2022-06-20 12:12 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten
On 19.06.2022 23:27, Dmitry Baryshkov wrote:
> Please excuse me for the spam, I've erroneously sent v2 without the
> requested change.
>
Please excuse me, I didn't notice and gave you R-bs on v2 instead..
Konrad
> Update gcc-msm8916 driver and bindings to use DT-specified clocks
> rather than fetching the clocks from the global clocks list.
>
> Changes since v2:
> - Use xo-board for the XO rather than RPM clock. This will be sorted
> out separately (requested by Stephan Gerhold).
>
> Changes since v1:
> - None.
>
> Dmitry Baryshkov (7):
> dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml
> dt-bindings: clock: separate bindings for MSM8916 GCC device
> clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying
> num_parents
> clk: qcom: gcc-msm8916: move clock parent tables down
> clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down
> clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names
> arm64: dts: qcom: msm8916: add clocks to the GCC device node
>
> .../bindings/clock/qcom,gcc-msm8916.yaml | 61 +
> .../bindings/clock/qcom,gcc-msm8976.yaml | 21 +-
> .../bindings/clock/qcom,gcc-msm8994.yaml | 21 +-
> .../bindings/clock/qcom,gcc-msm8996.yaml | 25 +-
> .../bindings/clock/qcom,gcc-msm8998.yaml | 25 +-
> .../bindings/clock/qcom,gcc-other.yaml | 1 -
> .../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sc7180.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sc7280.yaml | 21 +-
> .../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +-
> .../bindings/clock/qcom,gcc-sdm845.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sdx55.yaml | 21 +-
> .../bindings/clock/qcom,gcc-sdx65.yaml | 21 +-
> .../bindings/clock/qcom,gcc-sm6115.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sm6125.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sm6350.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sm8150.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sm8250.yaml | 25 +-
> .../bindings/clock/qcom,gcc-sm8350.yaml | 21 +-
> .../bindings/clock/qcom,gcc-sm8450.yaml | 21 +-
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 +
> drivers/clk/qcom/gcc-msm8916.c | 1020 +++++++++--------
> 23 files changed, 669 insertions(+), 870 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node
2022-06-19 21:27 ` [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node Dmitry Baryshkov
@ 2022-06-20 12:13 ` Konrad Dybcio
2022-06-27 21:29 ` Marijn Suijten
1 sibling, 0 replies; 21+ messages in thread
From: Konrad Dybcio @ 2022-06-20 12:13 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten
On 19.06.2022 23:27, Dmitry Baryshkov wrote:
> As we are converting this platform to use DT clock bindings, add clocks
> and clock-names properties to the MMCC device tree node.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Konrad
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 05472510e29d..562c42ce2c5c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -934,6 +934,20 @@ gcc: clock-controller@1800000 {
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> reg = <0x01800000 0x80000>;
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <&dsi_phy0 1>,
> + <&dsi_phy0 0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "xo",
> + "sleep_clk",
> + "dsi0pll",
> + "dsi0pllbyte",
> + "ext_mclk",
> + "ext_pri_i2s",
> + "ext_sec_i2s";
> };
>
> tcsr_mutex: hwlock@1905000 {
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents
2022-06-19 21:27 ` [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-06-27 21:03 ` Marijn Suijten
2022-07-04 17:12 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Marijn Suijten @ 2022-06-27 21:03 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 2022-06-20 00:27:31, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
But do read on about an accidental fix that you may want to pull out
into an explicit patch.
> ---
> drivers/clk/qcom/gcc-msm8916.c | 108 ++++++++++++++++-----------------
> 1 file changed, 54 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
> index 17e4a5a2a9fd..40c27ba6286f 100644
> --- a/drivers/clk/qcom/gcc-msm8916.c
> +++ b/drivers/clk/qcom/gcc-msm8916.c
> @@ -371,7 +371,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcnoc_bfdcd_clk_src",
> .parent_names = gcc_xo_gpll0_bimc,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -383,7 +383,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "system_noc_bfdcd_clk_src",
> .parent_names = gcc_xo_gpll0_bimc,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -403,7 +403,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_ahb_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -424,7 +424,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "apss_ahb_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -443,7 +443,7 @@ static struct clk_rcg2 csi0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -456,7 +456,7 @@ static struct clk_rcg2 csi1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -484,7 +484,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gfx3d_clk_src",
> .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -511,7 +511,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe0_clk_src",
> .parent_names = gcc_xo_gpll0_gpll2,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -530,7 +530,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -559,7 +559,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -572,7 +572,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -586,7 +586,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -599,7 +599,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -613,7 +613,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -626,7 +626,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -640,7 +640,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -653,7 +653,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -667,7 +667,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -680,7 +680,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_i2c_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -694,7 +694,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_spi_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -727,7 +727,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart1_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -741,7 +741,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart2_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -760,7 +760,7 @@ static struct clk_rcg2 cci_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cci_clk_src",
> .parent_names = gcc_xo_gpll0a,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -780,7 +780,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp0_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -794,7 +794,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp1_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -814,7 +814,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg0_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -835,7 +835,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk0_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -849,7 +849,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk1_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -868,7 +868,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0phytimer_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -881,7 +881,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1phytimer_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -901,7 +901,7 @@ static struct clk_rcg2 cpp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cpp_clk_src",
> .parent_names = gcc_xo_gpll0_gpll2,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -922,7 +922,7 @@ static struct clk_rcg2 crypto_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "crypto_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -941,7 +941,7 @@ static struct clk_rcg2 gp1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp1_clk_src",
Starting here...
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -955,7 +955,7 @@ static struct clk_rcg2 gp2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp2_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -969,7 +969,7 @@ static struct clk_rcg2 gp3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp3_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
And ending here, note that this array and the corresponding _map contain
four items instead of 3, making this a semantic change. The last
member, `sleep_clk`, couldn't previously be selected here.
- Marijn
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -981,7 +981,7 @@ static struct clk_rcg2 byte0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte0_clk_src",
> .parent_names = gcc_xo_gpll0a_dsibyte,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -1000,7 +1000,7 @@ static struct clk_rcg2 esc0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc0_clk_src",
> .parent_names = gcc_xo_dsibyte,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1025,7 +1025,7 @@ static struct clk_rcg2 mdp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mdp_clk_src",
> .parent_names = gcc_xo_gpll0_dsiphy,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1038,7 +1038,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk0_clk_src",
> .parent_names = gcc_xo_gpll0a_dsiphy,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -1057,7 +1057,7 @@ static struct clk_rcg2 vsync_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vsync_clk_src",
> .parent_names = gcc_xo_gpll0a,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1075,7 +1075,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pdm2_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1100,7 +1100,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc1_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> };
> @@ -1125,7 +1125,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc2_apps_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> };
> @@ -1145,7 +1145,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "apss_tcu_clk_src",
> .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1168,7 +1168,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "bimc_gpu_clk_src",
> .parent_names = gcc_xo_gpll0_bimc,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .flags = CLK_GET_RATE_NOCACHE,
> .ops = &clk_rcg2_ops,
> },
> @@ -1187,7 +1187,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hs_system_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1213,7 +1213,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_ahbfabric_clk_src",
> .parent_names = gcc_xo_gpll0_gpll1_sleep,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1292,7 +1292,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_lpaif_pri_i2s_clk_src",
> .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1323,7 +1323,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_lpaif_sec_i2s_clk_src",
> .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1354,7 +1354,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_lpaif_aux_i2s_clk_src",
> .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1389,7 +1389,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_xo_clk_src",
> .parent_names = gcc_xo_sleep,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1445,7 +1445,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "codec_digcodec_clk_src",
> .parent_names = gcc_xo_gpll1_emclk_sleep,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1515,7 +1515,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vcodec0_clk_src",
> .parent_names = gcc_xo_gpll0,
> - .num_parents = 2,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -2771,7 +2771,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "bimc_ddr_clk_src",
> .parent_names = gcc_xo_gpll0_bimc,
> - .num_parents = 3,
> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .ops = &clk_rcg2_ops,
> .flags = CLK_GET_RATE_NOCACHE,
> },
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device
2022-06-19 21:27 ` [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device Dmitry Baryshkov
2022-06-20 12:06 ` Dmitry Baryshkov
@ 2022-06-27 21:09 ` Marijn Suijten
1 sibling, 0 replies; 21+ messages in thread
From: Marijn Suijten @ 2022-06-27 21:09 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 2022-06-20 00:27:30, Dmitry Baryshkov wrote:
> Separate bindings for GCC on Qualcomm MSM8916 platforms. This adds new
> clocks/clock-names properties to be used for clock links.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../bindings/clock/qcom,gcc-msm8916.yaml | 61 +++++++++++++++++++
> .../bindings/clock/qcom,gcc-other.yaml | 1 -
> 2 files changed, 61 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
> new file mode 100644
> index 000000000000..564aa764b17b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for MSM8916
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> + - Taniya Das <quic_tdas@quicinc.com>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on MSM8916.
> +
> + See also:
> + - dt-bindings/clock/qcom,gcc-msm8916.h
> +
> +properties:
> + compatible:
> + const: qcom,gcc-msm8916
> +
> + clocks:
> + items:
> + - description: XO source
> + - description: Sleep clock source
> + - description: DSI phy instance 0 dsi clock
> + - description: DSI phy instance 0 byte clock
> + - description: External MCLK clock
> + - description: External Primary I2S clock
> + - description: External Secondary I2S clock
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: sleep_clk
> + - const: dsi0pll
> + - const: dsi0pllbyte
> + - const: ext_mclk
> + - const: ext_pri_i2s
> + - const: ext_sec_i2s
> +
> +required:
> + - compatible
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + clock-controller@300000 {
> + compatible = "qcom,gcc-msm8916";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0x300000 0x90000>;
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> index 6c78df0c46a9..61b90e836b5b 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> @@ -41,7 +41,6 @@ properties:
> - qcom,gcc-mdm9607
> - qcom,gcc-msm8226
> - qcom,gcc-msm8660
> - - qcom,gcc-msm8916
> - qcom,gcc-msm8939
> - qcom,gcc-msm8953
> - qcom,gcc-msm8974
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml
2022-06-19 21:27 ` [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Dmitry Baryshkov
2022-06-20 12:05 ` Dmitry Baryshkov
@ 2022-06-27 21:11 ` Marijn Suijten
1 sibling, 0 replies; 21+ messages in thread
From: Marijn Suijten @ 2022-06-27 21:11 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 2022-06-20 00:27:29, Dmitry Baryshkov wrote:
> Use qcom,gcc.yaml which contains a set of properties common to most
> Qualcomm GCC bindings.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Nice cleanup!
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> .../bindings/clock/qcom,gcc-msm8976.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-msm8994.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-msm8996.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-msm8998.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sc7180.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sc7280.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sdm845.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sdx55.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sdx65.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sm6115.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm6125.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm6350.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm8150.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm8250.yaml | 25 +++----------------
> .../bindings/clock/qcom,gcc-sm8350.yaml | 21 +++-------------
> .../bindings/clock/qcom,gcc-sm8450.yaml | 21 +++-------------
> 19 files changed, 76 insertions(+), 367 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
> index f3430b159caa..4b7d69518371 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
> @@ -45,29 +45,16 @@ properties:
> description:
> Phandle to voltage regulator providing power to the GX domain.
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - - reg
> - clocks
> - clock-names
> - vdd_gfx-supply
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> index 22e67b238bb6..7b9fef6d9b23 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
> @@ -32,28 +32,15 @@ properties:
> - const: xo
> - const: sleep
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
> index 5a5b2214f0ca..70f7d3101bd3 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
> @@ -33,30 +33,13 @@ properties:
> - const: cxo2
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
> index 8151c0a05649..544a2335cf05 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
> @@ -37,32 +37,15 @@ properties:
> - const: core_bi_pll_test_se # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
> index 5de9c8263138..aec37e3f5e30 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
> @@ -30,32 +30,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
> index a404c8fbee67..e4d490e65d14 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
> @@ -33,32 +33,15 @@ properties:
> - const: bi_tcxo_ao
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> index 5693b8997570..ea61367e5abc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> @@ -44,28 +44,15 @@ properties:
> - const: ufs_phy_tx_symbol_0_clk
> - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
> index f03ef96e57fa..30b5d1215fa8 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
> @@ -32,32 +32,15 @@ properties:
> - const: bi_tcxo_ao
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> index 0bcdc69c6f89..e33dea86fb9e 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> @@ -56,30 +56,17 @@ properties:
> - description: First EMAC controller reference clock
> - description: Second EMAC controller reference clock
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> protected-clocks:
> maxItems: 389
>
> required:
> - compatible
> - clocks
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> index d902f137ab17..2b8a35d8739e 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
> @@ -37,30 +37,13 @@ properties:
> - const: pcie_0_pipe_clk
> - const: pcie_1_pipe_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> # Example for GCC for SDM845:
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
> index b0d1c65aa354..13ffa16e0833 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
> @@ -35,28 +35,15 @@ properties:
> - const: core_bi_pll_test_se # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
> index 16c4cdc7b4d6..8a1419c4d465 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
> @@ -20,9 +20,6 @@ properties:
> compatible:
> const: qcom,gcc-sdx65
>
> - reg:
> - maxItems: 1
> -
> clocks:
> items:
> - description: Board XO source
> @@ -43,25 +40,15 @@ properties:
> - const: core_bi_pll_test_se # Optional clock
> minItems: 5
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> required:
> - compatible
> - - reg
> - clocks
> - clock-names
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
> index 26050da844d5..bb81a27a1b16 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
> @@ -30,32 +30,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> index ab12b391effc..03e84e15815c 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> @@ -30,32 +30,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
> index 20926cd8293e..cbe98c01c085 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
> @@ -32,32 +32,15 @@ properties:
> - const: bi_tcxo_ao
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
> index 12766a866625..0333ccb07d8d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
> @@ -31,32 +31,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> index 80bd6caf5bc9..4e2a9cac0a91 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
> @@ -31,32 +31,15 @@ properties:
> - const: bi_tcxo
> - const: sleep_clk
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> - protected-clocks:
> - description:
> - Protected clock specifier list as per common clock binding.
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> index 1122700dcc2b..3edbeca70a9c 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
> @@ -54,28 +54,15 @@ properties:
> - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - clocks
> - clock-names
> - - reg
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> index 58d98a766de6..102ce6862e24 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> @@ -46,28 +46,15 @@ properties:
> - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
> minItems: 2
>
> - '#clock-cells':
> - const: 1
> -
> - '#reset-cells':
> - const: 1
> -
> - '#power-domain-cells':
> - const: 1
> -
> - reg:
> - maxItems: 1
> -
> required:
> - compatible
> - - reg
> - clocks
> - clock-names
> - - '#clock-cells'
> - - '#reset-cells'
> - - '#power-domain-cells'
>
> -additionalProperties: false
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +unevaluatedProperties: false
>
> examples:
> - |
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down
2022-06-19 21:27 ` [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down Dmitry Baryshkov
@ 2022-06-27 21:18 ` Marijn Suijten
2022-06-28 12:40 ` Dmitry Baryshkov
0 siblings, 1 reply; 21+ messages in thread
From: Marijn Suijten @ 2022-06-27 21:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 2022-06-20 00:27:33, Dmitry Baryshkov wrote:
> The gcc_mss_q6_bimc_axi_clk clock depends on the bimc_ddr_clk_src clock.
> Move it down in the file to come after the source clock.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/clk/qcom/gcc-msm8916.c | 34 +++++++++++++++++-----------------
> 1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
> index 7962edbdbcf6..4d726ca4b0da 100644
> --- a/drivers/clk/qcom/gcc-msm8916.c
> +++ b/drivers/clk/qcom/gcc-msm8916.c
> @@ -2594,23 +2594,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
> },
> };
>
> -static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> - .halt_reg = 0x49004,
> - .clkr = {
> - .enable_reg = 0x49004,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "gcc_mss_q6_bimc_axi_clk",
> - .parent_names = (const char *[]){
> - "bimc_ddr_clk_src",
> - },
> - .num_parents = 1,
> - .flags = CLK_SET_RATE_PARENT,
> - .ops = &clk_branch2_ops,
> - },
> - },
> -};
> -
> static struct clk_branch gcc_oxili_ahb_clk = {
> .halt_reg = 0x59028,
> .clkr = {
> @@ -2860,6 +2843,23 @@ static struct clk_branch gcc_bimc_gpu_clk = {
> },
> };
>
> +static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
How'd you settle on placing it here? It isn't right below
bimc_ddr_clk_src, nor the last user of bimc_ddr_clk_src, doesn't seem to
have any alphabetical or .enable_reg related ordering to the other clks
either?
> + .halt_reg = 0x49004,
> + .clkr = {
> + .enable_reg = 0x49004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mss_q6_bimc_axi_clk",
> + .parent_names = (const char *[]){
> + "bimc_ddr_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static struct clk_branch gcc_jpeg_tbu_clk = {
> .halt_reg = 0x12034,
> .clkr = {
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 6/7] clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names
2022-06-19 21:27 ` [PATCH v3 6/7] clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-06-27 21:28 ` Marijn Suijten
0 siblings, 0 replies; 21+ messages in thread
From: Marijn Suijten @ 2022-06-27 21:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 2022-06-20 00:27:34, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/clk/qcom/gcc-msm8916.c | 682 +++++++++++++++++----------------
> 1 file changed, 349 insertions(+), 333 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
> index 4d726ca4b0da..148dbbf7cecc 100644
> --- a/drivers/clk/qcom/gcc-msm8916.c
> +++ b/drivers/clk/qcom/gcc-msm8916.c
> @@ -52,7 +52,9 @@ static struct clk_pll gpll0 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll0",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -63,7 +65,9 @@ static struct clk_regmap gpll0_vote = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gpll0_vote",
> - .parent_names = (const char *[]){ "gpll0" },
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll0.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -79,7 +83,9 @@ static struct clk_pll gpll1 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll1",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -90,7 +96,9 @@ static struct clk_regmap gpll1_vote = {
> .enable_mask = BIT(1),
> .hw.init = &(struct clk_init_data){
> .name = "gpll1_vote",
> - .parent_names = (const char *[]){ "gpll1" },
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll1.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -106,7 +114,9 @@ static struct clk_pll gpll2 = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gpll2",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -117,7 +127,9 @@ static struct clk_regmap gpll2_vote = {
> .enable_mask = BIT(2),
> .hw.init = &(struct clk_init_data){
> .name = "gpll2_vote",
> - .parent_names = (const char *[]){ "gpll2" },
> + .parent_hws = (const struct clk_hw*[]){
> + &gpll2.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -133,7 +145,9 @@ static struct clk_pll bimc_pll = {
> .status_bit = 17,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "bimc_pll",
> - .parent_names = (const char *[]){ "xo" },
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo", .name = "xo_board",
> + },
> .num_parents = 1,
> .ops = &clk_pll_ops,
> },
> @@ -144,7 +158,9 @@ static struct clk_regmap bimc_pll_vote = {
> .enable_mask = BIT(3),
> .hw.init = &(struct clk_init_data){
> .name = "bimc_pll_vote",
> - .parent_names = (const char *[]){ "bimc_pll" },
> + .parent_hws = (const struct clk_hw*[]){
> + &bimc_pll.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_pll_vote_ops,
> },
> @@ -155,9 +171,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
> { P_GPLL0, 1 },
> };
>
> -static const char * const gcc_xo_gpll0[] = {
> - "xo",
> - "gpll0_vote",
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
> @@ -166,10 +182,10 @@ static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
> { P_BIMC, 2 },
> };
>
> -static const char * const gcc_xo_gpll0_bimc[] = {
> - "xo",
> - "gpll0_vote",
> - "bimc_pll_vote",
> +static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &bimc_pll_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
> @@ -179,11 +195,11 @@ static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
> { P_GPLL2_AUX, 2 },
> };
>
> -static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll1_vote",
> - "gpll2_vote",
> +static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2a[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll1_vote.hw },
> + { .hw = &gpll2_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
> @@ -192,10 +208,10 @@ static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
> { P_GPLL2, 2 },
> };
>
> -static const char * const gcc_xo_gpll0_gpll2[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll2_vote",
> +static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll2_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0a_map[] = {
> @@ -203,9 +219,9 @@ static const struct parent_map gcc_xo_gpll0a_map[] = {
> { P_GPLL0_AUX, 2 },
> };
>
> -static const char * const gcc_xo_gpll0a[] = {
> - "xo",
> - "gpll0_vote",
> +static const struct clk_parent_data gcc_xo_gpll0a[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
> @@ -215,11 +231,11 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
> { P_SLEEP_CLK, 6 },
> };
>
> -static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll1_vote",
> - "sleep_clk",
> +static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll1_vote.hw },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
> @@ -228,10 +244,10 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
> { P_GPLL1_AUX, 2 },
> };
>
> -static const char * const gcc_xo_gpll0_gpll1a[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll1_vote",
> +static const struct clk_parent_data gcc_xo_gpll0_gpll1a[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll1_vote.hw },
> };
>
> static const struct parent_map gcc_xo_dsibyte_map[] = {
> @@ -239,9 +255,9 @@ static const struct parent_map gcc_xo_dsibyte_map[] = {
> { P_DSI0_PHYPLL_BYTE, 2 },
> };
>
> -static const char * const gcc_xo_dsibyte[] = {
> - "xo",
> - "dsi0pllbyte",
> +static const struct clk_parent_data gcc_xo_dsibyte[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
> };
>
> static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
> @@ -250,10 +266,10 @@ static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
> { P_DSI0_PHYPLL_BYTE, 1 },
> };
>
> -static const char * const gcc_xo_gpll0a_dsibyte[] = {
> - "xo",
> - "gpll0_vote",
> - "dsi0pllbyte",
> +static const struct clk_parent_data gcc_xo_gpll0a_dsibyte[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
> };
>
> static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
> @@ -262,10 +278,10 @@ static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
> { P_DSI0_PHYPLL_DSI, 2 },
> };
>
> -static const char * const gcc_xo_gpll0_dsiphy[] = {
> - "xo",
> - "gpll0_vote",
> - "dsi0pll",
> +static const struct clk_parent_data gcc_xo_gpll0_dsiphy[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .fw_name = "dsi0pll", .name = "dsi0pll" },
> };
>
> static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
> @@ -274,10 +290,10 @@ static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
> { P_DSI0_PHYPLL_DSI, 1 },
> };
>
> -static const char * const gcc_xo_gpll0a_dsiphy[] = {
> - "xo",
> - "gpll0_vote",
> - "dsi0pll",
> +static const struct clk_parent_data gcc_xo_gpll0a_dsiphy[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .fw_name = "dsi0pll", .name = "dsi0pll" },
> };
>
> static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
> @@ -287,11 +303,11 @@ static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
> { P_GPLL2, 2 },
> };
>
> -static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll1_vote",
> - "gpll2_vote",
> +static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll1_vote.hw },
> + { .hw = &gpll2_vote.hw },
> };
>
> static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
> @@ -301,11 +317,11 @@ static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
> { P_SLEEP_CLK, 6 }
> };
>
> -static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
> - "xo",
> - "gpll0_vote",
> - "gpll1_vote",
> - "sleep_clk",
> +static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll0_vote.hw },
> + { .hw = &gpll1_vote.hw },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
> @@ -316,12 +332,12 @@ static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
> { P_SLEEP_CLK, 6 }
> };
>
> -static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
> - "xo",
> - "gpll1_vote",
> - "ext_pri_i2s",
> - "ext_mclk",
> - "sleep_clk",
> +static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll1_vote.hw },
> + { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
> + { .fw_name = "ext_mclk", .name = "ext_mclk" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
> @@ -332,12 +348,12 @@ static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
> { P_SLEEP_CLK, 6 }
> };
>
> -static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
> - "xo",
> - "gpll1_vote",
> - "ext_sec_i2s",
> - "ext_mclk",
> - "sleep_clk",
> +static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll1_vote.hw },
> + { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
> + { .fw_name = "ext_mclk", .name = "ext_mclk" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static const struct parent_map gcc_xo_sleep_map[] = {
> @@ -345,9 +361,9 @@ static const struct parent_map gcc_xo_sleep_map[] = {
> { P_SLEEP_CLK, 6 }
> };
>
> -static const char * const gcc_xo_sleep[] = {
> - "xo",
> - "sleep_clk",
> +static const struct clk_parent_data gcc_xo_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
> @@ -357,11 +373,11 @@ static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
> { P_SLEEP_CLK, 6 }
> };
>
> -static const char * const gcc_xo_gpll1_emclk_sleep[] = {
> - "xo",
> - "gpll1_vote",
> - "ext_mclk",
> - "sleep_clk",
> +static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep[] = {
> + { .fw_name = "xo", .name = "xo_board" },
> + { .hw = &gpll1_vote.hw },
> + { .fw_name = "ext_mclk", .name = "ext_mclk" },
> + { .fw_name = "sleep_clk", .name = "sleep_clk" },
> };
>
> static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> @@ -370,7 +386,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> .parent_map = gcc_xo_gpll0_bimc_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pcnoc_bfdcd_clk_src",
> - .parent_names = gcc_xo_gpll0_bimc,
> + .parent_data = gcc_xo_gpll0_bimc,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .ops = &clk_rcg2_ops,
> },
> @@ -382,7 +398,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
> .parent_map = gcc_xo_gpll0_bimc_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "system_noc_bfdcd_clk_src",
> - .parent_names = gcc_xo_gpll0_bimc,
> + .parent_data = gcc_xo_gpll0_bimc,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .ops = &clk_rcg2_ops,
> },
> @@ -402,7 +418,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
> .freq_tbl = ftbl_gcc_camss_ahb_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_ahb_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -423,7 +439,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
> .freq_tbl = ftbl_apss_ahb_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "apss_ahb_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -442,7 +458,7 @@ static struct clk_rcg2 csi0_clk_src = {
> .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -455,7 +471,7 @@ static struct clk_rcg2 csi1_clk_src = {
> .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -483,7 +499,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
> .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gfx3d_clk_src",
> - .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
> + .parent_data = gcc_xo_gpll0a_gpll1_gpll2a,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
> .ops = &clk_rcg2_ops,
> },
> @@ -510,7 +526,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> .freq_tbl = ftbl_gcc_camss_vfe0_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe0_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll2,
> + .parent_data = gcc_xo_gpll0_gpll2,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> .ops = &clk_rcg2_ops,
> },
> @@ -529,7 +545,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -558,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup1_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -571,7 +587,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -585,7 +601,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup2_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -598,7 +614,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -612,7 +628,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup3_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -625,7 +641,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -639,7 +655,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup4_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -652,7 +668,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -666,7 +682,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup5_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -679,7 +695,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_i2c_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -693,7 +709,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_qup6_spi_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -726,7 +742,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -740,7 +756,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "blsp1_uart2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -759,7 +775,7 @@ static struct clk_rcg2 cci_clk_src = {
> .freq_tbl = ftbl_gcc_camss_cci_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cci_clk_src",
> - .parent_names = gcc_xo_gpll0a,
> + .parent_data = gcc_xo_gpll0a,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
> .ops = &clk_rcg2_ops,
> },
> @@ -779,7 +795,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp0_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -793,7 +809,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp1_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -813,7 +829,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg0_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -834,7 +850,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk0_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -848,7 +864,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk1_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -867,7 +883,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0phytimer_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a,
> + .parent_data = gcc_xo_gpll0_gpll1a,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
> .ops = &clk_rcg2_ops,
> },
> @@ -880,7 +896,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1phytimer_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a,
> + .parent_data = gcc_xo_gpll0_gpll1a,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
> .ops = &clk_rcg2_ops,
> },
> @@ -900,7 +916,7 @@ static struct clk_rcg2 cpp_clk_src = {
> .freq_tbl = ftbl_gcc_camss_cpp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cpp_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll2,
> + .parent_data = gcc_xo_gpll0_gpll2,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> .ops = &clk_rcg2_ops,
> },
> @@ -921,7 +937,7 @@ static struct clk_rcg2 crypto_clk_src = {
> .freq_tbl = ftbl_gcc_crypto_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "crypto_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -940,7 +956,7 @@ static struct clk_rcg2 gp1_clk_src = {
> .freq_tbl = ftbl_gcc_gp1_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp1_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -954,7 +970,7 @@ static struct clk_rcg2 gp2_clk_src = {
> .freq_tbl = ftbl_gcc_gp1_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp2_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -968,7 +984,7 @@ static struct clk_rcg2 gp3_clk_src = {
> .freq_tbl = ftbl_gcc_gp1_3_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gp3_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1a_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1a_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -980,7 +996,7 @@ static struct clk_rcg2 byte0_clk_src = {
> .parent_map = gcc_xo_gpll0a_dsibyte_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte0_clk_src",
> - .parent_names = gcc_xo_gpll0a_dsibyte,
> + .parent_data = gcc_xo_gpll0a_dsibyte,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -999,7 +1015,7 @@ static struct clk_rcg2 esc0_clk_src = {
> .freq_tbl = ftbl_gcc_mdss_esc0_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc0_clk_src",
> - .parent_names = gcc_xo_dsibyte,
> + .parent_data = gcc_xo_dsibyte,
> .num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
> .ops = &clk_rcg2_ops,
> },
> @@ -1024,7 +1040,7 @@ static struct clk_rcg2 mdp_clk_src = {
> .freq_tbl = ftbl_gcc_mdss_mdp_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mdp_clk_src",
> - .parent_names = gcc_xo_gpll0_dsiphy,
> + .parent_data = gcc_xo_gpll0_dsiphy,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
> .ops = &clk_rcg2_ops,
> },
> @@ -1037,7 +1053,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> .parent_map = gcc_xo_gpll0a_dsiphy_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk0_clk_src",
> - .parent_names = gcc_xo_gpll0a_dsiphy,
> + .parent_data = gcc_xo_gpll0a_dsiphy,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1056,7 +1072,7 @@ static struct clk_rcg2 vsync_clk_src = {
> .freq_tbl = ftbl_gcc_mdss_vsync_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vsync_clk_src",
> - .parent_names = gcc_xo_gpll0a,
> + .parent_data = gcc_xo_gpll0a,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
> .ops = &clk_rcg2_ops,
> },
> @@ -1074,7 +1090,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> .freq_tbl = ftbl_gcc_pdm2_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pdm2_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1099,7 +1115,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc1_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -1124,7 +1140,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "sdcc2_apps_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_floor_ops,
> },
> @@ -1144,7 +1160,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
> .freq_tbl = ftbl_gcc_apss_tcu_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "apss_tcu_clk_src",
> - .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
> + .parent_data = gcc_xo_gpll0a_gpll1_gpll2,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
> .ops = &clk_rcg2_ops,
> },
> @@ -1167,7 +1183,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
> .freq_tbl = ftbl_gcc_bimc_gpu_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "bimc_gpu_clk_src",
> - .parent_names = gcc_xo_gpll0_bimc,
> + .parent_data = gcc_xo_gpll0_bimc,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .flags = CLK_GET_RATE_NOCACHE,
> .ops = &clk_rcg2_ops,
> @@ -1186,7 +1202,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
> .freq_tbl = ftbl_gcc_usb_hs_system_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "usb_hs_system_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1212,7 +1228,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
> .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_ahbfabric_clk_src",
> - .parent_names = gcc_xo_gpll0_gpll1_sleep,
> + .parent_data = gcc_xo_gpll0_gpll1_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -1225,8 +1241,8 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_ahbfabric_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_ahbfabric_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1242,8 +1258,8 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_ahbfabric_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_ahbfabric_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1291,7 +1307,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
> .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_lpaif_pri_i2s_clk_src",
> - .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
> + .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -1304,8 +1320,8 @@ static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_lpaif_pri_i2s_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1322,7 +1338,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
> .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_lpaif_sec_i2s_clk_src",
> - .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
> + .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -1335,8 +1351,8 @@ static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_lpaif_sec_i2s_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1353,7 +1369,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
> .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_lpaif_aux_i2s_clk_src",
> - .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
> + .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -1366,8 +1382,8 @@ static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_lpaif_aux_i2s_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1388,7 +1404,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
> .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ultaudio_xo_clk_src",
> - .parent_names = gcc_xo_sleep,
> + .parent_data = gcc_xo_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -1401,8 +1417,8 @@ static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_avsync_xo_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_xo_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_xo_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1418,8 +1434,8 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_stc_xo_clk",
> - .parent_names = (const char *[]){
> - "ultaudio_xo_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &ultaudio_xo_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1444,7 +1460,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
> .freq_tbl = ftbl_codec_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "codec_digcodec_clk_src",
> - .parent_names = gcc_xo_gpll1_emclk_sleep,
> + .parent_data = gcc_xo_gpll1_emclk_sleep,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
> .ops = &clk_rcg2_ops,
> },
> @@ -1457,8 +1473,8 @@ static struct clk_branch gcc_codec_digcodec_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_codec_digcodec_clk",
> - .parent_names = (const char *[]){
> - "codec_digcodec_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &codec_digcodec_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1474,8 +1490,8 @@ static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_pcnoc_mport_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1490,8 +1506,8 @@ static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_ultaudio_pcnoc_sway_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1514,7 +1530,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vcodec0_clk_src",
> - .parent_names = gcc_xo_gpll0,
> + .parent_data = gcc_xo_gpll0,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> .ops = &clk_rcg2_ops,
> },
> @@ -1528,8 +1544,8 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
> .enable_mask = BIT(10),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1544,8 +1560,8 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk_src",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1561,8 +1577,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup1_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup1_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1578,8 +1594,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup1_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup1_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup1_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1595,8 +1611,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup2_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup2_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1612,8 +1628,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup2_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup2_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup2_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1629,8 +1645,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup3_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup3_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1646,8 +1662,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup3_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup3_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup3_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1663,8 +1679,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup4_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup4_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1680,8 +1696,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup4_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup4_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup4_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1697,8 +1713,8 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup5_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup5_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1714,8 +1730,8 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup5_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup5_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup5_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1731,8 +1747,8 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup6_i2c_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup6_i2c_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1748,8 +1764,8 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_qup6_spi_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_qup6_spi_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_qup6_spi_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1765,8 +1781,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart1_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart1_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart1_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1782,8 +1798,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_blsp1_uart2_apps_clk",
> - .parent_names = (const char *[]){
> - "blsp1_uart2_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &blsp1_uart2_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1800,8 +1816,8 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
> .enable_mask = BIT(7),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_boot_rom_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -1816,8 +1832,8 @@ static struct clk_branch gcc_camss_cci_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_cci_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1833,8 +1849,8 @@ static struct clk_branch gcc_camss_cci_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_cci_clk",
> - .parent_names = (const char *[]){
> - "cci_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &cci_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1850,8 +1866,8 @@ static struct clk_branch gcc_camss_csi0_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi0_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1867,8 +1883,8 @@ static struct clk_branch gcc_camss_csi0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi0_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1884,8 +1900,8 @@ static struct clk_branch gcc_camss_csi0phy_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi0phy_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1901,8 +1917,8 @@ static struct clk_branch gcc_camss_csi0pix_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi0pix_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1918,8 +1934,8 @@ static struct clk_branch gcc_camss_csi0rdi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi0rdi_clk",
> - .parent_names = (const char *[]){
> - "csi0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1935,8 +1951,8 @@ static struct clk_branch gcc_camss_csi1_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi1_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1952,8 +1968,8 @@ static struct clk_branch gcc_camss_csi1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi1_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1969,8 +1985,8 @@ static struct clk_branch gcc_camss_csi1phy_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi1phy_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1986,8 +2002,8 @@ static struct clk_branch gcc_camss_csi1pix_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi1pix_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2003,8 +2019,8 @@ static struct clk_branch gcc_camss_csi1rdi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi1rdi_clk",
> - .parent_names = (const char *[]){
> - "csi1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2020,8 +2036,8 @@ static struct clk_branch gcc_camss_csi_vfe0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi_vfe0_clk",
> - .parent_names = (const char *[]){
> - "vfe0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vfe0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2037,8 +2053,8 @@ static struct clk_branch gcc_camss_gp0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_gp0_clk",
> - .parent_names = (const char *[]){
> - "camss_gp0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_gp0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2054,8 +2070,8 @@ static struct clk_branch gcc_camss_gp1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_gp1_clk",
> - .parent_names = (const char *[]){
> - "camss_gp1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_gp1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2071,8 +2087,8 @@ static struct clk_branch gcc_camss_ispif_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_ispif_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2088,8 +2104,8 @@ static struct clk_branch gcc_camss_jpeg0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_jpeg0_clk",
> - .parent_names = (const char *[]){
> - "jpeg0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &jpeg0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2105,8 +2121,8 @@ static struct clk_branch gcc_camss_jpeg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_jpeg_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2122,8 +2138,8 @@ static struct clk_branch gcc_camss_jpeg_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_jpeg_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2139,8 +2155,8 @@ static struct clk_branch gcc_camss_mclk0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_mclk0_clk",
> - .parent_names = (const char *[]){
> - "mclk0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mclk0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2156,8 +2172,8 @@ static struct clk_branch gcc_camss_mclk1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_mclk1_clk",
> - .parent_names = (const char *[]){
> - "mclk1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mclk1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2173,8 +2189,8 @@ static struct clk_branch gcc_camss_micro_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_micro_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2190,8 +2206,8 @@ static struct clk_branch gcc_camss_csi0phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi0phytimer_clk",
> - .parent_names = (const char *[]){
> - "csi0phytimer_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi0phytimer_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2207,8 +2223,8 @@ static struct clk_branch gcc_camss_csi1phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_csi1phytimer_clk",
> - .parent_names = (const char *[]){
> - "csi1phytimer_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &csi1phytimer_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2224,8 +2240,8 @@ static struct clk_branch gcc_camss_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2241,8 +2257,8 @@ static struct clk_branch gcc_camss_top_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_top_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2258,8 +2274,8 @@ static struct clk_branch gcc_camss_cpp_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_cpp_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2275,8 +2291,8 @@ static struct clk_branch gcc_camss_cpp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_cpp_clk",
> - .parent_names = (const char *[]){
> - "cpp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &cpp_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2292,8 +2308,8 @@ static struct clk_branch gcc_camss_vfe0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_vfe0_clk",
> - .parent_names = (const char *[]){
> - "vfe0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vfe0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2309,8 +2325,8 @@ static struct clk_branch gcc_camss_vfe_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_vfe_ahb_clk",
> - .parent_names = (const char *[]){
> - "camss_ahb_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &camss_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2326,8 +2342,8 @@ static struct clk_branch gcc_camss_vfe_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_camss_vfe_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2344,8 +2360,8 @@ static struct clk_branch gcc_crypto_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_crypto_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2362,8 +2378,8 @@ static struct clk_branch gcc_crypto_axi_clk = {
> .enable_mask = BIT(1),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_crypto_axi_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2380,8 +2396,8 @@ static struct clk_branch gcc_crypto_clk = {
> .enable_mask = BIT(2),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_crypto_clk",
> - .parent_names = (const char *[]){
> - "crypto_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &crypto_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2397,8 +2413,8 @@ static struct clk_branch gcc_oxili_gmem_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_oxili_gmem_clk",
> - .parent_names = (const char *[]){
> - "gfx3d_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gfx3d_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2414,8 +2430,8 @@ static struct clk_branch gcc_gp1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gp1_clk",
> - .parent_names = (const char *[]){
> - "gp1_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gp1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2431,8 +2447,8 @@ static struct clk_branch gcc_gp2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gp2_clk",
> - .parent_names = (const char *[]){
> - "gp2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gp2_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2448,8 +2464,8 @@ static struct clk_branch gcc_gp3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gp3_clk",
> - .parent_names = (const char *[]){
> - "gp3_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gp3_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2465,8 +2481,8 @@ static struct clk_branch gcc_mdss_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2482,8 +2498,8 @@ static struct clk_branch gcc_mdss_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2499,8 +2515,8 @@ static struct clk_branch gcc_mdss_byte0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_byte0_clk",
> - .parent_names = (const char *[]){
> - "byte0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &byte0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2516,8 +2532,8 @@ static struct clk_branch gcc_mdss_esc0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_esc0_clk",
> - .parent_names = (const char *[]){
> - "esc0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &esc0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2533,8 +2549,8 @@ static struct clk_branch gcc_mdss_mdp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_mdp_clk",
> - .parent_names = (const char *[]){
> - "mdp_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &mdp_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2550,8 +2566,8 @@ static struct clk_branch gcc_mdss_pclk0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_pclk0_clk",
> - .parent_names = (const char *[]){
> - "pclk0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pclk0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2567,8 +2583,8 @@ static struct clk_branch gcc_mdss_vsync_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdss_vsync_clk",
> - .parent_names = (const char *[]){
> - "vsync_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vsync_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2584,8 +2600,8 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mss_cfg_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2601,8 +2617,8 @@ static struct clk_branch gcc_oxili_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_oxili_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2618,8 +2634,8 @@ static struct clk_branch gcc_oxili_gfx3d_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_oxili_gfx3d_clk",
> - .parent_names = (const char *[]){
> - "gfx3d_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gfx3d_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2635,8 +2651,8 @@ static struct clk_branch gcc_pdm2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pdm2_clk",
> - .parent_names = (const char *[]){
> - "pdm2_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pdm2_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2652,8 +2668,8 @@ static struct clk_branch gcc_pdm_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pdm_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2670,8 +2686,8 @@ static struct clk_branch gcc_prng_ahb_clk = {
> .enable_mask = BIT(8),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_prng_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2686,8 +2702,8 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2703,8 +2719,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc1_apps_clk",
> - .parent_names = (const char *[]){
> - "sdcc1_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sdcc1_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2720,8 +2736,8 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc2_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2737,8 +2753,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_sdcc2_apps_clk",
> - .parent_names = (const char *[]){
> - "sdcc2_apps_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &sdcc2_apps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2753,7 +2769,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
> .parent_map = gcc_xo_gpll0_bimc_map,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "bimc_ddr_clk_src",
> - .parent_names = gcc_xo_gpll0_bimc,
> + .parent_data = gcc_xo_gpll0_bimc,
> .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> .ops = &clk_rcg2_ops,
> .flags = CLK_GET_RATE_NOCACHE,
> @@ -2767,8 +2783,8 @@ static struct clk_branch gcc_apss_tcu_clk = {
> .enable_mask = BIT(1),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_apss_tcu_clk",
> - .parent_names = (const char *[]){
> - "bimc_ddr_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &bimc_ddr_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2783,8 +2799,8 @@ static struct clk_branch gcc_gfx_tcu_clk = {
> .enable_mask = BIT(2),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gfx_tcu_clk",
> - .parent_names = (const char *[]){
> - "bimc_ddr_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &bimc_ddr_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .ops = &clk_branch2_ops,
> @@ -2799,8 +2815,8 @@ static struct clk_branch gcc_gtcu_ahb_clk = {
> .enable_mask = BIT(13),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_gtcu_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2816,8 +2832,8 @@ static struct clk_branch gcc_bimc_gfx_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_bimc_gfx_clk",
> - .parent_names = (const char *[]){
> - "bimc_gpu_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &bimc_gpu_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2833,8 +2849,8 @@ static struct clk_branch gcc_bimc_gpu_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_bimc_gpu_clk",
> - .parent_names = (const char *[]){
> - "bimc_gpu_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &bimc_gpu_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2850,8 +2866,8 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mss_q6_bimc_axi_clk",
> - .parent_names = (const char *[]){
> - "bimc_ddr_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &bimc_ddr_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2867,8 +2883,8 @@ static struct clk_branch gcc_jpeg_tbu_clk = {
> .enable_mask = BIT(10),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_jpeg_tbu_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2884,8 +2900,8 @@ static struct clk_branch gcc_mdp_tbu_clk = {
> .enable_mask = BIT(4),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_mdp_tbu_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2901,8 +2917,8 @@ static struct clk_branch gcc_smmu_cfg_clk = {
> .enable_mask = BIT(12),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_smmu_cfg_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2918,8 +2934,8 @@ static struct clk_branch gcc_venus_tbu_clk = {
> .enable_mask = BIT(5),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_venus_tbu_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2935,8 +2951,8 @@ static struct clk_branch gcc_vfe_tbu_clk = {
> .enable_mask = BIT(9),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_vfe_tbu_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2952,8 +2968,8 @@ static struct clk_branch gcc_usb2a_phy_sleep_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb2a_phy_sleep_clk",
> - .parent_names = (const char *[]){
> - "sleep_clk_src",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "sleep_clk", .name = "sleep_clk_src",
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2969,8 +2985,8 @@ static struct clk_branch gcc_usb_hs_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -2986,8 +3002,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_usb_hs_system_clk",
> - .parent_names = (const char *[]){
> - "usb_hs_system_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &usb_hs_system_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3003,8 +3019,8 @@ static struct clk_branch gcc_venus0_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_venus0_ahb_clk",
> - .parent_names = (const char *[]){
> - "pcnoc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &pcnoc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3020,8 +3036,8 @@ static struct clk_branch gcc_venus0_axi_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_venus0_axi_clk",
> - .parent_names = (const char *[]){
> - "system_noc_bfdcd_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &system_noc_bfdcd_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -3037,8 +3053,8 @@ static struct clk_branch gcc_venus0_vcodec0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "gcc_venus0_vcodec0_clk",
> - .parent_names = (const char *[]){
> - "vcodec0_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &vcodec0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node
2022-06-19 21:27 ` [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node Dmitry Baryshkov
2022-06-20 12:13 ` Konrad Dybcio
@ 2022-06-27 21:29 ` Marijn Suijten
1 sibling, 0 replies; 21+ messages in thread
From: Marijn Suijten @ 2022-06-27 21:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 2022-06-20 00:27:35, Dmitry Baryshkov wrote:
> As we are converting this platform to use DT clock bindings, add clocks
> and clock-names properties to the MMCC device tree node.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 05472510e29d..562c42ce2c5c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -934,6 +934,20 @@ gcc: clock-controller@1800000 {
> #reset-cells = <1>;
> #power-domain-cells = <1>;
> reg = <0x01800000 0x80000>;
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <&dsi_phy0 1>,
> + <&dsi_phy0 0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "xo",
> + "sleep_clk",
> + "dsi0pll",
> + "dsi0pllbyte",
> + "ext_mclk",
> + "ext_pri_i2s",
> + "ext_sec_i2s";
> };
>
> tcsr_mutex: hwlock@1905000 {
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down
2022-06-27 21:18 ` Marijn Suijten
@ 2022-06-28 12:40 ` Dmitry Baryshkov
0 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-06-28 12:40 UTC (permalink / raw)
To: Marijn Suijten
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 28/06/2022 00:18, Marijn Suijten wrote:
> On 2022-06-20 00:27:33, Dmitry Baryshkov wrote:
>> The gcc_mss_q6_bimc_axi_clk clock depends on the bimc_ddr_clk_src clock.
>> Move it down in the file to come after the source clock.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
>> ---
>> drivers/clk/qcom/gcc-msm8916.c | 34 +++++++++++++++++-----------------
>> 1 file changed, 17 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
>> index 7962edbdbcf6..4d726ca4b0da 100644
>> --- a/drivers/clk/qcom/gcc-msm8916.c
>> +++ b/drivers/clk/qcom/gcc-msm8916.c
>> @@ -2594,23 +2594,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
>> },
>> };
>>
>> -static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
>> - .halt_reg = 0x49004,
>> - .clkr = {
>> - .enable_reg = 0x49004,
>> - .enable_mask = BIT(0),
>> - .hw.init = &(struct clk_init_data){
>> - .name = "gcc_mss_q6_bimc_axi_clk",
>> - .parent_names = (const char *[]){
>> - "bimc_ddr_clk_src",
>> - },
>> - .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT,
>> - .ops = &clk_branch2_ops,
>> - },
>> - },
>> -};
>> -
>> static struct clk_branch gcc_oxili_ahb_clk = {
>> .halt_reg = 0x59028,
>> .clkr = {
>> @@ -2860,6 +2843,23 @@ static struct clk_branch gcc_bimc_gpu_clk = {
>> },
>> };
>>
>> +static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
>
> How'd you settle on placing it here? It isn't right below
> bimc_ddr_clk_src, nor the last user of bimc_ddr_clk_src, doesn't seem to
> have any alphabetical or .enable_reg related ordering to the other clks
> either?
Hmm, I was looking for the last bimc_ddr_clk_src user. Let's see if I
can find a better place then.
>
>> + .halt_reg = 0x49004,
>> + .clkr = {
>> + .enable_reg = 0x49004,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_mss_q6_bimc_axi_clk",
>> + .parent_names = (const char *[]){
>> + "bimc_ddr_clk_src",
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static struct clk_branch gcc_jpeg_tbu_clk = {
>> .halt_reg = 0x12034,
>> .clkr = {
>> --
>> 2.35.1
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver
2022-06-20 12:12 ` [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Konrad Dybcio
@ 2022-07-04 16:24 ` Dmitry Baryshkov
0 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 16:24 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Marijn Suijten
On 20/06/2022 15:12, Konrad Dybcio wrote:
>
>
> On 19.06.2022 23:27, Dmitry Baryshkov wrote:
>> Please excuse me for the spam, I've erroneously sent v2 without the
>> requested change.
>>
> Please excuse me, I didn't notice and gave you R-bs on v2 instead..
N/p, I'll pick them while sending v4.
>
> Konrad
>> Update gcc-msm8916 driver and bindings to use DT-specified clocks
>> rather than fetching the clocks from the global clocks list.
>>
>> Changes since v2:
>> - Use xo-board for the XO rather than RPM clock. This will be sorted
>> out separately (requested by Stephan Gerhold).
>>
>> Changes since v1:
>> - None.
>>
>> Dmitry Baryshkov (7):
>> dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml
>> dt-bindings: clock: separate bindings for MSM8916 GCC device
>> clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying
>> num_parents
>> clk: qcom: gcc-msm8916: move clock parent tables down
>> clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down
>> clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names
>> arm64: dts: qcom: msm8916: add clocks to the GCC device node
>>
>> .../bindings/clock/qcom,gcc-msm8916.yaml | 61 +
>> .../bindings/clock/qcom,gcc-msm8976.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-msm8994.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-msm8996.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-msm8998.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-other.yaml | 1 -
>> .../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sc7180.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sc7280.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-sdm845.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sdx55.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-sdx65.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-sm6115.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sm6125.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sm6350.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sm8150.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sm8250.yaml | 25 +-
>> .../bindings/clock/qcom,gcc-sm8350.yaml | 21 +-
>> .../bindings/clock/qcom,gcc-sm8450.yaml | 21 +-
>> arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 +
>> drivers/clk/qcom/gcc-msm8916.c | 1020 +++++++++--------
>> 23 files changed, 669 insertions(+), 870 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents
2022-06-27 21:03 ` Marijn Suijten
@ 2022-07-04 17:12 ` Dmitry Baryshkov
0 siblings, 0 replies; 21+ messages in thread
From: Dmitry Baryshkov @ 2022-07-04 17:12 UTC (permalink / raw)
To: Marijn Suijten
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski, Taniya Das, linux-arm-msm,
linux-clk, devicetree, Konrad Dybcio
On 28/06/2022 00:03, Marijn Suijten wrote:
> On 2022-06-20 00:27:31, Dmitry Baryshkov wrote:
>> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
>> adding/removing entries to/from parent_data easy and errorproof.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> But do read on about an accidental fix that you may want to pull out
> into an explicit patch.
>> ---
>> drivers/clk/qcom/gcc-msm8916.c | 108 ++++++++++++++++-----------------
>> 1 file changed, 54 insertions(+), 54 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
>> index 17e4a5a2a9fd..40c27ba6286f 100644
>> --- a/drivers/clk/qcom/gcc-msm8916.c
>> +++ b/drivers/clk/qcom/gcc-msm8916.c
>> @@ -371,7 +371,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "pcnoc_bfdcd_clk_src",
>> .parent_names = gcc_xo_gpll0_bimc,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -383,7 +383,7 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "system_noc_bfdcd_clk_src",
>> .parent_names = gcc_xo_gpll0_bimc,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -403,7 +403,7 @@ static struct clk_rcg2 camss_ahb_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "camss_ahb_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -424,7 +424,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "apss_ahb_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -443,7 +443,7 @@ static struct clk_rcg2 csi0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "csi0_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -456,7 +456,7 @@ static struct clk_rcg2 csi1_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "csi1_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -484,7 +484,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "gfx3d_clk_src",
>> .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -511,7 +511,7 @@ static struct clk_rcg2 vfe0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "vfe0_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll2,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -530,7 +530,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup1_i2c_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -559,7 +559,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup1_spi_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -572,7 +572,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup2_i2c_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -586,7 +586,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup2_spi_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -599,7 +599,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup3_i2c_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -613,7 +613,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup3_spi_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -626,7 +626,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup4_i2c_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -640,7 +640,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup4_spi_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -653,7 +653,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup5_i2c_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -667,7 +667,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup5_spi_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -680,7 +680,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup6_i2c_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -694,7 +694,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_qup6_spi_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -727,7 +727,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_uart1_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -741,7 +741,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "blsp1_uart2_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -760,7 +760,7 @@ static struct clk_rcg2 cci_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "cci_clk_src",
>> .parent_names = gcc_xo_gpll0a,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -780,7 +780,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "camss_gp0_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -794,7 +794,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "camss_gp1_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -814,7 +814,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "jpeg0_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -835,7 +835,7 @@ static struct clk_rcg2 mclk0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "mclk0_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -849,7 +849,7 @@ static struct clk_rcg2 mclk1_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "mclk1_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -868,7 +868,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "csi0phytimer_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -881,7 +881,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "csi1phytimer_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -901,7 +901,7 @@ static struct clk_rcg2 cpp_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "cpp_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll2,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -922,7 +922,7 @@ static struct clk_rcg2 crypto_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "crypto_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -941,7 +941,7 @@ static struct clk_rcg2 gp1_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "gp1_clk_src",
>
> Starting here...
>
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -955,7 +955,7 @@ static struct clk_rcg2 gp2_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "gp2_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -969,7 +969,7 @@ static struct clk_rcg2 gp3_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "gp3_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1a_sleep,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
>
> And ending here, note that this array and the corresponding _map contain
> four items instead of 3, making this a semantic change. The last
> member, `sleep_clk`, couldn't previously be selected here.
I thought about it for quite a while. I suspect it doesn't make sense to
create a separate commit, changing 3 to 4 then replacing it with
ARRAY_SIZE. I think we'd better document the change in the commit
message and add proper fixes tags to this commit.
>
> - Marijn
>
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -981,7 +981,7 @@ static struct clk_rcg2 byte0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "byte0_clk_src",
>> .parent_names = gcc_xo_gpll0a_dsibyte,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
>> .ops = &clk_byte2_ops,
>> .flags = CLK_SET_RATE_PARENT,
>> },
>> @@ -1000,7 +1000,7 @@ static struct clk_rcg2 esc0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "esc0_clk_src",
>> .parent_names = gcc_xo_dsibyte,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1025,7 +1025,7 @@ static struct clk_rcg2 mdp_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "mdp_clk_src",
>> .parent_names = gcc_xo_gpll0_dsiphy,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1038,7 +1038,7 @@ static struct clk_rcg2 pclk0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "pclk0_clk_src",
>> .parent_names = gcc_xo_gpll0a_dsiphy,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
>> .ops = &clk_pixel_ops,
>> .flags = CLK_SET_RATE_PARENT,
>> },
>> @@ -1057,7 +1057,7 @@ static struct clk_rcg2 vsync_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "vsync_clk_src",
>> .parent_names = gcc_xo_gpll0a,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1075,7 +1075,7 @@ static struct clk_rcg2 pdm2_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "pdm2_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1100,7 +1100,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "sdcc1_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_floor_ops,
>> },
>> };
>> @@ -1125,7 +1125,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "sdcc2_apps_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_floor_ops,
>> },
>> };
>> @@ -1145,7 +1145,7 @@ static struct clk_rcg2 apss_tcu_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "apss_tcu_clk_src",
>> .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1168,7 +1168,7 @@ static struct clk_rcg2 bimc_gpu_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "bimc_gpu_clk_src",
>> .parent_names = gcc_xo_gpll0_bimc,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
>> .flags = CLK_GET_RATE_NOCACHE,
>> .ops = &clk_rcg2_ops,
>> },
>> @@ -1187,7 +1187,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "usb_hs_system_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1213,7 +1213,7 @@ static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "ultaudio_ahbfabric_clk_src",
>> .parent_names = gcc_xo_gpll0_gpll1_sleep,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1292,7 +1292,7 @@ static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "ultaudio_lpaif_pri_i2s_clk_src",
>> .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep,
>> - .num_parents = 5,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1323,7 +1323,7 @@ static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "ultaudio_lpaif_sec_i2s_clk_src",
>> .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
>> - .num_parents = 5,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1354,7 +1354,7 @@ static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "ultaudio_lpaif_aux_i2s_clk_src",
>> .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep,
>> - .num_parents = 5,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1389,7 +1389,7 @@ static struct clk_rcg2 ultaudio_xo_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "ultaudio_xo_clk_src",
>> .parent_names = gcc_xo_sleep,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1445,7 +1445,7 @@ static struct clk_rcg2 codec_digcodec_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "codec_digcodec_clk_src",
>> .parent_names = gcc_xo_gpll1_emclk_sleep,
>> - .num_parents = 4,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -1515,7 +1515,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "vcodec0_clk_src",
>> .parent_names = gcc_xo_gpll0,
>> - .num_parents = 2,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> .ops = &clk_rcg2_ops,
>> },
>> };
>> @@ -2771,7 +2771,7 @@ static struct clk_rcg2 bimc_ddr_clk_src = {
>> .clkr.hw.init = &(struct clk_init_data){
>> .name = "bimc_ddr_clk_src",
>> .parent_names = gcc_xo_gpll0_bimc,
>> - .num_parents = 3,
>> + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
>> .ops = &clk_rcg2_ops,
>> .flags = CLK_GET_RATE_NOCACHE,
>> },
>> --
>> 2.35.1
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2022-07-04 17:13 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-19 21:27 [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Dmitry Baryshkov
2022-06-20 12:05 ` Dmitry Baryshkov
2022-06-27 21:11 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 2/7] dt-bindings: clock: separate bindings for MSM8916 GCC device Dmitry Baryshkov
2022-06-20 12:06 ` Dmitry Baryshkov
2022-06-27 21:09 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 3/7] clk: qcom: gcc-msm8916: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-06-27 21:03 ` Marijn Suijten
2022-07-04 17:12 ` Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 4/7] clk: qcom: gcc-msm8916: move clock parent tables down Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 5/7] clk: qcom: gcc-msm8916: move gcc_mss_q6_bimc_axi_clk down Dmitry Baryshkov
2022-06-27 21:18 ` Marijn Suijten
2022-06-28 12:40 ` Dmitry Baryshkov
2022-06-19 21:27 ` [PATCH v3 6/7] clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-06-27 21:28 ` Marijn Suijten
2022-06-19 21:27 ` [PATCH v3 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node Dmitry Baryshkov
2022-06-20 12:13 ` Konrad Dybcio
2022-06-27 21:29 ` Marijn Suijten
2022-06-20 12:12 ` [PATCH v3 0/7] clk: qcom: gcc-msm8916: modernize the driver Konrad Dybcio
2022-07-04 16:24 ` Dmitry Baryshkov
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