From: Richard Henderson <richard.henderson@linaro.org> To: LIU Zhiwei <zhiwei_liu@c-sky.com>, QEMU Developers <qemu-devel@nongnu.org>, "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <alistair.francis@wdc.com> Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64 Date: Thu, 10 Jun 2021 06:29:56 -0700 [thread overview] Message-ID: <eb54d2d9-db15-e2d7-e245-f61587b0ca4e@linaro.org> (raw) In-Reply-To: <7ac5990e-5f87-3d96-d8b5-bd7997fac0ee@c-sky.com> On 6/9/21 6:43 PM, LIU Zhiwei wrote: > 1)First a multiply instruction, if the source value big enough, it will return > a result with some bits not zero in MSW 32-bit. Multiply is fine. Input bits outside the low 32 cannot appear in the low 32 of the output. Multiply-high-part on the other hand will require sign- or zero-extension of inputs. > 2)If next instruction is a divide instruction, the MSW 32-bit will influence > the divide instruction result. Yes, division requires extension too. > So I think use *_tl can't satisfy the need to run 32-bit program on qemu-riscv64. I said some operations will require extra work -- I gave right-shift as an example. You just have to be careful about deciding what extra work to do. I am suggesting that truncation to *_i32 is almost always not the correct answer. Perhaps make it easier by changing gen_get_gpr and gen_set_gpr: /* Return sign-extended version of gpr. */ static void get_gpr_s(DisasContext *ctx, TCGv t, int reg_num) { if (reg_num == 0) { tcg_gen_movi_tl(t, 0); } else if (is_32bit(ctx)) { tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); } else { tcg_gen_mov_tl(t, cpu_gpr[reg_num]); } } /* Return zero-extended version of gpr. */ static void get_gpr_u(DisasContext *ctx, TCGv t, int reg_num); { if (reg_num == 0) { tcg_gen_movi_tl(t, 0); } else if (is_32bit(ctx)) { tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); } else { tcg_gen_mov_tl(t, cpu_gpr[reg_num]); } } /* Return gpr with undefined high bits (which will be ignored). */ static void get_gpr_x(TCGv t, int reg_num); { if (reg_num == 0) { tcg_gen_movi_tl(t, 0); } else { tcg_gen_mov_tl(t, cpu_gpr[reg_num]); } } And similarly for set. r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: LIU Zhiwei <zhiwei_liu@c-sky.com>, QEMU Developers <qemu-devel@nongnu.org>, "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org> Cc: Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com> Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64 Date: Thu, 10 Jun 2021 06:29:56 -0700 [thread overview] Message-ID: <eb54d2d9-db15-e2d7-e245-f61587b0ca4e@linaro.org> (raw) In-Reply-To: <7ac5990e-5f87-3d96-d8b5-bd7997fac0ee@c-sky.com> On 6/9/21 6:43 PM, LIU Zhiwei wrote: > 1)First a multiply instruction, if the source value big enough, it will return > a result with some bits not zero in MSW 32-bit. Multiply is fine. Input bits outside the low 32 cannot appear in the low 32 of the output. Multiply-high-part on the other hand will require sign- or zero-extension of inputs. > 2)If next instruction is a divide instruction, the MSW 32-bit will influence > the divide instruction result. Yes, division requires extension too. > So I think use *_tl can't satisfy the need to run 32-bit program on qemu-riscv64. I said some operations will require extra work -- I gave right-shift as an example. You just have to be careful about deciding what extra work to do. I am suggesting that truncation to *_i32 is almost always not the correct answer. Perhaps make it easier by changing gen_get_gpr and gen_set_gpr: /* Return sign-extended version of gpr. */ static void get_gpr_s(DisasContext *ctx, TCGv t, int reg_num) { if (reg_num == 0) { tcg_gen_movi_tl(t, 0); } else if (is_32bit(ctx)) { tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); } else { tcg_gen_mov_tl(t, cpu_gpr[reg_num]); } } /* Return zero-extended version of gpr. */ static void get_gpr_u(DisasContext *ctx, TCGv t, int reg_num); { if (reg_num == 0) { tcg_gen_movi_tl(t, 0); } else if (is_32bit(ctx)) { tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); } else { tcg_gen_mov_tl(t, cpu_gpr[reg_num]); } } /* Return gpr with undefined high bits (which will be ignored). */ static void get_gpr_x(TCGv t, int reg_num); { if (reg_num == 0) { tcg_gen_movi_tl(t, 0); } else { tcg_gen_mov_tl(t, cpu_gpr[reg_num]); } } And similarly for set. r~
next prev parent reply other threads:[~2021-06-10 13:31 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-07 3:07 TCG op for 32 bit only cpu on qemu-riscv64 LIU Zhiwei 2021-06-07 3:07 ` LIU Zhiwei 2021-06-07 6:22 ` Alistair Francis 2021-06-07 6:22 ` Alistair Francis 2021-06-07 9:22 ` LIU Zhiwei 2021-06-07 9:22 ` LIU Zhiwei 2021-06-07 15:59 ` Richard Henderson 2021-06-07 15:59 ` Richard Henderson 2021-06-07 15:52 ` Richard Henderson 2021-06-07 15:52 ` Richard Henderson 2021-06-10 1:43 ` LIU Zhiwei 2021-06-10 1:43 ` LIU Zhiwei 2021-06-10 13:29 ` Richard Henderson [this message] 2021-06-10 13:29 ` Richard Henderson 2021-06-11 2:33 ` LIU Zhiwei 2021-06-11 2:33 ` LIU Zhiwei
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