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From: Julien Grall <julien.grall@arm.com>
To: Stefano Stabellini <sstabellini@kernel.org>
Cc: "Artem_Mygaiev@epam.com" <Artem_Mygaiev@epam.com>,
	"Andrii_Anisov@epam.com" <Andrii_Anisov@epam.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	"Oleksandr_Tyshchenko@epam.com" <Oleksandr_Tyshchenko@epam.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	nd <nd@arm.com>
Subject: Re: [PATCH 05/12] xen/arm64: bitops: Match the register size with the value size in flsl
Date: Thu, 18 Apr 2019 19:57:12 +0100	[thread overview]
Message-ID: <eb9dd02e-3b0d-19fc-9103-c7ceccc626ab@arm.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1904181131450.1370@sstabellini-ThinkPad-X260>

Hi,

On 18/04/2019 19:40, Stefano Stabellini wrote:
> On Wed, 17 Apr 2019, Julien Grall wrote:
>> On 4/17/19 9:24 PM, Stefano Stabellini wrote:
>>> On Wed, 27 Mar 2019, Julien Grall wrote:
>>>> Hi,
>>>>
>>>> On 27/03/2019 19:03, Andrew Cooper wrote:
>>>>> On 27/03/2019 18:45, Julien Grall wrote:
>>>>>> Clang is pickier than GCC for the register size in asm statement. It
>>>>>> expects
>>>>>> the register size to match the value size.
>>>>>>
>>>>>> The instruction clz is expecting the two operands to be the same size
>>>>>> (i.e 32-bit or 64-bit). As the flsl function is dealing with 64-bit
>>>>>> value, we need to make the destination variable 64-bit as well.
>>>>>>
>>>>>> While at it, add a newline before the return statement.
>>>>>>
>>>>>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>>>>>> ---
>>>>>>     xen/include/asm-arm/arm64/bitops.h | 3 ++-
>>>>>>     1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/xen/include/asm-arm/arm64/bitops.h
>>>>>> b/xen/include/asm-arm/arm64/bitops.h
>>>>>> index 6bf1922680..05045f1109 100644
>>>>>> --- a/xen/include/asm-arm/arm64/bitops.h
>>>>>> +++ b/xen/include/asm-arm/arm64/bitops.h
>>>>>> @@ -34,12 +34,13 @@ static /*__*/always_inline unsigned long
>>>>>> __ffs(unsigned long word)
>>>>>>        static inline int flsl(unsigned long x)
>>>>>>     {
>>>>>> -        int ret;
>>>>>> +        uint64_t ret;
>>>>>>                if (__builtin_constant_p(x))
>>>>>>                    return generic_flsl(x);
>>>>>>                asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
>>>>>
>>>>> As x is fixed by the ABI, ret should be unsigned long to match, surely?
>>>>
>>>> No need for it. The result of the instruction clz will always be smaller
>>>> than 64.
>>>>
>>>> I suspect they require a 64-bit register just for simplicity as they
>>>> encode the size for the 2 registers in only a single bit (i.e sf).
>>>>
>>>>>
>>>>> This will compile as it is arm64 specific, but it looks just as wrong
>>>>> (per the commit message) as using int in the first place.
>>>> See above. I can clarify it in the commit message.
>>>
>>> I agree with Andrew: I can see that the code is correct, but it really
>>> looks wrong at first sight. Why not use unsigned long? This is an arm64
>>> header anyway.
>>
>> While this is implemented in arm64, this is a function used in common code...
>> So the prototype would have to be changed everywhere.
>>
>> However, as I pointed out this is a design decision from Arm64 and I think it
>> would be wrong to return unsigned long.
>>
>> I offered the suggestion to update the commit message. I can also add a
>> comment in the code.
> 
> Reading your reply, I am pretty sure that we are talking about different
> things. I agree that we don't want to change the prototype everywhere,
> arm32, x86. It would be good to add a comment to the code or the commit
> message, I leave it to you.
> 
> My suggestion was basically "code style". I only meant the below. To me
> it looks nicer because at least the ret var is the same type of the
> argument, and it is more immediately obvious that the clz operation is
> correct. Not a big deal.

I find quite amusing that you suggest this when in the patch #7 you mention the 
MISRA rule 10.1 which forbid assigning a value to a narrower type (unsigned long 
-> int).

Regardless that, clz operation clearly ask for a 64-bit value. So uint64_t makes 
much more sense than "unsigned long". In general, I am a strong advocate to use 
uintX_t when the size is known. "unsigned long" should only be used in place you 
need compat between 32-bit and 64-bit code.

Cheers,

-- 
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

WARNING: multiple messages have this Message-ID (diff)
From: Julien Grall <julien.grall@arm.com>
To: Stefano Stabellini <sstabellini@kernel.org>
Cc: "Artem_Mygaiev@epam.com" <Artem_Mygaiev@epam.com>,
	"Andrii_Anisov@epam.com" <Andrii_Anisov@epam.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	"Oleksandr_Tyshchenko@epam.com" <Oleksandr_Tyshchenko@epam.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	nd <nd@arm.com>
Subject: Re: [Xen-devel] [PATCH 05/12] xen/arm64: bitops: Match the register size with the value size in flsl
Date: Thu, 18 Apr 2019 19:57:12 +0100	[thread overview]
Message-ID: <eb9dd02e-3b0d-19fc-9103-c7ceccc626ab@arm.com> (raw)
Message-ID: <20190418185712.DZrCtAbPTV4QicCHptSCVwZPjt6Nk__oRY_epJr9uAY@z> (raw)
In-Reply-To: <alpine.DEB.2.10.1904181131450.1370@sstabellini-ThinkPad-X260>

Hi,

On 18/04/2019 19:40, Stefano Stabellini wrote:
> On Wed, 17 Apr 2019, Julien Grall wrote:
>> On 4/17/19 9:24 PM, Stefano Stabellini wrote:
>>> On Wed, 27 Mar 2019, Julien Grall wrote:
>>>> Hi,
>>>>
>>>> On 27/03/2019 19:03, Andrew Cooper wrote:
>>>>> On 27/03/2019 18:45, Julien Grall wrote:
>>>>>> Clang is pickier than GCC for the register size in asm statement. It
>>>>>> expects
>>>>>> the register size to match the value size.
>>>>>>
>>>>>> The instruction clz is expecting the two operands to be the same size
>>>>>> (i.e 32-bit or 64-bit). As the flsl function is dealing with 64-bit
>>>>>> value, we need to make the destination variable 64-bit as well.
>>>>>>
>>>>>> While at it, add a newline before the return statement.
>>>>>>
>>>>>> Signed-off-by: Julien Grall <julien.grall@arm.com>
>>>>>> ---
>>>>>>     xen/include/asm-arm/arm64/bitops.h | 3 ++-
>>>>>>     1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/xen/include/asm-arm/arm64/bitops.h
>>>>>> b/xen/include/asm-arm/arm64/bitops.h
>>>>>> index 6bf1922680..05045f1109 100644
>>>>>> --- a/xen/include/asm-arm/arm64/bitops.h
>>>>>> +++ b/xen/include/asm-arm/arm64/bitops.h
>>>>>> @@ -34,12 +34,13 @@ static /*__*/always_inline unsigned long
>>>>>> __ffs(unsigned long word)
>>>>>>        static inline int flsl(unsigned long x)
>>>>>>     {
>>>>>> -        int ret;
>>>>>> +        uint64_t ret;
>>>>>>                if (__builtin_constant_p(x))
>>>>>>                    return generic_flsl(x);
>>>>>>                asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
>>>>>
>>>>> As x is fixed by the ABI, ret should be unsigned long to match, surely?
>>>>
>>>> No need for it. The result of the instruction clz will always be smaller
>>>> than 64.
>>>>
>>>> I suspect they require a 64-bit register just for simplicity as they
>>>> encode the size for the 2 registers in only a single bit (i.e sf).
>>>>
>>>>>
>>>>> This will compile as it is arm64 specific, but it looks just as wrong
>>>>> (per the commit message) as using int in the first place.
>>>> See above. I can clarify it in the commit message.
>>>
>>> I agree with Andrew: I can see that the code is correct, but it really
>>> looks wrong at first sight. Why not use unsigned long? This is an arm64
>>> header anyway.
>>
>> While this is implemented in arm64, this is a function used in common code...
>> So the prototype would have to be changed everywhere.
>>
>> However, as I pointed out this is a design decision from Arm64 and I think it
>> would be wrong to return unsigned long.
>>
>> I offered the suggestion to update the commit message. I can also add a
>> comment in the code.
> 
> Reading your reply, I am pretty sure that we are talking about different
> things. I agree that we don't want to change the prototype everywhere,
> arm32, x86. It would be good to add a comment to the code or the commit
> message, I leave it to you.
> 
> My suggestion was basically "code style". I only meant the below. To me
> it looks nicer because at least the ret var is the same type of the
> argument, and it is more immediately obvious that the clz operation is
> correct. Not a big deal.

I find quite amusing that you suggest this when in the patch #7 you mention the 
MISRA rule 10.1 which forbid assigning a value to a narrower type (unsigned long 
-> int).

Regardless that, clz operation clearly ask for a 64-bit value. So uint64_t makes 
much more sense than "unsigned long". In general, I am a strong advocate to use 
uintX_t when the size is known. "unsigned long" should only be used in place you 
need compat between 32-bit and 64-bit code.

Cheers,

-- 
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel

  reply	other threads:[~2019-04-18 18:57 UTC|newest]

Thread overview: 104+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-27 18:45 [PATCH 00/12] xen/arm: Add support to build with clang Julien Grall
2019-03-27 18:45 ` [PATCH 01/12] xen: clang: Support correctly cross-compile Julien Grall
2019-03-28  9:55   ` Jan Beulich
2019-03-28 10:14     ` Andrew Cooper
2019-03-28 10:28       ` Jan Beulich
2019-03-28 10:43         ` Andrew Cooper
2019-03-28 10:56           ` Jan Beulich
2019-03-29 10:09             ` Julien Grall
2019-03-29  9:41     ` Julien Grall
2019-03-29 10:14       ` Jan Beulich
2019-04-19 18:47         ` Stefano Stabellini
2019-04-19 18:47           ` [Xen-devel] " Stefano Stabellini
2019-04-24 20:18           ` Julien Grall
2019-04-24 20:18             ` [Xen-devel] " Julien Grall
2019-03-27 18:45 ` [PATCH 02/12] xen/arm: fix get_cpu_info() when built with clang Julien Grall
2019-04-17 20:45   ` Stefano Stabellini
2019-04-17 20:45     ` [Xen-devel] " Stefano Stabellini
2019-04-17 21:00     ` Julien Grall
2019-04-17 21:00       ` [Xen-devel] " Julien Grall
2019-04-18 18:03       ` Stefano Stabellini
2019-04-18 18:03         ` [Xen-devel] " Stefano Stabellini
2019-09-29 14:26         ` Julien Grall
2019-10-01  1:15           ` Stefano Stabellini
2019-10-01  1:22             ` Stefano Stabellini
2019-10-01  9:49               ` Julien Grall
2019-10-01  9:47             ` Julien Grall
2019-03-27 18:45 ` [PATCH 03/12] xen/arm: zynqmp: Fix header guard for xilinx-zynqmp-eemi.h Julien Grall
2019-04-17 20:20   ` Stefano Stabellini
2019-04-17 20:20     ` [Xen-devel] " Stefano Stabellini
2019-03-27 18:45 ` [PATCH 04/12] xen/arm: memaccess: Initialize correctly *access in __p2m_get_mem_access Julien Grall
2019-03-27 19:08   ` Razvan Cojocaru
2019-03-27 18:45 ` [PATCH 05/12] xen/arm64: bitops: Match the register size with the value size in flsl Julien Grall
2019-03-27 19:03   ` Andrew Cooper
2019-03-27 20:13     ` Julien Grall
2019-04-17 20:24       ` Stefano Stabellini
2019-04-17 20:24         ` [Xen-devel] " Stefano Stabellini
2019-04-17 21:02         ` Julien Grall
2019-04-17 21:02           ` [Xen-devel] " Julien Grall
2019-04-18 18:40           ` Stefano Stabellini
2019-04-18 18:40             ` [Xen-devel] " Stefano Stabellini
2019-04-18 18:57             ` Julien Grall [this message]
2019-04-18 18:57               ` Julien Grall
2019-04-18 19:00               ` Stefano Stabellini
2019-04-18 19:00                 ` [Xen-devel] " Stefano Stabellini
2019-03-27 18:45 ` [PATCH 06/12] xen/arm64: sysreg: Implement the 32-bit helpers using the 64-bit helpers Julien Grall
2019-03-27 19:15   ` Andrew Cooper
2019-03-27 20:21     ` Julien Grall
2019-04-17 20:26   ` Stefano Stabellini
2019-04-17 20:26     ` [Xen-devel] " Stefano Stabellini
2019-03-27 18:45 ` [PATCH 07/12] xen/arm: cpuerrata: Match register size with value size in check_workaround_* Julien Grall
2019-04-17 20:28   ` Stefano Stabellini
2019-04-17 20:28     ` [Xen-devel] " Stefano Stabellini
2019-04-17 21:15     ` Julien Grall
2019-04-17 21:15       ` [Xen-devel] " Julien Grall
2019-04-18 18:23       ` Stefano Stabellini
2019-04-18 18:23         ` [Xen-devel] " Stefano Stabellini
2019-04-18 18:47         ` Julien Grall
2019-04-18 18:47           ` [Xen-devel] " Julien Grall
2019-04-18 18:52           ` Stefano Stabellini
2019-04-18 18:52             ` [Xen-devel] " Stefano Stabellini
2019-04-18 19:01             ` Julien Grall
2019-04-18 19:01               ` [Xen-devel] " Julien Grall
2019-04-18 19:04               ` Stefano Stabellini
2019-04-18 19:04                 ` [Xen-devel] " Stefano Stabellini
2019-03-27 18:45 ` [PATCH 08/12] xen/arm: cpufeature: Match register size with value size in cpus_have_const_cap Julien Grall
2019-04-17 20:29   ` Stefano Stabellini
2019-04-17 20:29     ` [Xen-devel] " Stefano Stabellini
2019-04-17 21:16     ` Julien Grall
2019-04-17 21:16       ` [Xen-devel] " Julien Grall
2019-03-27 18:45 ` [PATCH 09/12] xen/arm: guest_walk: Avoid theoritical unitialized value in get_top_bit Julien Grall
2019-04-17 20:31   ` Stefano Stabellini
2019-04-17 20:31     ` [Xen-devel] " Stefano Stabellini
2019-03-27 18:45 ` [PATCH 10/12] xen/arm: mm: Mark check_memory_layout_alignment_constraints as unused Julien Grall
2019-03-27 19:10   ` Andrew Cooper
2019-04-09 12:09     ` Julien Grall
2019-04-09 12:09       ` [Xen-devel] " Julien Grall
2019-03-27 18:45 ` [PATCH 11/12] xen/arm: traps: Mark check_stack_alignment_constraints " Julien Grall
2019-03-27 18:45 ` [PATCH 12/12] xen/arm64: __cmpxchg and __cmpxchg_mb should always be inline Julien Grall
2019-04-17 20:35   ` Stefano Stabellini
2019-04-17 20:35     ` [Xen-devel] " Stefano Stabellini
2019-03-28 11:27 ` [PATCH 00/12] xen/arm: Add support to build with clang Artem Mygaiev
2019-03-29 10:13   ` Julien Grall
2019-04-16 22:43     ` Stefano Stabellini
2019-04-16 22:43       ` [Xen-devel] " Stefano Stabellini
2019-04-17  9:42       ` Julien Grall
2019-04-17  9:42         ` [Xen-devel] " Julien Grall
2019-04-18  9:15         ` Artem Mygaiev
2019-04-18  9:15           ` [Xen-devel] " Artem Mygaiev
2019-04-18 10:43           ` Julien Grall
2019-04-18 10:43             ` [Xen-devel] " Julien Grall
2019-04-18 11:15             ` Artem Mygaiev
2019-04-18 11:15               ` [Xen-devel] " Artem Mygaiev
2019-04-18 18:33               ` Julien Grall
2019-04-18 18:33                 ` [Xen-devel] " Julien Grall
2019-04-23 13:39                 ` Artem Mygaiev
2019-04-23 13:39                   ` [Xen-devel] " Artem Mygaiev
2019-04-24 21:07                   ` Julien Grall
2019-04-24 21:07                     ` [Xen-devel] " Julien Grall
2019-04-25  3:31                     ` Artem Mygaiev
2019-04-25  3:31                       ` [Xen-devel] " Artem Mygaiev
2019-04-24 11:01                 ` Roger Pau Monné
2019-04-24 11:01                   ` [Xen-devel] " Roger Pau Monné
2019-04-18 11:13 ` Julien Grall
2019-04-18 11:13   ` [Xen-devel] " Julien Grall

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