From: Lars-Peter Clausen <lars@metafoo.de> To: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>, vkoul@kernel.org, robh+dt@kernel.org, michal.simek@xilinx.com Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, git@xilinx.com Subject: Re: [RFC v2 PATCH 5/7] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Date: Thu, 15 Apr 2021 09:08:59 +0200 [thread overview] Message-ID: <ec177886-fc14-b52e-4c98-da523fa711d9@metafoo.de> (raw) In-Reply-To: <1617990965-35337-6-git-send-email-radhey.shyam.pandey@xilinx.com> On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote: > AXIDMA IP in SG mode sets completion bit to 1 when the transfer is > completed. Read this bit to move descriptor from active list to the > done list. This feature is needed when interrupt delay timeout and > IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing > interrupt threshold. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > - Check BD completion bit only for SG mode. > - Modify the logic to have early return path. > --- > drivers/dma/xilinx/xilinx_dma.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 890bf46b36e5..f2305a73cb91 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -177,6 +177,7 @@ > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > #define XILINX_DMA_BD_SOP BIT(27) > #define XILINX_DMA_BD_EOP BIT(26) > +#define XILINX_DMA_BD_COMP_MASK BIT(31) > #define XILINX_DMA_COALESCE_MAX 255 > #define XILINX_DMA_NUM_DESCS 512 > #define XILINX_DMA_NUM_APP_WORDS 5 > @@ -1683,12 +1684,18 @@ static void xilinx_dma_issue_pending(struct dma_chan *dchan) > static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) > { > struct xilinx_dma_tx_descriptor *desc, *next; > + struct xilinx_axidma_tx_segment *seg; > > /* This function was invoked with lock held */ > if (list_empty(&chan->active_list)) > return; > > list_for_each_entry_safe(desc, next, &chan->active_list, node) { > + /* TODO: remove hardcoding for axidma_tx_segment */ > + seg = list_last_entry(&desc->segments, > + struct xilinx_axidma_tx_segment, node); This needs to be fixed before this can be merged as it right now will break the non AXIDMA variants. > + if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) > + break; > if (chan->has_sg && chan->xdev->dma_config->dmatype != > XDMA_TYPE_VDMA) > desc->residue = xilinx_dma_get_residue(chan, desc);
WARNING: multiple messages have this Message-ID (diff)
From: Lars-Peter Clausen <lars@metafoo.de> To: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>, vkoul@kernel.org, robh+dt@kernel.org, michal.simek@xilinx.com Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, git@xilinx.com Subject: Re: [RFC v2 PATCH 5/7] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Date: Thu, 15 Apr 2021 09:08:59 +0200 [thread overview] Message-ID: <ec177886-fc14-b52e-4c98-da523fa711d9@metafoo.de> (raw) In-Reply-To: <1617990965-35337-6-git-send-email-radhey.shyam.pandey@xilinx.com> On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote: > AXIDMA IP in SG mode sets completion bit to 1 when the transfer is > completed. Read this bit to move descriptor from active list to the > done list. This feature is needed when interrupt delay timeout and > IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing > interrupt threshold. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > - Check BD completion bit only for SG mode. > - Modify the logic to have early return path. > --- > drivers/dma/xilinx/xilinx_dma.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 890bf46b36e5..f2305a73cb91 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -177,6 +177,7 @@ > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > #define XILINX_DMA_BD_SOP BIT(27) > #define XILINX_DMA_BD_EOP BIT(26) > +#define XILINX_DMA_BD_COMP_MASK BIT(31) > #define XILINX_DMA_COALESCE_MAX 255 > #define XILINX_DMA_NUM_DESCS 512 > #define XILINX_DMA_NUM_APP_WORDS 5 > @@ -1683,12 +1684,18 @@ static void xilinx_dma_issue_pending(struct dma_chan *dchan) > static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) > { > struct xilinx_dma_tx_descriptor *desc, *next; > + struct xilinx_axidma_tx_segment *seg; > > /* This function was invoked with lock held */ > if (list_empty(&chan->active_list)) > return; > > list_for_each_entry_safe(desc, next, &chan->active_list, node) { > + /* TODO: remove hardcoding for axidma_tx_segment */ > + seg = list_last_entry(&desc->segments, > + struct xilinx_axidma_tx_segment, node); This needs to be fixed before this can be merged as it right now will break the non AXIDMA variants. > + if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) > + break; > if (chan->has_sg && chan->xdev->dma_config->dmatype != > XDMA_TYPE_VDMA) > desc->residue = xilinx_dma_get_residue(chan, desc); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-04-15 7:09 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-09 17:55 [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Radhey Shyam Pandey 2021-04-09 17:55 ` Radhey Shyam Pandey 2021-04-09 17:55 ` [RFC v2 PATCH 1/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property Radhey Shyam Pandey 2021-04-09 17:55 ` [RFC v2 PATCH 1/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx, axistream-connected property Radhey Shyam Pandey 2021-04-12 18:25 ` [RFC v2 PATCH 1/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property Rob Herring 2021-04-12 18:25 ` Rob Herring 2021-04-09 17:56 ` [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Radhey Shyam Pandey 2021-04-09 17:56 ` [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx, irq-delay property Radhey Shyam Pandey 2021-04-12 18:25 ` [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Rob Herring 2021-04-12 18:25 ` Rob Herring 2021-04-09 17:56 ` [RFC v2 PATCH 3/7] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client Radhey Shyam Pandey 2021-04-09 17:56 ` Radhey Shyam Pandey 2021-04-09 17:56 ` [RFC v2 PATCH 4/7] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Radhey Shyam Pandey 2021-04-09 17:56 ` Radhey Shyam Pandey 2021-04-09 17:56 ` [RFC v2 PATCH 5/7] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey 2021-04-09 17:56 ` Radhey Shyam Pandey 2021-04-15 7:08 ` Lars-Peter Clausen [this message] 2021-04-15 7:08 ` Lars-Peter Clausen 2021-06-11 16:16 ` Radhey Shyam Pandey 2021-06-11 16:16 ` Radhey Shyam Pandey 2021-04-15 7:26 ` Lars-Peter Clausen 2021-04-15 7:26 ` Lars-Peter Clausen 2021-06-11 18:58 ` Radhey Shyam Pandey 2021-06-11 18:58 ` Radhey Shyam Pandey 2021-04-09 17:56 ` [RFC v2 PATCH 6/7] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Radhey Shyam Pandey 2021-04-09 17:56 ` Radhey Shyam Pandey 2021-04-15 7:10 ` Lars-Peter Clausen 2021-04-15 7:10 ` Lars-Peter Clausen 2021-06-11 18:30 ` Radhey Shyam Pandey 2021-06-11 18:30 ` Radhey Shyam Pandey 2021-04-09 17:56 ` [RFC v2 PATCH 7/7] dmaengine: xilinx_dma: Program interrupt delay timeout Radhey Shyam Pandey 2021-04-09 17:56 ` Radhey Shyam Pandey 2021-04-15 7:33 ` Lars-Peter Clausen 2021-04-15 7:33 ` Lars-Peter Clausen 2021-06-11 19:33 ` Radhey Shyam Pandey 2021-06-11 19:33 ` Radhey Shyam Pandey 2021-04-15 7:06 ` [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Lars-Peter Clausen 2021-04-15 7:06 ` Lars-Peter Clausen 2021-06-11 16:13 ` Radhey Shyam Pandey 2021-06-11 16:13 ` Radhey Shyam Pandey
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