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From: "Christoph Lameter (Ampere)" <cl@gentwo.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Yang Shi <yang@os.amperecomputing.com>,
	catalin.marinas@arm.com,  will@kernel.org,
	scott@os.amperecomputing.com,
	 linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: mm: force write fault for atomic RMW instructions
Date: Mon, 13 May 2024 15:39:46 -0700 (PDT)	[thread overview]
Message-ID: <ec207271-623a-f2c0-0adf-7ecbc47aa99b@gentwo.org> (raw)
In-Reply-To: <ea88e906-3219-48c0-884c-3bb13ca0d18f@arm.com>

On Thu, 9 May 2024, Anshuman Khandual wrote:

>
>>> Okay, I was about to ask, but is not calling get_user() for all data
>>> read page faults increase the cost for a hot code path in general for
>>> some potential savings for a very specific use case. Not sure if that
>>> is worth the trade-off.
>>
>> The instruction is cache hot since it must be present in the cpu cache for the fault. So the overhead is minimal.
>>
>
> But could not a pagefault_disable()-enable() window prevent concurring
> page faults for the current process thus degrading its performance.

The cpu is already executing a fault handler in kernel space. There cannot 
be an additional user space fault since we do not execute that code 
currently.



WARNING: multiple messages have this Message-ID (diff)
From: "Christoph Lameter (Ampere)" <cl@gentwo.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Yang Shi <yang@os.amperecomputing.com>,
	catalin.marinas@arm.com,  will@kernel.org,
	scott@os.amperecomputing.com,
	 linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: mm: force write fault for atomic RMW instructions
Date: Mon, 13 May 2024 15:39:46 -0700 (PDT)	[thread overview]
Message-ID: <ec207271-623a-f2c0-0adf-7ecbc47aa99b@gentwo.org> (raw)
In-Reply-To: <ea88e906-3219-48c0-884c-3bb13ca0d18f@arm.com>

On Thu, 9 May 2024, Anshuman Khandual wrote:

>
>>> Okay, I was about to ask, but is not calling get_user() for all data
>>> read page faults increase the cost for a hot code path in general for
>>> some potential savings for a very specific use case. Not sure if that
>>> is worth the trade-off.
>>
>> The instruction is cache hot since it must be present in the cpu cache for the fault. So the overhead is minimal.
>>
>
> But could not a pagefault_disable()-enable() window prevent concurring
> page faults for the current process thus degrading its performance.

The cpu is already executing a fault handler in kernel space. There cannot 
be an additional user space fault since we do not execute that code 
currently.



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  reply	other threads:[~2024-05-13 22:39 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-07 22:35 [PATCH] arm64: mm: force write fault for atomic RMW instructions Yang Shi
2024-05-07 22:35 ` Yang Shi
2024-05-07 22:42 ` Christoph Lameter (Ampere)
2024-05-08  6:45 ` Anshuman Khandual
2024-05-08  6:45   ` Anshuman Khandual
2024-05-08 17:15   ` Christoph Lameter (Ampere)
2024-05-08 17:15     ` Christoph Lameter (Ampere)
2024-05-09  4:23     ` Anshuman Khandual
2024-05-09  4:23       ` Anshuman Khandual
2024-05-13 22:39       ` Christoph Lameter (Ampere) [this message]
2024-05-13 22:39         ` Christoph Lameter (Ampere)
2024-05-08 18:37   ` Yang Shi
2024-05-08 18:37     ` Yang Shi
2024-05-09  4:31     ` Anshuman Khandual
2024-05-09  4:31       ` Anshuman Khandual
2024-05-09 21:46       ` Yang Shi
2024-05-09 21:46         ` Yang Shi
2024-05-10  4:28         ` Anshuman Khandual
2024-05-10  4:28           ` Anshuman Khandual
2024-05-10 16:37           ` Yang Shi
2024-05-10 16:37             ` Yang Shi
2024-05-10 12:11 ` Catalin Marinas
2024-05-10 12:11   ` Catalin Marinas
2024-05-10 17:13   ` Yang Shi
2024-05-10 17:13     ` Yang Shi
2024-05-13 22:41     ` Christoph Lameter (Ampere)
2024-05-13 22:41       ` Christoph Lameter (Ampere)
2024-05-14 10:39     ` Catalin Marinas
2024-05-14 10:39       ` Catalin Marinas
2024-05-14 15:57       ` David Hildenbrand
2024-05-14 15:57         ` David Hildenbrand
2024-05-17 16:30       ` Yang Shi
2024-05-17 16:30         ` Yang Shi
2024-05-17 17:25         ` Catalin Marinas
2024-05-17 17:25           ` Catalin Marinas
2024-05-17 17:35           ` Yang Shi
2024-05-17 17:35             ` Yang Shi
2024-05-14  3:19   ` Yang Shi
2024-05-14  3:19     ` Yang Shi
2024-05-14 10:53     ` Catalin Marinas
2024-05-14 10:53       ` Catalin Marinas
2024-05-17 16:10       ` Yang Shi
2024-05-17 16:10         ` Yang Shi

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