From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH] imx8mp_evk: Make SPL binary size smaller
Date: Fri, 8 May 2020 13:57:07 +0200 [thread overview]
Message-ID: <eda4c216-689c-5215-49f1-5df3071c249e@denx.de> (raw)
In-Reply-To: <CAOMZO5BybinT-mz_KKZ-XsVn72Li5gjGqGnDQiiCR3AYZEKxdQ@mail.gmail.com>
On 5/8/20 1:49 PM, Fabio Estevam wrote:
> On Fri, May 8, 2020 at 1:53 AM Fabio Estevam <festevam@gmail.com> wrote:
>>
>> Hi Marek,
>>
>> On Thu, May 7, 2020 at 11:56 PM Fabio Estevam <festevam@gmail.com> wrote:
>>
>>> I will activate them on SPL tomorrow.
>>
>> After activating the SPL clocks I see:
>>
>> clk 69 [ ] imx_clk_gate2 | |
>> `-- dram1_root_clk
>>
>> The dram1_root_clk is not getting turned on.
>
> Looks at the iMX8MM EVK log:
> https://pastebin.com/raw/XVc6AAvr
>
> It also has:
>
> [ ] clk_gate | | `-- dram_pll_out
>
> So it seems the problem is somewhere else.
Maybe you also need entries like
126dcc925d ("ARM: imx: imx8mm: Add missing clock entries for FEC clock")
for MX8MP ?
next prev parent reply other threads:[~2020-05-08 11:57 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 12:00 [PATCH] imx8mp_evk: Make SPL binary size smaller Fabio Estevam
2020-05-07 12:02 ` Marek Vasut
2020-05-07 12:08 ` Harald Seiler
2020-05-07 12:37 ` Fabio Estevam
2020-05-08 1:07 ` Fabio Estevam
2020-05-08 1:40 ` Marek Vasut
2020-05-08 2:56 ` Fabio Estevam
2020-05-08 2:59 ` Marek Vasut
2020-05-08 3:34 ` Fabio Estevam
2020-05-08 4:53 ` Fabio Estevam
2020-05-08 11:49 ` Fabio Estevam
2020-05-08 11:57 ` Marek Vasut [this message]
2020-05-08 12:04 ` Fabio Estevam
2020-05-08 12:04 ` Marek Vasut
2020-05-08 15:54 ` Fabio Estevam
2020-05-10 14:32 ` Peng Fan
2020-05-10 14:34 ` Marek Vasut
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