[Intel-gfx] [PATCH 1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[Intel-gfx] [PATCH 1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[José Roberto de Souza]

Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
"SF Partial Frame Enable" also on full update") and also setting
partial frame enable when psr_force_hw_tracking_exit() is called.

Also as PSR2_MAN_TRK_CTL is a double buffered registers do a RMW
is not a good idea so here also setting the man_trk_ctl_enable_bit()
that is required in TGL and only doing a register write.

v2:
- not doing a rmw

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 80002ca6a6ebe..2da2468f555ec 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1436,6 +1436,11 @@ void intel_psr_resume(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 }
 
+static inline u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
+{
+	return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
+}
+
 static inline u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
 {
 	return IS_ALDERLAKE_P(dev_priv) ?
@@ -1455,9 +1460,11 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	if (intel_dp->psr.psr2_sel_fetch_enabled)
-		intel_de_rmw(dev_priv,
-			     PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0,
-			     man_trk_ctl_single_full_frame_bit_get(dev_priv));
+		intel_de_write(dev_priv,
+			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+			       man_trk_ctl_enable_bit_get(dev_priv) |
+			       man_trk_ctl_partial_frame_bit_get(dev_priv) |
+			       man_trk_ctl_single_full_frame_bit_get(dev_priv));
 
 	/*
 	 * Display WA #0884: skl+
@@ -1554,10 +1561,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 val = 0;
-
-	if (!IS_ALDERLAKE_P(dev_priv))
-		val = PSR2_MAN_TRK_CTL_ENABLE;
+	u32 val = man_trk_ctl_enable_bit_get(dev_priv);
 
 	/* SF partial frame enable has to be set even on full update */
 	val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
-- 
2.35.1

[Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates

[José Roberto de Souza]

Frontbuffer rendering and page flips can race with each other
and this can potentialy cause issues with PSR2 selective fetch.

And because pipe/crtc updates are time sentive we can't grab the
PSR lock after intel_pipe_update_start() and before
intel_pipe_update_end().

So here adding the lock and unlock functions and calls, the
proper PSR2 selective fetch handling will come in a separated patch.

Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c |  6 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 69 ++++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_psr.h  |  5 +-
 3 files changed, 70 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index f655c16228776..a5439182d5ae4 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -507,6 +507,8 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
 						      VBLANK_EVASION_TIME_US);
 	max = vblank_start - 1;
 
+	intel_psr_lock(new_crtc_state);
+
 	if (min <= 0 || max <= 0)
 		goto irq_disable;
 
@@ -518,7 +520,7 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
 	 * VBL interrupts will start the PSR exit and prevent a PSR
 	 * re-entry as well.
 	 */
-	intel_psr_wait_for_idle(new_crtc_state);
+	intel_psr_wait_for_idle_locked(new_crtc_state);
 
 	local_irq_disable();
 
@@ -683,6 +685,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 
 	local_irq_enable();
 
+	intel_psr_unlock(new_crtc_state);
+
 	if (intel_vgpu_active(dev_priv))
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2da2468f555ec..58597480054eb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1548,10 +1548,19 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_encoder *encoder;
 
 	if (!crtc_state->enable_psr2_sel_fetch)
 		return;
 
+	for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
+					     crtc_state->uapi.encoder_mask) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		lockdep_assert_held(&intel_dp->psr.lock);
+		break;
+	}
+
 	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
 		       crtc_state->psr2_man_track_ctl);
 }
@@ -1919,13 +1928,13 @@ static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
 }
 
 /**
- * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
+ * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
  * @new_crtc_state: new CRTC state
  *
  * This function is expected to be called from pipe_update_start() where it is
  * not expected to race with PSR enable or disable.
  */
-void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
+void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
 	struct intel_encoder *encoder;
@@ -1938,12 +1947,10 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 		int ret;
 
-		mutex_lock(&intel_dp->psr.lock);
+		lockdep_assert_held(&intel_dp->psr.lock);
 
-		if (!intel_dp->psr.enabled) {
-			mutex_unlock(&intel_dp->psr.lock);
+		if (!intel_dp->psr.enabled)
 			continue;
-		}
 
 		if (intel_dp->psr.psr2_enabled)
 			ret = _psr2_ready_for_pipe_update_locked(intel_dp);
@@ -1952,8 +1959,6 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
 
 		if (ret)
 			drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
-
-		mutex_unlock(&intel_dp->psr.lock);
 	}
 }
 
@@ -2444,3 +2449,51 @@ bool intel_psr_enabled(struct intel_dp *intel_dp)
 
 	return ret;
 }
+
+/**
+ * intel_psr_lock - grab psr.lock mutex
+ * @crtc_state: the crtc state
+ *
+ * This is initially meant to be used by around CRTC update, when
+ * vblank sensitive registers are updated and we need grab the lock
+ * before it to avoid vblank evasion.
+ */
+void intel_psr_lock(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_encoder *encoder;
+
+	if (!crtc_state->has_psr)
+		return;
+
+	for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
+					     crtc_state->uapi.encoder_mask) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		mutex_lock(&intel_dp->psr.lock);
+		break;
+	}
+}
+
+/**
+ * intel_psr_lock - grab psr.lock mutex
+ * @crtc_state: the crtc state
+ *
+ * Release the PSR lock that was held during pipe update.
+ */
+void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_encoder *encoder;
+
+	if (!crtc_state->has_psr)
+		return;
+
+	for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
+					     crtc_state->uapi.encoder_mask) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		mutex_unlock(&intel_dp->psr.lock);
+		break;
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index f6526d9ccfdc6..2ac3a46cccc50 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -41,7 +41,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 			  struct intel_crtc_state *pipe_config);
 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
-void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
+void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
 bool intel_psr_enabled(struct intel_dp *intel_dp);
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc);
@@ -55,4 +55,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
 void intel_psr_pause(struct intel_dp *intel_dp);
 void intel_psr_resume(struct intel_dp *intel_dp);
 
+void intel_psr_lock(const struct intel_crtc_state *crtc_state);
+void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_PSR_H__ */
-- 
2.35.1

[Intel-gfx] [PATCH 3/3] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

[José Roberto de Souza]

Instead of exit PSR when a frontbuffer invalidation happens, we can
enable the PSR2 selective fetch continuous full frame, that will keep
the panel updated like PSR was disabled but without keeping PSR active.

So as soon as the frontbuffer flush happens we can disable the
continuous full frame and start to do selective fetches much quicker
than the path that would enable PSR, that will wait a few frames
to actually activate PSR.

Also this approach has proven to fix some glitches found in Alderlake-P
when there are a lot of invalidations happening together with page
flips.

Some may ask why it is writing to CURSURFLIVE(), it is because
that is the way that hardware team provided us to poke display to
handle PSR updates, and it is being used since display 9.

v2:
- handling possible race conditions between frontbuffer rendering and
page flips

Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
Cc: Shawn C Lee <shawn.c.lee@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 88 ++++++++++++++++---
 2 files changed, 77 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 96024f7d839d4..cfd042117b109 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1525,6 +1525,7 @@ struct intel_psr {
 	bool colorimetry_support;
 	bool psr2_enabled;
 	bool psr2_sel_fetch_enabled;
+	bool psr2_sel_fetch_cff_enabled;
 	bool req_psr2_sdp_prior_scanline;
 	u8 sink_sync_latency;
 	ktime_t last_entry_attempt;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 58597480054eb..5b1963b7743dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1221,6 +1221,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	intel_dp->psr.dc3co_exit_delay = val;
 	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
 	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 	intel_dp->psr.req_psr2_sdp_prior_scanline =
 		crtc_state->req_psr2_sdp_prior_scanline;
 
@@ -1455,6 +1456,13 @@ static inline u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
 	       PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
 }
 
+static inline u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
+{
+	return IS_ALDERLAKE_P(dev_priv) ?
+	       ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
+	       PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
+}
+
 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1558,6 +1566,8 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		lockdep_assert_held(&intel_dp->psr.lock);
+		if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
+			return;
 		break;
 	}
 
@@ -2135,6 +2145,27 @@ static void intel_psr_work(struct work_struct *work)
 	mutex_unlock(&intel_dp->psr.lock);
 }
 
+static void _psr_invalidate_handle(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (intel_dp->psr.psr2_sel_fetch_enabled) {
+		u32 val;
+
+		if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
+			return;
+
+		val = man_trk_ctl_enable_bit_get(dev_priv) |
+		      man_trk_ctl_partial_frame_bit_get(dev_priv) |
+		      man_trk_ctl_continuos_full_frame(dev_priv);
+		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);
+		intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+		intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
+	} else {
+		intel_psr_exit(intel_dp);
+	}
+}
+
 /**
  * intel_psr_invalidate - Invalidade PSR
  * @dev_priv: i915 device
@@ -2171,7 +2202,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv,
 		intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
 
 		if (pipe_frontbuffer_bits)
-			intel_psr_exit(intel_dp);
+			_psr_invalidate_handle(intel_dp);
 
 		mutex_unlock(&intel_dp->psr.lock);
 	}
@@ -2203,6 +2234,42 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
 			 intel_dp->psr.dc3co_exit_delay);
 }
 
+static void _psr_flush_handle(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (intel_dp->psr.psr2_sel_fetch_enabled) {
+		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
+			/* can we turn CFF off? */
+			if (intel_dp->psr.busy_frontbuffer_bits == 0) {
+				u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
+					  man_trk_ctl_partial_frame_bit_get(dev_priv) |
+					  man_trk_ctl_single_full_frame_bit_get(dev_priv);
+
+				/*
+				 * turn continuous full frame off and do a single
+				 * full frame
+				 */
+				intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+					       val);
+				intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+				intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
+			}
+		} else {
+			/*
+			 * continuous full frame is disabled, only a single full
+			 * frame is required
+			 */
+			psr_force_hw_tracking_exit(intel_dp);
+		}
+	} else {
+		psr_force_hw_tracking_exit(intel_dp);
+
+		if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
+			schedule_work(&intel_dp->psr.work);
+	}
+}
+
 /**
  * intel_psr_flush - Flush PSR
  * @dev_priv: i915 device
@@ -2240,25 +2307,22 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 		 * we have to ensure that the PSR is not activated until
 		 * intel_psr_resume() is called.
 		 */
-		if (intel_dp->psr.paused) {
-			mutex_unlock(&intel_dp->psr.lock);
-			continue;
-		}
+		if (intel_dp->psr.paused)
+			goto unlock;
 
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
 			tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
-			mutex_unlock(&intel_dp->psr.lock);
-			continue;
+			goto unlock;
 		}
 
-		/* By definition flush = invalidate + flush */
-		if (pipe_frontbuffer_bits)
-			psr_force_hw_tracking_exit(intel_dp);
+		if (pipe_frontbuffer_bits == 0)
+			goto unlock;
 
-		if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
-			schedule_work(&intel_dp->psr.work);
+		/* By definition flush = invalidate + flush */
+		_psr_flush_handle(intel_dp);
+unlock:
 		mutex_unlock(&intel_dp->psr.lock);
 	}
 }
-- 
2.35.1

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
URL   : https://patchwork.freedesktop.org/series/102095/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_psr.c:2549: warning: expecting prototype for intel_psr_lock(). Prototype was for intel_psr_unlock() instead
./drivers/gpu/drm/i915/display/intel_psr.c:2549: warning: expecting prototype for intel_psr_lock(). Prototype was for intel_psr_unlock() instead

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8797 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
URL   : https://patchwork.freedesktop.org/series/102095/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11440 -> Patchwork_22762
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/index.html

Participating hosts (46 -> 42)
------------------------------

  Additional (2): fi-kbl-soraka bat-rpls-2 
  Missing    (6): shard-tglu bat-dg2-8 fi-bsw-cyan fi-icl-u2 shard-rkl fi-bdw-samus 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22762:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - {bat-adlp-6}:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
Known issues
------------

  Here are the changes found in Patchwork_22762 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-hsw-4770:        NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-compute0:
    - fi-blb-e6850:       NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-blb-e6850/igt@amdgpu/amd_cs_nop@fork-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-rkl-11600:       [PASS][6] -> [INCOMPLETE][7] ([i915#5127])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [PASS][11] -> [INCOMPLETE][12] ([i915#4785])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-hsw-g3258:       NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#1436] / [i915#4312])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-g3258/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-blb-e6850:       [FAIL][16] ([i915#3194]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - {bat-adlm-1}:       [INCOMPLETE][18] -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlm-1/igt@i915_pm_rpm@basic-pci-d3-state.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/bat-adlm-1/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [INCOMPLETE][20] ([i915#4785]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [DMESG-FAIL][22] ([i915#4528]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-blb-e6850/igt@i915_selftest@live@requests.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - fi-tgl-u2:          [DMESG-WARN][24] ([i915#402]) -> [PASS][25] +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@kms_force_connector_basic@force-connector-state:
    - {bat-adlp-6}:       [DMESG-WARN][26] ([i915#3576]) -> [PASS][27] +2 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlp-6/igt@kms_force_connector_basic@force-connector-state.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/bat-adlp-6/igt@kms_force_connector_basic@force-connector-state.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
  [i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
  [i915#5306]: https://gitlab.freedesktop.org/drm/intel/issues/5306
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11440 -> Patchwork_22762

  CI-20190529: 20190529
  CI_DRM_11440: 1aba80b3bc8c8e2cc405cd96fe95770ecbadde71 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6405: 50f7bc405cc1411f57855ed23322c6c4d2510b58 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22762: ac61bb38d8b281ab747c5751b29b6f01517d564f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ac61bb38d8b2 drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations
32ec58c2f835 drm/i915/display/psr: Lock and unlock PSR around pipe updates
47158021485f drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/index.html

[-- Attachment #2: Type: text/html, Size: 10062 bytes --]

Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates

[kernel test robot]

Hi "José,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on v5.17 next-20220401]
[cannot apply to drm-intel/for-linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a011 (https://download.01.org/0day-ci/archive/20220402/202204020818.qEzCpUjb-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.2.0-19) 11.2.0
reproduce (this is a W=1 build):
        # https://github.com/intel-lab-lkp/linux/commit/955b4bf1a2fd2e6652980814983464f3db8f955f
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
        git checkout 955b4bf1a2fd2e6652980814983464f3db8f955f
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_psr.c:2485: warning: expecting prototype for intel_psr_lock(). Prototype was for intel_psr_unlock() instead


vim +2485 drivers/gpu/drm/i915/display/intel_psr.c

  2477	
  2478	/**
  2479	 * intel_psr_lock - grab psr.lock mutex
  2480	 * @crtc_state: the crtc state
  2481	 *
  2482	 * Release the PSR lock that was held during pipe update.
  2483	 */
  2484	void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> 2485	{

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates

[kernel test robot]

Hi "José,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on v5.17 next-20220401]
[cannot apply to drm-intel/for-linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a005 (https://download.01.org/0day-ci/archive/20220402/202204020818.P5BApjRe-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project cc2e2b80a1f36a28fa7c96c38c2674b10868f09f)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/955b4bf1a2fd2e6652980814983464f3db8f955f
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
        git checkout 955b4bf1a2fd2e6652980814983464f3db8f955f
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_psr.c:2485: warning: expecting prototype for intel_psr_lock(). Prototype was for intel_psr_unlock() instead


vim +2485 drivers/gpu/drm/i915/display/intel_psr.c

  2477	
  2478	/**
  2479	 * intel_psr_lock - grab psr.lock mutex
  2480	 * @crtc_state: the crtc state
  2481	 *
  2482	 * Release the PSR lock that was held during pipe update.
  2483	 */
  2484	void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> 2485	{

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30327 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
URL   : https://patchwork.freedesktop.org/series/102095/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11440_full -> Patchwork_22762_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_22762_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-tglb:         [PASS][1] -> [TIMEOUT][2] ([i915#3063])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb5/igt@gem_eio@in-flight-contexts-10ms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_eio@kms:
    - shard-tglb:         [PASS][3] -> [FAIL][4] ([i915#232])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb6/igt@gem_eio@kms.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb2/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([i915#4525])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-apl:          NOTRUN -> [FAIL][7] ([i915#2846])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_params@no-blt:
    - shard-tglb:         NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@gem_exec_params@no-blt.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][14] ([i915#180])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-skl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-apl:          NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-kbl:          NOTRUN -> [WARN][17] ([i915#2658])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl3/igt@gem_pwrite@basic-exhaustion.html
    - shard-apl:          NOTRUN -> [WARN][18] ([i915#2658])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][19] ([i915#3318])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_userptr_blits@vma-merge.html
    - shard-kbl:          NOTRUN -> [FAIL][20] ([i915#3318])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-apl:          [PASS][21] -> [DMESG-WARN][22] ([i915#1436])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-apl7/igt@gem_workarounds@suspend-resume-fd.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl6/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-apl6/igt@gen9_exec_parse@allowed-all.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl2/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([i915#4281])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][27] -> [INCOMPLETE][28] ([i915#3921])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-snb5/igt@i915_selftest@live@hangcheck.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-snb2/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-kbl:          NOTRUN -> [SKIP][29] ([fdo#109271]) +121 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
    - shard-glk:          [PASS][30] -> [DMESG-WARN][31] ([i915#118])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-kbl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_joiner@basic:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#2705])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689] / [i915#3886])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +6 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
    - shard-apl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@dp-hpd-after-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@kms_chamelium@dp-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-audio-edid:
    - shard-kbl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl3/igt@kms_chamelium@hdmi-audio-edid.html
    - shard-skl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@kms_chamelium@hdmi-audio-edid.html

  * igt@kms_color_chamelium@pipe-a-ctm-limited-range:
    - shard-apl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][44] -> [DMESG-WARN][45] ([i915#180]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-iclb:         [PASS][46] -> [FAIL][47] ([i915#2346])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
    - shard-glk:          [PASS][48] -> [FAIL][49] ([i915#2346] / [i915#533])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-skl:          [PASS][50] -> [FAIL][51] ([i915#2346])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
    - shard-skl:          [PASS][52] -> [DMESG-WARN][53] ([i915#1982]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [PASS][54] -> [FAIL][55] ([i915#2122])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][56] ([i915#3614])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          NOTRUN -> [FAIL][57] ([i915#2122])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-iclb:         [PASS][58] -> [SKIP][59] ([i915#3701]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
    - shard-skl:          [PASS][60] -> [FAIL][61] ([i915#1188])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl4/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl8/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#533])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-skl:          [PASS][63] -> [INCOMPLETE][64] ([i915#4939])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-skl:          NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][66] -> [FAIL][67] ([fdo#108145] / [i915#265])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#111615])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-skl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][72] -> [SKIP][73] ([fdo#109441])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb2/igt@kms_psr@psr2_basic.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb6/igt@kms_psr@psr2_basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][74] ([IGT#2])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-apl:          [PASS][75] -> [DMESG-WARN][76] ([i915#180]) +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-kbl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
    - shard-apl:          NOTRUN -> [SKIP][79] ([fdo#109271]) +90 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html

  * igt@nouveau_crc@pipe-d-source-outp-complete:
    - shard-skl:          NOTRUN -> [SKIP][80] ([fdo#109271]) +37 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@nouveau_crc@pipe-d-source-outp-complete.html

  * igt@sysfs_clients@fair-1:
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994]) +2 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@sysfs_clients@fair-1.html

  * igt@sysfs_clients@sema-25:
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994]) +3 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@sysfs_clients@sema-25.html

  * igt@sysfs_clients@split-50:
    - shard-skl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl1/igt@sysfs_clients@split-50.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][84] ([i915#2846]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-glk3/igt@gem_exec_fair@basic-deadline.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-glk2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][86] ([i915#2842]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          [FAIL][88] ([i915#2842]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-glk:          [FAIL][90] ([i915#2842]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-tglb:         [FAIL][92] ([i915#2842]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][94] ([i915#2849]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
    - shard-glk:          [DMESG-WARN][96] ([i915#118]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-glk3/igt@gem_exec_whisper@basic-contexts-priority-all.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-glk2/igt@gem_exec_whisper@basic-contexts-priority-all.html

  * igt@i915_pm_dc@dc6-dpms:
    - {shard-tglu}:       [FAIL][98] ([i915#454]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglu-6/igt@i915_pm_dc@dc6-dpms.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglu-4/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][100] ([i915#454]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb5/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [INCOMPLETE][102] ([i915#2828]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-iclb:         [FAIL][104] ([i915#2346]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
    - shard-glk:          [FAIL][106] ([i915#2346]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [FAIL][108] ([i915#2346]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [FAIL][110] ([i915#79]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +8 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a:
    - shard-apl:          [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +2 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-apl2/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html

  * igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format:
    - shard-iclb:         [INCOMPLETE][116] ([i915#5293]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb7/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][118] ([fdo#109441]) -> [PASS][119] +2 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-a-accuracy-idle:
    - shard-skl:          [FAIL][120] ([i915#43]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl3/igt@kms_vblank@pipe-a-accuracy-idle.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl10/igt@kms_vblank@pipe-a-accuracy-idle.html

  * igt@perf_pmu@module-unload:
    - shard-iclb:         [DMESG-WARN][122] ([i915#262] / [i915#2867]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb4/igt@perf_pmu@module-unload.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb8/igt@perf_pmu@module-unload.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [SKIP][124] ([i915#4525]) -> [DMESG-WARN][125] ([i915#5076])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb3/igt@gem_exec_balancer@parallel.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb1/igt@gem_exec_balancer@parallel.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][126] ([i915#2684]) -> [WARN][127] ([i915#1804] / [i915#2684])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs:
    - shard-skl:          [SKIP][128] ([fdo#109271] / [i915#1888]) -> [SKIP][129] ([fdo#109271])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl9/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_color@pipe-d-ctm-green-to-red:
    - shard-skl:          [SKIP][130] ([fdo#109271]) -> [SKIP][131] ([fdo#109271] / [i915#1888])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-skl9/igt@kms_color@pipe-d-ctm-green-to-red.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl6/igt@kms_color@pipe-d-ctm-green-to-red.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          [DMESG-WARN][132] ([i915#180]) -> [DMESG-WARN][133] ([i915#180] / [i915#1982])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-iclb:         [SKIP][134] ([fdo#111068] / [i915#658]) -> [SKIP][135] ([i915#2920])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#602]) -> ([FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#602])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl7/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl6/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl6/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl6/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl7/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl7/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl1/igt@runner@aborted.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl1/igt@runner@aborted.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl1/igt@runner@aborted.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl4/igt@runner@

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/index.html

[-- Attachment #2: Type: text/html, Size: 33795 bytes --]

Re: [Intel-gfx] [PATCH 3/3] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

[Hogander, Jouni]

Hello Jose,

One inline comment below...

On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> Instead of exit PSR when a frontbuffer invalidation happens, we can
> enable the PSR2 selective fetch continuous full frame, that will keep
> the panel updated like PSR was disabled but without keeping PSR
> active.

Probably this is nitpicking, but this is wrong. It's not like "PSR was
disabled" It's relying on that something is triggering the flip. There
is no full frame update sent unless you write 0 to CURSRUFLIVE. That is
also triggering only one update. Next one is sent in flush (or if there
is flip triggered by atomic commit in between). I see this as
important, because the workaround looks quite different when this is
understood.

Original invalidate callback is disabling PSR which makes full frame
updates sent on every VBLANK until there is flush callback.

As we are anyways targeting to get rid of these invalidates and rely
only on dirtyfb callback this approach is kind a step into right
direction. If it's not causing any harm and seems to be WA for some PSR
issue:

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>


> So as soon as the frontbuffer flush happens we can disable the
> continuous full frame and start to do selective fetches much quicker
> than the path that would enable PSR, that will wait a few frames
> to actually activate PSR.
> 
> Also this approach has proven to fix some glitches found in
> Alderlake-P
> when there are a lot of invalidations happening together with page
> flips.
> 
> Some may ask why it is writing to CURSURFLIVE(), it is because
> that is the way that hardware team provided us to poke display to
> handle PSR updates, and it is being used since display 9.
> 
> v2:
> - handling possible race conditions between frontbuffer rendering and
> page flips
> 
> Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
> Cc: Shawn C Lee <shawn.c.lee@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 88 ++++++++++++++++-
> --
>  2 files changed, 77 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 96024f7d839d4..cfd042117b109 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1525,6 +1525,7 @@ struct intel_psr {
>  	bool colorimetry_support;
>  	bool psr2_enabled;
>  	bool psr2_sel_fetch_enabled;
> +	bool psr2_sel_fetch_cff_enabled;
>  	bool req_psr2_sdp_prior_scanline;
>  	u8 sink_sync_latency;
>  	ktime_t last_entry_attempt;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 58597480054eb..5b1963b7743dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1221,6 +1221,7 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
>  	intel_dp->psr.dc3co_exit_delay = val;
>  	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
>  	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> >enable_psr2_sel_fetch;
> +	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
>  	intel_dp->psr.req_psr2_sdp_prior_scanline =
>  		crtc_state->req_psr2_sdp_prior_scanline;
>  
> @@ -1455,6 +1456,13 @@ static inline u32
> man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
>  	       PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
>  }
>  
> +static inline u32 man_trk_ctl_continuos_full_frame(struct
> drm_i915_private *dev_priv)
> +{
> +	return IS_ALDERLAKE_P(dev_priv) ?
> +	       ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
> +	       PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> +}
> +
>  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1558,6 +1566,8 @@ void intel_psr2_program_trans_man_trk_ctl(const
> struct intel_crtc_state *crtc_st
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
>  		lockdep_assert_held(&intel_dp->psr.lock);
> +		if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
> +			return;
>  		break;
>  	}
>  
> @@ -2135,6 +2145,27 @@ static void intel_psr_work(struct work_struct
> *work)
>  	mutex_unlock(&intel_dp->psr.lock);
>  }
>  
> +static void _psr_invalidate_handle(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (intel_dp->psr.psr2_sel_fetch_enabled) {
> +		u32 val;
> +
> +		if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
> +			return;
> +
> +		val = man_trk_ctl_enable_bit_get(dev_priv) |
> +		      man_trk_ctl_partial_frame_bit_get(dev_priv) |
> +		      man_trk_ctl_continuos_full_frame(dev_priv);
> +		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder), val);
> +		intel_de_write(dev_priv, CURSURFLIVE(intel_dp-
> >psr.pipe), 0);
> +		intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
> +	} else {
> +		intel_psr_exit(intel_dp);
> +	}
> +}
> +
>  /**
>   * intel_psr_invalidate - Invalidade PSR
>   * @dev_priv: i915 device
> @@ -2171,7 +2202,7 @@ void intel_psr_invalidate(struct
> drm_i915_private *dev_priv,
>  		intel_dp->psr.busy_frontbuffer_bits |=
> pipe_frontbuffer_bits;
>  
>  		if (pipe_frontbuffer_bits)
> -			intel_psr_exit(intel_dp);
> +			_psr_invalidate_handle(intel_dp);
>  
>  		mutex_unlock(&intel_dp->psr.lock);
>  	}
> @@ -2203,6 +2234,42 @@ tgl_dc3co_flush_locked(struct intel_dp
> *intel_dp, unsigned int frontbuffer_bits,
>  			 intel_dp->psr.dc3co_exit_delay);
>  }
>  
> +static void _psr_flush_handle(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (intel_dp->psr.psr2_sel_fetch_enabled) {
> +		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
> +			/* can we turn CFF off? */
> +			if (intel_dp->psr.busy_frontbuffer_bits == 0) {
> +				u32 val =
> man_trk_ctl_enable_bit_get(dev_priv) |
> +					  man_trk_ctl_partial_frame_bit
> _get(dev_priv) |
> +					  man_trk_ctl_single_full_frame
> _bit_get(dev_priv);
> +
> +				/*
> +				 * turn continuous full frame off and
> do a single
> +				 * full frame
> +				 */
> +				intel_de_write(dev_priv,
> PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +					       val);
> +				intel_de_write(dev_priv,
> CURSURFLIVE(intel_dp->psr.pipe), 0);
> +				intel_dp-
> >psr.psr2_sel_fetch_cff_enabled = false;
> +			}
> +		} else {
> +			/*
> +			 * continuous full frame is disabled, only a
> single full
> +			 * frame is required
> +			 */
> +			psr_force_hw_tracking_exit(intel_dp);
> +		}
> +	} else {
> +		psr_force_hw_tracking_exit(intel_dp);
> +
> +		if (!intel_dp->psr.active && !intel_dp-
> >psr.busy_frontbuffer_bits)
> +			schedule_work(&intel_dp->psr.work);
> +	}
> +}
> +
>  /**
>   * intel_psr_flush - Flush PSR
>   * @dev_priv: i915 device
> @@ -2240,25 +2307,22 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
>  		 * we have to ensure that the PSR is not activated
> until
>  		 * intel_psr_resume() is called.
>  		 */
> -		if (intel_dp->psr.paused) {
> -			mutex_unlock(&intel_dp->psr.lock);
> -			continue;
> -		}
> +		if (intel_dp->psr.paused)
> +			goto unlock;
>  
>  		if (origin == ORIGIN_FLIP ||
>  		    (origin == ORIGIN_CURSOR_UPDATE &&
>  		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
>  			tgl_dc3co_flush_locked(intel_dp,
> frontbuffer_bits, origin);
> -			mutex_unlock(&intel_dp->psr.lock);
> -			continue;
> +			goto unlock;
>  		}
>  
> -		/* By definition flush = invalidate + flush */
> -		if (pipe_frontbuffer_bits)
> -			psr_force_hw_tracking_exit(intel_dp);
> +		if (pipe_frontbuffer_bits == 0)
> +			goto unlock;
>  
> -		if (!intel_dp->psr.active && !intel_dp-
> >psr.busy_frontbuffer_bits)
> -			schedule_work(&intel_dp->psr.work);
> +		/* By definition flush = invalidate + flush */
> +		_psr_flush_handle(intel_dp);
> +unlock:
>  		mutex_unlock(&intel_dp->psr.lock);
>  	}
>  }

Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[Hogander, Jouni]

On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
> "SF Partial Frame Enable" also on full update") and also setting
> partial frame enable when psr_force_hw_tracking_exit() is called.
> 
> Also as PSR2_MAN_TRK_CTL is a double buffered registers do a RMW
> is not a good idea so here also setting the man_trk_ctl_enable_bit()
> that is required in TGL and only doing a register write.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> 
> v2:
> - not doing a rmw
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 80002ca6a6ebe..2da2468f555ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1436,6 +1436,11 @@ void intel_psr_resume(struct intel_dp
> *intel_dp)
>  	mutex_unlock(&psr->lock);
>  }
>  
> +static inline u32 man_trk_ctl_enable_bit_get(struct drm_i915_private
> *dev_priv)
> +{
> +	return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
> +}
> +
>  static inline u32 man_trk_ctl_single_full_frame_bit_get(struct
> drm_i915_private *dev_priv)
>  {
>  	return IS_ALDERLAKE_P(dev_priv) ?
> @@ -1455,9 +1460,11 @@ static void psr_force_hw_tracking_exit(struct
> intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
>  	if (intel_dp->psr.psr2_sel_fetch_enabled)
> -		intel_de_rmw(dev_priv,
> -			     PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder), 0,
> -			     man_trk_ctl_single_full_frame_bit_get(dev_
> priv));
> +		intel_de_write(dev_priv,
> +			       PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder),
> +			       man_trk_ctl_enable_bit_get(dev_priv) |
> +			       man_trk_ctl_partial_frame_bit_get(dev_pr
> iv) |
> +			       man_trk_ctl_single_full_frame_bit_get(de
> v_priv));
>  
>  	/*
>  	 * Display WA #0884: skl+
> @@ -1554,10 +1561,7 @@ static void psr2_man_trk_ctl_calc(struct
> intel_crtc_state *crtc_state,
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 val = 0;
> -
> -	if (!IS_ALDERLAKE_P(dev_priv))
> -		val = PSR2_MAN_TRK_CTL_ENABLE;
> +	u32 val = man_trk_ctl_enable_bit_get(dev_priv);
>  
>  	/* SF partial frame enable has to be set even on full update */
>  	val |= man_trk_ctl_partial_frame_bit_get(dev_priv);

Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates

[Hogander, Jouni]

Hello,

Couple of questions below.
On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> Frontbuffer rendering and page flips can race with each other
> and this can potentialy cause issues with PSR2 selective fetch.
> 
> And because pipe/crtc updates are time sentive we can't grab the
> PSR lock after intel_pipe_update_start() and before
> intel_pipe_update_end().
> 
> So here adding the lock and unlock functions and calls, the
> proper PSR2 selective fetch handling will come in a separated patch.
> 

Have you ensured that there is no case where pipe_update_end is not
called?

Why did you choose to add new hooks instead of using existing
intel_psr_pre_plane_update and intel_psr_post_plane_update?
 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c |  6 +-
>  drivers/gpu/drm/i915/display/intel_psr.c  | 69 ++++++++++++++++++++-
> --
>  drivers/gpu/drm/i915/display/intel_psr.h  |  5 +-
>  3 files changed, 70 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index f655c16228776..a5439182d5ae4 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -507,6 +507,8 @@ void intel_pipe_update_start(struct
> intel_crtc_state *new_crtc_state)
>  						      VBLANK_EVASION_TI
> ME_US);
>  	max = vblank_start - 1;
>  
> +	intel_psr_lock(new_crtc_state);
> +
>  	if (min <= 0 || max <= 0)
>  		goto irq_disable;
>  
> @@ -518,7 +520,7 @@ void intel_pipe_update_start(struct
> intel_crtc_state *new_crtc_state)
>  	 * VBL interrupts will start the PSR exit and prevent a PSR
>  	 * re-entry as well.
>  	 */
> -	intel_psr_wait_for_idle(new_crtc_state);
> +	intel_psr_wait_for_idle_locked(new_crtc_state);
>  
>  	local_irq_disable();
>  
> @@ -683,6 +685,8 @@ void intel_pipe_update_end(struct
> intel_crtc_state *new_crtc_state)
>  
>  	local_irq_enable();
>  
> +	intel_psr_unlock(new_crtc_state);
> +
>  	if (intel_vgpu_active(dev_priv))
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2da2468f555ec..58597480054eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1548,10 +1548,19 @@ void
> intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
>  void intel_psr2_program_trans_man_trk_ctl(const struct
> intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >uapi.crtc->dev);
> +	struct intel_encoder *encoder;
>  
>  	if (!crtc_state->enable_psr2_sel_fetch)
>  		return;
>  
> +	for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
> +					     crtc_state-
> >uapi.encoder_mask) {
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		lockdep_assert_held(&intel_dp->psr.lock);
> +		break;
> +	}
> +
>  	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> >cpu_transcoder),
>  		       crtc_state->psr2_man_track_ctl);
>  }
> @@ -1919,13 +1928,13 @@ static int
> _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
>  }
>  
>  /**
> - * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
> + * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe
> update
>   * @new_crtc_state: new CRTC state
>   *
>   * This function is expected to be called from pipe_update_start()
> where it is
>   * not expected to race with PSR enable or disable.
>   */
> -void intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state)
> +void intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> *new_crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(new_crtc_state-
> >uapi.crtc->dev);
>  	struct intel_encoder *encoder;
> @@ -1938,12 +1947,10 @@ void intel_psr_wait_for_idle(const struct
> intel_crtc_state *new_crtc_state)
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  		int ret;
>  
> -		mutex_lock(&intel_dp->psr.lock);
> +		lockdep_assert_held(&intel_dp->psr.lock);
>  
> -		if (!intel_dp->psr.enabled) {
> -			mutex_unlock(&intel_dp->psr.lock);
> +		if (!intel_dp->psr.enabled)
>  			continue;
> -		}
>  
>  		if (intel_dp->psr.psr2_enabled)
>  			ret =
> _psr2_ready_for_pipe_update_locked(intel_dp);
> @@ -1952,8 +1959,6 @@ void intel_psr_wait_for_idle(const struct
> intel_crtc_state *new_crtc_state)
>  
>  		if (ret)
>  			drm_err(&dev_priv->drm, "PSR wait timed out,
> atomic update may fail\n");
> -
> -		mutex_unlock(&intel_dp->psr.lock);
>  	}
>  }
>  
> @@ -2444,3 +2449,51 @@ bool intel_psr_enabled(struct intel_dp
> *intel_dp)
>  
>  	return ret;
>  }
> +
> +/**
> + * intel_psr_lock - grab psr.lock mutex
> + * @crtc_state: the crtc state
> + *
> + * This is initially meant to be used by around CRTC update, when
> + * vblank sensitive registers are updated and we need grab the lock
> + * before it to avoid vblank evasion.
> + */
> +void intel_psr_lock(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc-
> >dev);
> +	struct intel_encoder *encoder;
> +
> +	if (!crtc_state->has_psr)
> +		return;
> +
> +	for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
> +					     crtc_state-
> >uapi.encoder_mask) {
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		mutex_lock(&intel_dp->psr.lock);
> +		break;
> +	}
> +}
> +
> +/**
> + * intel_psr_lock - grab psr.lock mutex
> + * @crtc_state: the crtc state
> + *
> + * Release the PSR lock that was held during pipe update.
> + */
> +void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc-
> >dev);
> +	struct intel_encoder *encoder;
> +
> +	if (!crtc_state->has_psr)
> +		return;
> +
> +	for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
> +					     crtc_state-
> >uapi.encoder_mask) {
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> +		mutex_unlock(&intel_dp->psr.lock);
> +		break;
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index f6526d9ccfdc6..2ac3a46cccc50 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -41,7 +41,7 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,
>  			  struct intel_crtc_state *pipe_config);
>  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
>  void intel_psr_short_pulse(struct intel_dp *intel_dp);
> -void intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state);
> +void intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> *new_crtc_state);
>  bool intel_psr_enabled(struct intel_dp *intel_dp);
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc);
> @@ -55,4 +55,7 @@ void intel_psr2_disable_plane_sel_fetch(struct
> intel_plane *plane,
>  void intel_psr_pause(struct intel_dp *intel_dp);
>  void intel_psr_resume(struct intel_dp *intel_dp);
>  
> +void intel_psr_lock(const struct intel_crtc_state *crtc_state);
> +void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
> +
>  #endif /* __INTEL_PSR_H__ */

Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

[Jani Nikula]

On Fri, 01 Apr 2022, José Roberto de Souza <jose.souza@intel.com> wrote:
> Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
> "SF Partial Frame Enable" also on full update") and also setting
> partial frame enable when psr_force_hw_tracking_exit() is called.
>
> Also as PSR2_MAN_TRK_CTL is a double buffered registers do a RMW
> is not a good idea so here also setting the man_trk_ctl_enable_bit()
> that is required in TGL and only doing a register write.
>
> v2:
> - not doing a rmw
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 80002ca6a6ebe..2da2468f555ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1436,6 +1436,11 @@ void intel_psr_resume(struct intel_dp *intel_dp)
>  	mutex_unlock(&psr->lock);
>  }
>  
> +static inline u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)

As a rule of thumb, please don't use static inline in .c files, just let
the compiler do its job.

If that ever becomes unused, you won't get any error messages about it.

BR,
Jani.

> +{
> +	return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
> +}
> +
>  static inline u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
>  {
>  	return IS_ALDERLAKE_P(dev_priv) ?
> @@ -1455,9 +1460,11 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
>  	if (intel_dp->psr.psr2_sel_fetch_enabled)
> -		intel_de_rmw(dev_priv,
> -			     PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0,
> -			     man_trk_ctl_single_full_frame_bit_get(dev_priv));
> +		intel_de_write(dev_priv,
> +			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +			       man_trk_ctl_enable_bit_get(dev_priv) |
> +			       man_trk_ctl_partial_frame_bit_get(dev_priv) |
> +			       man_trk_ctl_single_full_frame_bit_get(dev_priv));
>  
>  	/*
>  	 * Display WA #0884: skl+
> @@ -1554,10 +1561,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 val = 0;
> -
> -	if (!IS_ALDERLAKE_P(dev_priv))
> -		val = PSR2_MAN_TRK_CTL_ENABLE;
> +	u32 val = man_trk_ctl_enable_bit_get(dev_priv);
>  
>  	/* SF partial frame enable has to be set even on full update */
>  	val |= man_trk_ctl_partial_frame_bit_get(dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates

[Souza, Jose]

On Mon, 2022-04-04 at 07:41 +0000, Hogander, Jouni wrote:
> Hello,
> 
> Couple of questions below.
> On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> > Frontbuffer rendering and page flips can race with each other
> > and this can potentialy cause issues with PSR2 selective fetch.
> > 
> > And because pipe/crtc updates are time sentive we can't grab the
> > PSR lock after intel_pipe_update_start() and before
> > intel_pipe_update_end().
> > 
> > So here adding the lock and unlock functions and calls, the
> > proper PSR2 selective fetch handling will come in a separated patch.
> > 
> 
> Have you ensured that there is no case where pipe_update_end is not
> called?

Yep.

> 
> Why did you choose to add new hooks instead of using existing
> intel_psr_pre_plane_update and intel_psr_post_plane_update?

The lock would be held for too much time we those functions were used.
In a modeset case it would take the lock before disable CRTC and only would release a way after pipes are enabled.

If in the mean time something needs the PSR lock it would be blocked for a few milliseconds while here would be very small window of time.

> 
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_crtc.c |  6 +-
> >  drivers/gpu/drm/i915/display/intel_psr.c  | 69 ++++++++++++++++++++-
> > --
> >  drivers/gpu/drm/i915/display/intel_psr.h  |  5 +-
> >  3 files changed, 70 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index f655c16228776..a5439182d5ae4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -507,6 +507,8 @@ void intel_pipe_update_start(struct
> > intel_crtc_state *new_crtc_state)
> >                                                     VBLANK_EVASION_TI
> > ME_US);
> >       max = vblank_start - 1;
> > 
> > +     intel_psr_lock(new_crtc_state);
> > +
> >       if (min <= 0 || max <= 0)
> >               goto irq_disable;
> > 
> > @@ -518,7 +520,7 @@ void intel_pipe_update_start(struct
> > intel_crtc_state *new_crtc_state)
> >        * VBL interrupts will start the PSR exit and prevent a PSR
> >        * re-entry as well.
> >        */
> > -     intel_psr_wait_for_idle(new_crtc_state);
> > +     intel_psr_wait_for_idle_locked(new_crtc_state);
> > 
> >       local_irq_disable();
> > 
> > @@ -683,6 +685,8 @@ void intel_pipe_update_end(struct
> > intel_crtc_state *new_crtc_state)
> > 
> >       local_irq_enable();
> > 
> > +     intel_psr_unlock(new_crtc_state);
> > +
> >       if (intel_vgpu_active(dev_priv))
> >               return;
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 2da2468f555ec..58597480054eb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1548,10 +1548,19 @@ void
> > intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state)
> >  {
> >       struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > > uapi.crtc->dev);
> > +     struct intel_encoder *encoder;
> > 
> >       if (!crtc_state->enable_psr2_sel_fetch)
> >               return;
> > 
> > +     for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
> > +                                          crtc_state-
> > > uapi.encoder_mask) {
> > +             struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > +             lockdep_assert_held(&intel_dp->psr.lock);
> > +             break;
> > +     }
> > +
> >       intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> > > cpu_transcoder),
> >                      crtc_state->psr2_man_track_ctl);
> >  }
> > @@ -1919,13 +1928,13 @@ static int
> > _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> >  }
> > 
> >  /**
> > - * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
> > + * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe
> > update
> >   * @new_crtc_state: new CRTC state
> >   *
> >   * This function is expected to be called from pipe_update_start()
> > where it is
> >   * not expected to race with PSR enable or disable.
> >   */
> > -void intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state)
> > +void intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> > *new_crtc_state)
> >  {
> >       struct drm_i915_private *dev_priv = to_i915(new_crtc_state-
> > > uapi.crtc->dev);
> >       struct intel_encoder *encoder;
> > @@ -1938,12 +1947,10 @@ void intel_psr_wait_for_idle(const struct
> > intel_crtc_state *new_crtc_state)
> >               struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >               int ret;
> > 
> > -             mutex_lock(&intel_dp->psr.lock);
> > +             lockdep_assert_held(&intel_dp->psr.lock);
> > 
> > -             if (!intel_dp->psr.enabled) {
> > -                     mutex_unlock(&intel_dp->psr.lock);
> > +             if (!intel_dp->psr.enabled)
> >                       continue;
> > -             }
> > 
> >               if (intel_dp->psr.psr2_enabled)
> >                       ret =
> > _psr2_ready_for_pipe_update_locked(intel_dp);
> > @@ -1952,8 +1959,6 @@ void intel_psr_wait_for_idle(const struct
> > intel_crtc_state *new_crtc_state)
> > 
> >               if (ret)
> >                       drm_err(&dev_priv->drm, "PSR wait timed out,
> > atomic update may fail\n");
> > -
> > -             mutex_unlock(&intel_dp->psr.lock);
> >       }
> >  }
> > 
> > @@ -2444,3 +2449,51 @@ bool intel_psr_enabled(struct intel_dp
> > *intel_dp)
> > 
> >       return ret;
> >  }
> > +
> > +/**
> > + * intel_psr_lock - grab psr.lock mutex
> > + * @crtc_state: the crtc state
> > + *
> > + * This is initially meant to be used by around CRTC update, when
> > + * vblank sensitive registers are updated and we need grab the lock
> > + * before it to avoid vblank evasion.
> > + */
> > +void intel_psr_lock(const struct intel_crtc_state *crtc_state)
> > +{
> > +     struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc-
> > > dev);
> > +     struct intel_encoder *encoder;
> > +
> > +     if (!crtc_state->has_psr)
> > +             return;
> > +
> > +     for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
> > +                                          crtc_state-
> > > uapi.encoder_mask) {
> > +             struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > +             mutex_lock(&intel_dp->psr.lock);
> > +             break;
> > +     }
> > +}
> > +
> > +/**
> > + * intel_psr_lock - grab psr.lock mutex
> > + * @crtc_state: the crtc state
> > + *
> > + * Release the PSR lock that was held during pipe update.
> > + */
> > +void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> > +{
> > +     struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc-
> > > dev);
> > +     struct intel_encoder *encoder;
> > +
> > +     if (!crtc_state->has_psr)
> > +             return;
> > +
> > +     for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
> > +                                          crtc_state-
> > > uapi.encoder_mask) {
> > +             struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > +             mutex_unlock(&intel_dp->psr.lock);
> > +             break;
> > +     }
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index f6526d9ccfdc6..2ac3a46cccc50 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -41,7 +41,7 @@ void intel_psr_get_config(struct intel_encoder
> > *encoder,
> >                         struct intel_crtc_state *pipe_config);
> >  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
> >  void intel_psr_short_pulse(struct intel_dp *intel_dp);
> > -void intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state);
> > +void intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> > *new_crtc_state);
> >  bool intel_psr_enabled(struct intel_dp *intel_dp);
> >  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> >                               struct intel_crtc *crtc);
> > @@ -55,4 +55,7 @@ void intel_psr2_disable_plane_sel_fetch(struct
> > intel_plane *plane,
> >  void intel_psr_pause(struct intel_dp *intel_dp);
> >  void intel_psr_resume(struct intel_dp *intel_dp);
> > 
> > +void intel_psr_lock(const struct intel_crtc_state *crtc_state);
> > +void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
> > +
> >  #endif /* __INTEL_PSR_H__ */
> 

Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates

[Hogander, Jouni]

On Mon, 2022-04-04 at 13:43 +0000, Souza, Jose wrote:
> On Mon, 2022-04-04 at 07:41 +0000, Hogander, Jouni wrote:
> > Hello,
> > 
> > Couple of questions below.
> > On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> > > Frontbuffer rendering and page flips can race with each other
> > > and this can potentialy cause issues with PSR2 selective fetch.
> > > 
> > > And because pipe/crtc updates are time sentive we can't grab the
> > > PSR lock after intel_pipe_update_start() and before
> > > intel_pipe_update_end().
> > > 
> > > So here adding the lock and unlock functions and calls, the
> > > proper PSR2 selective fetch handling will come in a separated
> > > patch.
> > > 
> > 
> > Have you ensured that there is no case where pipe_update_end is not
> > called?
> 
> Yep.
> 
> > Why did you choose to add new hooks instead of using existing
> > intel_psr_pre_plane_update and intel_psr_post_plane_update?
> 
> The lock would be held for too much time we those functions were
> used.
> In a modeset case it would take the lock before disable CRTC and only
> would release a way after pipes are enabled.
> 
> If in the mean time something needs the PSR lock it would be blocked
> for a few milliseconds while here would be very small window of time.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> 
> > > Cc: Jouni Högander <jouni.hogander@intel.com>
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_crtc.c |  6 +-
> > >  drivers/gpu/drm/i915/display/intel_psr.c  | 69
> > > ++++++++++++++++++++-
> > > --
> > >  drivers/gpu/drm/i915/display/intel_psr.h  |  5 +-
> > >  3 files changed, 70 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > index f655c16228776..a5439182d5ae4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > @@ -507,6 +507,8 @@ void intel_pipe_update_start(struct
> > > intel_crtc_state *new_crtc_state)
> > >                                                     VBLANK_EVASIO
> > > N_TI
> > > ME_US);
> > >       max = vblank_start - 1;
> > > 
> > > +     intel_psr_lock(new_crtc_state);
> > > +
> > >       if (min <= 0 || max <= 0)
> > >               goto irq_disable;
> > > 
> > > @@ -518,7 +520,7 @@ void intel_pipe_update_start(struct
> > > intel_crtc_state *new_crtc_state)
> > >        * VBL interrupts will start the PSR exit and prevent a PSR
> > >        * re-entry as well.
> > >        */
> > > -     intel_psr_wait_for_idle(new_crtc_state);
> > > +     intel_psr_wait_for_idle_locked(new_crtc_state);
> > > 
> > >       local_irq_disable();
> > > 
> > > @@ -683,6 +685,8 @@ void intel_pipe_update_end(struct
> > > intel_crtc_state *new_crtc_state)
> > > 
> > >       local_irq_enable();
> > > 
> > > +     intel_psr_unlock(new_crtc_state);
> > > +
> > >       if (intel_vgpu_active(dev_priv))
> > >               return;
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 2da2468f555ec..58597480054eb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1548,10 +1548,19 @@ void
> > > intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state)
> > >  {
> > >       struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > > > uapi.crtc->dev);
> > > +     struct intel_encoder *encoder;
> > > 
> > >       if (!crtc_state->enable_psr2_sel_fetch)
> > >               return;
> > > 
> > > +     for_each_intel_encoder_mask_with_psr(&dev_priv->drm,
> > > encoder,
> > > +                                          crtc_state-
> > > > uapi.encoder_mask) {
> > > +             struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder);
> > > +
> > > +             lockdep_assert_held(&intel_dp->psr.lock);
> > > +             break;
> > > +     }
> > > +
> > >       intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state-
> > > > cpu_transcoder),
> > >                      crtc_state->psr2_man_track_ctl);
> > >  }
> > > @@ -1919,13 +1928,13 @@ static int
> > > _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> > >  }
> > > 
> > >  /**
> > > - * intel_psr_wait_for_idle - wait for PSR be ready for a pipe
> > > update
> > > + * intel_psr_wait_for_idle_locked - wait for PSR be ready for a
> > > pipe
> > > update
> > >   * @new_crtc_state: new CRTC state
> > >   *
> > >   * This function is expected to be called from
> > > pipe_update_start()
> > > where it is
> > >   * not expected to race with PSR enable or disable.
> > >   */
> > > -void intel_psr_wait_for_idle(const struct intel_crtc_state
> > > *new_crtc_state)
> > > +void intel_psr_wait_for_idle_locked(const struct
> > > intel_crtc_state
> > > *new_crtc_state)
> > >  {
> > >       struct drm_i915_private *dev_priv = to_i915(new_crtc_state-
> > > > uapi.crtc->dev);
> > >       struct intel_encoder *encoder;
> > > @@ -1938,12 +1947,10 @@ void intel_psr_wait_for_idle(const struct
> > > intel_crtc_state *new_crtc_state)
> > >               struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder);
> > >               int ret;
> > > 
> > > -             mutex_lock(&intel_dp->psr.lock);
> > > +             lockdep_assert_held(&intel_dp->psr.lock);
> > > 
> > > -             if (!intel_dp->psr.enabled) {
> > > -                     mutex_unlock(&intel_dp->psr.lock);
> > > +             if (!intel_dp->psr.enabled)
> > >                       continue;
> > > -             }
> > > 
> > >               if (intel_dp->psr.psr2_enabled)
> > >                       ret =
> > > _psr2_ready_for_pipe_update_locked(intel_dp);
> > > @@ -1952,8 +1959,6 @@ void intel_psr_wait_for_idle(const struct
> > > intel_crtc_state *new_crtc_state)
> > > 
> > >               if (ret)
> > >                       drm_err(&dev_priv->drm, "PSR wait timed
> > > out,
> > > atomic update may fail\n");
> > > -
> > > -             mutex_unlock(&intel_dp->psr.lock);
> > >       }
> > >  }
> > > 
> > > @@ -2444,3 +2449,51 @@ bool intel_psr_enabled(struct intel_dp
> > > *intel_dp)
> > > 
> > >       return ret;
> > >  }
> > > +
> > > +/**
> > > + * intel_psr_lock - grab psr.lock mutex
> > > + * @crtc_state: the crtc state
> > > + *
> > > + * This is initially meant to be used by around CRTC update,
> > > when
> > > + * vblank sensitive registers are updated and we need grab the
> > > lock
> > > + * before it to avoid vblank evasion.
> > > + */
> > > +void intel_psr_lock(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +     struct drm_i915_private *i915 = to_i915(crtc_state-
> > > >uapi.crtc-
> > > > dev);
> > > +     struct intel_encoder *encoder;
> > > +
> > > +     if (!crtc_state->has_psr)
> > > +             return;
> > > +
> > > +     for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
> > > +                                          crtc_state-
> > > > uapi.encoder_mask) {
> > > +             struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder);
> > > +
> > > +             mutex_lock(&intel_dp->psr.lock);
> > > +             break;
> > > +     }
> > > +}
> > > +
> > > +/**
> > > + * intel_psr_lock - grab psr.lock mutex
> > > + * @crtc_state: the crtc state
> > > + *
> > > + * Release the PSR lock that was held during pipe update.
> > > + */
> > > +void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +     struct drm_i915_private *i915 = to_i915(crtc_state-
> > > >uapi.crtc-
> > > > dev);
> > > +     struct intel_encoder *encoder;
> > > +
> > > +     if (!crtc_state->has_psr)
> > > +             return;
> > > +
> > > +     for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
> > > +                                          crtc_state-
> > > > uapi.encoder_mask) {
> > > +             struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder);
> > > +
> > > +             mutex_unlock(&intel_dp->psr.lock);
> > > +             break;
> > > +     }
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index f6526d9ccfdc6..2ac3a46cccc50 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -41,7 +41,7 @@ void intel_psr_get_config(struct intel_encoder
> > > *encoder,
> > >                         struct intel_crtc_state *pipe_config);
> > >  void intel_psr_irq_handler(struct intel_dp *intel_dp, u32
> > > psr_iir);
> > >  void intel_psr_short_pulse(struct intel_dp *intel_dp);
> > > -void intel_psr_wait_for_idle(const struct intel_crtc_state
> > > *new_crtc_state);
> > > +void intel_psr_wait_for_idle_locked(const struct
> > > intel_crtc_state
> > > *new_crtc_state);
> > >  bool intel_psr_enabled(struct intel_dp *intel_dp);
> > >  int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > *state,
> > >                               struct intel_crtc *crtc);
> > > @@ -55,4 +55,7 @@ void intel_psr2_disable_plane_sel_fetch(struct
> > > intel_plane *plane,
> > >  void intel_psr_pause(struct intel_dp *intel_dp);
> > >  void intel_psr_resume(struct intel_dp *intel_dp);
> > > 
> > > +void intel_psr_lock(const struct intel_crtc_state *crtc_state);
> > > +void intel_psr_unlock(const struct intel_crtc_state
> > > *crtc_state);
> > > +
> > >  #endif /* __INTEL_PSR_H__ */