[GIT PULL] clk: meson: updates for v4.20

[GIT PULL] clk: meson: updates for v4.20

[Jerome Brunet]

Dear clock maintainers,

Below is a request to pull updates for Amlogic clocks.
There is not much out of the ordinary there, except:
- Even if we don't like it, the entire meson8b is now using
  CLK_OF_DECLARE_DRIVER(). Previously, only the reset controller
  part used this but it seems there is no way around it (yet) to
  handle certain things on this SoC, such as the TWD timer.
- We are a bit late compared to the usual schedule, sorry about that.

Thanks for pulling

Cheers
Jerome

The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:

  Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/meson-clk-4.20-1

for you to fetch changes up to 93c873d686461652921fe18b137ac28002dfe166:

  clk: meson: meson8b: use the regmap in the internal reset controller (2018-09-26 12:02:00 +0200)

----------------------------------------------------------------
Update for meson clocks targeted at v4.20

- clk-pll driver improvements and updates
- add axg audio controller system clocks
- drop mpll3 from the possible pcie clock parent of the axg
- register meson8b clock controller early

----------------------------------------------------------------
Jerome Brunet (5):
      clk: meson: clk-pll: add enable bit
      clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
      clk: meson: clk-pll: remove od parameters
      clk: meson: clk-pll: drop hard-coded rates from pll tables
      clk: meson: axg: round audio system master clocks down

Martin Blumenstingl (2):
      clk: meson: meson8b: register the clock controller early
      clk: meson: meson8b: use the regmap in the internal reset controller

Yixun Lan (1):
      clk: meson-axg: pcie: drop the mpll3 clock parent

 drivers/clk/meson/axg-audio.c |  34 ++-
 drivers/clk/meson/axg.c       | 332 +++++++++++++++------------
 drivers/clk/meson/axg.h       |   8 +-
 drivers/clk/meson/clk-pll.c   | 156 ++++++++-----
 drivers/clk/meson/clkc.h      |  16 +-
 drivers/clk/meson/gxbb.c      | 518 +++++++++++++++++++++---------------------
 drivers/clk/meson/gxbb.h      |  10 +-
 drivers/clk/meson/meson8b.c   | 280 +++++++++++------------
 drivers/clk/meson/meson8b.h   |   5 +-
 9 files changed, 732 insertions(+), 627 deletions(-)

[GIT PULL] clk: meson: updates for v4.20

[Jerome Brunet]

Dear clock maintainers,

Below is a request to pull updates for Amlogic clocks.
There is not much out of the ordinary there, except:
- Even if we don't like it, the entire meson8b is now using
  CLK_OF_DECLARE_DRIVER(). Previously, only the reset controller
  part used this but it seems there is no way around it (yet) to
  handle certain things on this SoC, such as the TWD timer.
- We are a bit late compared to the usual schedule, sorry about that.

Thanks for pulling

Cheers
Jerome

The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:

  Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/meson-clk-4.20-1

for you to fetch changes up to 93c873d686461652921fe18b137ac28002dfe166:

  clk: meson: meson8b: use the regmap in the internal reset controller (2018-09-26 12:02:00 +0200)

----------------------------------------------------------------
Update for meson clocks targeted at v4.20

- clk-pll driver improvements and updates
- add axg audio controller system clocks
- drop mpll3 from the possible pcie clock parent of the axg
- register meson8b clock controller early

----------------------------------------------------------------
Jerome Brunet (5):
      clk: meson: clk-pll: add enable bit
      clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
      clk: meson: clk-pll: remove od parameters
      clk: meson: clk-pll: drop hard-coded rates from pll tables
      clk: meson: axg: round audio system master clocks down

Martin Blumenstingl (2):
      clk: meson: meson8b: register the clock controller early
      clk: meson: meson8b: use the regmap in the internal reset controller

Yixun Lan (1):
      clk: meson-axg: pcie: drop the mpll3 clock parent

 drivers/clk/meson/axg-audio.c |  34 ++-
 drivers/clk/meson/axg.c       | 332 +++++++++++++++------------
 drivers/clk/meson/axg.h       |   8 +-
 drivers/clk/meson/clk-pll.c   | 156 ++++++++-----
 drivers/clk/meson/clkc.h      |  16 +-
 drivers/clk/meson/gxbb.c      | 518 +++++++++++++++++++++---------------------
 drivers/clk/meson/gxbb.h      |  10 +-
 drivers/clk/meson/meson8b.c   | 280 +++++++++++------------
 drivers/clk/meson/meson8b.h   |   5 +-
 9 files changed, 732 insertions(+), 627 deletions(-)

Re: [GIT PULL] clk: meson: updates for v4.20

[Stephen Boyd]

Quoting Jerome Brunet (2018-09-27 07:45:02)
> Dear clock maintainers,
> 
> Below is a request to pull updates for Amlogic clocks.
> There is not much out of the ordinary there, except:
> - Even if we don't like it, the entire meson8b is now using
>   CLK_OF_DECLARE_DRIVER(). Previously, only the reset controller
>   part used this but it seems there is no way around it (yet) to
>   handle certain things on this SoC, such as the TWD timer.
> - We are a bit late compared to the usual schedule, sorry about that.

No worries. I'm also late this time.

Pulled into clk-next. Thanks.

[GIT PULL] clk: meson: updates for v4.20

[Stephen Boyd]

Quoting Jerome Brunet (2018-09-27 07:45:02)
> Dear clock maintainers,
> 
> Below is a request to pull updates for Amlogic clocks.
> There is not much out of the ordinary there, except:
> - Even if we don't like it, the entire meson8b is now using
>   CLK_OF_DECLARE_DRIVER(). Previously, only the reset controller
>   part used this but it seems there is no way around it (yet) to
>   handle certain things on this SoC, such as the TWD timer.
> - We are a bit late compared to the usual schedule, sorry about that.

No worries. I'm also late this time.

Pulled into clk-next. Thanks.