* [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
@ 2019-08-21 18:38 Shirley Her (SC)
2019-08-22 8:35 ` Ulf Hansson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Shirley Her (SC) @ 2019-08-21 18:38 UTC (permalink / raw)
To: adrian.hunter, ulf.hansson, linux-mmc, linux-kernel
Cc: Chevron Li (WH), Shaper Liu (WH), Louis Lu (TP), Max Huang (SC),
Shirley Her (SC)
Change O2 Host PLL and DLL register name
Signed-off-by: Shirley Her <shirley.her@bayhubtech.com>
---
change in V8:
1. fix patch format error
change in V7:
1. change subject
change in V6:
1. change subject and commit message to match the patch
2. change register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1
change in V5:
1. split 2 patches into 3 patches
2. make dll_adjust_count start from 0
3. fix ret overwritten issue
4. use break instead of goto
change in V4:
1. add a bug fix for V3
change in V3:
1. add more explanation in dll_recovery and execute_tuning function
2. move dll_adjust_count to O2_host struct
3. fix some coding style error
4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1
change in V2:
1. use usleep_range instead of udelay
2. move dll_adjust_count to sdhci-pci-o2micro.c
chagne in V1:
1. add error recovery function to relock DLL with correct phase
2. retuning HS200 after DLL locked
---
drivers/mmc/host/sdhci-pci-o2micro.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index 9dc4548..b3a33d9 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -51,7 +51,7 @@
#define O2_SD_VENDOR_SETTING2 0x1C8
#define O2_SD_HW_TUNING_DISABLE BIT(4)
-#define O2_PLL_WDT_CONTROL1 0x1CC
+#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
#define O2_PLL_FORCE_ACTIVE BIT(18)
#define O2_PLL_LOCK_STATUS BIT(14)
#define O2_PLL_SOFT_RESET BIT(12)
@@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
u32 scratch32;
/* PLL software reset */
- scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
+ scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
scratch32 |= O2_PLL_SOFT_RESET;
- sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
+ sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
udelay(1);
scratch32 &= ~(O2_PLL_SOFT_RESET);
- sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
+ sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
/* PLL force active */
scratch32 |= O2_PLL_FORCE_ACTIVE;
- sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
+ sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
/* Wait max 20 ms */
timeout = ktime_add_ms(ktime_get(), 20);
while (1) {
bool timedout = ktime_after(ktime_get(), timeout);
- scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
+ scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
if (scratch & O2_PLL_LOCK_STATUS)
break;
if (timedout) {
@@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
out:
/* Cancel PLL force active */
- scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
+ scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
scratch32 &= ~O2_PLL_FORCE_ACTIVE;
- sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
+ sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
}
static int sdhci_o2_get_cd(struct mmc_host *mmc)
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
2019-08-21 18:38 [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name Shirley Her (SC)
@ 2019-08-22 8:35 ` Ulf Hansson
2019-08-22 16:16 ` Shirley Her (SC)
2019-08-28 8:32 ` Adrian Hunter
2019-09-04 9:52 ` Ulf Hansson
2 siblings, 1 reply; 5+ messages in thread
From: Ulf Hansson @ 2019-08-22 8:35 UTC (permalink / raw)
To: Shirley Her (SC)
Cc: adrian.hunter, linux-mmc, linux-kernel, Chevron Li (WH),
Shaper Liu (WH), Louis Lu (TP), Max Huang (SC)
On Wed, 21 Aug 2019 at 20:38, Shirley Her (SC)
<shirley.her@bayhubtech.com> wrote:
>
> Change O2 Host PLL and DLL register name
>
> Signed-off-by: Shirley Her <shirley.her@bayhubtech.com>
It seems like you managed to post the version 8, two times. Is there
any difference? Which one should we review?
Kind regards
Uffe
> ---
> change in V8:
> 1. fix patch format error
>
> change in V7:
> 1. change subject
>
> change in V6:
> 1. change subject and commit message to match the patch
> 2. change register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1
>
> change in V5:
> 1. split 2 patches into 3 patches
> 2. make dll_adjust_count start from 0
> 3. fix ret overwritten issue
> 4. use break instead of goto
>
> change in V4:
> 1. add a bug fix for V3
>
> change in V3:
> 1. add more explanation in dll_recovery and execute_tuning function
> 2. move dll_adjust_count to O2_host struct
> 3. fix some coding style error
> 4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1
>
> change in V2:
> 1. use usleep_range instead of udelay
> 2. move dll_adjust_count to sdhci-pci-o2micro.c
>
> chagne in V1:
> 1. add error recovery function to relock DLL with correct phase
> 2. retuning HS200 after DLL locked
> ---
> drivers/mmc/host/sdhci-pci-o2micro.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 9dc4548..b3a33d9 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -51,7 +51,7 @@
> #define O2_SD_VENDOR_SETTING2 0x1C8
> #define O2_SD_HW_TUNING_DISABLE BIT(4)
>
> -#define O2_PLL_WDT_CONTROL1 0x1CC
> +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
> #define O2_PLL_FORCE_ACTIVE BIT(18)
> #define O2_PLL_LOCK_STATUS BIT(14)
> #define O2_PLL_SOFT_RESET BIT(12)
> @@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
> u32 scratch32;
>
> /* PLL software reset */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 |= O2_PLL_SOFT_RESET;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> udelay(1);
> scratch32 &= ~(O2_PLL_SOFT_RESET);
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* PLL force active */
> scratch32 |= O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* Wait max 20 ms */
> timeout = ktime_add_ms(ktime_get(), 20);
> while (1) {
> bool timedout = ktime_after(ktime_get(), timeout);
>
> - scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
> + scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
> if (scratch & O2_PLL_LOCK_STATUS)
> break;
> if (timedout) {
> @@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
>
> out:
> /* Cancel PLL force active */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 &= ~O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> }
>
> static int sdhci_o2_get_cd(struct mmc_host *mmc)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
2019-08-22 8:35 ` Ulf Hansson
@ 2019-08-22 16:16 ` Shirley Her (SC)
0 siblings, 0 replies; 5+ messages in thread
From: Shirley Her (SC) @ 2019-08-22 16:16 UTC (permalink / raw)
To: Ulf Hansson
Cc: adrian.hunter, linux-mmc, linux-kernel, Chevron Li (WH),
Shaper Liu (WH), Louis Lu (TP), Max Huang (SC)
Sorry about the confusion and they are the same, please review the 2nd one. One of the email address is wrong when I send the 1st one.
Thanks for your help,
Shirley
-----Original Message-----
From: Ulf Hansson [mailto:ulf.hansson@linaro.org]
Sent: Thursday, August 22, 2019 1:35 AM
To: Shirley Her (SC) <shirley.her@bayhubtech.com>
Cc: adrian.hunter@intel.com; linux-mmc@vger.kernel.org; linux-kernel@vger.kernel.org; Chevron Li (WH) <chevron.li@bayhubtech.com>; Shaper Liu (WH) <shaper.liu@bayhubtech.com>; Louis Lu (TP) <louis.lu@bayhubtech.com>; Max Huang (SC) <max.huang@bayhubtech.com>
Subject: Re: [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
On Wed, 21 Aug 2019 at 20:38, Shirley Her (SC) <shirley.her@bayhubtech.com> wrote:
>
> Change O2 Host PLL and DLL register name
>
> Signed-off-by: Shirley Her <shirley.her@bayhubtech.com>
It seems like you managed to post the version 8, two times. Is there any difference? Which one should we review?
Kind regards
Uffe
> ---
> change in V8:
> 1. fix patch format error
>
> change in V7:
> 1. change subject
>
> change in V6:
> 1. change subject and commit message to match the patch 2. change
> register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1
>
> change in V5:
> 1. split 2 patches into 3 patches
> 2. make dll_adjust_count start from 0 3. fix ret overwritten issue
> 4. use break instead of goto
>
> change in V4:
> 1. add a bug fix for V3
>
> change in V3:
> 1. add more explanation in dll_recovery and execute_tuning function
> 2. move dll_adjust_count to O2_host struct 3. fix some coding style
> error 4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1
>
> change in V2:
> 1. use usleep_range instead of udelay 2. move dll_adjust_count to
> sdhci-pci-o2micro.c
>
> chagne in V1:
> 1. add error recovery function to relock DLL with correct phase 2.
> retuning HS200 after DLL locked
> ---
> drivers/mmc/host/sdhci-pci-o2micro.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c
> b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 9dc4548..b3a33d9 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -51,7 +51,7 @@
> #define O2_SD_VENDOR_SETTING2 0x1C8
> #define O2_SD_HW_TUNING_DISABLE BIT(4)
>
> -#define O2_PLL_WDT_CONTROL1 0x1CC
> +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
> #define O2_PLL_FORCE_ACTIVE BIT(18)
> #define O2_PLL_LOCK_STATUS BIT(14)
> #define O2_PLL_SOFT_RESET BIT(12)
> @@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
> u32 scratch32;
>
> /* PLL software reset */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 |= O2_PLL_SOFT_RESET;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> udelay(1);
> scratch32 &= ~(O2_PLL_SOFT_RESET);
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* PLL force active */
> scratch32 |= O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* Wait max 20 ms */
> timeout = ktime_add_ms(ktime_get(), 20);
> while (1) {
> bool timedout = ktime_after(ktime_get(), timeout);
>
> - scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
> + scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
> if (scratch & O2_PLL_LOCK_STATUS)
> break;
> if (timedout) {
> @@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct
> sdhci_host *host)
>
> out:
> /* Cancel PLL force active */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 &= ~O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> }
>
> static int sdhci_o2_get_cd(struct mmc_host *mmc)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
2019-08-21 18:38 [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name Shirley Her (SC)
2019-08-22 8:35 ` Ulf Hansson
@ 2019-08-28 8:32 ` Adrian Hunter
2019-09-04 9:52 ` Ulf Hansson
2 siblings, 0 replies; 5+ messages in thread
From: Adrian Hunter @ 2019-08-28 8:32 UTC (permalink / raw)
To: Shirley Her (SC), ulf.hansson, linux-mmc, linux-kernel
Cc: Chevron Li (WH), Shaper Liu (WH), Louis Lu (TP), Max Huang (SC)
On 21/08/19 9:38 PM, Shirley Her (SC) wrote:
> Change O2 Host PLL and DLL register name
>
> Signed-off-by: Shirley Her <shirley.her@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> change in V8:
> 1. fix patch format error
>
> change in V7:
> 1. change subject
>
> change in V6:
> 1. change subject and commit message to match the patch
> 2. change register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1
>
> change in V5:
> 1. split 2 patches into 3 patches
> 2. make dll_adjust_count start from 0
> 3. fix ret overwritten issue
> 4. use break instead of goto
>
> change in V4:
> 1. add a bug fix for V3
>
> change in V3:
> 1. add more explanation in dll_recovery and execute_tuning function
> 2. move dll_adjust_count to O2_host struct
> 3. fix some coding style error
> 4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1
>
> change in V2:
> 1. use usleep_range instead of udelay
> 2. move dll_adjust_count to sdhci-pci-o2micro.c
>
> chagne in V1:
> 1. add error recovery function to relock DLL with correct phase
> 2. retuning HS200 after DLL locked
> ---
> drivers/mmc/host/sdhci-pci-o2micro.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 9dc4548..b3a33d9 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -51,7 +51,7 @@
> #define O2_SD_VENDOR_SETTING2 0x1C8
> #define O2_SD_HW_TUNING_DISABLE BIT(4)
>
> -#define O2_PLL_WDT_CONTROL1 0x1CC
> +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
> #define O2_PLL_FORCE_ACTIVE BIT(18)
> #define O2_PLL_LOCK_STATUS BIT(14)
> #define O2_PLL_SOFT_RESET BIT(12)
> @@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
> u32 scratch32;
>
> /* PLL software reset */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 |= O2_PLL_SOFT_RESET;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> udelay(1);
> scratch32 &= ~(O2_PLL_SOFT_RESET);
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* PLL force active */
> scratch32 |= O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* Wait max 20 ms */
> timeout = ktime_add_ms(ktime_get(), 20);
> while (1) {
> bool timedout = ktime_after(ktime_get(), timeout);
>
> - scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
> + scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
> if (scratch & O2_PLL_LOCK_STATUS)
> break;
> if (timedout) {
> @@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
>
> out:
> /* Cancel PLL force active */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 &= ~O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> }
>
> static int sdhci_o2_get_cd(struct mmc_host *mmc)
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
2019-08-21 18:38 [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name Shirley Her (SC)
2019-08-22 8:35 ` Ulf Hansson
2019-08-28 8:32 ` Adrian Hunter
@ 2019-09-04 9:52 ` Ulf Hansson
2 siblings, 0 replies; 5+ messages in thread
From: Ulf Hansson @ 2019-09-04 9:52 UTC (permalink / raw)
To: Shirley Her (SC)
Cc: adrian.hunter, linux-mmc, linux-kernel, Chevron Li (WH),
Shaper Liu (WH), Louis Lu (TP), Max Huang (SC)
On Wed, 21 Aug 2019 at 20:38, Shirley Her (SC)
<shirley.her@bayhubtech.com> wrote:
>
> Change O2 Host PLL and DLL register name
>
> Signed-off-by: Shirley Her <shirley.her@bayhubtech.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> change in V8:
> 1. fix patch format error
>
> change in V7:
> 1. change subject
>
> change in V6:
> 1. change subject and commit message to match the patch
> 2. change register name O2_PLL_WDT_CONTROL1 to O2_PLL_DLL_WDT_CONTROL1
>
> change in V5:
> 1. split 2 patches into 3 patches
> 2. make dll_adjust_count start from 0
> 3. fix ret overwritten issue
> 4. use break instead of goto
>
> change in V4:
> 1. add a bug fix for V3
>
> change in V3:
> 1. add more explanation in dll_recovery and execute_tuning function
> 2. move dll_adjust_count to O2_host struct
> 3. fix some coding style error
> 4. renaming O2_PLL_WDT_CONTROL1 TO O2_PLL_DLL_WDT_CONTROL1
>
> change in V2:
> 1. use usleep_range instead of udelay
> 2. move dll_adjust_count to sdhci-pci-o2micro.c
>
> chagne in V1:
> 1. add error recovery function to relock DLL with correct phase
> 2. retuning HS200 after DLL locked
> ---
> drivers/mmc/host/sdhci-pci-o2micro.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 9dc4548..b3a33d9 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -51,7 +51,7 @@
> #define O2_SD_VENDOR_SETTING2 0x1C8
> #define O2_SD_HW_TUNING_DISABLE BIT(4)
>
> -#define O2_PLL_WDT_CONTROL1 0x1CC
> +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC
> #define O2_PLL_FORCE_ACTIVE BIT(18)
> #define O2_PLL_LOCK_STATUS BIT(14)
> #define O2_PLL_SOFT_RESET BIT(12)
> @@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
> u32 scratch32;
>
> /* PLL software reset */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 |= O2_PLL_SOFT_RESET;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> udelay(1);
> scratch32 &= ~(O2_PLL_SOFT_RESET);
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* PLL force active */
> scratch32 |= O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
>
> /* Wait max 20 ms */
> timeout = ktime_add_ms(ktime_get(), 20);
> while (1) {
> bool timedout = ktime_after(ktime_get(), timeout);
>
> - scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
> + scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
> if (scratch & O2_PLL_LOCK_STATUS)
> break;
> if (timedout) {
> @@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
>
> out:
> /* Cancel PLL force active */
> - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
> + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
> scratch32 &= ~O2_PLL_FORCE_ACTIVE;
> - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
> + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
> }
>
> static int sdhci_o2_get_cd(struct mmc_host *mmc)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-09-04 9:53 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-21 18:38 [PATCH V8 1/3] mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name Shirley Her (SC)
2019-08-22 8:35 ` Ulf Hansson
2019-08-22 16:16 ` Shirley Her (SC)
2019-08-28 8:32 ` Adrian Hunter
2019-09-04 9:52 ` Ulf Hansson
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