* [PATCH v8 01/22] dt-bindings: clock: tegra: Add IDs for OSC clocks
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Tegra has OSC, OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are
the possible parents of Tegra PMC clocks clk_out_1, clk_out_2, and
clk_out_3 for Tegra30 through Tegra210.
So, this patch adds ids for these clocks.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
include/dt-bindings/clock/tegra114-car.h | 4 +++-
include/dt-bindings/clock/tegra124-car-common.h | 4 +++-
include/dt-bindings/clock/tegra210-car.h | 4 +++-
include/dt-bindings/clock/tegra30-car.h | 4 +++-
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index bb5c2c999c05..df59aaf5bf34 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -228,6 +228,8 @@
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_OSC_DIV2 202
+#define TEGRA114_CLK_OSC_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
@@ -274,7 +276,7 @@
#define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248
-/* 249 */
+#define TEGRA114_CLK_OSC 249
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index 0c4f5be0a742..2a9acd592bff 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -227,6 +227,8 @@
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_OSC_DIV2 202
+#define TEGRA124_CLK_OSC_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
@@ -273,7 +275,7 @@
#define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248
-/* 249 */
+#define TEGRA124_CLK_OSC 249
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 44f60623f99b..7a8f10b9a66d 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -262,6 +262,8 @@
#define TEGRA210_CLK_CLK_M 233
#define TEGRA210_CLK_CLK_M_DIV2 234
#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_OSC_DIV2 234
+#define TEGRA210_CLK_OSC_DIV4 235
#define TEGRA210_CLK_PLL_REF 236
#define TEGRA210_CLK_PLL_C 237
#define TEGRA210_CLK_PLL_C_OUT1 238
@@ -355,7 +357,7 @@
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
/* 325 */
-/* 326 */
+#define TEGRA210_CLK_OSC 326
/* 327 */
/* 328 */
/* 329 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 3c90f1535551..7b542c10fc27 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -196,6 +196,8 @@
#define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_OSC_DIV2 172
+#define TEGRA30_CLK_OSC_DIV4 173
#define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176
@@ -243,7 +245,7 @@
#define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218
/* 219 */
-/* 220 */
+#define TEGRA30_CLK_OSC 220
/* 221 */
/* 222 */
/* 223 */
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 01/22] dt-bindings: clock: tegra: Add IDs for OSC clocks
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Tegra has OSC, OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are
the possible parents of Tegra PMC clocks clk_out_1, clk_out_2, and
clk_out_3 for Tegra30 through Tegra210.
So, this patch adds ids for these clocks.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
include/dt-bindings/clock/tegra114-car.h | 4 +++-
include/dt-bindings/clock/tegra124-car-common.h | 4 +++-
include/dt-bindings/clock/tegra210-car.h | 4 +++-
include/dt-bindings/clock/tegra30-car.h | 4 +++-
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index bb5c2c999c05..df59aaf5bf34 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -228,6 +228,8 @@
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_OSC_DIV2 202
+#define TEGRA114_CLK_OSC_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
@@ -274,7 +276,7 @@
#define TEGRA114_CLK_CLK_OUT_2 246
#define TEGRA114_CLK_CLK_OUT_3 247
#define TEGRA114_CLK_BLINK 248
-/* 249 */
+#define TEGRA114_CLK_OSC 249
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index 0c4f5be0a742..2a9acd592bff 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -227,6 +227,8 @@
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_OSC_DIV2 202
+#define TEGRA124_CLK_OSC_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
@@ -273,7 +275,7 @@
#define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248
-/* 249 */
+#define TEGRA124_CLK_OSC 249
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 44f60623f99b..7a8f10b9a66d 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -262,6 +262,8 @@
#define TEGRA210_CLK_CLK_M 233
#define TEGRA210_CLK_CLK_M_DIV2 234
#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_OSC_DIV2 234
+#define TEGRA210_CLK_OSC_DIV4 235
#define TEGRA210_CLK_PLL_REF 236
#define TEGRA210_CLK_PLL_C 237
#define TEGRA210_CLK_PLL_C_OUT1 238
@@ -355,7 +357,7 @@
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
/* 325 */
-/* 326 */
+#define TEGRA210_CLK_OSC 326
/* 327 */
/* 328 */
/* 329 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 3c90f1535551..7b542c10fc27 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -196,6 +196,8 @@
#define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_OSC_DIV2 172
+#define TEGRA30_CLK_OSC_DIV4 173
#define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176
@@ -243,7 +245,7 @@
#define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218
/* 219 */
-/* 220 */
+#define TEGRA30_CLK_OSC 220
/* 221 */
/* 222 */
/* 223 */
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 02/22] clk: tegra: Add support for OSC_DIV fixed clocks
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks
from the OSC pads.
This patch adds support for these clocks.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-id.h | 2 ++
drivers/clk/tegra/clk-tegra-fixed.c | 16 ++++++++++++++++
drivers/clk/tegra/clk-tegra114.c | 4 ++++
drivers/clk/tegra/clk-tegra124.c | 4 ++++
drivers/clk/tegra/clk-tegra210.c | 4 ++++
drivers/clk/tegra/clk-tegra30.c | 4 ++++
6 files changed, 34 insertions(+)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index c4faebd32760..17d8b252cd0a 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -46,6 +46,8 @@ enum clk_id {
tegra_clk_clk_m,
tegra_clk_clk_m_div2,
tegra_clk_clk_m_div4,
+ tegra_clk_osc_div2,
+ tegra_clk_osc_div4,
tegra_clk_clk_out_1,
tegra_clk_clk_out_1_mux,
tegra_clk_clk_out_2,
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 7c6c8abfcde6..990106391334 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -48,6 +48,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
+ /* osc_div2 */
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
+ if (dt_clk) {
+ clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
+ 0, 1, 2);
+ *dt_clk = clk;
+ }
+
+ /* osc_div4 */
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
+ if (dt_clk) {
+ clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
+ 0, 1, 4);
+ *dt_clk = clk;
+ }
+
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
if (!dt_clk)
return 0;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 4efcaaf51b3a..d44cb8db0ef6 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -737,6 +737,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
@@ -817,6 +819,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index b3110d5b5a6c..32f3dd1ccbad 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
@@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 762cd186f714..899d8ca68c4f 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2373,6 +2373,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
@@ -2499,6 +2501,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c8bc18e4d7e5..c2da1f1d2b58 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -583,6 +583,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
@@ -685,6 +687,8 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 02/22] clk: tegra: Add support for OSC_DIV fixed clocks
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks
from the OSC pads.
This patch adds support for these clocks.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/clk/tegra/clk-id.h | 2 ++
drivers/clk/tegra/clk-tegra-fixed.c | 16 ++++++++++++++++
drivers/clk/tegra/clk-tegra114.c | 4 ++++
drivers/clk/tegra/clk-tegra124.c | 4 ++++
drivers/clk/tegra/clk-tegra210.c | 4 ++++
drivers/clk/tegra/clk-tegra30.c | 4 ++++
6 files changed, 34 insertions(+)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index c4faebd32760..17d8b252cd0a 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -46,6 +46,8 @@ enum clk_id {
tegra_clk_clk_m,
tegra_clk_clk_m_div2,
tegra_clk_clk_m_div4,
+ tegra_clk_osc_div2,
+ tegra_clk_osc_div4,
tegra_clk_clk_out_1,
tegra_clk_clk_out_1_mux,
tegra_clk_clk_out_2,
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 7c6c8abfcde6..990106391334 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -48,6 +48,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
+ /* osc_div2 */
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
+ if (dt_clk) {
+ clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
+ 0, 1, 2);
+ *dt_clk = clk;
+ }
+
+ /* osc_div4 */
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
+ if (dt_clk) {
+ clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
+ 0, 1, 4);
+ *dt_clk = clk;
+ }
+
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
if (!dt_clk)
return 0;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 4efcaaf51b3a..d44cb8db0ef6 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -737,6 +737,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
@@ -817,6 +819,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index b3110d5b5a6c..32f3dd1ccbad 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
@@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 762cd186f714..899d8ca68c4f 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2373,6 +2373,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
@@ -2499,6 +2501,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c8bc18e4d7e5..c2da1f1d2b58 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -583,6 +583,8 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
+ { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
+ { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
@@ -685,6 +687,8 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
+ [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 03/22] clk: tegra: Add Tegra OSC to clock lookup
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2,
and clk_out_3.
This patch adds Tegra OSC to clock lookup.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-fixed.c | 5 +++++
drivers/clk/tegra/clk-tegra114.c | 2 ++
drivers/clk/tegra/clk-tegra124.c | 2 ++
drivers/clk/tegra/clk-tegra210.c | 2 ++
drivers/clk/tegra/clk-tegra30.c | 2 ++
6 files changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 17d8b252cd0a..17c13d1aa6bc 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -46,6 +46,7 @@ enum clk_id {
tegra_clk_clk_m,
tegra_clk_clk_m_div2,
tegra_clk_clk_m_div4,
+ tegra_clk_osc,
tegra_clk_osc_div2,
tegra_clk_osc_div4,
tegra_clk_clk_out_1,
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 990106391334..0dc2d5f5cfb5 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -46,7 +46,12 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
return -EINVAL;
}
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
+ if (!dt_clk)
+ return 0;
+
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
+ *dt_clk = osc;
/* osc_div2 */
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d44cb8db0ef6..e3c68eca54b7 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -737,6 +737,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
@@ -819,6 +820,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 32f3dd1ccbad..ef0f928f0259 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -862,6 +862,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
@@ -945,6 +946,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 899d8ca68c4f..958f5f6c894d 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2373,6 +2373,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
@@ -2501,6 +2502,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c2da1f1d2b58..5f3484758123 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -583,6 +583,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
@@ -687,6 +688,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 03/22] clk: tegra: Add Tegra OSC to clock lookup
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2,
and clk_out_3.
This patch adds Tegra OSC to clock lookup.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-fixed.c | 5 +++++
drivers/clk/tegra/clk-tegra114.c | 2 ++
drivers/clk/tegra/clk-tegra124.c | 2 ++
drivers/clk/tegra/clk-tegra210.c | 2 ++
drivers/clk/tegra/clk-tegra30.c | 2 ++
6 files changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 17d8b252cd0a..17c13d1aa6bc 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -46,6 +46,7 @@ enum clk_id {
tegra_clk_clk_m,
tegra_clk_clk_m_div2,
tegra_clk_clk_m_div4,
+ tegra_clk_osc,
tegra_clk_osc_div2,
tegra_clk_osc_div4,
tegra_clk_clk_out_1,
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
index 990106391334..0dc2d5f5cfb5 100644
--- a/drivers/clk/tegra/clk-tegra-fixed.c
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -46,7 +46,12 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
return -EINVAL;
}
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
+ if (!dt_clk)
+ return 0;
+
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
+ *dt_clk = osc;
/* osc_div2 */
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d44cb8db0ef6..e3c68eca54b7 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -737,6 +737,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
@@ -819,6 +820,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 32f3dd1ccbad..ef0f928f0259 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -862,6 +862,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
@@ -945,6 +946,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 899d8ca68c4f..958f5f6c894d 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2373,6 +2373,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
@@ -2501,6 +2502,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index c2da1f1d2b58..5f3484758123 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -583,6 +583,7 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
+ { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
@@ -687,6 +688,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
+ [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 08/22] soc: tegra: Add Tegra PMC clocks registration into PMC driver
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
these PMC clocks are registered by Tegra clock driver with each clock as
separate mux and gate clocks using clk_register_mux and clk_register_gate
by passing PMC base address and register offsets and PMC programming for
these clocks happens through direct PMC access by the clock driver.
With this, when PMC is in secure mode any direct PMC access from the
non-secure world does not go through and these clocks will not be
functional.
This patch adds these PMC clocks registration to pmc driver with PMC as
a clock provider and registers each clock as single clock.
clk_ops callback implementations for these clocks uses tegra_pmc_readl and
tegra_pmc_writel which supports PMC programming in both secure mode and
non-secure mode.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/soc/tegra/pmc.c | 242 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 242 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 1699dda6b393..ecce91517af2 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -13,9 +13,13 @@
#include <linux/arm-smccc.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/clk-conf.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
+#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
@@ -48,6 +52,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/gpio/tegra194-gpio.h>
+#include <dt-bindings/soc/tegra-pmc.h>
#define PMC_CNTRL 0x0
#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
@@ -100,6 +105,8 @@
#define PMC_WAKE2_STATUS 0x168
#define PMC_SW_WAKE2_STATUS 0x16c
+#define PMC_CLK_OUT_CNTRL 0x1a8
+#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
#define PMC_SENSOR_CTRL 0x1b0
#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
@@ -155,6 +162,63 @@
#define TEGRA_SMC_PMC_READ 0xaa
#define TEGRA_SMC_PMC_WRITE 0xbb
+struct pmc_clk {
+ struct clk_hw hw;
+ unsigned long offs;
+ u32 mux_shift;
+ u32 force_en_shift;
+};
+
+#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
+
+struct pmc_clk_init_data {
+ char *name;
+ const char *const *parents;
+ int num_parents;
+ int clk_id;
+ u8 mux_shift;
+ u8 force_en_shift;
+};
+
+static const char * const clk_out1_parents[] = { "osc", "osc_div2",
+ "osc_div4", "extern1",
+};
+
+static const char * const clk_out2_parents[] = { "osc", "osc_div2",
+ "osc_div4", "extern2",
+};
+
+static const char * const clk_out3_parents[] = { "osc", "osc_div2",
+ "osc_div4", "extern3",
+};
+
+static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
+ {
+ .name = "pmc_clk_out_1",
+ .parents = clk_out1_parents,
+ .num_parents = ARRAY_SIZE(clk_out1_parents),
+ .clk_id = TEGRA_PMC_CLK_OUT_1,
+ .mux_shift = 6,
+ .force_en_shift = 2,
+ },
+ {
+ .name = "pmc_clk_out_2",
+ .parents = clk_out2_parents,
+ .num_parents = ARRAY_SIZE(clk_out2_parents),
+ .clk_id = TEGRA_PMC_CLK_OUT_2,
+ .mux_shift = 14,
+ .force_en_shift = 10,
+ },
+ {
+ .name = "pmc_clk_out_3",
+ .parents = clk_out3_parents,
+ .num_parents = ARRAY_SIZE(clk_out3_parents),
+ .clk_id = TEGRA_PMC_CLK_OUT_3,
+ .mux_shift = 22,
+ .force_en_shift = 18,
+ },
+};
+
struct tegra_powergate {
struct generic_pm_domain genpd;
struct tegra_pmc *pmc;
@@ -254,6 +318,9 @@ struct tegra_pmc_soc {
*/
const struct tegra_wake_event *wake_events;
unsigned int num_wake_events;
+
+ const struct pmc_clk_init_data *pmc_clks_data;
+ unsigned int num_pmc_clks;
};
static const char * const tegra186_reset_sources[] = {
@@ -2163,6 +2230,166 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
return NOTIFY_OK;
}
+static void pmc_clk_fence_udelay(u32 offset)
+{
+ tegra_pmc_readl(pmc, offset);
+ /* pmc clk propagation delay 2 us */
+ udelay(2);
+}
+
+static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
+ val &= PMC_CLK_OUT_MUX_MASK;
+
+ return val;
+}
+
+static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, clk->offs);
+ val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
+ val |= index << clk->mux_shift;
+ tegra_pmc_writel(pmc, val, clk->offs);
+ pmc_clk_fence_udelay(clk->offs);
+
+ return 0;
+}
+
+static int pmc_clk_is_enabled(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
+
+ return val ? 1 : 0;
+}
+
+static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
+{
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, offs);
+ val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
+ tegra_pmc_writel(pmc, val, offs);
+ pmc_clk_fence_udelay(offs);
+}
+
+static int pmc_clk_enable(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+
+ pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
+
+ return 0;
+}
+
+static void pmc_clk_disable(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+
+ pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
+}
+
+static const struct clk_ops pmc_clk_ops = {
+ .get_parent = pmc_clk_mux_get_parent,
+ .set_parent = pmc_clk_mux_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+ .is_enabled = pmc_clk_is_enabled,
+ .enable = pmc_clk_enable,
+ .disable = pmc_clk_disable,
+};
+
+static struct clk *
+tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
+ const struct pmc_clk_init_data *data,
+ unsigned long offset)
+{
+ struct clk_init_data init;
+ struct pmc_clk *pmc_clk;
+
+ pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
+ if (!pmc_clk)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = data->name;
+ init.ops = &pmc_clk_ops;
+ init.parent_names = data->parents;
+ init.num_parents = data->num_parents;
+ init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+ CLK_SET_PARENT_GATE;
+
+ pmc_clk->hw.init = &init;
+ pmc_clk->offs = offset;
+ pmc_clk->mux_shift = data->mux_shift;
+ pmc_clk->force_en_shift = data->force_en_shift;
+
+ return clk_register(NULL, &pmc_clk->hw);
+}
+
+static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
+ struct device_node *np)
+{
+ struct clk *clk;
+ struct clk_onecell_data *clk_data;
+ unsigned int num_clks;
+ int i, err;
+
+ num_clks = pmc->soc->num_pmc_clks;
+
+ if (!num_clks)
+ return;
+
+ clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
+ sizeof(*clk_data->clks), GFP_KERNEL);
+ if (!clk_data->clks)
+ return;
+
+ clk_data->clk_num = TEGRA_PMC_CLK_MAX;
+
+ for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
+ clk_data->clks[i] = ERR_PTR(-ENOENT);
+
+ for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
+ const struct pmc_clk_init_data *data;
+
+ data = pmc->soc->pmc_clks_data + i;
+
+ clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
+ if (IS_ERR(clk)) {
+ dev_warn(pmc->dev, "unable to register clock %s: %d\n",
+ data->name, PTR_ERR_OR_ZERO(clk));
+ return;
+ }
+
+ err = clk_register_clkdev(clk, data->name, NULL);
+ if (err) {
+ dev_warn(pmc->dev,
+ "unable to register %s clock lookup: %d\n",
+ data->name, err);
+ return;
+ }
+
+ clk_data->clks[data->clk_id] = clk;
+ }
+
+ err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+ if (err)
+ dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
+ err);
+}
+
static int tegra_pmc_probe(struct platform_device *pdev)
{
void __iomem *base;
@@ -2281,6 +2508,7 @@ static int tegra_pmc_probe(struct platform_device *pdev)
pmc->base = base;
mutex_unlock(&pmc->powergates_lock);
+ tegra_pmc_clock_register(pmc, pdev->dev.of_node);
platform_set_drvdata(pdev, pmc);
return 0;
@@ -2422,6 +2650,8 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
.num_reset_sources = 0,
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = NULL,
+ .num_pmc_clks = 0,
};
static const char * const tegra30_powergates[] = {
@@ -2469,6 +2699,8 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
static const char * const tegra114_powergates[] = {
@@ -2520,6 +2752,8 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
static const char * const tegra124_powergates[] = {
@@ -2631,6 +2865,8 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
static const char * const tegra210_powergates[] = {
@@ -2745,6 +2981,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
.num_reset_levels = 0,
.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
.wake_events = tegra210_wake_events,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
#define TEGRA186_IO_PAD_TABLE(_pad) \
@@ -2874,6 +3112,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
.wake_events = tegra186_wake_events,
+ .pmc_clks_data = NULL,
+ .num_pmc_clks = 0,
};
static const struct tegra_io_pad_soc tegra194_io_pads[] = {
@@ -2991,6 +3231,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra194_wake_events),
.wake_events = tegra194_wake_events,
+ .pmc_clks_data = NULL,
+ .num_pmc_clks = 0,
};
static const struct of_device_id tegra_pmc_match[] = {
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 08/22] soc: tegra: Add Tegra PMC clocks registration into PMC driver
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3 clocks and currently
these PMC clocks are registered by Tegra clock driver with each clock as
separate mux and gate clocks using clk_register_mux and clk_register_gate
by passing PMC base address and register offsets and PMC programming for
these clocks happens through direct PMC access by the clock driver.
With this, when PMC is in secure mode any direct PMC access from the
non-secure world does not go through and these clocks will not be
functional.
This patch adds these PMC clocks registration to pmc driver with PMC as
a clock provider and registers each clock as single clock.
clk_ops callback implementations for these clocks uses tegra_pmc_readl and
tegra_pmc_writel which supports PMC programming in both secure mode and
non-secure mode.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/soc/tegra/pmc.c | 242 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 242 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 1699dda6b393..ecce91517af2 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -13,9 +13,13 @@
#include <linux/arm-smccc.h>
#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/clk-conf.h>
#include <linux/clk/tegra.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
+#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
@@ -48,6 +52,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/gpio/tegra194-gpio.h>
+#include <dt-bindings/soc/tegra-pmc.h>
#define PMC_CNTRL 0x0
#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
@@ -100,6 +105,8 @@
#define PMC_WAKE2_STATUS 0x168
#define PMC_SW_WAKE2_STATUS 0x16c
+#define PMC_CLK_OUT_CNTRL 0x1a8
+#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
#define PMC_SENSOR_CTRL 0x1b0
#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
@@ -155,6 +162,63 @@
#define TEGRA_SMC_PMC_READ 0xaa
#define TEGRA_SMC_PMC_WRITE 0xbb
+struct pmc_clk {
+ struct clk_hw hw;
+ unsigned long offs;
+ u32 mux_shift;
+ u32 force_en_shift;
+};
+
+#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
+
+struct pmc_clk_init_data {
+ char *name;
+ const char *const *parents;
+ int num_parents;
+ int clk_id;
+ u8 mux_shift;
+ u8 force_en_shift;
+};
+
+static const char * const clk_out1_parents[] = { "osc", "osc_div2",
+ "osc_div4", "extern1",
+};
+
+static const char * const clk_out2_parents[] = { "osc", "osc_div2",
+ "osc_div4", "extern2",
+};
+
+static const char * const clk_out3_parents[] = { "osc", "osc_div2",
+ "osc_div4", "extern3",
+};
+
+static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
+ {
+ .name = "pmc_clk_out_1",
+ .parents = clk_out1_parents,
+ .num_parents = ARRAY_SIZE(clk_out1_parents),
+ .clk_id = TEGRA_PMC_CLK_OUT_1,
+ .mux_shift = 6,
+ .force_en_shift = 2,
+ },
+ {
+ .name = "pmc_clk_out_2",
+ .parents = clk_out2_parents,
+ .num_parents = ARRAY_SIZE(clk_out2_parents),
+ .clk_id = TEGRA_PMC_CLK_OUT_2,
+ .mux_shift = 14,
+ .force_en_shift = 10,
+ },
+ {
+ .name = "pmc_clk_out_3",
+ .parents = clk_out3_parents,
+ .num_parents = ARRAY_SIZE(clk_out3_parents),
+ .clk_id = TEGRA_PMC_CLK_OUT_3,
+ .mux_shift = 22,
+ .force_en_shift = 18,
+ },
+};
+
struct tegra_powergate {
struct generic_pm_domain genpd;
struct tegra_pmc *pmc;
@@ -254,6 +318,9 @@ struct tegra_pmc_soc {
*/
const struct tegra_wake_event *wake_events;
unsigned int num_wake_events;
+
+ const struct pmc_clk_init_data *pmc_clks_data;
+ unsigned int num_pmc_clks;
};
static const char * const tegra186_reset_sources[] = {
@@ -2163,6 +2230,166 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
return NOTIFY_OK;
}
+static void pmc_clk_fence_udelay(u32 offset)
+{
+ tegra_pmc_readl(pmc, offset);
+ /* pmc clk propagation delay 2 us */
+ udelay(2);
+}
+
+static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
+ val &= PMC_CLK_OUT_MUX_MASK;
+
+ return val;
+}
+
+static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, clk->offs);
+ val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
+ val |= index << clk->mux_shift;
+ tegra_pmc_writel(pmc, val, clk->offs);
+ pmc_clk_fence_udelay(clk->offs);
+
+ return 0;
+}
+
+static int pmc_clk_is_enabled(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
+
+ return val ? 1 : 0;
+}
+
+static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
+{
+ u32 val;
+
+ val = tegra_pmc_readl(pmc, offs);
+ val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
+ tegra_pmc_writel(pmc, val, offs);
+ pmc_clk_fence_udelay(offs);
+}
+
+static int pmc_clk_enable(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+
+ pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
+
+ return 0;
+}
+
+static void pmc_clk_disable(struct clk_hw *hw)
+{
+ struct pmc_clk *clk = to_pmc_clk(hw);
+
+ pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
+}
+
+static const struct clk_ops pmc_clk_ops = {
+ .get_parent = pmc_clk_mux_get_parent,
+ .set_parent = pmc_clk_mux_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+ .is_enabled = pmc_clk_is_enabled,
+ .enable = pmc_clk_enable,
+ .disable = pmc_clk_disable,
+};
+
+static struct clk *
+tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
+ const struct pmc_clk_init_data *data,
+ unsigned long offset)
+{
+ struct clk_init_data init;
+ struct pmc_clk *pmc_clk;
+
+ pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
+ if (!pmc_clk)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = data->name;
+ init.ops = &pmc_clk_ops;
+ init.parent_names = data->parents;
+ init.num_parents = data->num_parents;
+ init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+ CLK_SET_PARENT_GATE;
+
+ pmc_clk->hw.init = &init;
+ pmc_clk->offs = offset;
+ pmc_clk->mux_shift = data->mux_shift;
+ pmc_clk->force_en_shift = data->force_en_shift;
+
+ return clk_register(NULL, &pmc_clk->hw);
+}
+
+static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
+ struct device_node *np)
+{
+ struct clk *clk;
+ struct clk_onecell_data *clk_data;
+ unsigned int num_clks;
+ int i, err;
+
+ num_clks = pmc->soc->num_pmc_clks;
+
+ if (!num_clks)
+ return;
+
+ clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
+ sizeof(*clk_data->clks), GFP_KERNEL);
+ if (!clk_data->clks)
+ return;
+
+ clk_data->clk_num = TEGRA_PMC_CLK_MAX;
+
+ for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
+ clk_data->clks[i] = ERR_PTR(-ENOENT);
+
+ for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
+ const struct pmc_clk_init_data *data;
+
+ data = pmc->soc->pmc_clks_data + i;
+
+ clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
+ if (IS_ERR(clk)) {
+ dev_warn(pmc->dev, "unable to register clock %s: %d\n",
+ data->name, PTR_ERR_OR_ZERO(clk));
+ return;
+ }
+
+ err = clk_register_clkdev(clk, data->name, NULL);
+ if (err) {
+ dev_warn(pmc->dev,
+ "unable to register %s clock lookup: %d\n",
+ data->name, err);
+ return;
+ }
+
+ clk_data->clks[data->clk_id] = clk;
+ }
+
+ err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+ if (err)
+ dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
+ err);
+}
+
static int tegra_pmc_probe(struct platform_device *pdev)
{
void __iomem *base;
@@ -2281,6 +2508,7 @@ static int tegra_pmc_probe(struct platform_device *pdev)
pmc->base = base;
mutex_unlock(&pmc->powergates_lock);
+ tegra_pmc_clock_register(pmc, pdev->dev.of_node);
platform_set_drvdata(pdev, pmc);
return 0;
@@ -2422,6 +2650,8 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
.num_reset_sources = 0,
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = NULL,
+ .num_pmc_clks = 0,
};
static const char * const tegra30_powergates[] = {
@@ -2469,6 +2699,8 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
static const char * const tegra114_powergates[] = {
@@ -2520,6 +2752,8 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
static const char * const tegra124_powergates[] = {
@@ -2631,6 +2865,8 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
.reset_levels = NULL,
.num_reset_levels = 0,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
static const char * const tegra210_powergates[] = {
@@ -2745,6 +2981,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
.num_reset_levels = 0,
.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
.wake_events = tegra210_wake_events,
+ .pmc_clks_data = tegra_pmc_clks_data,
+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
};
#define TEGRA186_IO_PAD_TABLE(_pad) \
@@ -2874,6 +3112,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
.wake_events = tegra186_wake_events,
+ .pmc_clks_data = NULL,
+ .num_pmc_clks = 0,
};
static const struct tegra_io_pad_soc tegra194_io_pads[] = {
@@ -2991,6 +3231,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {
.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
.num_wake_events = ARRAY_SIZE(tegra194_wake_events),
.wake_events = tegra194_wake_events,
+ .pmc_clks_data = NULL,
+ .num_pmc_clks = 0,
};
static const struct of_device_id tegra_pmc_match[] = {
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 09/22] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Tegra PMC has blink functionality that allows 32KHz clock out to
blink pin of the Tegra.
This patch adds id for this blink clock to use for enabling or
disabling blink output through device tree.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 2 ++
include/dt-bindings/soc/tegra-pmc.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 5b5c42a00264..f17bb353f65e 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -44,6 +44,8 @@ properties:
const: 1
description:
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
+ PMC also has blink control which allows 32Khz clock output to
+ Tegra blink pad.
Consumer of PMC clock should specify the desired clock by having
the clock ID in its "clocks" phandle cell with pmc clock provider.
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h
index f7c866404456..a99a457471ee 100644
--- a/include/dt-bindings/soc/tegra-pmc.h
+++ b/include/dt-bindings/soc/tegra-pmc.h
@@ -9,7 +9,8 @@
#define TEGRA_PMC_CLK_OUT_1 0
#define TEGRA_PMC_CLK_OUT_2 1
#define TEGRA_PMC_CLK_OUT_3 2
+#define TEGRA_PMC_CLK_BLINK 3
-#define TEGRA_PMC_CLK_MAX 3
+#define TEGRA_PMC_CLK_MAX 4
#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 09/22] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Tegra PMC has blink functionality that allows 32KHz clock out to
blink pin of the Tegra.
This patch adds id for this blink clock to use for enabling or
disabling blink output through device tree.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 2 ++
include/dt-bindings/soc/tegra-pmc.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 5b5c42a00264..f17bb353f65e 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -44,6 +44,8 @@ properties:
const: 1
description:
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
+ PMC also has blink control which allows 32Khz clock output to
+ Tegra blink pad.
Consumer of PMC clock should specify the desired clock by having
the clock ID in its "clocks" phandle cell with pmc clock provider.
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h
index f7c866404456..a99a457471ee 100644
--- a/include/dt-bindings/soc/tegra-pmc.h
+++ b/include/dt-bindings/soc/tegra-pmc.h
@@ -9,7 +9,8 @@
#define TEGRA_PMC_CLK_OUT_1 0
#define TEGRA_PMC_CLK_OUT_2 1
#define TEGRA_PMC_CLK_OUT_3 2
+#define TEGRA_PMC_CLK_BLINK 3
-#define TEGRA_PMC_CLK_MAX 3
+#define TEGRA_PMC_CLK_MAX 4
#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
are moved to Tegra PMC driver with pmc as clock provider and using pmc
clock ids.
New device tree uses clk_out_1 from pmc clock provider as audio mclk.
So, this patch adds implementation for mclk fallback to extern1 when
retrieving mclk returns -ENOENT to be backward compatible of new device
tree with older kernels.
Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index 536a578e9512..74d3ffe7e603 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -191,9 +191,21 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
data->clk_cdev1 = clk_get(dev, "mclk");
if (IS_ERR(data->clk_cdev1)) {
- dev_err(data->dev, "Can't retrieve clk cdev1\n");
- ret = PTR_ERR(data->clk_cdev1);
- goto err_put_pll_a_out0;
+ if (PTR_ERR(data->clk_cdev1) != -ENOENT) {
+ dev_err(data->dev, "Can't retrieve clk cdev1\n");
+ ret = PTR_ERR(data->clk_cdev1);
+ goto err_put_pll_a_out0;
+ }
+
+ /* Fall back to extern1 */
+ data->clk_cdev1 = clk_get(dev, "extern1");
+ if (IS_ERR(data->clk_cdev1)) {
+ dev_err(data->dev, "Can't retrieve clk extern1\n");
+ ret = PTR_ERR(data->clk_cdev1);
+ goto err_put_pll_a_out0;
+ }
+
+ dev_info(data->dev, "Falling back to extern1\n");
}
ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
are moved to Tegra PMC driver with pmc as clock provider and using pmc
clock ids.
New device tree uses clk_out_1 from pmc clock provider as audio mclk.
So, this patch adds implementation for mclk fallback to extern1 when
retrieving mclk returns -ENOENT to be backward compatible of new device
tree with older kernels.
Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
index 536a578e9512..74d3ffe7e603 100644
--- a/sound/soc/tegra/tegra_asoc_utils.c
+++ b/sound/soc/tegra/tegra_asoc_utils.c
@@ -191,9 +191,21 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
data->clk_cdev1 = clk_get(dev, "mclk");
if (IS_ERR(data->clk_cdev1)) {
- dev_err(data->dev, "Can't retrieve clk cdev1\n");
- ret = PTR_ERR(data->clk_cdev1);
- goto err_put_pll_a_out0;
+ if (PTR_ERR(data->clk_cdev1) != -ENOENT) {
+ dev_err(data->dev, "Can't retrieve clk cdev1\n");
+ ret = PTR_ERR(data->clk_cdev1);
+ goto err_put_pll_a_out0;
+ }
+
+ /* Fall back to extern1 */
+ data->clk_cdev1 = clk_get(dev, "extern1");
+ if (IS_ERR(data->clk_cdev1)) {
+ dev_err(data->dev, "Can't retrieve clk extern1\n");
+ ret = PTR_ERR(data->clk_cdev1);
+ goto err_put_pll_a_out0;
+ }
+
+ dev_info(data->dev, "Falling back to extern1\n");
}
ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
2020-01-14 7:24 ` Sowjanya Komatineni
(?)
@ 2020-01-23 23:56 ` Dmitry Osipenko
[not found] ` <aef36b46-789a-c44e-4cd1-9d4183435ba9-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
-1 siblings, 1 reply; 85+ messages in thread
From: Dmitry Osipenko @ 2020-01-23 23:56 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, broonie,
lgirdwood, perex, tiwai, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
14.01.2020 10:24, Sowjanya Komatineni пишет:
> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
> are moved to Tegra PMC driver with pmc as clock provider and using pmc
> clock ids.
>
> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>
> So, this patch adds implementation for mclk fallback to extern1 when
> retrieving mclk returns -ENOENT to be backward compatible of new device
> tree with older kernels.
>
> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
>
> Tested-by: Dmitry Osipenko <digetx@gmail.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/tegra/tegra_asoc_utils.c b/sound/soc/tegra/tegra_asoc_utils.c
> index 536a578e9512..74d3ffe7e603 100644
> --- a/sound/soc/tegra/tegra_asoc_utils.c
> +++ b/sound/soc/tegra/tegra_asoc_utils.c
> @@ -191,9 +191,21 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
>
> data->clk_cdev1 = clk_get(dev, "mclk");
> if (IS_ERR(data->clk_cdev1)) {
> - dev_err(data->dev, "Can't retrieve clk cdev1\n");
> - ret = PTR_ERR(data->clk_cdev1);
> - goto err_put_pll_a_out0;
> + if (PTR_ERR(data->clk_cdev1) != -ENOENT) {
> + dev_err(data->dev, "Can't retrieve clk cdev1\n");
> + ret = PTR_ERR(data->clk_cdev1);
> + goto err_put_pll_a_out0;
> + }
> +
> + /* Fall back to extern1 */
> + data->clk_cdev1 = clk_get(dev, "extern1");
> + if (IS_ERR(data->clk_cdev1)) {
> + dev_err(data->dev, "Can't retrieve clk extern1\n");
> + ret = PTR_ERR(data->clk_cdev1);
> + goto err_put_pll_a_out0;
> + }
> +
> + dev_info(data->dev, "Falling back to extern1\n");
> }
>
> ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
>
I tried to double-check if audio works using the updated DT works with
this fallback and unfortunately it is not (maybe I actually missed to
test this case before).. the driver doesn't probe at all because of the
assigned-clocks presence, which makes clk core to fail finding the MCLK
and thus assigned-clocks configuration fails, preventing the driver's
loading.
I'm not sure what could be done about it. Perhaps just to give up on the
compatibility of older kernels with the new DTs, missing audio isn't
really that critical (perhaps).
^ permalink raw reply [flat|nested] 85+ messages in thread
[parent not found: <1578986667-16041-12-git-send-email-skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-19 15:08 ` Dmitry Osipenko
-1 siblings, 0 replies; 85+ messages in thread
From: Dmitry Osipenko @ 2020-01-19 15:08 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
14.01.2020 10:24, Sowjanya Komatineni пишет:
> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
> are moved to Tegra PMC driver with pmc as clock provider and using pmc
> clock ids.
>
> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>
> So, this patch adds implementation for mclk fallback to extern1 when
> retrieving mclk returns -ENOENT to be backward compatible of new device
> tree with older kernels.
>
> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
I don't think that it is correct to use the Fixes tag here because this
patch doesn't fix any real problem of the referenced commit, instead the
Stable CC tag should be used.
> Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---[snip]
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
@ 2020-01-19 15:08 ` Dmitry Osipenko
0 siblings, 0 replies; 85+ messages in thread
From: Dmitry Osipenko @ 2020-01-19 15:08 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, broonie,
lgirdwood, perex, tiwai, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
14.01.2020 10:24, Sowjanya Komatineni пишет:
> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
> are moved to Tegra PMC driver with pmc as clock provider and using pmc
> clock ids.
>
> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>
> So, this patch adds implementation for mclk fallback to extern1 when
> retrieving mclk returns -ENOENT to be backward compatible of new device
> tree with older kernels.
>
> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
I don't think that it is correct to use the Fixes tag here because this
patch doesn't fix any real problem of the referenced commit, instead the
Stable CC tag should be used.
> Tested-by: Dmitry Osipenko <digetx@gmail.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---[snip]
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-02-17 9:40 ` Thierry Reding
-1 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-02-17 9:40 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 1107 bytes --]
On Mon, Jan 13, 2020 at 11:24:16PM -0800, Sowjanya Komatineni wrote:
> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
> are moved to Tegra PMC driver with pmc as clock provider and using pmc
> clock ids.
>
> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>
> So, this patch adds implementation for mclk fallback to extern1 when
> retrieving mclk returns -ENOENT to be backward compatible of new device
> tree with older kernels.
>
> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
>
> Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
There's some inconsistent spelling of PMC in the above, but other than
that:
Acked-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
@ 2020-02-17 9:40 ` Thierry Reding
0 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-02-17 9:40 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, broonie, lgirdwood, perex, tiwai, digetx, mperttunen,
gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 989 bytes --]
On Mon, Jan 13, 2020 at 11:24:16PM -0800, Sowjanya Komatineni wrote:
> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
> are moved to Tegra PMC driver with pmc as clock provider and using pmc
> clock ids.
>
> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>
> So, this patch adds implementation for mclk fallback to extern1 when
> retrieving mclk returns -ENOENT to be backward compatible of new device
> tree with older kernels.
>
> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
>
> Tested-by: Dmitry Osipenko <digetx@gmail.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
There's some inconsistent spelling of PMC in the above, but other than
that:
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
2020-02-17 9:40 ` Thierry Reding
@ 2020-02-17 14:51 ` Dmitry Osipenko
-1 siblings, 0 replies; 85+ messages in thread
From: Dmitry Osipenko @ 2020-02-17 14:51 UTC (permalink / raw)
To: Thierry Reding, Sowjanya Komatineni
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
17.02.2020 12:40, Thierry Reding пишет:
> On Mon, Jan 13, 2020 at 11:24:16PM -0800, Sowjanya Komatineni wrote:
>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>> clock ids.
>>
>> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>>
>> So, this patch adds implementation for mclk fallback to extern1 when
>> retrieving mclk returns -ENOENT to be backward compatible of new device
>> tree with older kernels.
>>
>> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
>>
>> Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
>> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> There's some inconsistent spelling of PMC in the above, but other than
> that:
>
> Acked-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
Seems you missed my point.. this patch doesn't work at all, and thus, it
should be dropped.
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk
@ 2020-02-17 14:51 ` Dmitry Osipenko
0 siblings, 0 replies; 85+ messages in thread
From: Dmitry Osipenko @ 2020-02-17 14:51 UTC (permalink / raw)
To: Thierry Reding, Sowjanya Komatineni
Cc: jonathanh, broonie, lgirdwood, perex, tiwai, mperttunen, gregkh,
sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad, spujar,
josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
17.02.2020 12:40, Thierry Reding пишет:
> On Mon, Jan 13, 2020 at 11:24:16PM -0800, Sowjanya Komatineni wrote:
>> mclk is from clk_out_1 which is part of Tegra PMC block and pmc clocks
>> are moved to Tegra PMC driver with pmc as clock provider and using pmc
>> clock ids.
>>
>> New device tree uses clk_out_1 from pmc clock provider as audio mclk.
>>
>> So, this patch adds implementation for mclk fallback to extern1 when
>> retrieving mclk returns -ENOENT to be backward compatible of new device
>> tree with older kernels.
>>
>> Fixes: 110147c8c513 ("ASoC: tegra: always use clk_get() in utility code")
>>
>> Tested-by: Dmitry Osipenko <digetx@gmail.com>
>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> sound/soc/tegra/tegra_asoc_utils.c | 18 +++++++++++++++---
>> 1 file changed, 15 insertions(+), 3 deletions(-)
>
> There's some inconsistent spelling of PMC in the above, but other than
> that:
>
> Acked-by: Thierry Reding <treding@nvidia.com>
>
Seems you missed my point.. this patch doesn't work at all, and thus, it
should be dropped.
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v8 13/22] ARM: dts: tegra: Add clock-cells property to pmc
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock.
These clocks are moved from clock driver to pmc driver with pmc
as the clock provider for these clocks.
This patch adds #clock-cells property with 1 clock specifier to
the Tegra PMC node in device tree.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/tegra114.dtsi | 4 +++-
arch/arm/boot/dts/tegra124.dtsi | 4 +++-
arch/arm/boot/dts/tegra20.dtsi | 4 +++-
arch/arm/boot/dts/tegra30.dtsi | 4 +++-
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0d7a6327e404..450a1f1b12a0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra114-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra114";
@@ -514,11 +515,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 413bfb981de8..bd7fad35d29a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra124-car.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra124";
@@ -595,11 +596,12 @@
clocks = <&tegra_car TEGRA124_CLK_RTC>;
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9c58e7fcf5c0..c3b8ad53b967 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra20-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra20";
@@ -608,11 +609,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
mc: memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 55ae050042ce..d2d05f1da274 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra30-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra30";
@@ -714,11 +715,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
mc: memory-controller@7000f000 {
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 13/22] ARM: dts: tegra: Add clock-cells property to pmc
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Tegra PMC has clk_out_1, clk_out_2, clk_out_3, and blink clock.
These clocks are moved from clock driver to pmc driver with pmc
as the clock provider for these clocks.
This patch adds #clock-cells property with 1 clock specifier to
the Tegra PMC node in device tree.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm/boot/dts/tegra114.dtsi | 4 +++-
arch/arm/boot/dts/tegra124.dtsi | 4 +++-
arch/arm/boot/dts/tegra20.dtsi | 4 +++-
arch/arm/boot/dts/tegra30.dtsi | 4 +++-
4 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0d7a6327e404..450a1f1b12a0 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra114-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra114";
@@ -514,11 +515,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 413bfb981de8..bd7fad35d29a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra124-car.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra124";
@@ -595,11 +596,12 @@
clocks = <&tegra_car TEGRA124_CLK_RTC>;
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 9c58e7fcf5c0..c3b8ad53b967 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra20-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra20";
@@ -608,11 +609,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
mc: memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 55ae050042ce..d2d05f1da274 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra30-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra30";
@@ -714,11 +715,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
mc: memory-controller@7000f000 {
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 14/22] arm64: tegra: Add clock-cells property to Tegra PMC node
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3,
and a blink clock as a part of PMC.
These clocks are moved from clock driver to pmc driver with pmc as a
clock provider.
Clock ids for these clocks are defined in pmc dt-bindings.
This patch updated device tree to include pmc dt-binding and adds
#clock-cells property with one clock specifier to pmc node.
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++-
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 631a7f77c386..79b1e3b01096 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra132", "nvidia,tegra124";
@@ -577,11 +578,12 @@
clock-names = "rtc";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 48c63256ba7f..3e73b76249f9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra210";
@@ -770,16 +771,17 @@
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&pmc>;
+ interrupt-parent = <&tegra_pmc>;
clocks = <&tegra_car TEGRA210_CLK_RTC>;
clock-names = "rtc";
};
- pmc: pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 14/22] arm64: tegra: Add clock-cells property to Tegra PMC node
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3,
and a blink clock as a part of PMC.
These clocks are moved from clock driver to pmc driver with pmc as a
clock provider.
Clock ids for these clocks are defined in pmc dt-bindings.
This patch updated device tree to include pmc dt-binding and adds
#clock-cells property with one clock specifier to pmc node.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++-
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 631a7f77c386..79b1e3b01096 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra132", "nvidia,tegra124";
@@ -577,11 +578,12 @@
clock-names = "rtc";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 48c63256ba7f..3e73b76249f9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra210";
@@ -770,16 +771,17 @@
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&pmc>;
+ interrupt-parent = <&tegra_pmc>;
clocks = <&tegra_car TEGRA210_CLK_RTC>;
clock-names = "rtc";
};
- pmc: pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 16/22] arm64: tegra: smaug: Change clk_out_2 provider to pmc
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
clk_out_2 is one of the clocks from Tegra PMC block and Tegra PMC
clocks are moved from clock driver to pmc driver with pmc as clock
provider and using pmc clock ids.
This patch changes clk_out_2 provider to pmc and uses corresponding
pmc clock id for clk_out_2.
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 72c7a04ac1df..2faab6390552 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1592,7 +1592,7 @@
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
- clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>;
clock-names = "mclk";
nuvoton,jkdet-enable;
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 16/22] arm64: tegra: smaug: Change clk_out_2 provider to pmc
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
clk_out_2 is one of the clocks from Tegra PMC block and Tegra PMC
clocks are moved from clock driver to pmc driver with pmc as clock
provider and using pmc clock ids.
This patch changes clk_out_2 provider to pmc and uses corresponding
pmc clock id for clk_out_2.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 72c7a04ac1df..2faab6390552 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1592,7 +1592,7 @@
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
- clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>;
clock-names = "mclk";
nuvoton,jkdet-enable;
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 20/22] clk: tegra: Remove tegra_pmc_clk_init along with clk ids
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct
PMC register access during clk_ops and these PMC register read and write
access will not happen when PMC is in secure mode.
Any direct PMC register access from non-secure world will not go
through.
All the PMC clocks are moved to Tegra PMC driver with PMC as a clock
provider.
This patch removes tegra_pmc_clk_init along with corresponding clk ids
from Tegra clock driver.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/Makefile | 1 -
drivers/clk/tegra/clk-id.h | 7 ---
drivers/clk/tegra/clk-tegra-pmc.c | 122 --------------------------------------
drivers/clk/tegra/clk-tegra114.c | 17 +-----
drivers/clk/tegra/clk-tegra124.c | 33 ++++-------
drivers/clk/tegra/clk-tegra20.c | 4 --
drivers/clk/tegra/clk-tegra210.c | 17 +-----
drivers/clk/tegra/clk-tegra30.c | 18 +-----
drivers/clk/tegra/clk.h | 1 -
9 files changed, 19 insertions(+), 201 deletions(-)
delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index df966ca06788..1f7c30f87ece 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -12,7 +12,6 @@ obj-y += clk-sdmmc-mux.o
obj-y += clk-super.o
obj-y += clk-tegra-audio.o
obj-y += clk-tegra-periph.o
-obj-y += clk-tegra-pmc.o
obj-y += clk-tegra-fixed.o
obj-y += clk-tegra-super-gen4.o
obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index cf42e5995794..ff7da2d3e94d 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -32,7 +32,6 @@ enum clk_id {
tegra_clk_audio4,
tegra_clk_audio4_2x,
tegra_clk_audio4_mux,
- tegra_clk_blink,
tegra_clk_bsea,
tegra_clk_bsev,
tegra_clk_cclk_g,
@@ -47,12 +46,6 @@ enum clk_id {
tegra_clk_osc,
tegra_clk_osc_div2,
tegra_clk_osc_div4,
- tegra_clk_clk_out_1,
- tegra_clk_clk_out_1_mux,
- tegra_clk_clk_out_2,
- tegra_clk_clk_out_2_mux,
- tegra_clk_clk_out_3,
- tegra_clk_clk_out_3_mux,
tegra_clk_cml0,
tegra_clk_cml1,
tegra_clk_csi,
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
deleted file mode 100644
index 5e044ba1ae36..000000000000
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <linux/io.h>
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/clk/tegra.h>
-
-#include "clk.h"
-#include "clk-id.h"
-
-#define PMC_CLK_OUT_CNTRL 0x1a8
-#define PMC_DPD_PADS_ORIDE 0x1c
-#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
-#define PMC_CTRL 0
-#define PMC_CTRL_BLINK_ENB 7
-#define PMC_BLINK_TIMER 0x40
-
-struct pmc_clk_init_data {
- char *mux_name;
- char *gate_name;
- const char **parents;
- int num_parents;
- int mux_id;
- int gate_id;
- char *dev_name;
- u8 mux_shift;
- u8 gate_shift;
-};
-
-#define PMC_CLK(_num, _mux_shift, _gate_shift)\
- {\
- .mux_name = "clk_out_" #_num "_mux",\
- .gate_name = "clk_out_" #_num,\
- .parents = clk_out ##_num ##_parents,\
- .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
- .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
- .gate_id = tegra_clk_clk_out_ ##_num,\
- .dev_name = "extern" #_num,\
- .mux_shift = _mux_shift,\
- .gate_shift = _gate_shift,\
- }
-
-static DEFINE_SPINLOCK(clk_out_lock);
-
-static const char *clk_out1_parents[] = { "osc", "osc_div2",
- "osc_div4", "extern1",
-};
-
-static const char *clk_out2_parents[] = { "osc", "osc_div2",
- "osc_div4", "extern2",
-};
-
-static const char *clk_out3_parents[] = { "osc", "osc_div2",
- "osc_div4", "extern3",
-};
-
-static struct pmc_clk_init_data pmc_clks[] = {
- PMC_CLK(1, 6, 2),
- PMC_CLK(2, 14, 10),
- PMC_CLK(3, 22, 18),
-};
-
-void __init tegra_pmc_clk_init(void __iomem *pmc_base,
- struct tegra_clk *tegra_clks)
-{
- struct clk *clk;
- struct clk **dt_clk;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
- struct pmc_clk_init_data *data;
-
- data = pmc_clks + i;
-
- dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
- if (!dt_clk)
- continue;
-
- clk = clk_register_mux(NULL, data->mux_name, data->parents,
- data->num_parents,
- CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
- pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
- 3, 0, &clk_out_lock);
- *dt_clk = clk;
-
-
- dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
- if (!dt_clk)
- continue;
-
- clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
- CLK_SET_RATE_PARENT,
- pmc_base + PMC_CLK_OUT_CNTRL,
- data->gate_shift, 0, &clk_out_lock);
- *dt_clk = clk;
- clk_register_clkdev(clk, data->dev_name, data->gate_name);
- }
-
- /* blink */
- writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
- clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
- pmc_base + PMC_DPD_PADS_ORIDE,
- PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
-
- dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
- if (!dt_clk)
- return;
-
- clk = clk_register_gate(NULL, "blink", "blink_override", 0,
- pmc_base + PMC_CTRL,
- PMC_CTRL_BLINK_ENB, 0, NULL);
- clk_register_clkdev(clk, "blink", NULL);
- *dt_clk = clk;
-}
-
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 180ddc2abfd2..c138ef75480b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -779,10 +779,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
@@ -804,9 +800,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
@@ -865,10 +858,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
@@ -1147,8 +1139,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
- { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1350,7 +1340,6 @@ static void __init tegra114_clock_init(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
tegra114_audio_plls,
ARRAY_SIZE(tegra114_audio_plls), 24000000);
- tegra_pmc_clk_init(pmc_base, tegra114_clks);
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
&pll_x_params);
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 7a16e50eb20f..54cac77deaa3 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -903,10 +903,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
[tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
[tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
@@ -932,9 +928,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
};
@@ -990,10 +983,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
{ .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
{ .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
@@ -1303,8 +1295,6 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
- { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1459,11 +1449,9 @@ static void __init tegra132_clock_apply_init_table(void)
* tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
* @np: struct device_node * of the DT node for the SoC CAR IP block
*
- * Register most of the clocks controlled by the CAR IP block, along
- * with a few clocks controlled by the PMC IP block. Everything in
- * this function should be common to Tegra124 and Tegra132. XXX The
- * PMC clock initialization should probably be moved to PMC-specific
- * driver code. No return value.
+ * Register most of the clocks controlled by the CAR IP block.
+ * Everything in this function should be common to Tegra124 and Tegra132.
+ * No return value.
*/
static void __init tegra124_132_clock_init_pre(struct device_node *np)
{
@@ -1506,7 +1494,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
tegra124_audio_plls,
ARRAY_SIZE(tegra124_audio_plls), 24576000);
- tegra_pmc_clk_init(pmc_base, tegra124_clks);
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
plld_base = readl(clk_base + PLLD_BASE);
@@ -1518,11 +1505,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
* tegra124_132_clock_init_post - clock initialization postamble for T124/T132
* @np: struct device_node * of the DT node for the SoC CAR IP block
*
- * Register most of the along with a few clocks controlled by the PMC
- * IP block. Everything in this function should be common to Tegra124
+ * Register most of the clocks controlled by the CAR IP block.
+ * Everything in this function should be common to Tegra124
* and Tegra132. This function must be called after
- * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
- * not be set. No return value.
+ * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
+ * No return value.
*/
static void __init tegra124_132_clock_init_post(struct device_node *np)
{
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 4d8222f5c638..fe536f1d770d 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
- { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
{ .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
@@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
[tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
[tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
[tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
[tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
[tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
@@ -1034,7 +1032,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
- { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
@@ -1148,7 +1145,6 @@ static void __init tegra20_clock_init(struct device_node *np)
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
tegra20_periph_clk_init();
tegra20_audio_clk_init();
- tegra_pmc_clk_init(pmc_base, tegra20_clks);
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 45d54ead30bc..d2f1e9c0ed25 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2418,10 +2418,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
@@ -2453,9 +2449,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
@@ -2542,10 +2535,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
@@ -3453,8 +3445,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
- { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -3695,7 +3685,6 @@ static void __init tegra210_clock_init(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
tegra210_audio_plls,
ARRAY_SIZE(tegra210_audio_plls), 24576000);
- tegra_pmc_clk_init(pmc_base, tegra210_clks);
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
value = readl(clk_base + PLLD_BASE);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ddc5ab66d09e..5732fdbe20db 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -569,10 +569,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
{ .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
{ .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
@@ -713,13 +712,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
[tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
[tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
[tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
[tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
@@ -1232,9 +1224,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
- { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
- { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1366,7 +1355,6 @@ static void __init tegra30_clock_init(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
tegra30_audio_plls,
ARRAY_SIZE(tegra30_audio_plls), 24000000);
- tegra_pmc_clk_init(pmc_base, tegra30_clks);
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 416a6b09f6a3..2c9a68302e02 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -854,7 +854,6 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params);
-void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned long *input_freqs, unsigned int num,
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 20/22] clk: tegra: Remove tegra_pmc_clk_init along with clk ids
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct
PMC register access during clk_ops and these PMC register read and write
access will not happen when PMC is in secure mode.
Any direct PMC register access from non-secure world will not go
through.
All the PMC clocks are moved to Tegra PMC driver with PMC as a clock
provider.
This patch removes tegra_pmc_clk_init along with corresponding clk ids
from Tegra clock driver.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/clk/tegra/Makefile | 1 -
drivers/clk/tegra/clk-id.h | 7 ---
drivers/clk/tegra/clk-tegra-pmc.c | 122 --------------------------------------
drivers/clk/tegra/clk-tegra114.c | 17 +-----
drivers/clk/tegra/clk-tegra124.c | 33 ++++-------
drivers/clk/tegra/clk-tegra20.c | 4 --
drivers/clk/tegra/clk-tegra210.c | 17 +-----
drivers/clk/tegra/clk-tegra30.c | 18 +-----
drivers/clk/tegra/clk.h | 1 -
9 files changed, 19 insertions(+), 201 deletions(-)
delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index df966ca06788..1f7c30f87ece 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -12,7 +12,6 @@ obj-y += clk-sdmmc-mux.o
obj-y += clk-super.o
obj-y += clk-tegra-audio.o
obj-y += clk-tegra-periph.o
-obj-y += clk-tegra-pmc.o
obj-y += clk-tegra-fixed.o
obj-y += clk-tegra-super-gen4.o
obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index cf42e5995794..ff7da2d3e94d 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -32,7 +32,6 @@ enum clk_id {
tegra_clk_audio4,
tegra_clk_audio4_2x,
tegra_clk_audio4_mux,
- tegra_clk_blink,
tegra_clk_bsea,
tegra_clk_bsev,
tegra_clk_cclk_g,
@@ -47,12 +46,6 @@ enum clk_id {
tegra_clk_osc,
tegra_clk_osc_div2,
tegra_clk_osc_div4,
- tegra_clk_clk_out_1,
- tegra_clk_clk_out_1_mux,
- tegra_clk_clk_out_2,
- tegra_clk_clk_out_2_mux,
- tegra_clk_clk_out_3,
- tegra_clk_clk_out_3_mux,
tegra_clk_cml0,
tegra_clk_cml1,
tegra_clk_csi,
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
deleted file mode 100644
index 5e044ba1ae36..000000000000
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
- */
-
-#include <linux/io.h>
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/clk/tegra.h>
-
-#include "clk.h"
-#include "clk-id.h"
-
-#define PMC_CLK_OUT_CNTRL 0x1a8
-#define PMC_DPD_PADS_ORIDE 0x1c
-#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
-#define PMC_CTRL 0
-#define PMC_CTRL_BLINK_ENB 7
-#define PMC_BLINK_TIMER 0x40
-
-struct pmc_clk_init_data {
- char *mux_name;
- char *gate_name;
- const char **parents;
- int num_parents;
- int mux_id;
- int gate_id;
- char *dev_name;
- u8 mux_shift;
- u8 gate_shift;
-};
-
-#define PMC_CLK(_num, _mux_shift, _gate_shift)\
- {\
- .mux_name = "clk_out_" #_num "_mux",\
- .gate_name = "clk_out_" #_num,\
- .parents = clk_out ##_num ##_parents,\
- .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
- .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
- .gate_id = tegra_clk_clk_out_ ##_num,\
- .dev_name = "extern" #_num,\
- .mux_shift = _mux_shift,\
- .gate_shift = _gate_shift,\
- }
-
-static DEFINE_SPINLOCK(clk_out_lock);
-
-static const char *clk_out1_parents[] = { "osc", "osc_div2",
- "osc_div4", "extern1",
-};
-
-static const char *clk_out2_parents[] = { "osc", "osc_div2",
- "osc_div4", "extern2",
-};
-
-static const char *clk_out3_parents[] = { "osc", "osc_div2",
- "osc_div4", "extern3",
-};
-
-static struct pmc_clk_init_data pmc_clks[] = {
- PMC_CLK(1, 6, 2),
- PMC_CLK(2, 14, 10),
- PMC_CLK(3, 22, 18),
-};
-
-void __init tegra_pmc_clk_init(void __iomem *pmc_base,
- struct tegra_clk *tegra_clks)
-{
- struct clk *clk;
- struct clk **dt_clk;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
- struct pmc_clk_init_data *data;
-
- data = pmc_clks + i;
-
- dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
- if (!dt_clk)
- continue;
-
- clk = clk_register_mux(NULL, data->mux_name, data->parents,
- data->num_parents,
- CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
- pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
- 3, 0, &clk_out_lock);
- *dt_clk = clk;
-
-
- dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
- if (!dt_clk)
- continue;
-
- clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
- CLK_SET_RATE_PARENT,
- pmc_base + PMC_CLK_OUT_CNTRL,
- data->gate_shift, 0, &clk_out_lock);
- *dt_clk = clk;
- clk_register_clkdev(clk, data->dev_name, data->gate_name);
- }
-
- /* blink */
- writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
- clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
- pmc_base + PMC_DPD_PADS_ORIDE,
- PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
-
- dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
- if (!dt_clk)
- return;
-
- clk = clk_register_gate(NULL, "blink", "blink_override", 0,
- pmc_base + PMC_CTRL,
- PMC_CTRL_BLINK_ENB, 0, NULL);
- clk_register_clkdev(clk, "blink", NULL);
- *dt_clk = clk;
-}
-
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 180ddc2abfd2..c138ef75480b 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -779,10 +779,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
@@ -804,9 +800,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
@@ -865,10 +858,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
@@ -1147,8 +1139,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
- { TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1350,7 +1340,6 @@ static void __init tegra114_clock_init(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
tegra114_audio_plls,
ARRAY_SIZE(tegra114_audio_plls), 24000000);
- tegra_pmc_clk_init(pmc_base, tegra114_clks);
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
&pll_x_params);
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 7a16e50eb20f..54cac77deaa3 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -903,10 +903,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
[tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
[tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
@@ -932,9 +928,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
};
@@ -990,10 +983,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
{ .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
{ .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
@@ -1303,8 +1295,6 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
- { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1459,11 +1449,9 @@ static void __init tegra132_clock_apply_init_table(void)
* tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
* @np: struct device_node * of the DT node for the SoC CAR IP block
*
- * Register most of the clocks controlled by the CAR IP block, along
- * with a few clocks controlled by the PMC IP block. Everything in
- * this function should be common to Tegra124 and Tegra132. XXX The
- * PMC clock initialization should probably be moved to PMC-specific
- * driver code. No return value.
+ * Register most of the clocks controlled by the CAR IP block.
+ * Everything in this function should be common to Tegra124 and Tegra132.
+ * No return value.
*/
static void __init tegra124_132_clock_init_pre(struct device_node *np)
{
@@ -1506,7 +1494,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
tegra124_audio_plls,
ARRAY_SIZE(tegra124_audio_plls), 24576000);
- tegra_pmc_clk_init(pmc_base, tegra124_clks);
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
plld_base = readl(clk_base + PLLD_BASE);
@@ -1518,11 +1505,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
* tegra124_132_clock_init_post - clock initialization postamble for T124/T132
* @np: struct device_node * of the DT node for the SoC CAR IP block
*
- * Register most of the along with a few clocks controlled by the PMC
- * IP block. Everything in this function should be common to Tegra124
+ * Register most of the clocks controlled by the CAR IP block.
+ * Everything in this function should be common to Tegra124
* and Tegra132. This function must be called after
- * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
- * not be set. No return value.
+ * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
+ * No return value.
*/
static void __init tegra124_132_clock_init_post(struct device_node *np)
{
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 4d8222f5c638..fe536f1d770d 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
- { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
{ .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
@@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
[tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
[tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
[tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
[tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
[tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
@@ -1034,7 +1032,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
- { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
@@ -1148,7 +1145,6 @@ static void __init tegra20_clock_init(struct device_node *np)
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
tegra20_periph_clk_init();
tegra20_audio_clk_init();
- tegra_pmc_clk_init(pmc_base, tegra20_clks);
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 45d54ead30bc..d2f1e9c0ed25 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2418,10 +2418,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
@@ -2453,9 +2449,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
@@ -2542,10 +2535,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
@@ -3453,8 +3445,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
- { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -3695,7 +3685,6 @@ static void __init tegra210_clock_init(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
tegra210_audio_plls,
ARRAY_SIZE(tegra210_audio_plls), 24576000);
- tegra_pmc_clk_init(pmc_base, tegra210_clks);
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
value = readl(clk_base + PLLD_BASE);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ddc5ab66d09e..5732fdbe20db 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -569,10 +569,9 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
{ .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
{ .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
- { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
- { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
- { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
- { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
+ { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
+ { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
+ { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
{ .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
{ .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
{ .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
@@ -713,13 +712,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
[tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
[tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
[tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
- [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
- [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
- [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
- [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
- [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
- [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
- [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
[tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
[tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
[tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
@@ -1232,9 +1224,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
- { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
- { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
- { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
@@ -1366,7 +1355,6 @@ static void __init tegra30_clock_init(struct device_node *np)
tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
tegra30_audio_plls,
ARRAY_SIZE(tegra30_audio_plls), 24000000);
- tegra_pmc_clk_init(pmc_base, tegra30_clks);
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 416a6b09f6a3..2c9a68302e02 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -854,7 +854,6 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
struct tegra_clk *tegra_clks,
struct tegra_clk_pll_params *pll_params);
-void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
unsigned long *input_freqs, unsigned int num,
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v8 20/22] clk: tegra: Remove tegra_pmc_clk_init along with clk ids
2020-01-14 7:24 ` Sowjanya Komatineni
(?)
@ 2020-02-17 9:55 ` Thierry Reding
-1 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-02-17 9:55 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, broonie, lgirdwood, perex, tiwai, digetx, mperttunen,
gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1755 bytes --]
On Mon, Jan 13, 2020 at 11:24:25PM -0800, Sowjanya Komatineni wrote:
> Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
> clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct
> PMC register access during clk_ops and these PMC register read and write
> access will not happen when PMC is in secure mode.
>
> Any direct PMC register access from non-secure world will not go
> through.
>
> All the PMC clocks are moved to Tegra PMC driver with PMC as a clock
> provider.
>
> This patch removes tegra_pmc_clk_init along with corresponding clk ids
> from Tegra clock driver.
>
> Tested-by: Dmitry Osipenko <digetx@gmail.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/Makefile | 1 -
> drivers/clk/tegra/clk-id.h | 7 ---
> drivers/clk/tegra/clk-tegra-pmc.c | 122 --------------------------------------
> drivers/clk/tegra/clk-tegra114.c | 17 +-----
> drivers/clk/tegra/clk-tegra124.c | 33 ++++-------
> drivers/clk/tegra/clk-tegra20.c | 4 --
> drivers/clk/tegra/clk-tegra210.c | 17 +-----
> drivers/clk/tegra/clk-tegra30.c | 18 +-----
> drivers/clk/tegra/clk.h | 1 -
> 9 files changed, 19 insertions(+), 201 deletions(-)
> delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
I think it's best to defer this patch (along with 21 and 22) until all
the others have been merged to make sure we don't regress. Other than
that it should be fine to apply the others in any order, right? Well,
maybe not any order, but at least the ASoC patches should be able to
go through the ASoC tree without impacting functionality, right?
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 85+ messages in thread
* [PATCH v8 21/22] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block and
these clocks are moved to Tegra PMC driver with pmc as clock provider
and uses clock ids from dt-bindings/soc/tegra-pmc.h
So, this patch removes ids for these clocks from Tegra clock dt-bindings.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
include/dt-bindings/clock/tegra114-car.h | 14 +++++++-------
include/dt-bindings/clock/tegra124-car-common.h | 14 +++++++-------
include/dt-bindings/clock/tegra20-car.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 14 +++++++-------
include/dt-bindings/clock/tegra30-car.h | 14 +++++++-------
5 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index df59aaf5bf34..a93426f008ac 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -272,10 +272,10 @@
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
-#define TEGRA114_CLK_CLK_OUT_1 245
-#define TEGRA114_CLK_CLK_OUT_2 246
-#define TEGRA114_CLK_CLK_OUT_3 247
-#define TEGRA114_CLK_BLINK 248
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
#define TEGRA114_CLK_OSC 249
/* 250 */
/* 251 */
@@ -335,9 +335,9 @@
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
-#define TEGRA114_CLK_CLK_OUT_1_MUX 306
-#define TEGRA114_CLK_CLK_OUT_2_MUX 307
-#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_XUSB_SS_DIV2 311
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index 2a9acd592bff..c59f9de01b4d 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -271,10 +271,10 @@
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
-#define TEGRA124_CLK_CLK_OUT_1 245
-#define TEGRA124_CLK_CLK_OUT_2 246
-#define TEGRA124_CLK_CLK_OUT_3 247
-#define TEGRA124_CLK_BLINK 248
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
#define TEGRA124_CLK_OSC 249
/* 250 */
/* 251 */
@@ -334,9 +334,9 @@
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
-#define TEGRA124_CLK_CLK_OUT_1_MUX 306
-#define TEGRA124_CLK_CLK_OUT_2_MUX 307
-#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
/* 309 */
/* 310 */
#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index b21a0eb32921..fe541f627965 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -131,7 +131,7 @@
#define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110
-#define TEGRA20_CLK_BLINK 111
+/* 111 */
#define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 7a8f10b9a66d..55592c214bf3 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -306,10 +306,10 @@
#define TEGRA210_CLK_AUDIO3 274
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
-#define TEGRA210_CLK_CLK_OUT_1 277
-#define TEGRA210_CLK_CLK_OUT_2 278
-#define TEGRA210_CLK_CLK_OUT_3 279
-#define TEGRA210_CLK_BLINK 280
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
#define TEGRA210_CLK_SOR0_OUT 281
#define TEGRA210_CLK_SOR1_OUT 282
@@ -388,9 +388,9 @@
#define TEGRA210_CLK_AUDIO3_MUX 353
#define TEGRA210_CLK_AUDIO4_MUX 354
#define TEGRA210_CLK_SPDIF_MUX 355
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+/* 356 */
+/* 357 */
+/* 358 */
#define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360
/* 361 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 7b542c10fc27..f193663e6f28 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -232,11 +232,11 @@
#define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206
-#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
-#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
-#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+/* 207 */
+/* 208 */
+/* 209 */
#define TEGRA30_CLK_SCLK 210
-#define TEGRA30_CLK_BLINK 211
+/* 211 */
#define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214
@@ -262,9 +262,9 @@
/* 297 */
/* 298 */
/* 299 */
-#define TEGRA30_CLK_CLK_OUT_1_MUX 300
-#define TEGRA30_CLK_CLK_OUT_2_MUX 301
-#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+/* 300 */
+/* 301 */
+/* 302 */
#define TEGRA30_CLK_AUDIO0_MUX 303
#define TEGRA30_CLK_AUDIO1_MUX 304
#define TEGRA30_CLK_AUDIO2_MUX 305
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 21/22] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block and
these clocks are moved to Tegra PMC driver with pmc as clock provider
and uses clock ids from dt-bindings/soc/tegra-pmc.h
So, this patch removes ids for these clocks from Tegra clock dt-bindings.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
include/dt-bindings/clock/tegra114-car.h | 14 +++++++-------
include/dt-bindings/clock/tegra124-car-common.h | 14 +++++++-------
include/dt-bindings/clock/tegra20-car.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 14 +++++++-------
include/dt-bindings/clock/tegra30-car.h | 14 +++++++-------
5 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index df59aaf5bf34..a93426f008ac 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -272,10 +272,10 @@
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
-#define TEGRA114_CLK_CLK_OUT_1 245
-#define TEGRA114_CLK_CLK_OUT_2 246
-#define TEGRA114_CLK_CLK_OUT_3 247
-#define TEGRA114_CLK_BLINK 248
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
#define TEGRA114_CLK_OSC 249
/* 250 */
/* 251 */
@@ -335,9 +335,9 @@
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
-#define TEGRA114_CLK_CLK_OUT_1_MUX 306
-#define TEGRA114_CLK_CLK_OUT_2_MUX 307
-#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_XUSB_SS_DIV2 311
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index 2a9acd592bff..c59f9de01b4d 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -271,10 +271,10 @@
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
-#define TEGRA124_CLK_CLK_OUT_1 245
-#define TEGRA124_CLK_CLK_OUT_2 246
-#define TEGRA124_CLK_CLK_OUT_3 247
-#define TEGRA124_CLK_BLINK 248
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
#define TEGRA124_CLK_OSC 249
/* 250 */
/* 251 */
@@ -334,9 +334,9 @@
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
-#define TEGRA124_CLK_CLK_OUT_1_MUX 306
-#define TEGRA124_CLK_CLK_OUT_2_MUX 307
-#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
/* 309 */
/* 310 */
#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index b21a0eb32921..fe541f627965 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -131,7 +131,7 @@
#define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110
-#define TEGRA20_CLK_BLINK 111
+/* 111 */
#define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 7a8f10b9a66d..55592c214bf3 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -306,10 +306,10 @@
#define TEGRA210_CLK_AUDIO3 274
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
-#define TEGRA210_CLK_CLK_OUT_1 277
-#define TEGRA210_CLK_CLK_OUT_2 278
-#define TEGRA210_CLK_CLK_OUT_3 279
-#define TEGRA210_CLK_BLINK 280
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
#define TEGRA210_CLK_SOR0_OUT 281
#define TEGRA210_CLK_SOR1_OUT 282
@@ -388,9 +388,9 @@
#define TEGRA210_CLK_AUDIO3_MUX 353
#define TEGRA210_CLK_AUDIO4_MUX 354
#define TEGRA210_CLK_SPDIF_MUX 355
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+/* 356 */
+/* 357 */
+/* 358 */
#define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360
/* 361 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 7b542c10fc27..f193663e6f28 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -232,11 +232,11 @@
#define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206
-#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
-#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
-#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+/* 207 */
+/* 208 */
+/* 209 */
#define TEGRA30_CLK_SCLK 210
-#define TEGRA30_CLK_BLINK 211
+/* 211 */
#define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214
@@ -262,9 +262,9 @@
/* 297 */
/* 298 */
/* 299 */
-#define TEGRA30_CLK_CLK_OUT_1_MUX 300
-#define TEGRA30_CLK_CLK_OUT_2_MUX 301
-#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+/* 300 */
+/* 301 */
+/* 302 */
#define TEGRA30_CLK_AUDIO0_MUX 303
#define TEGRA30_CLK_AUDIO1_MUX 304
#define TEGRA30_CLK_AUDIO2_MUX 305
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration from clock driver
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-01-14 7:24 ` Sowjanya Komatineni
-1 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni-DDmLM1+adcrQT0dZR+AlfA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Current clock driver enables PLLA, cdev1 on Tegra20 and extern1 on
Tegra30 and above as a part of clocks init and there is no need to
have these audio clocks enabled by the clock driver.
extern1 is used as parent for clk_out_1 and clk_out_1 is dedicated
for audio mclk on Tegra30 and above Tegra platforms and these clocks
are taken care by ASoC driver.
So, this patch removes audio related clocks configuration from clock
init of Tegra20 and above.
Tested-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Sowjanya Komatineni <skomatineni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-tegra114.c | 5 ++---
drivers/clk/tegra/clk-tegra124.c | 5 ++---
drivers/clk/tegra/clk-tegra20.c | 5 ++---
drivers/clk/tegra/clk-tegra210.c | 5 ++---
drivers/clk/tegra/clk-tegra30.c | 5 ++---
5 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index c138ef75480b..bc9e47a4cb60 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1136,9 +1136,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
- { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 54cac77deaa3..64e229ddf2a5 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1292,9 +1292,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
- { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index fe536f1d770d..0da402c144d8 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1029,9 +1029,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
- { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
- { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
+ { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
+ { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index d2f1e9c0ed25..c6304f5e813e 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3442,9 +3442,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
{ TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
{ TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
- { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 5732fdbe20db..53d1c48532ae 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1221,9 +1221,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
- { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration from clock driver
@ 2020-01-14 7:24 ` Sowjanya Komatineni
0 siblings, 0 replies; 85+ messages in thread
From: Sowjanya Komatineni @ 2020-01-14 7:24 UTC (permalink / raw)
To: skomatineni, thierry.reding, jonathanh, broonie, lgirdwood,
perex, tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
Current clock driver enables PLLA, cdev1 on Tegra20 and extern1 on
Tegra30 and above as a part of clocks init and there is no need to
have these audio clocks enabled by the clock driver.
extern1 is used as parent for clk_out_1 and clk_out_1 is dedicated
for audio mclk on Tegra30 and above Tegra platforms and these clocks
are taken care by ASoC driver.
So, this patch removes audio related clocks configuration from clock
init of Tegra20 and above.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/clk/tegra/clk-tegra114.c | 5 ++---
drivers/clk/tegra/clk-tegra124.c | 5 ++---
drivers/clk/tegra/clk-tegra20.c | 5 ++---
drivers/clk/tegra/clk-tegra210.c | 5 ++---
drivers/clk/tegra/clk-tegra30.c | 5 ++---
5 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index c138ef75480b..bc9e47a4cb60 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1136,9 +1136,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
- { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 54cac77deaa3..64e229ddf2a5 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1292,9 +1292,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
- { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index fe536f1d770d..0da402c144d8 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1029,9 +1029,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
- { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
- { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
+ { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
+ { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index d2f1e9c0ed25..c6304f5e813e 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3442,9 +3442,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
{ TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
{ TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
- { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 5732fdbe20db..53d1c48532ae 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1221,9 +1221,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
- { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
- { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
- { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
+ { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
+ { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
--
2.7.4
^ permalink raw reply related [flat|nested] 85+ messages in thread
* Re: [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration from clock driver
2020-01-14 7:24 ` Sowjanya Komatineni
(?)
@ 2020-01-19 15:04 ` Dmitry Osipenko
[not found] ` <d69fe7a8-71cc-c560-a567-f89b936753ad-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
-1 siblings, 1 reply; 85+ messages in thread
From: Dmitry Osipenko @ 2020-01-19 15:04 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, broonie,
lgirdwood, perex, tiwai, mperttunen, gregkh, sboyd, robh+dt,
mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
14.01.2020 10:24, Sowjanya Komatineni пишет:
[snip]
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 5732fdbe20db..53d1c48532ae 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1221,9 +1221,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
> { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
> { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
> { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
> - { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
> - { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
> - { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
> + { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
> + { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
> { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
> { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
> { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
>
What about to use the assigned-clock-rates in device-tree and thus to
remove those PLL_A entries?
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-02-17 9:59 ` Thierry Reding
-1 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-02-17 9:59 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh-DDmLM1+adcrQT0dZR+AlfA, broonie-DgEjT+Ai2ygdnm+yROfE0A,
lgirdwood-Re5JQEeQqe8AvxtiuMwx3w, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 12561 bytes --]
On Mon, Jan 13, 2020 at 11:24:05PM -0800, Sowjanya Komatineni wrote:
> This patch series moves Tegra PMC clocks from clock driver to pmc driver
> along with the device trees changes and audio driver which uses one of
> the pmc clock for audio mclk.
>
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
>
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
>
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removes them from Tegra clock
> driver.
>
> PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
> and clock driver does inital parent configuration for it and enables them.
> But this clock should be taken care by audio driver as there is no need
> to have this clock pre enabled.
>
> So, this series also includes patch that updates ASoC utils to take
> care of parent configuration for mclk if device tree don't specify
> initial parent configuration using assigned-clock-parents and enable
> audio mclk during utils init.
>
> DTs are also updated to use clk_out_1 as audio mclk rather than extern1.
>
> This series also includes a patch for mclk fallback to extern1 when
> retrieving mclk fails to have this backward compatible of new DT with
> old kernels.
>
> [v8]: Changes between v7 and v8 are
> - v7 minor feedback
>
> - Audio mclk is needed only for audio, but there is some unknown
> dependency of audio mclk and suspend-resume on Tegra30 where when
> mclk is disable, suspend-resume doesn't work.
> So v8 undoes v7 change of mclk enable and disable during machine
> startup and shutdown and keeps audio mclk enabled in ASoC driver
> tegra_asoc_utils_init.
>
> - change in the patches order.
>
> Note:
> - Patches 1 thru 5 are to change CLK_M_DIV clocks to OSC_DIV clocks.
> OSC_DIV clocks uses same ID as CLK_M_DIV clocks during the
> transition to replace CLK_M_DIV with OSC_DIV.
> - Patches 8 and 10 registers pmc clocks as pmc_clk_out_1/2/3, and
> pmc_blink to avoid using same clock names as pmc clocks from
> tegra_car provider to have them functionally work with all the
> transition patches.
> - Patch 11 adds audio mclk fallback to extern1 to have new DT work
> with old kernels. This patch need to be back-ported.
> - Patch 18 adds audio mclk parent configuration when DT doesn't
> specify parent configs. This patch retrieves pmc_clk_out_1 as audio
> mclk so added this patch after all DT updates to use pmc clocks
> from tegra_pmc.
> - Patch 19 does audio mclk enable during utils init to have it
> enabled all the time.
> - Patch 20 and 21 removes PMC clocks from clock driver and their IDs
> at the end of PMC clocks transition to tegra_pmc.
>
>
> [v7]: Changes between v6 and v7 are
> - v6 minor feedback
> - Added DT id for Tegra OSC to use in device tree for pmc clock
> parent.
>
> [v6]: Changes between v5 and v6 are
> - v5 feedback
> - Added ASoC machine startup and shutdown callbacks to control audio
> mclk enable/disable and removed default mclk enable from clock driver.
> - Updated tegra_asoc_utils_set_rate to disable mclk only during PLLA
> rate change and removed disabling PLLA as its already taken care by
> pll clock driver.
> - Removed tegra_asoc_utils_set_rate call from utils_init as set_rate
> is set during machine hw_params and during utils_init mclk is
> already in disabled state and this causes warning during mclk disable
> in utils_set_rate.
>
> [v5]: Changes between v4 and v5 are
> - v4 feedback
> - updated dt-binding pmc YAML schema with more description on power
> gate nodes and pad configuration state nodes.
> - update tegra_asoc_utils_set_rate to disable audio mclk only if
> its in enable state.
>
> [v4]: Changes between v3 and v4 are
> - v3 Feedback
> - Updated clocks clk_m_div2 and clk_m_div4 as osc_div2 and osc_div4.
> Tegra don't have clk_m_div2, clk_m_div4 and they should actually
> be osc_div2 and osc_div4 clocks from osc pads.
> - Fixed PMC clock parents to use osc, osc_div2, osc_div4.
> This is not a functional bug fix but correction to use proper parent
> name.
> - Register each PMC clock as single clock rather than separate
> mux and gate clocks.
> - Update ASoC utils to use resource managed APIs rather than
> using clk_get and clk_put.
> - Updated device tree and ASoC driver to use clk_out_1 instead of
> clk_out_1_mux as PMC clocks are registered as single clock.
> - Update clock driver init_table to not enable audio related clocks
> as ASoC utils will do audio clock enables.
>
> [v3]: Changes between v2 and v3 are
> - Removes set parent of clk_out_1_mux to extern1 and enabling
> extern1 from the clock driver.
> - Doesn't enable clk_out_1 and blink by default in pmc driver
> - Updates ASoC driver to take care of audio mclk parent
> configuration incase if device tree don't specify assigned
> clock parent properties and enables mclk using both clk_out_1
> and extern1.
> - updates all device trees using extern1 as mclk in sound node
> to use clk_out_1 from pmc.
> - patch for YAML format pmc dt-binding
> - Includes v2 feedback
>
> [v2]: Changes between v1 and v2 are
> - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> - feedback related to pmc clocks in Tegra PMC driver from v1
> - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> by the clock driver using helper functions from Tegra PMC.
>
> Note:
> To use helper functions from PMC driver, PMC early init need to
> happen prior to using helper functions and these helper functions are
> for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> clock registration which happen in clock_init prior to Tegra PMC
> probe.
> Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> impacts other clocks EMC, MC and corresponding tegra_emc_init and
> tegra_mc_init.
> This implementation of configuring PMC registers thru helper
> functions in clock driver needs proper changes across PMC, Clock,
> EMC and MC inits to have it work across all Tegra platforms.
>
> Currently PLLM Override is not enabled in the bootloader so proper
> patches for this fix will be taken care separately.
>
> [v1]: v1 includes patches for below fixes.
> - adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
> driver and removing clk-tegra-pmc.
> - updated clock provider from tegra_car to pmc in the device tree
> tegra210-smaug.dts that uses clk_out_2.
> - Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
> IDDQ programming to use by clock driver and updated clock driver to
> use these helper functions and removed direct PMC access from clock
> driver and all pmc base address references in clock driver.
>
> Sowjanya Komatineni (22):
> dt-bindings: clock: tegra: Add IDs for OSC clocks
> clk: tegra: Add support for OSC_DIV fixed clocks
> clk: tegra: Add Tegra OSC to clock lookup
> clk: tegra: Fix Tegra PMC clock out parents
> clk: tegra: Remove CLK_M_DIV fixed clocks
> dt-bindings: tegra: Convert Tegra PMC bindings to YAML
> dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
> soc: tegra: Add Tegra PMC clocks registration into PMC driver
> dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
> soc: tegra: Add support for 32KHz blink clock
> ASoC: tegra: Add fallback implementation for audio mclk
> ASoC: tegra: Use device managed resource APIs to get the clock
> ARM: dts: tegra: Add clock-cells property to pmc
> arm64: tegra: Add clock-cells property to Tegra PMC node
> ARM: tegra: Update sound node clocks in device tree
> arm64: tegra: smaug: Change clk_out_2 provider to pmc
> ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc
> ASoC: tegra: Add audio mclk parent configuration
> ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init
> clk: tegra: Remove tegra_pmc_clk_init along with clk ids
> dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
> clk: tegra: Remove audio clocks configuration from clock driver
>
> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 -----------------
> .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 354 +++++++++++++++++++++
> .../devicetree/bindings/sound/nau8825.txt | 2 +-
> arch/arm/boot/dts/tegra114-dalmore.dts | 8 +-
> arch/arm/boot/dts/tegra114.dtsi | 4 +-
> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 8 +-
> arch/arm/boot/dts/tegra124-apalis.dtsi | 8 +-
> arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +-
> arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +-
> arch/arm/boot/dts/tegra124-venice2.dts | 8 +-
> arch/arm/boot/dts/tegra124.dtsi | 4 +-
> arch/arm/boot/dts/tegra20.dtsi | 4 +-
> arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 8 +-
> arch/arm/boot/dts/tegra30-apalis.dtsi | 8 +-
> arch/arm/boot/dts/tegra30-beaver.dts | 8 +-
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 8 +-
> arch/arm/boot/dts/tegra30-colibri.dtsi | 8 +-
> arch/arm/boot/dts/tegra30.dtsi | 4 +-
> arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +-
> arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +-
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +-
> drivers/clk/tegra/Makefile | 1 -
> drivers/clk/tegra/clk-id.h | 12 +-
> drivers/clk/tegra/clk-tegra-fixed.c | 37 ++-
> drivers/clk/tegra/clk-tegra-pmc.c | 122 -------
> drivers/clk/tegra/clk-tegra114.c | 43 +--
> drivers/clk/tegra/clk-tegra124.c | 48 ++-
> drivers/clk/tegra/clk-tegra20.c | 9 +-
> drivers/clk/tegra/clk-tegra210.c | 32 +-
> drivers/clk/tegra/clk-tegra30.c | 33 +-
> drivers/clk/tegra/clk.h | 1 -
> drivers/soc/tegra/pmc.c | 354 +++++++++++++++++++++
> include/dt-bindings/clock/tegra114-car.h | 18 +-
> include/dt-bindings/clock/tegra124-car-common.h | 18 +-
> include/dt-bindings/clock/tegra20-car.h | 2 +-
> include/dt-bindings/clock/tegra210-car.h | 18 +-
> include/dt-bindings/clock/tegra30-car.h | 18 +-
> include/dt-bindings/soc/tegra-pmc.h | 16 +
> sound/soc/tegra/tegra_alc5632.c | 7 +-
> sound/soc/tegra/tegra_asoc_utils.c | 126 ++++----
> sound/soc/tegra/tegra_asoc_utils.h | 1 -
> sound/soc/tegra/tegra_max98090.c | 22 +-
> sound/soc/tegra/tegra_rt5640.c | 22 +-
> sound/soc/tegra/tegra_rt5677.c | 7 +-
> sound/soc/tegra/tegra_sgtl5000.c | 7 +-
> sound/soc/tegra/tegra_wm8753.c | 22 +-
> sound/soc/tegra/tegra_wm8903.c | 22 +-
> sound/soc/tegra/tegra_wm9712.c | 8 +-
> sound/soc/tegra/trimslice.c | 18 +-
> 49 files changed, 1041 insertions(+), 775 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
> create mode 100644 include/dt-bindings/soc/tegra-pmc.h
I've applied patches 1-10 and 13-16 to the Tegra tree, but I think it
should be fine for Mark to pick up the ASoC patches into his tree,
right?
As I mentioned in my reply to patch 20, I think we need to hold off on
applying patches 20-22 until all the rest have been merged, otherwise
we'll regress.
Thierry
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^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
@ 2020-02-17 9:59 ` Thierry Reding
0 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-02-17 9:59 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, broonie, lgirdwood, perex, tiwai, digetx, mperttunen,
gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 12561 bytes --]
On Mon, Jan 13, 2020 at 11:24:05PM -0800, Sowjanya Komatineni wrote:
> This patch series moves Tegra PMC clocks from clock driver to pmc driver
> along with the device trees changes and audio driver which uses one of
> the pmc clock for audio mclk.
>
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
>
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
>
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removes them from Tegra clock
> driver.
>
> PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
> and clock driver does inital parent configuration for it and enables them.
> But this clock should be taken care by audio driver as there is no need
> to have this clock pre enabled.
>
> So, this series also includes patch that updates ASoC utils to take
> care of parent configuration for mclk if device tree don't specify
> initial parent configuration using assigned-clock-parents and enable
> audio mclk during utils init.
>
> DTs are also updated to use clk_out_1 as audio mclk rather than extern1.
>
> This series also includes a patch for mclk fallback to extern1 when
> retrieving mclk fails to have this backward compatible of new DT with
> old kernels.
>
> [v8]: Changes between v7 and v8 are
> - v7 minor feedback
>
> - Audio mclk is needed only for audio, but there is some unknown
> dependency of audio mclk and suspend-resume on Tegra30 where when
> mclk is disable, suspend-resume doesn't work.
> So v8 undoes v7 change of mclk enable and disable during machine
> startup and shutdown and keeps audio mclk enabled in ASoC driver
> tegra_asoc_utils_init.
>
> - change in the patches order.
>
> Note:
> - Patches 1 thru 5 are to change CLK_M_DIV clocks to OSC_DIV clocks.
> OSC_DIV clocks uses same ID as CLK_M_DIV clocks during the
> transition to replace CLK_M_DIV with OSC_DIV.
> - Patches 8 and 10 registers pmc clocks as pmc_clk_out_1/2/3, and
> pmc_blink to avoid using same clock names as pmc clocks from
> tegra_car provider to have them functionally work with all the
> transition patches.
> - Patch 11 adds audio mclk fallback to extern1 to have new DT work
> with old kernels. This patch need to be back-ported.
> - Patch 18 adds audio mclk parent configuration when DT doesn't
> specify parent configs. This patch retrieves pmc_clk_out_1 as audio
> mclk so added this patch after all DT updates to use pmc clocks
> from tegra_pmc.
> - Patch 19 does audio mclk enable during utils init to have it
> enabled all the time.
> - Patch 20 and 21 removes PMC clocks from clock driver and their IDs
> at the end of PMC clocks transition to tegra_pmc.
>
>
> [v7]: Changes between v6 and v7 are
> - v6 minor feedback
> - Added DT id for Tegra OSC to use in device tree for pmc clock
> parent.
>
> [v6]: Changes between v5 and v6 are
> - v5 feedback
> - Added ASoC machine startup and shutdown callbacks to control audio
> mclk enable/disable and removed default mclk enable from clock driver.
> - Updated tegra_asoc_utils_set_rate to disable mclk only during PLLA
> rate change and removed disabling PLLA as its already taken care by
> pll clock driver.
> - Removed tegra_asoc_utils_set_rate call from utils_init as set_rate
> is set during machine hw_params and during utils_init mclk is
> already in disabled state and this causes warning during mclk disable
> in utils_set_rate.
>
> [v5]: Changes between v4 and v5 are
> - v4 feedback
> - updated dt-binding pmc YAML schema with more description on power
> gate nodes and pad configuration state nodes.
> - update tegra_asoc_utils_set_rate to disable audio mclk only if
> its in enable state.
>
> [v4]: Changes between v3 and v4 are
> - v3 Feedback
> - Updated clocks clk_m_div2 and clk_m_div4 as osc_div2 and osc_div4.
> Tegra don't have clk_m_div2, clk_m_div4 and they should actually
> be osc_div2 and osc_div4 clocks from osc pads.
> - Fixed PMC clock parents to use osc, osc_div2, osc_div4.
> This is not a functional bug fix but correction to use proper parent
> name.
> - Register each PMC clock as single clock rather than separate
> mux and gate clocks.
> - Update ASoC utils to use resource managed APIs rather than
> using clk_get and clk_put.
> - Updated device tree and ASoC driver to use clk_out_1 instead of
> clk_out_1_mux as PMC clocks are registered as single clock.
> - Update clock driver init_table to not enable audio related clocks
> as ASoC utils will do audio clock enables.
>
> [v3]: Changes between v2 and v3 are
> - Removes set parent of clk_out_1_mux to extern1 and enabling
> extern1 from the clock driver.
> - Doesn't enable clk_out_1 and blink by default in pmc driver
> - Updates ASoC driver to take care of audio mclk parent
> configuration incase if device tree don't specify assigned
> clock parent properties and enables mclk using both clk_out_1
> and extern1.
> - updates all device trees using extern1 as mclk in sound node
> to use clk_out_1 from pmc.
> - patch for YAML format pmc dt-binding
> - Includes v2 feedback
>
> [v2]: Changes between v1 and v2 are
> - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> - feedback related to pmc clocks in Tegra PMC driver from v1
> - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> by the clock driver using helper functions from Tegra PMC.
>
> Note:
> To use helper functions from PMC driver, PMC early init need to
> happen prior to using helper functions and these helper functions are
> for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> clock registration which happen in clock_init prior to Tegra PMC
> probe.
> Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> impacts other clocks EMC, MC and corresponding tegra_emc_init and
> tegra_mc_init.
> This implementation of configuring PMC registers thru helper
> functions in clock driver needs proper changes across PMC, Clock,
> EMC and MC inits to have it work across all Tegra platforms.
>
> Currently PLLM Override is not enabled in the bootloader so proper
> patches for this fix will be taken care separately.
>
> [v1]: v1 includes patches for below fixes.
> - adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
> driver and removing clk-tegra-pmc.
> - updated clock provider from tegra_car to pmc in the device tree
> tegra210-smaug.dts that uses clk_out_2.
> - Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
> IDDQ programming to use by clock driver and updated clock driver to
> use these helper functions and removed direct PMC access from clock
> driver and all pmc base address references in clock driver.
>
> Sowjanya Komatineni (22):
> dt-bindings: clock: tegra: Add IDs for OSC clocks
> clk: tegra: Add support for OSC_DIV fixed clocks
> clk: tegra: Add Tegra OSC to clock lookup
> clk: tegra: Fix Tegra PMC clock out parents
> clk: tegra: Remove CLK_M_DIV fixed clocks
> dt-bindings: tegra: Convert Tegra PMC bindings to YAML
> dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
> soc: tegra: Add Tegra PMC clocks registration into PMC driver
> dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
> soc: tegra: Add support for 32KHz blink clock
> ASoC: tegra: Add fallback implementation for audio mclk
> ASoC: tegra: Use device managed resource APIs to get the clock
> ARM: dts: tegra: Add clock-cells property to pmc
> arm64: tegra: Add clock-cells property to Tegra PMC node
> ARM: tegra: Update sound node clocks in device tree
> arm64: tegra: smaug: Change clk_out_2 provider to pmc
> ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc
> ASoC: tegra: Add audio mclk parent configuration
> ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init
> clk: tegra: Remove tegra_pmc_clk_init along with clk ids
> dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
> clk: tegra: Remove audio clocks configuration from clock driver
>
> .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 300 -----------------
> .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 354 +++++++++++++++++++++
> .../devicetree/bindings/sound/nau8825.txt | 2 +-
> arch/arm/boot/dts/tegra114-dalmore.dts | 8 +-
> arch/arm/boot/dts/tegra114.dtsi | 4 +-
> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 8 +-
> arch/arm/boot/dts/tegra124-apalis.dtsi | 8 +-
> arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +-
> arch/arm/boot/dts/tegra124-nyan.dtsi | 8 +-
> arch/arm/boot/dts/tegra124-venice2.dts | 8 +-
> arch/arm/boot/dts/tegra124.dtsi | 4 +-
> arch/arm/boot/dts/tegra20.dtsi | 4 +-
> arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 8 +-
> arch/arm/boot/dts/tegra30-apalis.dtsi | 8 +-
> arch/arm/boot/dts/tegra30-beaver.dts | 8 +-
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 8 +-
> arch/arm/boot/dts/tegra30-colibri.dtsi | 8 +-
> arch/arm/boot/dts/tegra30.dtsi | 4 +-
> arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +-
> arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +-
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +-
> drivers/clk/tegra/Makefile | 1 -
> drivers/clk/tegra/clk-id.h | 12 +-
> drivers/clk/tegra/clk-tegra-fixed.c | 37 ++-
> drivers/clk/tegra/clk-tegra-pmc.c | 122 -------
> drivers/clk/tegra/clk-tegra114.c | 43 +--
> drivers/clk/tegra/clk-tegra124.c | 48 ++-
> drivers/clk/tegra/clk-tegra20.c | 9 +-
> drivers/clk/tegra/clk-tegra210.c | 32 +-
> drivers/clk/tegra/clk-tegra30.c | 33 +-
> drivers/clk/tegra/clk.h | 1 -
> drivers/soc/tegra/pmc.c | 354 +++++++++++++++++++++
> include/dt-bindings/clock/tegra114-car.h | 18 +-
> include/dt-bindings/clock/tegra124-car-common.h | 18 +-
> include/dt-bindings/clock/tegra20-car.h | 2 +-
> include/dt-bindings/clock/tegra210-car.h | 18 +-
> include/dt-bindings/clock/tegra30-car.h | 18 +-
> include/dt-bindings/soc/tegra-pmc.h | 16 +
> sound/soc/tegra/tegra_alc5632.c | 7 +-
> sound/soc/tegra/tegra_asoc_utils.c | 126 ++++----
> sound/soc/tegra/tegra_asoc_utils.h | 1 -
> sound/soc/tegra/tegra_max98090.c | 22 +-
> sound/soc/tegra/tegra_rt5640.c | 22 +-
> sound/soc/tegra/tegra_rt5677.c | 7 +-
> sound/soc/tegra/tegra_sgtl5000.c | 7 +-
> sound/soc/tegra/tegra_wm8753.c | 22 +-
> sound/soc/tegra/tegra_wm8903.c | 22 +-
> sound/soc/tegra/tegra_wm9712.c | 8 +-
> sound/soc/tegra/trimslice.c | 18 +-
> 49 files changed, 1041 insertions(+), 775 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
> create mode 100644 include/dt-bindings/soc/tegra-pmc.h
I've applied patches 1-10 and 13-16 to the Tegra tree, but I think it
should be fine for Mark to pick up the ASoC patches into his tree,
right?
As I mentioned in my reply to patch 20, I think we need to hold off on
applying patches 20-22 until all the rest have been merged, otherwise
we'll regress.
Thierry
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^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
2020-02-17 9:59 ` Thierry Reding
(?)
@ 2020-03-04 19:26 ` Dmitry Osipenko
2020-03-04 21:22 ` Dmitry Osipenko
-1 siblings, 1 reply; 85+ messages in thread
From: Dmitry Osipenko @ 2020-03-04 19:26 UTC (permalink / raw)
To: Thierry Reding, Sowjanya Komatineni
Cc: jonathanh, broonie, lgirdwood, perex, tiwai, mperttunen, gregkh,
sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad, spujar,
josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
17.02.2020 12:59, Thierry Reding пишет:
...
> I've applied patches 1-10 and 13-16 to the Tegra tree, but I think it
> should be fine for Mark to pick up the ASoC patches into his tree,
> right?
>
> As I mentioned in my reply to patch 20, I think we need to hold off on
> applying patches 20-22 until all the rest have been merged, otherwise
> we'll regress.
Hello Thierry and Sowjanya,
I was trying today's next-20200304 and found that WiFi / Bluetooth got
broken:
[ 23.130017] ieee80211 phy0: brcmf_proto_bcdc_query_dcmd:
brcmf_proto_bcdc_msg failed w/status -110
[ 23.130167] ieee80211 phy0: brcmf_cfg80211_get_channel: chanspec
failed (-110)
[ 25.690008] ieee80211 phy0: brcmf_proto_bcdc_query_dcmd:
brcmf_proto_bcdc_msg failed w/status -110
[ 30.811972] ieee80211 phy0: brcmf_dongle_scantime: Scan assoc time
error (-110)
[ 33.370184] ieee80211 phy0: brcmf_netdev_open: failed to bring up
cfg80211
[ 35.929994] ieee80211 phy0: brcmf_proto_bcdc_query_dcmd:
brcmf_proto_bcdc_msg failed w/status -110
[ 35.930181] ieee80211 phy0: brcmf_cfg80211_get_channel: chanspec
failed (-110)
The fix is to replace TEGRA30_CLK_BLINK with TEGRA_PMC_CLK_BLINK in a
device-tree.
I'm not sure that the TEGRA30_CLK_BLINK breakage is expected to happen
because all clk/tegra/ PMC code is still in place. Please take a look,
thanks in advance.
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
2020-03-04 19:26 ` Dmitry Osipenko
@ 2020-03-04 21:22 ` Dmitry Osipenko
0 siblings, 0 replies; 85+ messages in thread
From: Dmitry Osipenko @ 2020-03-04 21:22 UTC (permalink / raw)
To: Thierry Reding, Sowjanya Komatineni
Cc: jonathanh, broonie, lgirdwood, perex, tiwai, mperttunen, gregkh,
sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad, spujar,
josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
04.03.2020 22:26, Dmitry Osipenko пишет:
> 17.02.2020 12:59, Thierry Reding пишет:
> ...
>> I've applied patches 1-10 and 13-16 to the Tegra tree, but I think it
>> should be fine for Mark to pick up the ASoC patches into his tree,
>> right?
>>
>> As I mentioned in my reply to patch 20, I think we need to hold off on
>> applying patches 20-22 until all the rest have been merged, otherwise
>> we'll regress.
>
> Hello Thierry and Sowjanya,
>
> I was trying today's next-20200304 and found that WiFi / Bluetooth got
> broken:
>
> [ 23.130017] ieee80211 phy0: brcmf_proto_bcdc_query_dcmd:
> brcmf_proto_bcdc_msg failed w/status -110
> [ 23.130167] ieee80211 phy0: brcmf_cfg80211_get_channel: chanspec
> failed (-110)
> [ 25.690008] ieee80211 phy0: brcmf_proto_bcdc_query_dcmd:
> brcmf_proto_bcdc_msg failed w/status -110
> [ 30.811972] ieee80211 phy0: brcmf_dongle_scantime: Scan assoc time
> error (-110)
> [ 33.370184] ieee80211 phy0: brcmf_netdev_open: failed to bring up
> cfg80211
> [ 35.929994] ieee80211 phy0: brcmf_proto_bcdc_query_dcmd:
> brcmf_proto_bcdc_msg failed w/status -110
> [ 35.930181] ieee80211 phy0: brcmf_cfg80211_get_channel: chanspec
> failed (-110)
>
> The fix is to replace TEGRA30_CLK_BLINK with TEGRA_PMC_CLK_BLINK in a
> device-tree.
>
> I'm not sure that the TEGRA30_CLK_BLINK breakage is expected to happen
> because all clk/tegra/ PMC code is still in place. Please take a look,
> thanks in advance.
This happens because the unused "pmc_blink" is getting auto-disabled by
the CCF. Which means that it's wrong to apply this series partially.
@Thierry, please re-apply it all properly. All patches, excluding patch
#11, should be applied. Thanks in advance.
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-03-25 21:27 ` Thierry Reding
-1 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-03-25 21:27 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Sowjanya Komatineni, jonathanh-DDmLM1+adcrQT0dZR+AlfA,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
digetx-Re5JQEeQqe8AvxtiuMwx3w, mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
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On Mon, Jan 13, 2020 at 11:24:05PM -0800, Sowjanya Komatineni wrote:
> This patch series moves Tegra PMC clocks from clock driver to pmc driver
> along with the device trees changes and audio driver which uses one of
> the pmc clock for audio mclk.
>
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
>
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
>
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removes them from Tegra clock
> driver.
>
> PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
> and clock driver does inital parent configuration for it and enables them.
> But this clock should be taken care by audio driver as there is no need
> to have this clock pre enabled.
>
> So, this series also includes patch that updates ASoC utils to take
> care of parent configuration for mclk if device tree don't specify
> initial parent configuration using assigned-clock-parents and enable
> audio mclk during utils init.
>
> DTs are also updated to use clk_out_1 as audio mclk rather than extern1.
>
> This series also includes a patch for mclk fallback to extern1 when
> retrieving mclk fails to have this backward compatible of new DT with
> old kernels.
>
> [v8]: Changes between v7 and v8 are
> - v7 minor feedback
>
> - Audio mclk is needed only for audio, but there is some unknown
> dependency of audio mclk and suspend-resume on Tegra30 where when
> mclk is disable, suspend-resume doesn't work.
> So v8 undoes v7 change of mclk enable and disable during machine
> startup and shutdown and keeps audio mclk enabled in ASoC driver
> tegra_asoc_utils_init.
>
> - change in the patches order.
>
> Note:
> - Patches 1 thru 5 are to change CLK_M_DIV clocks to OSC_DIV clocks.
> OSC_DIV clocks uses same ID as CLK_M_DIV clocks during the
> transition to replace CLK_M_DIV with OSC_DIV.
> - Patches 8 and 10 registers pmc clocks as pmc_clk_out_1/2/3, and
> pmc_blink to avoid using same clock names as pmc clocks from
> tegra_car provider to have them functionally work with all the
> transition patches.
> - Patch 11 adds audio mclk fallback to extern1 to have new DT work
> with old kernels. This patch need to be back-ported.
> - Patch 18 adds audio mclk parent configuration when DT doesn't
> specify parent configs. This patch retrieves pmc_clk_out_1 as audio
> mclk so added this patch after all DT updates to use pmc clocks
> from tegra_pmc.
> - Patch 19 does audio mclk enable during utils init to have it
> enabled all the time.
> - Patch 20 and 21 removes PMC clocks from clock driver and their IDs
> at the end of PMC clocks transition to tegra_pmc.
>
>
> [v7]: Changes between v6 and v7 are
> - v6 minor feedback
> - Added DT id for Tegra OSC to use in device tree for pmc clock
> parent.
>
> [v6]: Changes between v5 and v6 are
> - v5 feedback
> - Added ASoC machine startup and shutdown callbacks to control audio
> mclk enable/disable and removed default mclk enable from clock driver.
> - Updated tegra_asoc_utils_set_rate to disable mclk only during PLLA
> rate change and removed disabling PLLA as its already taken care by
> pll clock driver.
> - Removed tegra_asoc_utils_set_rate call from utils_init as set_rate
> is set during machine hw_params and during utils_init mclk is
> already in disabled state and this causes warning during mclk disable
> in utils_set_rate.
>
> [v5]: Changes between v4 and v5 are
> - v4 feedback
> - updated dt-binding pmc YAML schema with more description on power
> gate nodes and pad configuration state nodes.
> - update tegra_asoc_utils_set_rate to disable audio mclk only if
> its in enable state.
>
> [v4]: Changes between v3 and v4 are
> - v3 Feedback
> - Updated clocks clk_m_div2 and clk_m_div4 as osc_div2 and osc_div4.
> Tegra don't have clk_m_div2, clk_m_div4 and they should actually
> be osc_div2 and osc_div4 clocks from osc pads.
> - Fixed PMC clock parents to use osc, osc_div2, osc_div4.
> This is not a functional bug fix but correction to use proper parent
> name.
> - Register each PMC clock as single clock rather than separate
> mux and gate clocks.
> - Update ASoC utils to use resource managed APIs rather than
> using clk_get and clk_put.
> - Updated device tree and ASoC driver to use clk_out_1 instead of
> clk_out_1_mux as PMC clocks are registered as single clock.
> - Update clock driver init_table to not enable audio related clocks
> as ASoC utils will do audio clock enables.
>
> [v3]: Changes between v2 and v3 are
> - Removes set parent of clk_out_1_mux to extern1 and enabling
> extern1 from the clock driver.
> - Doesn't enable clk_out_1 and blink by default in pmc driver
> - Updates ASoC driver to take care of audio mclk parent
> configuration incase if device tree don't specify assigned
> clock parent properties and enables mclk using both clk_out_1
> and extern1.
> - updates all device trees using extern1 as mclk in sound node
> to use clk_out_1 from pmc.
> - patch for YAML format pmc dt-binding
> - Includes v2 feedback
>
> [v2]: Changes between v1 and v2 are
> - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> - feedback related to pmc clocks in Tegra PMC driver from v1
> - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> by the clock driver using helper functions from Tegra PMC.
>
> Note:
> To use helper functions from PMC driver, PMC early init need to
> happen prior to using helper functions and these helper functions are
> for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> clock registration which happen in clock_init prior to Tegra PMC
> probe.
> Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> impacts other clocks EMC, MC and corresponding tegra_emc_init and
> tegra_mc_init.
> This implementation of configuring PMC registers thru helper
> functions in clock driver needs proper changes across PMC, Clock,
> EMC and MC inits to have it work across all Tegra platforms.
>
> Currently PLLM Override is not enabled in the bootloader so proper
> patches for this fix will be taken care separately.
>
> [v1]: v1 includes patches for below fixes.
> - adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
> driver and removing clk-tegra-pmc.
> - updated clock provider from tegra_car to pmc in the device tree
> tegra210-smaug.dts that uses clk_out_2.
> - Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
> IDDQ programming to use by clock driver and updated clock driver to
> use these helper functions and removed direct PMC access from clock
> driver and all pmc base address references in clock driver.
>
> Sowjanya Komatineni (22):
> dt-bindings: clock: tegra: Add IDs for OSC clocks
> clk: tegra: Add support for OSC_DIV fixed clocks
> clk: tegra: Add Tegra OSC to clock lookup
> clk: tegra: Fix Tegra PMC clock out parents
> clk: tegra: Remove CLK_M_DIV fixed clocks
> dt-bindings: tegra: Convert Tegra PMC bindings to YAML
> dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
> soc: tegra: Add Tegra PMC clocks registration into PMC driver
> dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
> soc: tegra: Add support for 32KHz blink clock
> ASoC: tegra: Add fallback implementation for audio mclk
> ASoC: tegra: Use device managed resource APIs to get the clock
> ARM: dts: tegra: Add clock-cells property to pmc
> arm64: tegra: Add clock-cells property to Tegra PMC node
> ARM: tegra: Update sound node clocks in device tree
> arm64: tegra: smaug: Change clk_out_2 provider to pmc
> ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc
> ASoC: tegra: Add audio mclk parent configuration
> ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init
> clk: tegra: Remove tegra_pmc_clk_init along with clk ids
> dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
> clk: tegra: Remove audio clocks configuration from clock driver
Liam, Mark,
there's a few runtime dependencies between the various patches in this
series, so I think it'd probably be best if I picked up the ASoC patches
into the Tegra tree and let them soak for a day or two in linux-next to
make sure everything is there and in the right order.
Do you mind if I pick them up and send to you as a pull request in the
next few days?
If you'd prefer to pick these up yourself that should be fine as well.
They've all got acks from me and the runtime dependencies are causing
annoying, though harmless, warnings during boot, so I think it'd be fine
as long as all the patches end up getting merged for v5.7-rc1.
If you do decide to pick these up yourselves, please omit patch 11 in
the series since that doesn't do what it's expected to.
Thierry
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^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
@ 2020-03-25 21:27 ` Thierry Reding
0 siblings, 0 replies; 85+ messages in thread
From: Thierry Reding @ 2020-03-25 21:27 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Sowjanya Komatineni, jonathanh, perex, tiwai, digetx, mperttunen,
gregkh, sboyd, robh+dt, mark.rutland, pdeschrijver, pgaikwad,
spujar, josephl, daniel.lezcano, mmaddireddy, markz, devicetree,
linux-clk, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 9486 bytes --]
On Mon, Jan 13, 2020 at 11:24:05PM -0800, Sowjanya Komatineni wrote:
> This patch series moves Tegra PMC clocks from clock driver to pmc driver
> along with the device trees changes and audio driver which uses one of
> the pmc clock for audio mclk.
>
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
>
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
>
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removes them from Tegra clock
> driver.
>
> PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
> and clock driver does inital parent configuration for it and enables them.
> But this clock should be taken care by audio driver as there is no need
> to have this clock pre enabled.
>
> So, this series also includes patch that updates ASoC utils to take
> care of parent configuration for mclk if device tree don't specify
> initial parent configuration using assigned-clock-parents and enable
> audio mclk during utils init.
>
> DTs are also updated to use clk_out_1 as audio mclk rather than extern1.
>
> This series also includes a patch for mclk fallback to extern1 when
> retrieving mclk fails to have this backward compatible of new DT with
> old kernels.
>
> [v8]: Changes between v7 and v8 are
> - v7 minor feedback
>
> - Audio mclk is needed only for audio, but there is some unknown
> dependency of audio mclk and suspend-resume on Tegra30 where when
> mclk is disable, suspend-resume doesn't work.
> So v8 undoes v7 change of mclk enable and disable during machine
> startup and shutdown and keeps audio mclk enabled in ASoC driver
> tegra_asoc_utils_init.
>
> - change in the patches order.
>
> Note:
> - Patches 1 thru 5 are to change CLK_M_DIV clocks to OSC_DIV clocks.
> OSC_DIV clocks uses same ID as CLK_M_DIV clocks during the
> transition to replace CLK_M_DIV with OSC_DIV.
> - Patches 8 and 10 registers pmc clocks as pmc_clk_out_1/2/3, and
> pmc_blink to avoid using same clock names as pmc clocks from
> tegra_car provider to have them functionally work with all the
> transition patches.
> - Patch 11 adds audio mclk fallback to extern1 to have new DT work
> with old kernels. This patch need to be back-ported.
> - Patch 18 adds audio mclk parent configuration when DT doesn't
> specify parent configs. This patch retrieves pmc_clk_out_1 as audio
> mclk so added this patch after all DT updates to use pmc clocks
> from tegra_pmc.
> - Patch 19 does audio mclk enable during utils init to have it
> enabled all the time.
> - Patch 20 and 21 removes PMC clocks from clock driver and their IDs
> at the end of PMC clocks transition to tegra_pmc.
>
>
> [v7]: Changes between v6 and v7 are
> - v6 minor feedback
> - Added DT id for Tegra OSC to use in device tree for pmc clock
> parent.
>
> [v6]: Changes between v5 and v6 are
> - v5 feedback
> - Added ASoC machine startup and shutdown callbacks to control audio
> mclk enable/disable and removed default mclk enable from clock driver.
> - Updated tegra_asoc_utils_set_rate to disable mclk only during PLLA
> rate change and removed disabling PLLA as its already taken care by
> pll clock driver.
> - Removed tegra_asoc_utils_set_rate call from utils_init as set_rate
> is set during machine hw_params and during utils_init mclk is
> already in disabled state and this causes warning during mclk disable
> in utils_set_rate.
>
> [v5]: Changes between v4 and v5 are
> - v4 feedback
> - updated dt-binding pmc YAML schema with more description on power
> gate nodes and pad configuration state nodes.
> - update tegra_asoc_utils_set_rate to disable audio mclk only if
> its in enable state.
>
> [v4]: Changes between v3 and v4 are
> - v3 Feedback
> - Updated clocks clk_m_div2 and clk_m_div4 as osc_div2 and osc_div4.
> Tegra don't have clk_m_div2, clk_m_div4 and they should actually
> be osc_div2 and osc_div4 clocks from osc pads.
> - Fixed PMC clock parents to use osc, osc_div2, osc_div4.
> This is not a functional bug fix but correction to use proper parent
> name.
> - Register each PMC clock as single clock rather than separate
> mux and gate clocks.
> - Update ASoC utils to use resource managed APIs rather than
> using clk_get and clk_put.
> - Updated device tree and ASoC driver to use clk_out_1 instead of
> clk_out_1_mux as PMC clocks are registered as single clock.
> - Update clock driver init_table to not enable audio related clocks
> as ASoC utils will do audio clock enables.
>
> [v3]: Changes between v2 and v3 are
> - Removes set parent of clk_out_1_mux to extern1 and enabling
> extern1 from the clock driver.
> - Doesn't enable clk_out_1 and blink by default in pmc driver
> - Updates ASoC driver to take care of audio mclk parent
> configuration incase if device tree don't specify assigned
> clock parent properties and enables mclk using both clk_out_1
> and extern1.
> - updates all device trees using extern1 as mclk in sound node
> to use clk_out_1 from pmc.
> - patch for YAML format pmc dt-binding
> - Includes v2 feedback
>
> [v2]: Changes between v1 and v2 are
> - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> - feedback related to pmc clocks in Tegra PMC driver from v1
> - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> by the clock driver using helper functions from Tegra PMC.
>
> Note:
> To use helper functions from PMC driver, PMC early init need to
> happen prior to using helper functions and these helper functions are
> for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> clock registration which happen in clock_init prior to Tegra PMC
> probe.
> Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> impacts other clocks EMC, MC and corresponding tegra_emc_init and
> tegra_mc_init.
> This implementation of configuring PMC registers thru helper
> functions in clock driver needs proper changes across PMC, Clock,
> EMC and MC inits to have it work across all Tegra platforms.
>
> Currently PLLM Override is not enabled in the bootloader so proper
> patches for this fix will be taken care separately.
>
> [v1]: v1 includes patches for below fixes.
> - adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
> driver and removing clk-tegra-pmc.
> - updated clock provider from tegra_car to pmc in the device tree
> tegra210-smaug.dts that uses clk_out_2.
> - Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
> IDDQ programming to use by clock driver and updated clock driver to
> use these helper functions and removed direct PMC access from clock
> driver and all pmc base address references in clock driver.
>
> Sowjanya Komatineni (22):
> dt-bindings: clock: tegra: Add IDs for OSC clocks
> clk: tegra: Add support for OSC_DIV fixed clocks
> clk: tegra: Add Tegra OSC to clock lookup
> clk: tegra: Fix Tegra PMC clock out parents
> clk: tegra: Remove CLK_M_DIV fixed clocks
> dt-bindings: tegra: Convert Tegra PMC bindings to YAML
> dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
> soc: tegra: Add Tegra PMC clocks registration into PMC driver
> dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock
> soc: tegra: Add support for 32KHz blink clock
> ASoC: tegra: Add fallback implementation for audio mclk
> ASoC: tegra: Use device managed resource APIs to get the clock
> ARM: dts: tegra: Add clock-cells property to pmc
> arm64: tegra: Add clock-cells property to Tegra PMC node
> ARM: tegra: Update sound node clocks in device tree
> arm64: tegra: smaug: Change clk_out_2 provider to pmc
> ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc
> ASoC: tegra: Add audio mclk parent configuration
> ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init
> clk: tegra: Remove tegra_pmc_clk_init along with clk ids
> dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
> clk: tegra: Remove audio clocks configuration from clock driver
Liam, Mark,
there's a few runtime dependencies between the various patches in this
series, so I think it'd probably be best if I picked up the ASoC patches
into the Tegra tree and let them soak for a day or two in linux-next to
make sure everything is there and in the right order.
Do you mind if I pick them up and send to you as a pull request in the
next few days?
If you'd prefer to pick these up yourself that should be fine as well.
They've all got acks from me and the runtime dependencies are causing
annoying, though harmless, warnings during boot, so I think it'd be fine
as long as all the patches end up getting merged for v5.7-rc1.
If you do decide to pick these up yourselves, please omit patch 11 in
the series since that doesn't do what it's expected to.
Thierry
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^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
2020-03-25 21:27 ` Thierry Reding
@ 2020-03-27 15:45 ` Mark Brown
-1 siblings, 0 replies; 85+ messages in thread
From: Mark Brown @ 2020-03-27 15:45 UTC (permalink / raw)
To: Thierry Reding
Cc: Liam Girdwood, Sowjanya Komatineni,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, perex-/Fr2/VpizcU,
tiwai-IBi9RG/b67k, digetx-Re5JQEeQqe8AvxtiuMwx3w,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 628 bytes --]
On Wed, Mar 25, 2020 at 10:27:08PM +0100, Thierry Reding wrote:
> there's a few runtime dependencies between the various patches in this
> series, so I think it'd probably be best if I picked up the ASoC patches
> into the Tegra tree and let them soak for a day or two in linux-next to
> make sure everything is there and in the right order.
> Do you mind if I pick them up and send to you as a pull request in the
> next few days?
I guess, I think I lost track of what was going on with this as it
seemed to continually be getting lots of discussions:
Acked-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
@ 2020-03-27 15:45 ` Mark Brown
0 siblings, 0 replies; 85+ messages in thread
From: Mark Brown @ 2020-03-27 15:45 UTC (permalink / raw)
To: Thierry Reding
Cc: Liam Girdwood, Sowjanya Komatineni, jonathanh, perex, tiwai,
digetx, mperttunen, gregkh, sboyd, robh+dt, mark.rutland,
pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 599 bytes --]
On Wed, Mar 25, 2020 at 10:27:08PM +0100, Thierry Reding wrote:
> there's a few runtime dependencies between the various patches in this
> series, so I think it'd probably be best if I picked up the ASoC patches
> into the Tegra tree and let them soak for a day or two in linux-next to
> make sure everything is there and in the right order.
> Do you mind if I pick them up and send to you as a pull request in the
> next few days?
I guess, I think I lost track of what was going on with this as it
seemed to continually be getting lots of discussions:
Acked-by: Mark Brown <broonie@kernel.org>
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^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
2020-01-14 7:24 ` Sowjanya Komatineni
@ 2020-04-21 13:52 ` Jon Hunter
-1 siblings, 0 replies; 85+ messages in thread
From: Jon Hunter @ 2020-04-21 13:52 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
broonie-DgEjT+Ai2ygdnm+yROfE0A, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
digetx-Re5JQEeQqe8AvxtiuMwx3w, mperttunen-DDmLM1+adcrQT0dZR+AlfA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
sboyd-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8
Cc: pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA, spujar-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
mmaddireddy-DDmLM1+adcrQT0dZR+AlfA, markz-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 14/01/2020 07:24, Sowjanya Komatineni wrote:
> This patch series moves Tegra PMC clocks from clock driver to pmc driver
> along with the device trees changes and audio driver which uses one of
> the pmc clock for audio mclk.
>
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
>
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
>
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removes them from Tegra clock
> driver.
>
> PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
> and clock driver does inital parent configuration for it and enables them.
> But this clock should be taken care by audio driver as there is no need
> to have this clock pre enabled.
>
> So, this series also includes patch that updates ASoC utils to take
> care of parent configuration for mclk if device tree don't specify
> initial parent configuration using assigned-clock-parents and enable
> audio mclk during utils init.
>
> DTs are also updated to use clk_out_1 as audio mclk rather than extern1.
>
> This series also includes a patch for mclk fallback to extern1 when
> retrieving mclk fails to have this backward compatible of new DT with
> old kernels.
On the current mainline kernel I am seeing the following WARNING on boot
for tegra20-ventana, tegra30-cardhu-a04 and tegra124-jetson-tk1 ...
[ 10.723511] ------------[ cut here ]------------
[ 10.730901] WARNING: CPU: 0 PID: 126 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/clk/clk.c:954 clk_core_disable+0xf4/0x280
[ 10.745986] cdev1 already disabled
[ 10.752309] Modules linked in: snd_soc_tegra_wm8903(+) snd_soc_tegra20_i2s snd_soc_tegra_utils snd_soc_tegra_pcm snd_soc_wm8903 snd_soc_core ac97_bus snd_pcm_dmaengine snd_pcm snd_timer snd soundcore snd_soc_tegra20_das
[ 10.778071] CPU: 0 PID: 126 Comm: systemd-udevd Not tainted 5.7.0-rc2-next-20200420-g6735c84f78e4 #1
[ 10.790485] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
[ 10.800088] [<c0311a70>] (unwind_backtrace) from [<c030bd14>] (show_stack+0x10/0x14)
[ 10.811227] [<c030bd14>] (show_stack) from [<c0714710>] (dump_stack+0xc0/0xd4)
[ 10.821863] [<c0714710>] (dump_stack) from [<c0345b64>] (__warn+0xe0/0xf8)
[ 10.832118] [<c0345b64>] (__warn) from [<c0345bf0>] (warn_slowpath_fmt+0x74/0xb8)
[ 10.843006] [<c0345bf0>] (warn_slowpath_fmt) from [<c0812dcc>] (clk_core_disable+0xf4/0x280)
[ 10.854863] [<c0812dcc>] (clk_core_disable) from [<c0812f70>] (clk_core_disable_lock+0x18/0x24)
[ 10.867021] [<c0812f70>] (clk_core_disable_lock) from [<bf072230>] (tegra_asoc_utils_set_rate+0x74/0x2b4 [snd_soc_tegra_utils])
[ 10.882055] [<bf072230>] (tegra_asoc_utils_set_rate [snd_soc_tegra_utils]) from [<bf072504>] (tegra_asoc_utils_init+0x94/0xb90 [snd_soc_tegra_utils])
[ 10.899177] [<bf072504>] (tegra_asoc_utils_init [snd_soc_tegra_utils]) from [<bf07c558>] (tegra_wm8903_driver_probe+0x294/0x310 [snd_soc_tegra_wm8903])
[ 10.916562] [<bf07c558>] (tegra_wm8903_driver_probe [snd_soc_tegra_wm8903]) from [<c09d2944>] (platform_drv_probe+0x48/0x98)
[ 10.931678] [<c09d2944>] (platform_drv_probe) from [<c09d09f0>] (really_probe+0x218/0x348)
[ 10.943886] [<c09d09f0>] (really_probe) from [<c09d0c60>] (driver_probe_device+0x60/0x168)
[ 10.956140] [<c09d0c60>] (driver_probe_device) from [<c09d0f10>] (device_driver_attach+0x58/0x60)
[ 10.969029] [<c09d0f10>] (device_driver_attach) from [<c09d0f98>] (__driver_attach+0x80/0xbc)
[ 10.981613] [<c09d0f98>] (__driver_attach) from [<c09ced9c>] (bus_for_each_dev+0x74/0xb4)
[ 10.993891] [<c09ced9c>] (bus_for_each_dev) from [<c09cfd90>] (bus_add_driver+0x164/0x1e8)
[ 11.006298] [<c09cfd90>] (bus_add_driver) from [<c09d1a1c>] (driver_register+0x7c/0x114)
[ 11.018586] [<c09d1a1c>] (driver_register) from [<c0302040>] (do_one_initcall+0x54/0x22c)
[ 11.031016] [<c0302040>] (do_one_initcall) from [<c03ddc98>] (do_init_module+0x60/0x210)
[ 11.043370] [<c03ddc98>] (do_init_module) from [<c03dcdac>] (load_module+0x1f9c/0x2480)
[ 11.055684] [<c03dcdac>] (load_module) from [<c03dd4b4>] (sys_finit_module+0xac/0xd8)
[ 11.067843] [<c03dd4b4>] (sys_finit_module) from [<c03002a0>] (__sys_trace_return+0x0/0x20)
[ 11.080560] Exception stack(0xede3bfa8 to 0xede3bff0)
[ 11.089988] bfa0: b6eb9a8c 00000000 00000010 b6eb91bc 00000000 b6eb9cd0
[ 11.102625] bfc0: b6eb9a8c 00000000 fca6e200 0000017b 00555918 bea799ac 00000000 00564640
[ 11.115289] bfe0: bea798a8 bea79898 b6eb3951 b6f61f42
[ 11.124833] ---[ end trace 3752c80347dfd3ca ]---
It appears that some of the patches in this series made v5.7-rc1 but not
all and I am guessing the ASoC changes are the ones we are missing to
avoid this.
Sowjanya, any ideas on the best way to resolve this for v5.7?
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 85+ messages in thread
* Re: [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver
@ 2020-04-21 13:52 ` Jon Hunter
0 siblings, 0 replies; 85+ messages in thread
From: Jon Hunter @ 2020-04-21 13:52 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, broonie, lgirdwood, perex,
tiwai, digetx, mperttunen, gregkh, sboyd, robh+dt, mark.rutland
Cc: pdeschrijver, pgaikwad, spujar, josephl, daniel.lezcano,
mmaddireddy, markz, devicetree, linux-clk, linux-tegra,
linux-kernel
On 14/01/2020 07:24, Sowjanya Komatineni wrote:
> This patch series moves Tegra PMC clocks from clock driver to pmc driver
> along with the device trees changes and audio driver which uses one of
> the pmc clock for audio mclk.
>
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
>
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
>
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removes them from Tegra clock
> driver.
>
> PMC clock clk_out_1 is dedicated for audio mclk from Tegra30 thru Tegra210
> and clock driver does inital parent configuration for it and enables them.
> But this clock should be taken care by audio driver as there is no need
> to have this clock pre enabled.
>
> So, this series also includes patch that updates ASoC utils to take
> care of parent configuration for mclk if device tree don't specify
> initial parent configuration using assigned-clock-parents and enable
> audio mclk during utils init.
>
> DTs are also updated to use clk_out_1 as audio mclk rather than extern1.
>
> This series also includes a patch for mclk fallback to extern1 when
> retrieving mclk fails to have this backward compatible of new DT with
> old kernels.
On the current mainline kernel I am seeing the following WARNING on boot
for tegra20-ventana, tegra30-cardhu-a04 and tegra124-jetson-tk1 ...
[ 10.723511] ------------[ cut here ]------------
[ 10.730901] WARNING: CPU: 0 PID: 126 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/clk/clk.c:954 clk_core_disable+0xf4/0x280
[ 10.745986] cdev1 already disabled
[ 10.752309] Modules linked in: snd_soc_tegra_wm8903(+) snd_soc_tegra20_i2s snd_soc_tegra_utils snd_soc_tegra_pcm snd_soc_wm8903 snd_soc_core ac97_bus snd_pcm_dmaengine snd_pcm snd_timer snd soundcore snd_soc_tegra20_das
[ 10.778071] CPU: 0 PID: 126 Comm: systemd-udevd Not tainted 5.7.0-rc2-next-20200420-g6735c84f78e4 #1
[ 10.790485] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
[ 10.800088] [<c0311a70>] (unwind_backtrace) from [<c030bd14>] (show_stack+0x10/0x14)
[ 10.811227] [<c030bd14>] (show_stack) from [<c0714710>] (dump_stack+0xc0/0xd4)
[ 10.821863] [<c0714710>] (dump_stack) from [<c0345b64>] (__warn+0xe0/0xf8)
[ 10.832118] [<c0345b64>] (__warn) from [<c0345bf0>] (warn_slowpath_fmt+0x74/0xb8)
[ 10.843006] [<c0345bf0>] (warn_slowpath_fmt) from [<c0812dcc>] (clk_core_disable+0xf4/0x280)
[ 10.854863] [<c0812dcc>] (clk_core_disable) from [<c0812f70>] (clk_core_disable_lock+0x18/0x24)
[ 10.867021] [<c0812f70>] (clk_core_disable_lock) from [<bf072230>] (tegra_asoc_utils_set_rate+0x74/0x2b4 [snd_soc_tegra_utils])
[ 10.882055] [<bf072230>] (tegra_asoc_utils_set_rate [snd_soc_tegra_utils]) from [<bf072504>] (tegra_asoc_utils_init+0x94/0xb90 [snd_soc_tegra_utils])
[ 10.899177] [<bf072504>] (tegra_asoc_utils_init [snd_soc_tegra_utils]) from [<bf07c558>] (tegra_wm8903_driver_probe+0x294/0x310 [snd_soc_tegra_wm8903])
[ 10.916562] [<bf07c558>] (tegra_wm8903_driver_probe [snd_soc_tegra_wm8903]) from [<c09d2944>] (platform_drv_probe+0x48/0x98)
[ 10.931678] [<c09d2944>] (platform_drv_probe) from [<c09d09f0>] (really_probe+0x218/0x348)
[ 10.943886] [<c09d09f0>] (really_probe) from [<c09d0c60>] (driver_probe_device+0x60/0x168)
[ 10.956140] [<c09d0c60>] (driver_probe_device) from [<c09d0f10>] (device_driver_attach+0x58/0x60)
[ 10.969029] [<c09d0f10>] (device_driver_attach) from [<c09d0f98>] (__driver_attach+0x80/0xbc)
[ 10.981613] [<c09d0f98>] (__driver_attach) from [<c09ced9c>] (bus_for_each_dev+0x74/0xb4)
[ 10.993891] [<c09ced9c>] (bus_for_each_dev) from [<c09cfd90>] (bus_add_driver+0x164/0x1e8)
[ 11.006298] [<c09cfd90>] (bus_add_driver) from [<c09d1a1c>] (driver_register+0x7c/0x114)
[ 11.018586] [<c09d1a1c>] (driver_register) from [<c0302040>] (do_one_initcall+0x54/0x22c)
[ 11.031016] [<c0302040>] (do_one_initcall) from [<c03ddc98>] (do_init_module+0x60/0x210)
[ 11.043370] [<c03ddc98>] (do_init_module) from [<c03dcdac>] (load_module+0x1f9c/0x2480)
[ 11.055684] [<c03dcdac>] (load_module) from [<c03dd4b4>] (sys_finit_module+0xac/0xd8)
[ 11.067843] [<c03dd4b4>] (sys_finit_module) from [<c03002a0>] (__sys_trace_return+0x0/0x20)
[ 11.080560] Exception stack(0xede3bfa8 to 0xede3bff0)
[ 11.089988] bfa0: b6eb9a8c 00000000 00000010 b6eb91bc 00000000 b6eb9cd0
[ 11.102625] bfc0: b6eb9a8c 00000000 fca6e200 0000017b 00555918 bea799ac 00000000 00564640
[ 11.115289] bfe0: bea798a8 bea79898 b6eb3951 b6f61f42
[ 11.124833] ---[ end trace 3752c80347dfd3ca ]---
It appears that some of the patches in this series made v5.7-rc1 but not
all and I am guessing the ASoC changes are the ones we are missing to
avoid this.
Sowjanya, any ideas on the best way to resolve this for v5.7?
Cheers
Jon
--
nvpublic
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